Dual resistive random access memory with two transistors

Abstract

An approach is provided for forming a semiconductor structure. The semiconductor structure comprises two adjacent fins on a substrate. A gate stack is on each of the two adjacent fins. The semiconductor structure comprises a first source / drain on a first end of each fin of the two adjacent fins and a second source / drain on a second end of each fin of the two adjacent fins. The semiconductor structure comprises a switching layer on at least the first source / drain on the first end of each fin of the two adjacent fins and a top electrode on the switching layer. A metal material covers the top electrode in the semiconductor structure.

Description

[Technical Field]

[0001] The present application relates to a semiconductor structure and a method for forming the same, and more particularly to a semiconductor structure comprising two electrically connected resistive random access memories (ReRAMs) formed on the source / drains of two fin field effect transistors. [Background technology]

[0002] Many modern electronic devices contain electronic memory, which can be volatile or non-volatile. Non-volatile memory retains the data stored therein in the absence of power, while volatile memory loses the data stored therein when power is removed.

[0003] Resistive random access memory (ReRAM or RRAM) is one of the promising candidates for next-generation non-volatile memory due to its simple structure and compatibility with complementary metal-oxide-semiconductor (CMOS) logic manufacturing processes. Resistive random access memory operates by changing the resistance value across a dielectric solid material. A typical ReRAM consists of a bottom electrode, a top electrode, and an oxide layer between the two electrodes. Summary of the Invention [Means for solving the problem]

[0004] According to one embodiment of the present invention, there is provided a semiconductor structure comprising two adjacent fins on a substrate, each having a gate stack on the two adjacent fins. The semiconductor structure comprises a first source / drain on a first end of each of the two adjacent fins and a second source / drain on a second end of each of the two adjacent fins. The semiconductor structure comprises a switching layer on at least the first source / drain on the first end of each of the two adjacent fins, and an upper electrode on the switching layer. A metal material covers the upper electrode in the semiconductor structure.

[0005] According to another embodiment of the present invention, a method for forming a pair of resistive random access devices on a pair of adjacent fins is provided. The method includes depositing a gate on a portion of each of the pair of adjacent fins and on a first portion of an oxide layer. The method includes forming source / drains on each end of each fin of the pair of adjacent fins and depositing a first layer of interlayer dielectric material. The method further includes selectively etching a portion of the first layer of interlayer dielectric material covering at least a pair of first source / drains on the first end of each fin of the pair of adjacent fins. The method includes depositing a layer of switching material covering the first layer of interlayer dielectric, covering the exposed portion of the oxide layer, and covering the pair of first source / drains. Additionally, the method includes depositing a top electrode material covering the layer of switching material. The method includes depositing a first metal layer covering the top electrode material. Furthermore, the method includes removing an upper portion of the first metal layer, an upper portion of the top electrode material, and an upper portion of the switching layer by chemical mechanical polishing, followed by forming contacts.

[0006] The following detailed description is given by way of example and is not intended to be limiting of the invention only, and will be best understood in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0007] [Figure 1A] FIG. 1A is a top view illustrating a semiconductor structure according to an exemplary embodiment of the present invention. [Figure 1B] FIG. 1B is a top view illustrating a semiconductor structure according to one embodiment of the present invention. [Figure 2] FIG. 2 is a top view illustrating a semiconductor structure having a fin and a dummy gate with spacers, in accordance with an exemplary embodiment of the present invention. [Figure 3] FIG. 3 is a cross-sectional view along line X1-X1 illustrating a semiconductor structure after depositing a dummy gate overlying a fin on a semiconductor substrate in accordance with an exemplary embodiment of the present invention. [Figure 4] FIG. 4 is a cross-sectional view of the semiconductor structure taken along line X2-X2 after depositing a dummy gate overlying the fin on the semiconductor substrate in accordance with an exemplary embodiment of the present invention. [Figure 5] FIG. 5 is a top view of a semiconductor structure after source / drain formation in accordance with an exemplary embodiment of the present invention. [Figure 6] FIG. 6 is a cross-sectional view along line X1-X1 illustrating the semiconductor structure after source / drain formation, according to an exemplary embodiment of the present invention. [Figure 7] FIG. 7 is a cross-sectional view of the semiconductor structure taken along line X2-X2 after source / drain formation, according to an exemplary embodiment of the present invention. [Figure 8] FIG. 8 is a top view of a semiconductor structure after interlayer dielectric (ILD) deposition, dummy gate replacement, and ILD etching, in accordance with an exemplary embodiment of the present invention. [Figure 9] FIG. 9 is a cross-sectional view along line X1-X1 illustrating the semiconductor structure after ILD deposition, dummy gate replacement, and ILD etching, in accordance with an exemplary embodiment of the present invention. [Figure 10] FIG. 10 is a cross-sectional view along line X2-X2 illustrating the semiconductor structure after ILD deposition, dummy gate replacement, and ILD etching, in accordance with an exemplary embodiment of the present invention. [Figure 11]FIG. 11 is a cross-sectional view along line X1-X1 illustrating the semiconductor structure after depositing the switching layer and top electrode material, according to an exemplary embodiment of the present invention. [Figure 12] FIG. 12 is a cross-sectional view of the semiconductor structure taken along line X2-X2 after depositing a switching layer and a top electrode, according to an exemplary embodiment of the present invention. [Figure 13] FIG. 13 is a cross-sectional view along line X1-X1 illustrating a semiconductor structure after deposition of a metal layer and chemical mechanical polishing (CMP) in accordance with an exemplary embodiment of the present invention. [Figure 14] FIG. 14 is a cross-sectional view of the semiconductor structure taken along line X2-X2 after deposition of a metal layer and chemical mechanical polishing (CMP) in accordance with an exemplary embodiment of the present invention. [Figure 15] FIG. 15 is a top view of a semiconductor structure after CMP and contact formation, according to an exemplary embodiment of the present invention. [Figure 16] FIG. 16 is a cross-sectional view of the semiconductor structure after CMP and contact formation, according to an exemplary embodiment of the present invention. [Figure 17] FIG. 17 is a cross-sectional view along line X1-X1 illustrating the semiconductor structure after CMP and contact formation, according to an exemplary embodiment of the present invention. [Figure 18] FIG. 18 is a cross-sectional view of the semiconductor structure taken along line X2-X2 after CMP and contact formation, in accordance with an exemplary embodiment of the present invention. [Figure 19] FIG. 19 is a cross-sectional view of the semiconductor structure taken along line X1-X1 after source / drain formation, according to one embodiment of the present invention. [Figure 20] FIG. 20 is a cross-sectional view of the semiconductor structure taken along line X2-X2 after source / drain formation, according to one embodiment of the present invention. [Figure 21] FIG. 21 is a cross-sectional view along line X1-X1 showing the semiconductor structure after ILD deposition, dummy gate replacement, and ILD etching, according to one embodiment of the present invention. [Figure 22]FIG. 22 is a cross-sectional view of the semiconductor structure taken along line X2-X2 after ILD deposition, dummy gate replacement, and ILD etching, in accordance with one embodiment of the present invention. [Figure 23] FIG. 23 is a cross-sectional view of the semiconductor structure taken along line X1-X1 after deposition of the switching layer and top electrode material, according to one embodiment of the present invention. [Figure 24] FIG. 24 is a cross-sectional view of the semiconductor structure taken along line X2-X2 after deposition of the switching layer and top electrode material, according to one embodiment of the present invention. [Figure 25] FIG. 25 is a cross-sectional view of the semiconductor structure taken along line X2-X2 after depositing a metal layer and forming contacts, according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0008] One embodiment of the present invention recognizes that resistive random access memory (ReRAM) is a promising technology for electronic synapse devices or memristors in neuromorphic computing, and is a technology for use in high-density, high-speed non-volatile memory applications. In neuromorphic computing applications, ReRAM devices can be used as connections or synapses between pre-neurons and post-neurons, where the amount of ReRAM device resistance is used to represent the connection weight. One embodiment of the present invention recognizes that multiple pre-neurons and multiple post-neurons can be connected with an array of ReRAM devices, which can naturally be represented as a fully connected neural network.

[0009] One embodiment of the present invention recognizes that for online training of deep neural networks, ideally, either one bipolar ReRAM device with symmetric switching or two unipolar ReRAM devices with linear switching can be used to determine differential weights. One embodiment of the present invention recognizes that no bipolar ReRAM devices with symmetric switching exist. One embodiment of the present invention recognizes that using two unipolar ReRAM devices with linear switching requires more devices and more peripheral circuitry to represent weights in training of deep neural networks, and therefore using two unipolar ReRAM devices with linear switching requires significant semiconductor real estate or area.

[0010] Additionally, embodiments of the present invention recognize that electroforming of current-conducting filaments occurs in the oxide of a ReRAM device. Currently, the location of the conducting filaments formed in the oxide of a ReRAM device is not controlled. If the location of the current-conducting filaments is not controlled, as ReRAM cells are scaled, higher voltages may be required to form the filaments in the ReRAM, which may result in higher variability in the ReRAM device.

[0011] Embodiments of the present invention generally relate to semiconductor structures and methods for forming the semiconductor structures. Embodiments of the present invention provide a semiconductor structure including two electrically connected ReRAM devices on two adjacent transistors. Embodiments of the present invention provide a semiconductor structure and a method for forming the semiconductor structure that facilitates controlled current-conducting filament location in the ReRAM oxide. The method for forming the semiconductor structure provides a two-transistor device integrated with two ReRAM devices that can be formed with a tight pitch. The ReRAM devices are each formed on the source / drain of one transistor of a pair of transistors.

[0012] Embodiments of the present invention provide a faceted epitaxy source / drain that provides a higher electric field at the tip of the faceted epitaxy source / drain. The higher electric field at the tip of the faceted epitaxy source / drain provides a controlled location for filament formation in the oxide of the ReRAM device. Thus, embodiments of the present invention provide two densely scaled transistor devices integrated with two unipolar ReRAM devices representing one synaptic weight to accelerate training of deep neural networks.

[0013] According to some embodiments of the present invention, two electrically connected ReRAM devices are provided, where each ReRAM device resides on a transistor. Each ReRAM device is formed on a source / drain in a portion of one fin on one side of the transistor gate. For purposes of the present invention, each of the two source / drains on one side of the transistor gate to be covered by a ReRAM device will be referred to as a first source / drain. Each of the two source / drains on the other side of the transistor gate will be referred to as a second source / drain in the present invention. The second source / drains are connected to other semiconductor devices by contacts in a conventional manner.

[0014] Detailed embodiments of the claimed structures and methods are disclosed herein. However, it should be understood that the disclosed embodiments are merely examples of the claimed structures and methods, which may be embodied in various forms. However, the present invention may be embodied in various forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the detailed description of the invention, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0015] For purposes of the following description, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives shall refer to the described structures and methods as oriented in the depicted figures. The terms "overlapping," "on," "overlying," or "on top" mean that a first element, e.g., a first structure, is above a second element, e.g., a second structure, and intervening elements, e.g., interface structures, may be present between the first and second elements. The term "direct contact" means that a first element, e.g., a first structure, and a second element, e.g., a second structure, are connected at the interface between the two elements without an intermediate conductive, insulating, or semiconducting layer.

[0016] In the following detailed description of the invention, some process steps or operations known in the art may be combined together for purposes of illustration and explanation so as not to obscure the presentation of the various embodiments of the invention, and in some instances may not be described in the detailed description of the invention. In other instances, some process steps or operations known in the art may not be described at all. It should be understood that the following description focuses on features or elements unique to various embodiments of the invention. The drawings are not necessarily to scale. The drawings are merely schematic representations and are not intended to depict specific parameters of example embodiments. The drawings are intended to depict only example, typical embodiments. In the drawings, like numbering represents like elements.

[0017] 1-18 illustrate an exemplary semiconductor structure comprising two electrically connected resistive random access memory (ReRAM) devices integrated with two fin field effect transistors (FinFETs).

[0018] FIG. 1A is a top view illustrating a semiconductor structure 100A in accordance with an exemplary embodiment of the present invention. As shown, FIG. 1A includes an oxide 3 and a fin 4, where oxide 3 is the top surface of an insulator layer of a silicon-on-insulator (SOI) substrate. In various embodiments, oxide 3 is silicon oxide, but is not limited to this material. Oxide 3 and fin 4 can be formed using known semiconductor fabrication processes.

[0019] Although two adjacent or nearby fins 4 are shown in FIG. 1A, any number of fins 4 may be present in the semiconductor structure 100A. The fins 4 may be composed of a semiconductor material, such as silicon, or a combination of semiconductor materials (e.g., SiGe), and may include one or more undoped or doped portions (e.g., portions doped with n-type or p-type material). The fins 4 may be formed using known semiconductor processes.

[0020] 1A illustrates the locations of the X1-X1 and X2-X2 cross sections on fin 4 in semiconductor structure 100A. The X1-X1 and X2-X2 locations are constant for each semiconductor structure in each view of the present invention (e.g., FIGS. 1B-25).

[0021] FIG. 1B is a top view illustrating a semiconductor structure 100B in accordance with an exemplary embodiment of the present invention. As shown, FIG. 1B includes two adjacent fins 4 on a semiconductor substrate 2 (e.g., semiconductor structure 100B does not include oxide 3). Although FIGS. 1A and 2-25 include oxide 3 as a buried oxide (BOX) of the SOI substrate below fin 4, in various embodiments, the semiconductor structures illustrated in FIGS. 2-25 are formed on semiconductor structure 100B instead of semiconductor structure 100A. In these embodiments, the semiconductor structures of FIGS. 2-25 can be formed on a bulk semiconductor substrate 2 in the absence of oxide 3.

[0022] Semiconductor substrate 2 may be composed of a semiconductor material, such as silicon, or a combination of semiconductor materials (e.g., SiGe), and may include one or more doped portions (e.g., portions doped with n-type material or p-type material). In various embodiments, semiconductor substrate 2 includes one or more semiconductor materials. Non-limiting examples of suitable semiconductor substrate 2 materials may include Si (silicon), strained Si, Ge (germanium), SiGe (silicon germanium), Si alloys, Ge alloys, III-V materials such as GaAs (gallium arsenide), InAs (indium arsenide), InP (indium phosphide), or indium gallium arsenide (InGaAs), II-VI materials such as CdSe (cadmium selenide), CdS (cadmium sulfide), CdTe (cadmium telluride), ZnO (zinc oxide), ZnSe (zinc selenide), ZnS (zinc sulfide), or ZnTe (zinc telluride), or any combination thereof. In one embodiment, semiconductor substrate 2 may include silicon. In one embodiment, semiconductor substrate 2 is a bulk semiconductor substrate. The term "bulk semiconductor substrate" refers to a substrate composed entirely of one or more semiconductor materials. The semiconductor substrate 2 may be a single-crystal semiconductor material. The semiconductor substrate 2 may have any of the well-known crystal orientations. For example, the crystal orientation of the semiconductor substrate 2 may be {100}, {110}, or {111}. Crystal orientations other than those specifically mentioned may also be used herein. In various embodiments, the semiconductor substrate 2 is a wafer or a portion of a wafer. In some embodiments, the semiconductor substrate 2 comprises one or more of a doped region, an undoped region, a strained region, or a defect-rich region.

[0023] FIG. 2 is a top view illustrating a semiconductor structure 200 having a fin 4 and a dummy gate 20 with spacers 21, in accordance with an exemplary embodiment of the present invention. As illustrated, FIG. 2 includes an oxide 3, a fin 4, a dummy gate 20, and spacers 21. In various embodiments, the dummy gate 20 is a sacrificial gate or dummy gate. For example, the dummy gate formed from polysilicon may be removed and replaced in a later process step with a replacement gate, typically formed of a metal electrode overlying a gate dielectric material (not shown). The dummy gate 20 may be made of polysilicon, amorphous silicon, or a combination of multiple layers thereof, deposited, for example, by chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD) onto the top surface of the oxide 3 and may surround a portion of the fin 4. The dummy gate 20 may cover a middle portion of the fin 4 and may cover a portion of the oxide 3. The spacers 21 may be any spacer material suitable for use in transistor devices. For example, the spacers 21 may be made of a dielectric material, such as silicon nitride or other known spacer materials, and may be deposited on the side surfaces of the dummy gate 20 using known spacer formation processes.

[0024] FIG. 3 is an X1-X1 cross-sectional view showing a semiconductor structure 300 after depositing a dummy gate overlying the fin 4 on the oxide 3, in accordance with an exemplary embodiment of the present invention. As illustrated in FIGS. 1A and 1B, the X1-X1 cross-sectional view bisects the middle portion of the fin 4. The X1-X1 cross-sectional view in FIG. 3 illustrates the dummy gate 20 overlying the fin 4 and on a portion of the oxide 3, the oxide 3 under the fin 4, and the oxide 3 on the semiconductor substrate 2. As mentioned above, FIG. 3 illustrates the oxide 3 in an SOI semiconductor substrate consisting of the semiconductor substrate 2 and the oxide 3, although other embodiments of the present invention use a semiconductor structure 100B that does not include the oxide 3, in which case the fin 4 and the dummy gate 20 are on the semiconductor substrate 2.

[0025] FIG. 4 is an X2-X2 cross-sectional view showing a semiconductor structure 400 having a fin 4, according to an exemplary embodiment of the present invention. As illustrated in FIGS. 1A and 1B, the X2-X2 cross-sectional view bisects one end of the fin 4 at the bottom of the semiconductor structure 400. As shown, the X2-X2 cross-sectional view in FIG. 4 includes the semiconductor substrate 2 below the oxide 3, and the fin 4 on a portion of the oxide 3. As discussed above, while FIG. 4 illustrates the oxide 3 (e.g., a box in an SOI semiconductor substrate consisting of the semiconductor substrate 2 and the oxide 3), other embodiments of the present invention do not include the oxide 3. In these embodiments (i.e., without the oxide 3), the fin 4 is formed directly on a portion of the semiconductor substrate 2.

[0026] 5 is a top view of a semiconductor structure 500 after formation of source / drains (S / Ds) 50, in accordance with an exemplary embodiment of the present invention. As shown, FIG. 5 includes the S / Ds 50, spacers 21, dummy gate 20, oxide 3, X1-X1 cross-sectional locations, and X2-X2 cross-sectional locations on the semiconductor structure 500. The semiconductor structure 500 comprises four source / drains (S / Ds 50), where, as described above, the first S / D 50 is the source / drain pair illustrated below the dummy gate 20 on X2-X2 in FIG. 5, and the second S / D 50 is the source / drain pair illustrated above the dummy gate 20 in FIG. 5. 2 can have one first S / D 50 on one end of each fin of the pair of adjacent fins on X2-X2 at the bottom of the semiconductor structure 500, and one second S / D 50 on the other end of each fin of the pair of adjacent fins 4 that approximately contacts the dummy gate 20 and above the spacer 21 above the dummy gate 20 (e.g., each fin has one first S / D 50 and one second S / D 50). In other words, each of the pair of first S / D 50 illustrated in FIG. 5 approximately contacts the spacer 21 below the dummy gate 20 on X2-X2. Similarly, each of the pair of second S / D 50 approximately contacts the spacer 21 above the dummy gate 20 in FIG. 5.

[0027] Each of the four S / Ds 50 may be formed by facet epitaxy using an epitaxial growth process, such as molecular beam epitaxy (MBE). For example, each of the pair of first S / Ds 50 below the dummy gate 20 may be formed by facet epitaxy to extend away from the spacers 21 on the dummy gate 20 (e.g., extend below the spacers 21 on the dummy gate 20), and the pair of second S / Ds 50 above the dummy gate 20 may be formed by facet epitaxy to extend away from or out of the spacers 21 on the dummy gate 20. Other methods, such as rapid thermal chemical vapor deposition (RTCVD), low pressure chemical vapor deposition (LPCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), and atmospheric pressure chemical vapor deposition (APCVD), may also be used to epitaxially grow each of the S / Ds 50.

[0028] In various embodiments, each of the plurality of source / drains (e.g., the two first S / Ds 50 below the dummy gate 20 on X2-X2 and the two second S / Ds 50 above the dummy gate 20) is faceted. The faceted epitaxy forming each of the plurality of source / drains may be grown on the exposed surface of the end of the fin 4 (as shown in FIG. 2). As described above, the faceted epitaxy may be grown on the exposed surface of the end of the fin 4 (as shown in FIG. 7) with a diamond facet shape ( <111> The faceted epitaxy source / drain regions 50 can be grown by lattice plane bound epitaxy. As a result, the faceted epitaxy source / drain regions 50 can include, for example, four or more facets. The pointed shape of the faceted epitaxy of each source / drain region 50 enhances the electric field at the tip of the pointed shape. In this manner, the pointed shape of the faceted epitaxy can enhance the electric field at each tip of the diamond shape in each source / drain region 50. Furthermore, the pointed shape of the pair of first source / drain regions 50, on which the ReRAM devices will later be formed, will promote current-conducting filament formation at specific locations of each ReRAM device (i.e., on the pointed tip of the first source / drain region 50) when each ReRAM device is completed.

[0029] In various embodiments, the doping of each of the S / Ds 50 occurs during epitaxial source / drain growth. For example, each of the S / Ds 50 can be doped with a dopant, which can be an n-type dopant or a p-type dopant. Each of the four source / drains (i.e., each of the S / Ds 50) formed by facet epitaxy can have the same type of doping (e.g., all n-type dopants) and the same dopant level or amount contained in each source / drain. As known to those skilled in the art, the term "n-type" refers to the addition of an impurity that contributes free electrons to an intrinsic semiconductor. In silicon-containing semiconductor materials, examples of n-type dopants, i.e., impurities, can include, but are not limited to, antimony, arsenic, and phosphorus. The term "p-type" refers to the addition of an impurity to an intrinsic semiconductor that creates a deficiency of valence electrons. In silicon-containing semiconductor materials, examples of p-type dopants, i.e., impurities, can include, but are not limited to, boron, aluminum, gallium, and indium. For example, all four source / drains (i.e., the first pair of S / Ds 50 and the second pair of S / Ds 50) may be heavily doped with one of phosphorus or boron, where the doping level is 4x10 20 cm -3 ~1.5x10 21 cm -3 In various embodiments, the first S / D 50 below the dummy gate 20 and the second S / D 50 above the dummy gate 20 of the semiconductor structure 500 each have the same level of doping with the same type of dopant. For example, if the first S / D 50 and the second S / D 50 in the semiconductor structure 500 are each doped with an n-type dopant, such as phosphorus or arsenic, then depending on the transistor completion (described below in FIG. 15 ), the transistor can be an n-type field effect transistor (nFET).

[0030] 6 is a cross-sectional view of semiconductor structure 600 taken along line X1-X1 after source / drain 50 formation, according to an exemplary embodiment of the present invention. As shown, FIG. 6 includes dummy gate 20 covering fin 4 and on a portion of oxide 3, fin 4 on a portion of oxide 3, and oxide 3 on semiconductor substrate 2. As described above, in embodiments when oxide 3 is not present, as illustrated in FIG. 1B, fin 4 and dummy gate 20 are present on semiconductor substrate 2.

[0031] FIG. 7 is a cross-sectional view of the semiconductor structure 700 taken along line X2-X2 after forming the first source / drain 50 using faceted epitaxy, in accordance with an exemplary embodiment of the present invention. As shown, FIG. 7 includes the first source / drain 50 covering a portion of the fin 4. For example, the first source / drain 50 can be formed at the end of each of the fins 4 below the dummy gate 20 in FIG. 5. As described above with respect to FIG. 5, the faceted epitaxy is used to grow the diamond facet shape ( <111> lattice-plane boundary epitaxy) to form the first source / drain regions 50. Each of the t source / drain regions 50 comprising the first source / drain regions 50 in FIG. 7 may be grown to a particular thickness, such as 10 nm to 30 nm on the fin 4, although other thicknesses are possible.

[0032] FIG. 8 is a top view illustrating a semiconductor structure 800 after ILD 90 deposition, dummy gate 20 replacement with gate stack 60, and selective ILD etching, in accordance with an exemplary embodiment of the present invention. As shown, FIG. 8 includes ILD 90, first S / D 50, oxide 3, location of X1-X1, and location of X2-X2. FIG. 8 illustrates the first S / D 50 exposed after selective etching of a portion of ILD 90 deposited over semiconductor structure 800 after replacing dummy gate 20. The selective etching of ILD 90 over semiconductor structure 800 exposes the first S / D 50 at the bottom of FIG. 8 (e.g., first S / D 50 on X2-X2).

[0033] A portion of the ILD 90 can be removed from a portion of the semiconductor structure 800 using known etching processes, such as photolithography and reactive ion etching (RIE). Although FIG. 8 illustrates a portion of the ILD 90 removed from the pair of first S / Ds 50 illustrated on X2-X2 at the bottom of the semiconductor structure 800, in other examples, instead of removing the ILD 90 from the pair of first S / Ds 50, the ILD 90 can be selectively removed from the pair of second S / Ds 50 above the dummy gate 20 in FIG. 5. In these examples, when the ILD 90 is then selectively removed from the top of the semiconductor structure 800 to expose the pair of second S / Ds 50, a ReRAM device can be formed on the second S / Ds 50 in a later step (e.g., instead of on the first S / Ds 50).

[0034] 9 is an X1-X1 cross-sectional view illustrating a semiconductor structure 900 after ILD 90 deposition, dummy gate 20 replacement, and ILD 90 etching, in accordance with an exemplary embodiment of the present invention. As discussed above, the X1-X1 cross-section bisects the central portion of fin 4. As shown, FIG. 9 includes deposited ILD 90 covering a portion of gate stack 60 and oxide 3, fin 4 below gate stack 60 and above oxide 3. Oxide 3 is present over semiconductor substrate 2.

[0035] The ILD 90 layer can be composed of silicon dioxide, silicon nitride, or other ILD dielectric materials. The ILD 90 can be deposited over the semiconductor structure 800 using a suitable deposition process, such as CVD or ALD. Using a known dummy gate replacement process, CMP can be performed to planarize the semiconductor structure 800 after deposition of the ILD 90, exposing the top surface of the dummy gate 20, before selectively removing the dummy gate 20 and replacing it with the gate stack 60. The gate stack 60 can also include a gate electrode (not shown) overlying the gate dielectric material with spacers formed on the sides of the gate electrode. For example, the gate electrode in the gate stack 60 can be composed of a conductive material, such as doped polycrystalline or amorphous silicon, germanium, silicon germanium, a metal (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), hafnium (Hf), zirconium (Zr)), or other suitable gate electrode material. The gate dielectric material (not shown) may be a dielectric material or a high-k dielectric material, such as, but not limited to, oxide, nitride, oxynitride, silicate (e.g., metal silicate), aluminate, titanate, nitride, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, tantalum carbide (TaC), titanium carbide (TiC), or aluminum carbide (TiAlC). The gate stack 60 may be deposited by one or more of the following processes: CVD, PECVD, atomic layer deposition (ALD), or chemical deposition processes. The gate stack 60 may be deposited on a portion of the oxide 3 in place of the dummy gate 20.

[0036] After replacing dummy gate 20 with gate stack 60, another layer of ILD 90 can be deposited over semiconductor structure 800. The layer of ILD 90 covers the exposed surfaces of gate stack 60 and oxide 3 in Figure 9, as well as the first S / D 50 and second S / D 50, which are not shown in Figure 9. Portions of ILD 90 are selectively removed (as shown in Figure 10).

[0037] Figure 10 is a cross-sectional view of semiconductor structure 1000 taken along line X2-X2 after ILD 90 deposition and etching of ILD 90, in accordance with an exemplary embodiment of the present invention. As shown, Figure 10 includes ILD 90 over a portion of oxide 3, first S / D 50 over fin 4, fin 4 over a portion of oxide 3, and semiconductor substrate 2 below oxide 3. In some embodiments, oxide 3 is absent, and fin 4 and a portion of ILD 90 are present on semiconductor substrate 2.

[0038] Portions of the ILDs 90 can be selectively removed from the first S / Ds 50. As described above, each of the first S / Ds 50 is present in the X2-X2 cross section. Each of the first S / Ds 50 can cover the ends of two adjacent fins 4 (as shown in FIG. 5 ). The ILDs 90 can be selectively removed using known photolithography and etching processes suitable for selective removal of ILD material. The selective etching of the ILDs 90 can stop at the top surface of the oxide 3.

[0039] FIG. 11 is a cross-sectional view along line X1-X1 illustrating a semiconductor structure 1100 after deposition of a switching layer 110 and a top electrode 111, in accordance with an exemplary embodiment of the present invention. As shown, FIG. 11 includes the elements of FIG. 9 and the top electrode 111 on the switching layer 110, with an ILD 90 below the switching layer 110. Using a deposition process, such as ALD, a layer of metal oxide for the switching layer 110 can be conformally deposited over the ILD 90. Another deposition process, such as ALD or CVD, can deposit a layer of top electrode 111 over the switching layer 110. In various embodiments, the switching layer 110 is a high-k metal oxide. For example, the switching layer 110 can be a compound or alloy, such as hafnium and oxygen (HfO x ), tantalum and oxygen (e.g., TaO x ), titanium and oxygen (e.g., TiO x ) and other combinations thereof. The thickness of the switching layer 110 can be between 3 nm and 10 nm, but is not limited to these thicknesses. As shown in FIG. 11, the switching layer 110 is deposited over the ILD 90.

[0040] A layer of electrode material can be deposited over the switching layer 110 using known deposition methods, such as ALD or CVD, to form the top electrode 111. The top electrode 111 can be composed of, but is not limited to, a titanium-nickel (TiN) alloy, a titanium-nickel-aluminum alloy (TiN / Al), or a titanium-aluminum-containing alloy, such as a titanium-aluminum-carbon (TiAlC) alloy. The top electrode 111 can have a thickness of 3 nm to 10 nm, but is not limited to this thickness.

[0041] FIG. 12 is an X2-X2 cross-sectional view illustrating a semiconductor structure 1200 after deposition of a top electrode 111 over the switching layer 110, according to an exemplary embodiment of the present invention. As shown, FIG. 12 includes the elements of FIG. 10 and a top electrode 111 over the switching layer 110, where the switching layer 110 covers a portion of oxide 3, a remaining portion of ILD 90, and the first source / discharge 50. In one embodiment, a silicide is formed on the first source / discharge 50 prior to deposition of the switching layer 110. In the X2-X2 cross-sectional view, the switching layer 110 is deposited over the remaining portion of ILD 90, over the exposed portion of oxide 3, and on the first source / discharge 50 using the process described above with respect to FIG. 11. The top electrode 111 can be deposited over the switching layer 110 as described above with respect to FIG. 11.

[0042] Figure 13 is a cross-sectional view along line X1-X1 illustrating a semiconductor structure 1300 after deposition of a metal layer 116, in accordance with an exemplary embodiment of the present invention. As shown, Figure 13 includes the elements of Figure 11 and a metal layer 116 overlying the top electrode 111. Using a known deposition process, such as ALD, a layer of a low resistivity metal, such as tungsten (W), titanium nitride (TiN), aluminum-doped titanium nitride, or copper (Cu), is conformally deposited over the top electrode 111 in the semiconductor structure 1300.

[0043] FIG. 14 is a cross-sectional view taken along line X2-X2 illustrating a semiconductor structure 1400 after deposition of a metal layer 116, in accordance with an exemplary embodiment of the present invention. As shown, FIG. 14 includes a metal layer 116 covering the elements of FIG. 12 (e.g., switching layer 110, ILD 90, dummy gate 20, fin 4, oxide 3, and semiconductor substrate 2) and top electrode 111. The metal layer 116 can be conformally deposited over the top electrode 111, filling the opening or trench where ILD 90 was removed (e.g., as illustrated in FIG. 12). The metal layer 116 covers the top electrode 111 and fills the trench where ILD 90 was removed. The metal layer 116 can be deposited to a level higher than the top surface of the top electrode 111 on the remaining portions of the ILD 90.

[0044] 15 is a top view illustrating a semiconductor structure 1500 after formation of a plurality of contacts 115, in accordance with an exemplary embodiment of the present invention. As shown, FIG. 15 includes five contacts 115, ILD 90 surrounding four of the five contacts 115, ILD 90 surrounding a metal layer 116, and one of the five contacts 115 within the metal layer 116.

[0045] FIG. 15 illustrates the top surface of semiconductor structure 1500 after CMP, which removes the upper portion of ILD 90, the upper portion of top electrode 111, and the upper portion of switching layer 110 overlying ILD 90, and before forming multiple contacts 115.

[0046] The contacts 115 can be formed by known contact formation processes. For example, the contacts 115 can be formed by depositing another layer of ILD 90 and selectively etching the deposited ILD 90. Depositing a conductive material over the semiconductor structure 1500 can occur to form the contacts 115. For example, depositing the conductive material for the contacts 115 can occur using one of CVD, plasma-enhanced CVD, physical vapor deposition (PVD), plating, and electron beam evaporation, or by ALD. The conductive material fill for the contacts 115 can be a conductive metal, such as aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof.

[0047] A planarization process, such as CMP, is performed to remove any conductive material from the top surface of ILD 90. CMP can remove portions of the contact metal layer overlying ILD 90 to form contacts 115 in the remaining ILD 90 and remaining metal layer 116. After contacts 115 are formed, additional layers of ILD 90 can be deposited, and standard back-end-of-the-line (BEOL) processes can be used to form vias and lines for interlevel metal layers of the semiconductor chip and contact pads (not shown) of external semiconductor chips.

[0048] FIG. 15 also shows the location of the X1-X1 cross section, which is later shown in FIG. 16. The X1-X1 cross section covers a central portion of semiconductor structure 1500 through two of the plurality of contacts 115. FIG. 15 also shows the location of the X2-X2 cross section, which is a bottom portion of semiconductor structure 1500, which is later shown in FIG. 17. In addition, FIG. 15 shows the location of the MM cross section through two of the plurality of contacts 115 at the top of semiconductor structure 1500, which is later shown in FIG. 18.

[0049] The two upper contacts 115 located along the MM line can provide electrical connection to a pair of second S / Ds 50 (shown in FIG. 5) on each of the fins 4 in the two FinFET transistors, as later shown in FIG. 16 . The two contacts 115 located along the X1-X1 line can provide electrical connection to each of the gate stacks 60 (shown in FIG. 17 ). The contacts 115 shown on the X2-X2 line, surrounded by a metal layer 116, can provide electrical connection to two ReRAM devices (shown in FIG. 18 ) on the two FinFET transistors (e.g., the contacts 115 are in direct contact with the metal layer 116 connecting the two ReRAMs formed by the top electrode 111 and the switching layer 110 on the first S / Ds 50). In some embodiments, the semiconductor structures 1500, 1600, 1700, and 1800 can be formed without the oxide 3.

[0050] 16 is a cross-sectional view of a semiconductor structure 1600 taken along line M-M after CMP and after formation of a plurality of contacts 115, in accordance with an exemplary embodiment of the present invention. As shown, FIG. 16 includes a plurality of contacts 115 overlying each second source / drain 50 overlying a fin 4.

[0051] As described above with reference to FIG. 15 , a pair of contacts 115 are each formed over one of the second S / Ds 50 using known contact formation processes (e.g., one or more CMP processes, ILD 90 deposition, selective ILD 90 etching, contact metal layer deposition, and another CMP to remove the metal of the contacts 115 overlying the ILD 90). The contacts 115 provide electrical connection to the second S / Ds 50 on the end of each of the fins 4 (e.g., the second S / D 50 is on the end of the fin 4 that is above the dummy gate 20 in FIG. 5 ). Each of the contacts 115 illustrated in FIG. 16 provides electrical connection to one of the fins 4 of two adjacent transistors (e.g., FinFETs). The contacts 115 in FIG. 16 provide electrical connection through the second S / Ds 50 to each of the FinFETs formed on the oxide 3. In some embodiments, when oxide 3 is not present, contacts 115 provide connections to two FinFETs formed on semiconductor substrate 2 .

[0052] 17 is an X1-X1 cross-sectional view illustrating a semiconductor structure 1700 after CMP and after the formation of contacts 115, in accordance with an exemplary embodiment of the present invention. As shown, FIG. 17 includes a pair of contacts 115, with each contact overlying one of the gate stacks 60. While each of the fins 4 is shown below one of the gate stacks 60, an oxide 3 may be present below each of the fins 4 and below the gate stacks 60. A semiconductor substrate 2 is present below the oxide 3.

[0053] The CMP removes an upper portion of metal layer 116, a portion of top electrode 111, an upper portion of switching layer 110, and an upper portion of ILD 90. As described above with respect to FIG. 15 , using known contact formation processes (e.g., CMP, ILD deposition, selective ILD etch, contact metal deposition, and another CMP), a plurality of contacts 115 can be formed over each of a pair of gate stacks 60. The plurality of contacts 115 illustrated in FIG. 17 provide electrical connection to the gate stacks 60 in each of the FinFETs formed over fin 4.

[0054] FIG. 18 is a cross-sectional view taken along line X2-X2 illustrating a semiconductor structure 1800 after CMP and formation of a plurality of contacts 115, according to an exemplary embodiment of the invention. As shown, FIG. 18 includes a metal layer 116 below and surrounding one of the plurality of contacts 115, a top electrode 111 surrounded by the metal layer 116 (e.g., the top electrode 111 below the metal layer 116 and approximately abutting a vertical side of the metal layer 116), a switching layer 110 below the top electrode 111, and an ILD 90 outside the vertical side of the switching layer 110. Oxide 3 may be below the bottom of the switching layer 110, below fin 4, and under a portion of ILD 90. 1 may be below oxide 3. In some embodiments, oxide 3 is not present, and semiconductor substrate 2 is below fin 4, under a portion of the switching layer 110, and under a portion of ILD 90.

[0055] CMP removes the top of metal layer 116, a portion of top electrode 111 over the remaining portion of ILD 90, the top of switching layer 110 below the removed portion of top electrode 111, and the top of the remaining ILD 90. Using the process described above in FIG. 15 (e.g., CMP, ILD deposition, selective ILD etch, metal layer deposition, and another CMP), one of a plurality of contacts 115 is formed in metal layer 116. As shown in FIG. 18 , the plurality of contacts 115 can provide electrical connection to two ReRAM devices through metal layer 116, where each of the ReRAM devices on each of the first S / Ds 50 can be constructed using the first S / D 50 over the switching layer 110, top electrode 111, and fin 4 as a bottom electrode.

[0056] The semiconductor structure 1800 includes a metal layer 116 connecting two ReRAM devices. Each ReRAM device surrounds one of a pair of first S / Ds 50 on two adjacent fins 4 of two adjacent transistor devices (e.g., FinFETs). As described above, the two ReRAM devices of the semiconductor structure 1800, consisting of the switching layer 110 and top electrode 111 on the first S / Ds 50 of the two adjacent FinFETs, can form a current-conducting filament associated with the faceted epitaxy points of the first S / Ds 50 during semiconductor device operation.

[0057] The ReRAM devices on the first S / D 50 can be composed of a metal oxide (e.g., switching layer 110) between a top electrode 111 and a bottom electrode (e.g., first S / D 50). The pointed end of the bottom electrode (i.e., the bottom electrode of the first S / D 50) provides a higher electric field that promotes the formation of a current-conducting filament in the switching layer 110. The use of the pointed end of the faceted, diamond-shaped epitaxy that forms the first S / D 50 enhances the electric field and localizes or positions the current-conducting filament within the switching layer 110 for each of the two ReRAM devices. The two ReRAM devices on different first S / Ds 50 (e.g., on one of the two fins 4) face each other and are electrically connected by a metal layer 116. In another embodiment, two ReRAM devices are each formed on one of the first S / Ds 50 on one end of each of the fins 4 above the gate stack 60. In this case, each of the second S / Ds 50 on the other end of each of the fins 4 below the gate stack 60 provides conventional connections to other devices within the semiconductor chip.

[0058] Each of the two ReRAM devices is unipolar. For example, one ReRAM device in a pair of ReRAM devices is on a first FinFET transistor and can represent a positive value, while the other ReRAM device on a second FinFET transistor can represent a negative value. In other words, one unipolar ReRAM of the pair of ReRAMs can be used as a reference cell, and the second unipolar ReRAM can be used for weight update. In training a deep neural network, differential weights can represent both positive and negative values. In this way, the two ReRAM devices illustrated in the semiconductor structure 1800, electrically connected by the metal layer 116 and located on two adjacent fins 4, can provide differential weights of positive and negative values. The method of forming two ReRAM devices on the fins of two adjacent FinFETs enables a densely scaled device architecture that provides two transistors with two ReRAM devices. The use of this tightly scaled two transistor / two ReRAM architecture improves the ability to train deep neural networks (e.g., using two unipolar ReRAMs to provide differential weights).

[0059] 19 is a cross-sectional view of a semiconductor structure 1900 taken along line X1-X1 after source / drain formation according to one embodiment of the present invention. A second embodiment of the present invention provides another method for forming two ReRAM devices on two transistors (FinFETs). The method for forming two ReRAM devices in the second embodiment begins using the same process and semiconductor structure formed as illustrated in FIGS.

[0060] Semiconductor structure 1900 is essentially the same as semiconductor structure 600 illustrated in FIG. 6 and can be formed by the same semiconductor processes described with respect to FIGS. 1-6. As shown, FIG. 19 includes a dummy gate 20 covering each fin of a pair of fins 4, with an oxide 3 underlying the fins 4 and below the bottom surface of each of the dummy gates 20. The oxide 3 can cover the semiconductor substrate 2. In some embodiments, the oxide 3 is not present as illustrated in FIG. 1B.

[0061] Figure 20 is a cross-sectional view taken along line X2-X2 showing a semiconductor structure 2000 after source / drain formation, according to one embodiment of the present invention. The semiconductor structure 2000 is essentially the same as the semiconductor structure 700 described in Figure 7 and can be formed by the same semiconductor processes described with respect to Figures 1-7. As shown, Figure 20 includes a pair of first S / Ds 50. In some embodiments, oxide 3 is not present.

[0062] As described above with reference to FIG. 7 , faceted epitaxy forms a pair of first S / Ds 50, where the faceted epitaxy forms sharp tips or points in the first S / Ds 50. The faceted source / drain material can be grown over the ends of the fins 4, overlying each of the fins 4 to form a diamond-shaped structure of the first S / Ds 50. As described above, doping of each of the source / drains can occur, where the doping for all of the source / drains (e.g., each of the first S / Ds 50 and second S / Ds 50 illustrated in FIG. 5 ) can be the same type of dopant and provide the same doping level. As described above, forming the faceted first S / Ds 50 using a faceted epitaxial growth process produces pointed or conical features in the diamond-shaped first S / Ds 50. The sharp features or points of the diamond epitaxy that form each of the pair of first S / Ds 50 can enhance the electric field at the tips or points of each of the pair of first S / Ds 50 to control the formation or location of current-conducting filaments in the two ReRAM devices that are later formed in FIG. 25.

[0063] FIG. 21 is a cross-sectional view along line X1-X1 illustrating a semiconductor structure 2100 after replacing dummy gate 20 with gate stack 60, after depositing ILD 90, and after selective etching of a portion of ILD 90, in accordance with one embodiment of the present invention. As shown, FIG. 21 includes ILD 90 covering gate stack 60 and a portion of oxide 3 covering semiconductor substrate 2. Fin 4 is below gate stack 60 and above the portion of oxide 3. Semiconductor structure 2100 is essentially the same as semiconductor structure 900 illustrated in FIG. 9. The method of forming semiconductor structure 2100 is essentially the same as the method of forming semiconductor structure 900 previously described in detail with respect to FIG. 9.

[0064] 22 is a cross-sectional view along line X2-X2 illustrating a semiconductor structure 2200 after deposition of ILD 90, replacement of dummy gate 20 with gate stack 60, and selective etching of a portion of ILD 90, in accordance with one embodiment of the present invention. As shown, FIG. 22 includes a portion of ILD 90 covering a portion of each of a pair of first S / Ds 50 and covering a portion of oxide 3, where a middle portion of oxide 3 is exposed and a portion of each of the pair of first S / Ds 50 is exposed. Fin 4 can be on the portion of oxide 3 that may be covering semiconductor substrate 2.

[0065] The deposition of the layer of ILD 90 and the replacement of the dummy gate 20 with the gate stack 60 can occur with the same materials and processes as described with reference to FIG. 10 , except that a smaller portion of the ILD 90 is removed in FIG. 22 than in FIG. 10 . The selective etching of the ILD 90 is similar to the selective etching of the semiconductor structure 1000, except that the portion of the ILD 90 removed in the semiconductor structure 2200 is smaller than the portion of the ILD 90 removed in the semiconductor structure 1000. As illustrated in FIG. 22 , the ILD 90 is removed from approximately half of the first S / D 50 from each opposing side of the first S / D 50. Etching the ILD 90 removes portions of the ILD 90 on adjacent or opposing sides of the first S / D 50. After etching, substantially the ILD 90 remains on the outer surface of the first S / D 50 (e.g., the ILD 90 remains on the opposite or outer-facing side of the first S / D 50). In other words, the ILD 90 remains on approximately half of the first S / D 50. For example, as illustrated in semiconductor structure 2200, etching the ILD 90 can remove the ILD 90 from approximately the pointed top end of the diamond shape of one of the pair of first S / Ds 50 to the pointed top end of the other of the pair of first S / Ds 50.

[0066] FIG. 23 is a cross-sectional view along line X1-X1 illustrating a semiconductor structure 2300 after deposition of a switching layer 110 and a top electrode material 111, according to one embodiment of the present invention. As shown, FIG. 22 includes the elements of FIG. 21 and a top electrode 111 overlying the switching layer 110, where the switching layer 110 is deposited over the ILD 90 of the semiconductor structure 2200. The deposition process, materials, and thicknesses of the switching layer 110 and top electrode 111 are essentially the same processes and materials as described in detail with reference to FIG. 13. As shown, FIG. 23 includes the top electrode 111 deposited over the switching layer 110 and the switching layer 110 deposited over the ILD 90 in the semiconductor structure 2200 (e.g., a semiconductor structure 2200 having an ILD 90 overlying the gate stack 60 and an oxide 3 overlying the semiconductor substrate 2). However, as discussed above, in some embodiments, the oxide 3 is not present.

[0067] Figure 24 is a cross-sectional view along line X2-X2 illustrating a semiconductor structure 2400 after deposition of a switching layer 110 and a top electrode material 111, in accordance with one embodiment of the present invention. As shown, Figure 24 includes the elements of Figure 22 and a top electrode 111 deposited over the switching layer 110. The top electrode 111 can be deposited over the switching layer 110 using the processes and materials described in detail above with reference to Figure 11.

[0068] 24, however, the switching layer 110 may be deposited over approximately half of each of the first S / Ds 50, over exposed portions of the ILD 90, and over exposed portions of the oxide 3. For example, using ALD, the switching layer 110 is deposited on exposed adjacent, opposing surfaces of the first S / Ds 50. The switching layer 110 can also be deposited over exposed portions of the oxide 3 between a pair of first S / Ds 50 and over exposed surfaces of the ILD 90. Unlike the semiconductor structure 1100 illustrated in FIG. 11, the switching layer 110 is not deposited on the outer or opposing sides or surfaces of the first S / Ds 50. In other words, the switching layer 110 is deposited over approximately half of each of the first S / Ds 50.

[0069] 11 and 12, deposition of the top electrode 111 can occur on the switching layer 110. Like the switching layer 110, the top electrode 111 is deposited on an adjacent or opposite side of the first S / D 50, but not on the outward facing surface or side opposite the first SD 50.

[0070] 25 is an X2-X2 cross-sectional view illustrating a semiconductor structure 2500 after CMP, depositing a metal layer 116, and forming a plurality of contacts 115, according to one embodiment of the present invention. As shown, FIG. 25 includes one of the plurality of contacts 115 in the metal layer 116, where the metal layer 116 is surrounded by a top electrode 111 and the switching layer 110 is below the top electrode 111. The metal layer 116 is deposited between adjacent opposing sides of the first S / D 50 that electrically connects a first ReRAM on the first S / D 50 on the left-most fin of Fin 4 (e.g., on the left-most FinFET) to a second ReRAM on the first S / D 50 on the right-most fin of Fin 4 (e.g., on the right-most FinFET). The ILD 90 can cover a portion of the oxide 3 on the semiconductor substrate 2 and surround the exposed portion of the switching layer 110 and the outer exposed portions of each S / D 50 (e.g., exposed surfaces of the S / Ds 50 facing outward and away from each other). In some embodiments, the oxide 3 is not present.

[0071] Formation of the contacts of the plurality of contacts 115 in the metal layer 116 occurs using known processes and materials described above with reference to FIG. 15 (e.g., ILD deposition, CMP, selective metal layer 116, etch, contact metal deposition, followed by CMP to remove the metal layer 116 overlying the ILD 90).

[0072] As shown, each of the two ReRAM devices can be composed of a switching layer 110 and a top electrode 111 using the first S / D 50 as a bottom electrode, where each of the two ReRAM devices is on adjacent, opposite sides of the first S / D 50 on each fin of the multiple fins 4. The ReRAM device formed with the top electrode 111 and switching layer 110 on the first S / D 50 does not surround the first S / D 50 as in the ReRAM device illustrated in FIG. 18. The two electrically connected ReRAM devices in FIG. 25 can be formed on opposite sides of the two first S / Ds 50, thus covering approximately half of each of the two first S / Ds 50. Two adjacent fins 4 each form a ReRAM and a FinFET with adjacent surfaces of the first S / D 50.

[0073] As shown in FIG. 25, in contrast to the ReRAM device formed in FIG. 18, the ReRAM device can be formed inside or on the opposite side of a portion of the first S / D 50, where the ReRAM device consisting of the top electrode 111 and the switching layer 110 extends on both sides of the first S / D 50 (e.g., covers all sides of the first S / D 50).

[0074] As described above, one ReRAM device of a pair of ReRAM devices can be used as a reference cell and the other ReRAM device can be used for weight updating. In this way, each unipolar ReRAM device can provide linear switching for differential weights (e.g., required to improve training of deep neural networks).

[0075] Although not shown, the X1-X1 and MM cross sections of the formed semiconductor structure after depositing metal layer 116 and forming the plurality of contacts 115, as well as the X1-X1 cross section through gate stack 60, will be the same as semiconductor structure 1700 shown in Figure 17, and the MM cross section through the other pair of second S / Ds 50 will be the same as semiconductor structure 1600 of Figure 16. As discussed above, in some embodiments, oxide 3 is not present in Figure 25, or is not present in the X1-X1 cross sections, X2-X2 cross sections, and MM cross sections associated with semiconductor structures formed using the processes illustrated in Figures 19-25.

[0076] While the present application has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the above and other changes in form and detail may be made therein without departing from the spirit and scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.

Claims

1. 1. A semiconductor structure, comprising: two adjacent fins on a substrate; a gate stack on each of the two adjacent fins; a first source / drain on a first end of each fin of the two adjacent fins, and a second source / drain on a second end of each fin of the two adjacent fins; a switching layer on at least the first source / drain on the first end of each fin of the two adjacent fins; a top electrode on the switching layer; and the metal material covering the upper electrode It is equipped with the top electrode on the switching layer over the first source / drain on a first fin of the two adjacent fins, the switching layer over the first source / drain on the first fin of the two adjacent fins, and the one first source / drain on the first fin of the two adjacent fins form a first resistive random access memory device on a first transistor; the top electrode on the switching layer on the first source / drain on a second fin of the two adjacent fins, the switching layer on the first source / drain on the second fin of the two adjacent fins, and the first source / drain on the second fin of the two adjacent fins form a second resistive random access memory device on a second transistor; the first resistive random access memory device is electrically connected to the second resistive random access memory device by the metal material covering the top electrode; The semiconductor structure.

2. 2. The semiconductor structure of claim 1 , wherein the first source / drain on the first end of each fin of the two adjacent fins and the second source / drain on the second end of each fin of the two adjacent fins have a diamond shape with pointed ends.

3. 3. The semiconductor structure of claim 2, wherein one or more points forming said first source / drain indicate a location of a current-conducting filament in said switching layer on at least said first source / drain on said first end of each fin of said two adjacent fins.

4. 10. The semiconductor structure of claim 1 , wherein said first resistive random access memory device on said first fin of said first transistor represents a positive value, and said second resistive random access memory device on said second fin of said second transistor represents a negative value.

5. 5. The semiconductor structure of claim 4, wherein the first resistive random access memory device on the first fin of a first transistor represents a positive value and the second resistive random access memory device on the second fin of the second transistor represents a negative value, and wherein differential weights represent both positive and negative values for training a deep neural network.

6. 1. A semiconductor structure, comprising: two adjacent fins on a substrate; a first source / drain on a first end of each fin of the two adjacent fins, and a second source / drain on a second end of each fin of the two adjacent fins; a switching layer on at least one side of the first source / drain on the first end of each fin of the two adjacent fins; a top electrode on the switching layer; a metal material covering the upper electrode; and Contacts in the metallic material It is equipped with the switching layer on the at least one side of the first source / drain on the first end of each fin of the two adjacent fins is on a part of an oxide layer between the two adjacent fins, on opposite sides of each of the first source / drain on each end of each fin of the two adjacent fins, and on a part of an interlayer insulating film above the first source / drain; The semiconductor structure.

7. 7. The semiconductor structure of claim 6, wherein said at least one side of said first source / drain on said first end of each fin of said two adjacent fins is adjacent opposite sides of each of said first source / drain on said first end of each fin of said two adjacent fins.

8. 7. The semiconductor structure of claim 6, wherein said switching layer on said at least one side of said first source / drain on said first end of each fin of said two adjacent fins and said top electrode on said switching layer form a pair of resistive random access devices.

9. 1. A method of forming a pair of resistive random access devices on a pair of adjacent fins, comprising: depositing a gate over a portion of each of the pair of adjacent fins and over a first portion of the oxide layer; forming a source / drain on each end of each fin of the pair of adjacent fins; depositing a first layer of interlayer dielectric material; selectively etching a portion of a first layer of interlayer dielectric material covering at least a pair of first source / drains on a first end of each fin of the pair of adjacent fins; depositing a layer of switching material over the first layer of interlayer dielectric, over the exposed portion of the oxide layer, and over the first source / drain pair; depositing a top electrode material overlying the layer of switching material; and depositing a first metal layer overlying the top electrode material; The method comprising:

10. depositing at least a second interlayer dielectric material; selectively etching one or more portions of the second interlayer dielectric material; depositing a contact material; and forming more than one contact via, wherein one contact via of the more than one contact via is within a portion of the first metal layer; The method of claim 9 further comprising:

11. 10. The method of claim 9, wherein forming a source / drain on each end of each fin of the pair of adjacent fins includes forming each of the source / drains with faceted epitaxy to form a diamond facet shape having points at each of the source / drains on each end of each of the pair of adjacent fins.

12. The facet epitaxy is <111> 12. The method of claim 11, comprising forming the diamond facet shape using lattice plane boundary epitaxy.

13. 10. The method of claim 9, wherein forming the source / drains on opposite ends of each of the pair of adjacent fins comprises doping each of the source / drains at each end of each fin of the pair of adjacent fins with the same type of dopant and the same level of dopant.

14. 12. The method of claim 11, wherein the points at each of the source / drains on both ends of each of the pair of adjacent fins enhance an electric field at a tip of the points at each of a first pair of source / drains on the first end of each fin of the pair of adjacent fins to form a current-conducting filament within a portion of a switching layer overlying the points at each of the first source / drain pairs.

15. 10. The method of claim 9, wherein the switching material overlying the pair of first source / drains, the top electrode material overlying the layer of switching material, and the pair of first source / drains on the first end of each fin of the pair of adjacent fins form two resistive random access devices on the two adjacent fins electrically connected by the first metal layer.

Images