Imaging device and control method thereof

Abstract

To provide an imaging apparatus that enables both high image quality and high readout speed by selecting an AD (analog-to-digital) conversion method suitable for a mode according to an operating condition.SOLUTION: An imaging device 12 provided in an imaging apparatus 1 includes an AD conversion circuit that performs AD conversion of pixel signals by comparing pixel signals output from multiple pixels with a slope voltage whose potential changes over time. A synchronization control unit 15 selects a first mode or a second mode according to the driving mode of the imaging device 12. In the first mode, AD conversion of the pixel signal is performed by selecting one slope voltage from a plurality of slope voltages, and, in the second mode, AD conversion of the pixel signal is performed by comparing the predetermined slope voltage and the pixel signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a technique for analog-to-digital conversion processing in an imaging device. [Background technology]

[0002] As CMOS (complementary metal-oxide semiconductor) image sensors installed in imaging devices become more pixel-rich and faster, a method that can read out pixel signals at higher speeds is required. One method for high-speed readout of pixel signals is to place an analog-to-digital conversion (hereinafter referred to as "AD conversion") circuit section on each column within the imaging element and output the digital signal. In the following, the AD conversion circuit section will be abbreviated as "ADC."

[0003] Patent Document 1 discloses a slope-based column AD conversion method using a comparator and a counter. While an analog pixel signal is input to one input terminal of the comparator, a slope voltage that varies with time as a reference signal is input to the other input terminal. The output of the comparator inverts when the magnitude relationship between the pixel signal and the reference signal inverts. The counter counts over time, and stops counting when the comparator output inverts. When the counting stops, the output of the counter indicates the digital value of the analog pixel signal.

[0004] Furthermore, faster readout is possible by switching between a low-bit resolution ADC and a high-bit resolution ADC depending on the signal output. For large-amplitude signals, all that is required is a resolution sufficient to ensure the S / N ratio (signal-to-noise ratio), so the selection circuit within the ADC selects a slope voltage with a large inclination during AD conversion of large-amplitude signals, resulting in low-bit resolution AD conversion. On the other hand, for AD conversion of small-amplitude signals, a slope voltage with a small inclination is selected, resulting in high-bit resolution AD conversion. In other words, this is a dual-slope system, which makes it possible to shorten the AD conversion time for large-amplitude signals. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-9087 Summary of the Invention [Problem to be solved by the invention]

[0006] However, although the dual slope method is excellent for increasing speed, the effect of increasing speed may not be obtained depending on the time required for AD conversion of pixel signals and the time required for transferring the pixel signals converted into digital signals. For example, if it takes a long time to transfer the AD converted pixel signals, the effect of increasing speed using the dual slope method cannot be obtained.

[0007] Additionally, dual-slope AD conversion can pose a problem of gradation differences that occur when combining results converted at different resolutions. The difference in gradation is more pronounced when the AD conversion resolution is low.

[0008] An object of the present invention is to provide an imaging device that can achieve both high image quality and high readout speed by selecting an AD conversion method that is suited to a mode according to operating conditions. [Means for solving the problem]

[0009] An imaging device according to an embodiment of the present invention includes a conversion unit that converts pixel signals output from a plurality of pixels of an image sensor into digital signals by comparing the pixel signals with a slope voltage whose potential changes over time, and a control unit that controls the conversion unit in a plurality of modes corresponding to operating conditions for reading out the pixel signals. In a first mode, the control unit controls the conversion of the pixel signals by the conversion unit by comparing the pixel signals with a slope voltage selected from a plurality of slope voltages, and in a second mode, controls the conversion of the pixel signals by the conversion unit by comparing the pixel signals with a predetermined slope voltage, and selects the first or second mode by comparing a first period from reading out the pixel signals of the image sensor to conversion by the conversion unit with a second period required for transferring the image signals converted by the conversion unit. [Effects of the Invention]

[0010] According to the present invention, an imaging device can be provided that can achieve both high image quality and high readout speed by selecting an AD conversion method that is suitable for a mode according to operating conditions. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a block diagram showing a configuration of an imaging apparatus according to an embodiment of the present invention. [Figure 2] FIG. 2 is a block diagram showing the configuration of an imaging element according to the present embodiment. [Figure 3] FIG. 2 is a circuit diagram showing a circuit configuration of a pixel according to the present embodiment. [Figure 4] FIG. 2 is a diagram illustrating a circuit configuration of a column signal processing unit according to the present embodiment. [Figure 5] 10 is a timing chart in a multiple slope AD conversion mode. [Figure 6] 10 is a timing chart in a single-slope AD conversion mode. [Figure 7] 4 is a flowchart illustrating the operation of the first embodiment. [Figure 8]10 is a flowchart illustrating the operation of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Fig. 1 is a block diagram showing the configuration of an imaging device according to the present invention. The imaging device 1 is a digital still camera, a digital video camera, or the like. The imaging device 1 includes an imaging optical system 11, an imaging element 12, a signal processing unit 13, a compression / decompression unit 14, a synchronization control unit 15, an operation unit 16, an image display unit 17, and an image recording unit 18.

[0013] The imaging optical system 11 includes a lens, a lens driving mechanism, a mechanical shutter mechanism, an aperture mechanism, etc. Among these, the movable parts are driven based on control signals from the synchronization control unit 15.

[0014] The imaging element 12 is an XY address type CMOS image sensor, and performs imaging operations in response to control signals from the synchronization control unit 15. The imaging element 12 outputs image signals digitized by an internal AD conversion circuit unit to the signal processing unit 13. The configuration of the imaging element 12 will be described in detail later.

[0015] The signal processing unit 13, under the control of the synchronization control unit 15, performs signal processing on the digitized image signal input from the image sensor 12 and acquires control information such as AF (Auto Focus) and AE (Auto Exposure). The signal processing unit 13 outputs the processed image signal and the control information to the synchronization control unit 15.

[0016] The compression / decompression unit 14 operates under the control of the synchronization control unit 15, and performs compression / encoding processing of image signals as well as decompression / decoding processing of encoded data of still images. The compression / decompression unit 14 may also perform compression / encoding / decompression / decoding processing of moving images.

[0017] The synchronization control unit 15 is a microcontroller including, for example, a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), etc. The synchronization control unit 15 comprehensively controls each unit of the imaging device 1 by executing a program stored in the ROM, etc.

[0018] The operation unit 16 is composed of various operation members such as a shutter release button, etc. The operation unit 16 outputs an operation instruction signal according to an input operation by the user to the synchronization control unit 15. The synchronization control unit 15 controls each unit according to the operation instruction signal.

[0019] The image display unit 17 has a display device such as an LCD (Liquid Crystal Display) and displays an image according to an image signal. The image recording unit 18 has, for example, a portable recording medium and records the compressed and encoded image data file on the recording medium.

[0020] Next, the basic operation of the imaging device 1 will be described. Before capturing a still image, image signals output from the imaging element 12 are sequentially supplied to the signal processing unit 13. The signal processing unit 13 performs signal processing on the image signal from the imaging element 12 and supplies it to the image display unit 17 via the synchronization control unit 15 as a camera-through image signal. The image display unit 17 displays the camera-through image, allowing the user to adjust the angle of view by looking at the displayed image. When the shutter release button included in the operation unit 16 is pressed, one frame's worth of image signals from the imaging element 12 are taken into the signal processing unit 13 under the control of the synchronization control unit 15.

[0021] The signal processing unit 13 performs signal processing on the captured image signal for one frame, and supplies the processed image signal to the compression / expansion unit 14. The compression / expansion unit 14 compresses and encodes the input image signal. The generated encoded data is supplied to the image recording unit 18 via the synchronization control unit 15. A data file of the captured still image is recorded in the image recording unit 18.

[0022] On the other hand, when playing back a data file of a still image recorded in the image recording unit 18, the synchronization control unit 15 reads the selected data file from the image recording unit 18 in response to an operation input by the user using the operation unit 16. The compression / decompression unit 14 executes a data decompression / decoding process. The decoded image signal is supplied to the image display unit 17 via the synchronization control unit 15, and the still image is played back and displayed.

[0023] When recording moving images, the compression / decompression unit 14 performs compression / encoding processing on the image signals sequentially processed by the signal processing unit 13. The generated encoded data of the moving images is sequentially transferred to the image recording unit 18 for recording processing. When playing back moving images, the moving image data file is read from the image recording unit 18 and the compression / decompression unit 14 performs decompression / decoding processing. The processed data is supplied to the image display unit 17, where the moving images are displayed.

[0024] The configuration of the image sensor 12 will be described with reference to Fig. 2. Fig. 2 is a block diagram showing a schematic configuration of the image sensor 12. The image sensor 12 includes a pixel region 201 consisting of a plurality of pixels 200, a vertical scanning unit 202, a plurality of column signal processing units 203, a slope voltage generating unit 204, a horizontal scanning unit 205, a DSP 206, and a timing unit 207. DSP is an abbreviation for "Digital Signal Processor." The following description will be given assuming a pixel array with n × m pixels.

[0025] The pixel region 201 is made up of a plurality of pixels 200, which are arranged in a matrix in the horizontal and vertical directions as indicated by P11 to Pnm (n and m are natural number variables). The pixels in the first row are denoted as P11 to P1m, and the pixels in the nth row are denoted as Pn1 to Pnm. The plurality of pixels 200 are also assumed to be arranged with color filters in a 2x2 array, with R (red) filters and G (green) filters repeated in odd-numbered rows and G (green) filters and B (blue) filters repeated in even-numbered rows.

[0026] The vertical scanning unit 202 selects the pixel array in the pixel region 201 row by row and controls the drive of the reset operation and readout operation of the selected pixel row. Pixel control lines 211 are connected to each pixel in each pixel row, and transmit drive control signals from the vertical scanning unit 202 for each row. Vertical signal lines 212 are connected to each pixel in each pixel column. Pixel signals of the row selected by the pixel control lines 211 are read out to the corresponding vertical signal lines 212.

[0027] The slope voltage generating unit 204 generates slope voltages used for AD conversion performed by the multiple column signal processing units 203. The slope voltage is a ramp-shaped voltage whose potential changes over time. In other words, the slope voltage generating unit 204 generates slope voltages whose potential changes at a constant rate over time, and can simultaneously generate slope voltages with different slopes in multiple patterns. The slope voltage generating unit 204 also generates a reference voltage VREF.

[0028] The plurality of column signal processing units 203 are provided for the respective corresponding vertical signal lines 212, and perform signal processing, which will be described later, on each of the pixel signals in row units sent through the vertical signal lines 212, based on a slope voltage.

[0029] The horizontal scanning unit 205 selects a column signal processing unit 203 for each column via a plurality of column selection lines 213, and transfers the stored pixel signals to a horizontal output line 214. The DSP 206 performs signal processing on the image signals transferred from the horizontal output line 214 and outputs the processed image signals to the external signal processing unit 13. The timing unit 207 outputs various clock signals, control signals, and the like required for the operation of each unit of the image sensor 12, based on control signals from the synchronization control unit 15. Control lines 215 to 219 are control lines that transmit clock signals, control signals, and the like from the timing unit 207 to the vertical scanning unit 202, column signal processing unit 203, slope voltage generating unit 204, horizontal scanning unit 205, and DSP 206, respectively.

[0030] 3 is a diagram showing the circuit configuration of a pixel 200 of the image sensor 12. The pixel 200 enclosed in a dotted rectangular frame is shown as a representative one of the pixels constituting a pixel region 201. The pixel 200 is connected to other circuits by a pixel control line 211 and a vertical signal line 212. In this embodiment, the description will be given assuming that the P11 pixel is connected to the vertical signal line 212.

[0031] The vertical signal lines 212 are connected to a load circuit (see Tlod) and the column signal processing unit 203, and are also connected in common to a vertical pixel column to output signals from the pixels 200. The pixel control lines 211 are connected to the vertical scanning unit 202, and are also connected in common to one horizontal row of pixels. By simultaneously controlling one horizontal row of pixels, resetting and signal readout are possible. In FIG. 3, the pixel control lines 211 are collectively shown as a reset control line PRES, a transfer control line PTX, and a vertical selection line PSEL.

[0032] The photoelectric conversion element (referred to as D1) is a photodiode (also called PD) that converts light into an electric charge and stores the converted electric charge. The photoelectric conversion element D1 has a P-side (anode) of a PN junction connected to GND (ground) and an N-side (cathode) of the PN junction connected to the source of the transfer transistor T1.

[0033] The transfer transistor T1 functions as a transfer switch element. The transfer transistor T1 has a gate connected to a transfer control line PTX and a drain connected to a floating diffusion (hereinafter abbreviated as FD) capacitance Cfd. The transfer transistor T1 controls the charge transfer from the photoelectric conversion element D1 to the FD capacitance Cfd. One terminal of the FD capacitance Cfd is connected to GND (ground) and converts the charge transferred from the photoelectric conversion element D1 into a voltage. Hereinafter, the connection point between the drain of the transfer transistor T1 and the FD capacitance Cfd will be referred to as the FD node 301.

[0034] The reset transistor T2 functions as a reset switch element. The reset transistor T2 has a gate connected to a reset control line PRES, a drain connected to a terminal of a power supply voltage VDD, and a source connected to the FD node 301, and resets the potential of the FD node 301 to the power supply voltage VDD.

[0035] The driving transistor Tdrv is a transistor that constitutes an in-pixel amplifier. The driving transistor Tdrv has a gate connected to the FD node 301, a drain connected to a terminal for the power supply voltage VDD, and a source connected to the drain of the selection transistor T3, and outputs a voltage according to the voltage of the FD capacitance Cfd.

[0036] The selection transistor T3 functions as a selection switch element. The selection transistor T3 has a gate connected to a vertical selection line PSEL and a source connected to a vertical signal line 212, and outputs the output of the drive transistor Tdrv to the vertical signal line 212 as an output signal of the pixel 200.

[0037] The load circuit provided for each vertical signal line 212 is composed of a load transistor Tlod. The source and gate of the load transistor Tlod are grounded, and the drain is connected to the vertical signal line 212. The load transistor Tlod, together with the drive transistor Tdrv of the pixel 200 in the column connected by the vertical signal line 212, constitutes a source follower circuit that serves as an in-pixel amplifier. When a signal from the pixel 200 is output, the load transistor Tlod operates as a constant current source with its gate grounded.

[0038] The transistors other than the drive transistor Tdrv and the load transistor Tlod act as switching elements, turning on when the signal level of the control line connected to the gate is high and turning off when the signal level is low.

[0039] 4 is a diagram showing the circuit configuration of the column signal processing unit 203 of the image sensor 12. In the column signal processing unit 203, the image signal output from the vertical signal line 212 is input to an amplifier 401. The amplifier 401 amplifies the image signal from the vertical signal line 212. A switch 402 is connected to the output terminal of the amplifier 401, and a capacitor 403 is connected to the switch 402. The on / off state of the switch 402 is determined by a control signal PSH. The capacitor 403 is used to hold an image signal voltage. Writing of the signal voltage to the capacitor 403 is controlled by the switch 402, which is turned on / off by the control signal PSH.

[0040] The comparator 405 has first and second input terminals. A signal corresponding to the selection result of the selection circuit 404 is input to the first input terminal. The selection circuit 404 selects and outputs the reference voltage VREF supplied from the slope voltage generating unit 204 in FIG. 2 or the slope voltage VRmpL or VRmpH, which is a reference voltage. Details regarding the operation of the selection circuit 404 will be described later. The output of the amplifier 401 written to the capacitor 403 is input to the second input terminal of the comparator 405.

[0041] Comparator 405 compares the output of amplifier 401 with a reference voltage VREF or a slope voltage which is a reference voltage, and outputs one of two values, low level or high level, depending on which is larger. Specifically, if the voltage input to comparator 405 from selection circuit 404 is smaller than the output of amplifier 401, comparator 405 outputs low level. On the other hand, if the voltage input to comparator 405 from selection circuit 404 is larger than the output of amplifier 401, comparator 405 outputs high level. The output of comparator 405 is supplied to counter 406, decision value memory 407, and selection circuit 404, respectively.

[0042] At the same time as the transition of the slope voltage, which is the reference voltage, begins, a clock (the signal of which is denoted as CLK) starts operating, and the counter 406 performs counting operation of the CLK. The counter 406 performs count-up operation in response to the CLK when the output of the comparator 405 is at a high level, and stops counting operation at the same time when the output of the comparator 405 is inverted to a low level (the magnitude relationship is reversed).

[0043] The judgment value memory 407 stores and holds a signal representing the judgment result of the comparator 405. For example, a signal representing the result of the comparison between the reference voltage VREF and the output from the amplifier 401 by the comparator 405 is held.

[0044] The N memory H408, the N memory L409, and the S memory 410 are connected to the counter 406. The N memory H408 holds, for example, a digital signal obtained by AD converting a reset level signal of the FD (hereinafter referred to as the N signal) using a slope voltage VrmPH. The N memory L409 holds, for example, a digital signal obtained by AD converting an N signal of the FD 304 using a slope voltage VrmPL. The S memory 410 holds, for example, a digital signal obtained by AD converting a signal obtained by superimposing a signal from the photoelectric conversion element D1 on the N signal of the FD (hereinafter referred to as the S signal) using a slope voltage VrmPL or VrmPH. Details of the signals held in the judgment value memory 407, the N memory H408, the N memory L409, and the S memory 410 will be described later.

[0045] The signals held in the judgment value memory 407, N memory H 408, N memory L 409, and S memory 410 are sent to the DSP 206 via horizontal output lines 411, 412, 413, and 414, respectively, in response to a control signal from the horizontal scanning unit 205. The DSP 206 subtracts the N signal from the S signal, and outputs a signal from which the reset noise component of the FD, which is a cause of noise, has been removed. The processing by the DSP 206 will be described later.

[0046] Next, the operation of reading out charges from one row of pixels 200 of the image sensor 12 will be described. The image sensor 12 of this embodiment has two AD conversion modes. The first AD conversion mode is a mode in which AD conversion is performed by selecting from multiple slope voltages depending on the signal output level. An example of a dual slope method using two slope voltages will be described below. The second AD conversion mode is a mode in which AD conversion is performed using a single slope voltage regardless of the signal output level.

[0047] 5 and 6 are timing charts showing examples of charge readout operations in each AD conversion mode. They schematically illustrate temporal changes in the horizontal synchronization signal, the signals of the control lines PSEL, PRES, and PTX, the control signal PSH, the slope voltage VRmp, the potential Vl output from the amplifier 401, the output levels COMP and CLK of the comparator 405, and the horizontal scanning signal. The slope voltage VRmp includes the reference voltage VREF. In addition, in FIGS. 5 and 6, the periods from t500 to t518 and from t600 to t613 respectively indicate vertical transfer periods (see Tvd and Tvs) leading up to AD conversion of pixel signals. In FIGS. 5 and 6, the periods from t518 to t519 and from t613 to t614 respectively indicate horizontal transfer periods (see Thd and Ths) during which AD-converted signals are read out to the outside.

[0048] 5 is a timing chart showing an example of a charge readout operation in the first AD conversion mode (multiple-slope AD conversion mode). Hereinafter, regarding the level of a binary signal, a high level is represented as Hi and a low level is represented as Lo. At time t500, prior to reading out a signal from PD (photoelectric conversion element D1), the control signal PRES of the reset transistor T2 becomes Hi. This resets the voltage of the FD node 301 to the reset power supply voltage VDD.

[0049] During the period from time t501 to time t502, the control signal PSEL becomes Hi, and the drive transistor Tdrv becomes active. Then, at time t502, the control signal PRES becomes Lo, and the reset of the FD capacitance Cfd is released. The potential of the FD at this time is read out to the vertical signal line 212 as a reset signal level (N signal) and input to the column signal processing unit 203 that constitutes the readout circuit.

[0050] The control signal PSH becomes Hi at time t503 and Lo at time t504. The control signal PSH is a signal input from the timing unit 207 to the column signal processing unit 203. The switch 402 (FIG. 4) turns on at time t503 and turns off at time t504. As a result, the N signal read out to the vertical signal line 212 is amplified by the amplifier 401 at a desired gain and then held in the capacitor 403. The N signal held in the capacitor 403 is supplied as one input to the comparator 405.

[0051] After the switch 402 is turned off at time t504, during the period from time t505 to time t507, the slope voltage generating unit 204 decreases the slope voltage VRmpH (see solid line) from its initial value over time. The slope voltage generating unit 204 can simultaneously generate multiple slope voltages with different slopes and supply them to the column signal processing unit 203. A slope voltage with a relatively large absolute value of slope is denoted as VRmpH, and a slope voltage with a relatively small absolute value of slope is denoted as VRmpL. In this embodiment, the slope voltage VRmpH is first generated and input to the comparator 405 via the selection circuit 404 of the column signal processing unit 203.

[0052] At time t505, as the transition of the slope voltage VRMPH begins, CLK is supplied to the counter 406. The value of the counter 406 increases according to the number of counted CLKs. At time t506, the slope voltage VRMPH input to the comparator 405 becomes the same level as the N signal. At this time, the output COMP of the comparator 405 becomes Lo, and at the same time, the operation of the counter 406 stops. The count value when the operation of the counter 406 stops is the value obtained by AD converting the N signal with reference to the slope voltage VRMPH, and is held in the N memory H408 as the N signal for the slope voltage VRMPH.

[0053] At time t507, the period of the N signal for the slope voltage VRMPH ends. After the counter 406 is reset, the slope voltage generation unit 204 generates the slope voltage VRMPL. The slope voltage VRMPL is input to the comparator 405 via the selection circuit 404 of the column signal processing unit 203. During the period from time t508 to time t510, the slope voltage generation unit 204 decreases the slope voltage VRMPL (see the dashed line) from its initial value over time.

[0054] At time t508, as the slope voltage VRmpL starts to transition, CLK is supplied to the counter 406. The value of the counter 406 increases according to the number of CLKs being counted. At time t509, the slope voltage VRmpL input to the comparator 405 becomes the same level as the N signal. At this time, the output COMP of the comparator 405 becomes Lo, and at the same time, the operation of the counter 406 stops. The count value when the operation of the counter 406 stops is a value obtained by AD converting the N signal with reference to the slope voltage VRmpL, and is held in the N memory L409 as the N signal for the slope voltage VRmpL.

[0055] After the digitized N signal is stored in each N memory (408, 409), the control signal PTX goes high at time t510, and then goes low at time t511, causing the photocharge accumulated in the PD to be transferred to the FD. The potential fluctuation of the FD according to the amount of charge is read out as an S signal level (light component+reset noise component (N signal)) to the vertical signal line 212 and input to the column signal processing unit 203.

[0056] The amplifier 401 amplifies the S signal with a desired gain. At time t512, the control signal PSH becomes Hi, turning on the switch 402. At time t513, the control signal PSH becomes Lo, turning off the switch 402. As a result, the potential held in the capacitor 403 is input to one terminal of the comparator 405.

[0057] After the switch 402 is turned off at time t513, during the period from time t514 to time t515, the reference voltage VREF is input to the other terminal of the comparator 405. The reference voltage VREF is generated by the slope voltage generating unit 204 and input to the comparator 405 via the selection circuit 404 of the column signal processing unit 203.

[0058] Subsequently, during the period from time t516 to time t518, the slope voltage generating section 204 decreases the slope voltages VRmpL and VRmpH from their initial values over time.

[0059] In the column signal processing unit 203, which of the slope voltages VRmpH and VRmpL is input to the comparator 405 is determined according to the value of the output COMP of the comparator 405 during the period from time t514 to time t515. In the following description, the value of the output COMP of the comparator 405 is assumed to be a logical value "1" or "0."

[0060] 5, when the level of the output Vl is compared with the level of the reference voltage VREF (reference value), the reference voltage VREF is greater than the output Vl during the period from time t514 to time t515. Therefore, the output COMP becomes Hi (logical value "1"). The output COMP is input to the selection circuit 404 (see FIG. 4). When the value of the output COMP is logical value "1", the selection circuit 404 selects the slope voltage VRmpH, which has a relatively large slope, and supplies it to the comparator 405.

[0061] On the other hand, when the output Vl is equal to or higher than the reference voltage VREF (above the reference value), that is, when the output COMP is Lo (logical value "0"), the selection circuit 404 selects a slope voltage VRmpL with a relatively small slope and supplies it to the comparator 405. Here, the logical value that is the value of the output COMP during the period from time t514 to time t515 is represented as a judgment value J. The signal of the judgment value J is input to the selection circuit 404 and is also held in the judgment value memory 407.

[0062] Although not shown in FIG. 4, a separate switch may be provided to control input of the output of comparator 405 to selection circuit 404 and decision value memory 407 only during the period from time t514 to time t515.

[0063] 5, at time t516, the slope voltage VRMPH starts to transition and CLK is supplied to the counter 406. The value of the counter 406 increases in accordance with the number of CLKs being counted. At time t517, the slope voltage VRMPH, which is the reference voltage input to the comparator 405, becomes the same level as the S signal. At this time, the output COMP of the comparator 405 becomes Lo, and at the same time, the operation of the counter 406 stops. The count value when the operation of the counter 406 stops is the value obtained by AD converting the S signal and is held in the S memory 410.

[0064] Subsequently, from time t518, the signals held in the judgment value memory 407, N memory H 408, N memory L 409, and S memory 410 are read out by the horizontal scanning unit 205. The signals held in each of the memories 407 to 410 are sent to the DSP 206 via horizontal output lines 411, 412, 413, and 414, respectively.

[0065] The DSP206 calculates a differential signal (pixel signal of the light component) by subtracting the N signal from the S signal. At this time, the N signal value in the N memory H408 or the N memory L409 is selected as the N signal value to be subtracted from the S signal based on the judgment value J held in the judgment value memory 407. If the judgment value J is a logical value of "1," the slope voltage VRmpH is selected, and the DSP206 subtracts the N signal value in the N memory H408 from the S signal value in the S memory 410. If the judgment value J is a logical value of "0," the slope voltage VRmpL is selected, and the DSP206 subtracts the N signal value in the N memory L409 from the S signal value in the S memory 410. After the above subtraction, the DSP206 performs a correction process on the AD conversion result according to the slope voltage selected during the AD conversion of the S signal.

[0066] Here, we will explain the correction process for the AD conversion results. For example, assume that the slope of the slope voltage VRMPH is four times that of the slope voltage VRMPL. In this case, the signal amplitude corresponding to 1 CLK, i.e., 1 count of output, is four times larger in the case of VRMPH. Therefore, in order to adjust the digital output to match the signal potential level, the DSP 206 performs a process of quadrupling the digital gain of the differential signal value calculated from VRMPH.

[0067] The DSP 206 determines whether correction processing is required for the calculated differential signal. This determination can be made based on the judgment value J stored in the judgment value memory 407. If the judgment value J is a logical value of "1," the slope voltage VRmpH is selected, and processing is performed to quadruple the digital gain of the differential signal. If the judgment value J is a logical value of "0," the slope voltage VRmpL is selected, and the quadruple gain setting processing is not performed.

[0068] After the DSP 206 performs the calculation process, pixel signal data for one row is output to the outside of the image sensor 12 during the period from time t518 to time t519.

[0069] In this embodiment, the level of the reference voltage VREF for determining the judgment value J can be set arbitrarily. For example, if the slope of the slope voltage VrmPH is four times the slope of the slope voltage VrmPL, the reference voltage VREF should be set to at least ¼ of the amplitude of the output signal to be AD converted. If the reference voltage VREF is set to ¼ of the output signal amplitude and the amplitude of the output signal to be AD converted is 1 [V], the reference voltage VREF is set to an amplitude equivalent to 0.25 [V].

[0070] For example, if the counter used for AD conversion is a 12-bit counter configured to count up to 4095, the slope voltage VRmpL is controlled to have an amplitude of 0.25 V at 4095 counts. The slope voltage VRmpH is controlled to have an amplitude of 1 V at 4095 counts. When AD conversion is performed with this configuration, the output results after correction are output in 1-count increments from 0 to 4095 for small amplitudes of 0.25 V or less, i.e., low brightness output. Also, for large amplitudes greater than 0.25 V and less than 1 V, i.e., high brightness output, the output results are output in 4-count increments from 4096 to 16380. Thus, although the resolution of high brightness output is coarser than that of low brightness output, AD conversion can be performed without taking too long to reach a 14-bit count.

[0071] At time t518, the signal level of the control line PSEL applied to the relevant row becomes Lo, the vertical transfer is completed, and the vertical transfer readout for the next row starts.

[0072] Next, the charge read operation in the second AD conversion mode (single-slope AD conversion mode) will be described with reference to Fig. 6. Fig. 6 is a timing chart showing an example of the charge read operation in the second AD conversion mode. Note that the operation from time t600 to time t605 is the same as the operation from time t500 to time t505 in Fig. 5, and therefore a description thereof will be omitted. In addition, the single-slope voltage VRmp will be described as VRmpL.

[0073] At time t605, as the transition to the slope voltage VRmpL begins, CLK is supplied to the counter 406, and the value of the counter 406 increases according to the number of counted CLKs. At time t606, the slope voltage VRmpL input to the comparator 405 becomes the same level as the N signal. At this time, the output COMP of the comparator 405 becomes Lo, and at the same time, the operation of the counter 406 stops. The count value when the operation of the counter 406 stops is the value obtained by AD converting the N signal with reference to the slope voltage VRmpL, and is held in the N memory L409 as the N signal for the slope voltage VRmpL.

[0074] After the digitized N signal is stored in the N memory L409, the signal on the control line PTX goes high at time t607 and low at time t608, causing the photocharge accumulated in the PD to be transferred to the FD. The potential fluctuation of the FD according to the amount of charge is read out to the vertical signal line 212 as an S signal level (light component+reset noise component (N signal)) and input to the column signal processing unit 203. The S signal is amplified by the amplifier 401 at a desired gain.

[0075] At time t609, the control signal PSH becomes Hi, turning on the switch 402, and at time t610, the control signal PSH becomes Lo, turning off the switch 402. The potential held in the capacitor 403 is input to one terminal of the comparator 405.

[0076] During the period from time t611 to time t613, the slope voltage generating unit 204 decreases the slope voltage VRmpL from its initial value over time. In the second AD conversion mode, AD conversion is performed using a single slope voltage as a reference voltage. Therefore, unlike the first AD conversion mode, there is no need to perform AD conversion of the N signal at an unselected slope voltage (VRmpH) or to perform determination and driving using the reference voltage VREF as an input.

[0077] In the second AD conversion mode, the slope voltage generating unit 204 generates only one type of slope voltage and supplies it to the column signal processing unit 203. That is, the slope voltage VRmpL is input to one terminal of the comparator 405 via the selection circuit 404.

[0078] As the slope voltage VRmpL starts to transition, CLK is supplied to the counter 406. The value of the counter 406 increases according to the number of CLKs being counted. At time t612, the slope voltage VRmpL, which is the reference voltage input to the comparator 405, becomes the same level as the S signal. At this time, the output COMP of the comparator 405 becomes Lo, and at the same time, the operation of the counter 406 stops. The count value when the operation of the counter 406 stops is the value obtained by AD converting the S signal, and is held in the S memory 410, which is a memory for the S signal.

[0079] Next, the signals held in the N memory L409 and the S memory 410 are read out by the horizontal scanning unit 205. From time t613 to time t614, the column signal processing unit 203 is operated sequentially, and the signals held in the N memory L409 and the S memory 410 are sent to the DSP 206 via the horizontal output lines 412 and 413, respectively. The DSP 206 performs processing such as subtracting the N signal from the S signal to calculate a differential signal (pixel signal of the light component). The signal after processing by the DSP 206 is output to the outside of the image sensor 12.

[0080] As described above, the imaging device 1 of this embodiment has a multi-slope AD conversion mode and a single-slope AD conversion mode for the image sensor 12. By selecting an AD conversion mode that is suited to the drive mode according to the operating conditions, it is possible to achieve both high image quality and high readout speed.

[0081] [First Example] In this embodiment, we will explain control that enables readout suitable for high speed by selecting multiple AD conversion modes based on the relationship between the vertical transfer period and the horizontal transfer period. The readout operation during the vertical transfer period and the horizontal transfer period described with reference to Figures 5 and 6 is performed sequentially for each row. For example, the row including the P11 pixel shown in Figure 2 is the first row, and the row including the P21 pixel is the second row. In this case, the vertical transfer operation for the second row of the pixel area 201 is started under the control of the vertical scanning unit 202 after the vertical transfer period for the first row.

[0082] In this embodiment, horizontal transfer of the first row and vertical transfer of the second row are performed simultaneously, and operations are continued sequentially until horizontal transfer of the nth row is completed. At this time, the length of the vertical transfer period (vertical transfer time) is the time required for AD conversion of pixel signals, and therefore does not depend on the number of horizontal pixels to be read out. On the other hand, the length of the horizontal transfer period (horizontal transfer time) is the time required to transfer pixel signals for one horizontal row to the outside, and therefore the time required varies depending on the number of pixels to be read out. In other words, the relationship in length between the vertical transfer time and the horizontal transfer time changes depending on the number of horizontal pixels to be read out.

[0083] The length of the vertical transfer period from time t500 to time t518 shown in Fig. 5 until the pixel signals are AD converted is denoted as Tvd. The length of the horizontal transfer period from time t518 to time t519 shown in Fig. 5 during which the AD converted signals are read out to the outside is denoted as Thd. The length of the vertical transfer period from time t600 to time t613 shown in Fig. 6 during which the pixel signals are AD converted is denoted as Tvs. The length of the horizontal transfer period from time t613 to time t614 shown in Fig. 6 during which the AD converted signals are read out to the outside is denoted as Ths.

[0084] 6, when "Tvs>Ths," switching from the second AD conversion mode to the first AD conversion mode shortens the time it takes to read out pixel signals, thereby enabling an increase in the readout speed. On the other hand, when "Tvs≦Ths," switching from the second AD conversion mode to the first AD conversion mode does not result in an increase in speed, since the rate is determined by the horizontal transfer period.

[0085] Modern imaging devices, such as digital cameras, have various drive modes. For example, there are modes for still images, 4K video, FHD video, and the like, which can be arbitrarily set by user operation. Optimization is generally achieved by changing the number of pixels read from the image sensor according to each drive mode. In this embodiment, pixel signal readout control suitable for high speed is performed by selecting an AD conversion mode according to the relationship between the vertical transfer period and the horizontal transfer period in the drive mode.

[0086] The operation of this embodiment will be described with reference to the flowchart of Fig. 7. Processing starts in S100. The user turns on the power button included in the operation unit 16 of the imaging device. After various initial settings are made in the next S101, a drive mode is selected in accordance with the user's operation (S102).

[0087] In S103, the synchronization control unit 15 determines whether the length Ths of the horizontal transfer period or the length Tvs of the vertical transfer period, which are preset in accordance with the drive mode selected in S102, is larger or smaller. If the length Tvs of the vertical transfer period in the selected drive mode is greater than the length Ths of the horizontal transfer period, the process proceeds to S104. If Tvs is equal to or smaller than Ths, the process proceeds to S105.

[0088] In S104, the synchronization control unit 15 selects the first AD conversion mode. In S105, the synchronization control unit 15 selects the second AD conversion mode. After S104 and S105, the process proceeds to S106.

[0089] In S106, the synchronization control unit 15 controls the drive mode selected in S102 in accordance with the AD conversion mode selected in S104 or S105, and executes the photographing process (development process, recording process, etc.).

[0090] In S107, the synchronization control unit 15 determines whether or not the image capture has ended. If it is determined that the image capture should continue, the process returns to S102 and continues. If it is determined that the image capture should end, the process proceeds to S108. The power is turned off and the image capture ends.

[0091] In this embodiment, by selecting an AD conversion mode according to the relationship between the vertical transfer period and the horizontal transfer period, it is possible to realize readout control suitable for high speed. Note that in this embodiment, the number of pixels read in the horizontal direction has been used as an example of control in which the length of the horizontal transfer period is changed. Alternatively, similar control can be applied by changing the number of output bits of the pixel signal when output from the image sensor or the output bit rate when output.

[0092] [Second Example] Next, as a second embodiment, an imaging device capable of reducing the influence of gray scale differences by selecting an AD conversion mode according to the AD conversion resolution will be described. In this embodiment, the resolution during AD conversion can be switched by the synchronization control unit 15.

[0093] Modern imaging devices, such as digital cameras, have multiple drive modes for still images, video, etc. For example, there is a still image drive mode that emphasizes image quality and a video drive mode that requires high speed, and the AD conversion resolution is switched depending on the drive mode. In the still image drive mode, the AD conversion bit resolution is set to 14 bits or more to ensure the dynamic range of the pixel signal. In the video drive mode, the AD conversion bit resolution is generally set to 12 bits or less to improve processing speed and frame rate.

[0094] Another issue with the first AD conversion mode is that if the grayscale changes before and after the slope switches, the grayscale difference may affect the image. This is particularly noticeable when the AD conversion resolution is low.

[0095] For example, assume that the AD conversion bit resolution is 14 bits. In this case, the dynamic range of the pixel signal is 16383 LSB. In the first AD conversion mode, the value when switching between VRmpL and VRmpH (which has a slope four times that of VRmpL) is 16384 / 4 = 4096 LSB. The bit precision of signal values above 4096 LSB becomes four times coarser, and around 4096 LSB near the switching point, a difference of up to 4 LSB occurs when switching between VRmpL and VRmpH.

[0096] Also, assume that the AD conversion bit resolution is 12 bits. In this case, the dynamic range of the pixel signal is 4095 LSB. In the first AD conversion mode, the value when switching between VRmpL and VRmpH (which has a slope four times that of VRmpL) is 4096 / 4 = 512 LSB. The bit precision of signal values above 512 LSB becomes four times coarser, and around 512 LSB near the switching point, a difference of up to 4 LSB occurs when switching between VRmpL and VRmpH.

[0097] When the relationship between the slope of VRmpL and the slope of VRmpH is constant (set to four times in this embodiment), the same amount of gradation difference occurs at the VRmp switching point regardless of the AD conversion resolution. Therefore, when the AD conversion resolution is low, the proportion of the gradation difference becomes larger, making the roughness of the gradation more noticeable in the image. Therefore, this embodiment describes an imaging device that can suppress the impact of the gradation difference (joint step) on the image by selecting an AD conversion mode according to the AD conversion resolution.

[0098] The operation of this embodiment will be described with reference to the flowchart of Fig. 8. Note that the description of the same processes as in Fig. 7 will be omitted, and only the differences from the first embodiment will be described. After a drive mode is selected in accordance with a user operation in S102, the process proceeds to S201.

[0099] In S201, the synchronization control unit 15 determines whether the bit resolution of AD conversion in the drive mode selected in S102 is equal to or greater than a threshold value (e.g., 14 bits). If it is determined in S102 that the bit resolution of AD conversion in the drive mode selected is equal to or greater than the threshold value, the process proceeds to S104, where the first AD conversion mode is selected. If it is determined in S102 that the bit resolution of AD conversion in the drive mode selected is smaller than the threshold value, the process proceeds to S105, where the second AD conversion mode is selected. Thereafter, the processes from S106 to S108 are executed.

[0100] In this embodiment, by selecting the first or second AD conversion mode depending on the resolution of the AD conversion, it is possible to perform read control that can suppress the influence of gray level differences on the image.

[0101] According to the embodiment, an imaging device can be provided that can achieve both high image quality and high readout speed by selecting an AD conversion method that is suitable for the operating conditions.

[0102] Although the imaging device according to the present embodiment has been described above, the present invention is not limited to the above embodiment and various modifications are possible. For example, an AD conversion mode suitable for a drive mode may be selected depending on the relationship between the number of vertical readout lines, etc., without being limited by the relationship between the temporal magnitudes of the vertical transfer period and the horizontal transfer period or the AD conversion resolution. For example, if the thinning number related to the number of vertical readout lines is equal to or greater than a threshold, a first AD conversion mode is selected, and if the thinning number is less than the threshold, a second AD conversion mode is selected. [Explanation of symbols]

[0103] 1. Imaging device 12 Image sensor 200 pixels 203 column signal processing section 204 Slope voltage generator 401 Amplifier 404 Selection Circuit 405 Comparator 406 Counter

Claims

1. a conversion means for converting pixel signals output from a plurality of pixels of the image sensor into digital signals by comparing the pixel signals with a slope voltage whose potential changes over time; a control unit that controls the conversion unit in a plurality of modes corresponding to operation conditions when the pixel signals are read out; The control means In a first mode, the conversion of the pixel signal performed by the converting means is controlled by comparing the pixel signal with a slope voltage selected from a plurality of slope voltages; In a second mode, the conversion of the pixel signal performed by the conversion means is controlled by comparing the pixel signal with a predetermined slope voltage; The first or second mode is selected by comparing a first period taken from reading out pixel signals from the image sensor to conversion by the conversion means with a second period taken to transfer the image signals converted by the conversion means. An imaging device characterized by:

2. The control means selects the first mode when the length of the first period is longer than the length of the second period, and selects the second mode when the length of the first period is shorter than the length of the second period.

2. The imaging device according to claim 1.

3. the first period is a vertical transfer period for the pixel signal, and the second period is a horizontal transfer period for the image signal, The control means selects the first or second mode depending on a mode for reading out the pixel signals from the imaging element.

3. The imaging device according to claim 2.

4. a conversion means for converting pixel signals output from a plurality of pixels of the image sensor into digital signals by comparing the pixel signals with a slope voltage whose potential changes over time; a control unit that controls the conversion unit in a plurality of modes corresponding to operation conditions when the pixel signals are read out; The control means In a first mode, the conversion of the pixel signal performed by the converting means is controlled by comparing the pixel signal with a slope voltage selected from a plurality of slope voltages; In a second mode, the conversion of the pixel signal performed by the conversion means is controlled by comparing the pixel signal with a predetermined slope voltage; The first or second mode is selected depending on the resolution at which the conversion means performs conversion. An imaging device characterized by:

5. The control means selects the first mode when the resolution is equal to or greater than a threshold value, and selects the second mode when the resolution is smaller than the threshold value.

5. The imaging device according to claim 4.

6. The control means controls switching of the resolution depending on a mode for reading out the pixel signals from the image sensor.

6. The imaging device according to claim 5.

7. The control means controls switching to the first mode in a driving mode related to a still image and switching to the second mode in a driving mode related to a moving image.

7. The imaging device according to claim 6.

8. a conversion means for converting pixel signals output from a plurality of pixels of the image sensor into digital signals by comparing the pixel signals with a slope voltage whose potential changes over time; a control unit that controls the conversion unit in a plurality of modes corresponding to operation conditions when the pixel signals are read out; The control means In a first mode, the conversion of the pixel signal performed by the converting means is controlled by comparing the pixel signal with a slope voltage selected from a plurality of slope voltages; In a second mode, the conversion of the pixel signal performed by the conversion means is controlled by comparing the pixel signal with a predetermined slope voltage; The first or second mode is selected depending on the number of vertical readout lines of the image sensor. The imaging device according to the present invention is characterized in that

9. The conversion means a selection circuit that selects a signal of one of the plurality of slope voltages; a comparator that compares the pixel signal with the signal selected by the selection circuit; a counter that counts the output of the comparator; The selection circuit selects the slope voltage signal corresponding to the output of the comparator.

9. The imaging device according to claim 1, wherein the imaging device is a lens.

10. A control method executed in an imaging device including an imaging element, a step of converting pixel signals output from a plurality of pixels of the image sensor into digital signals by a conversion means by comparing the pixel signals with a slope voltage whose potential changes over time; a control step in which a control unit controls the conversion unit in a plurality of modes corresponding to operation conditions when the pixel signals are read out; In the control step, the control means In a first mode, the conversion of the pixel signal performed by the converting means is controlled by comparing the pixel signal with a slope voltage selected from a plurality of slope voltages; In a second mode, the conversion of the pixel signal performed by the conversion means is controlled by comparing the pixel signal with a predetermined slope voltage; The first or second mode is selected by comparing a first period taken from reading out pixel signals from the image sensor to conversion by the conversion means with a second period taken to transfer the image signals converted by the conversion means.

10. A method for controlling an imaging device comprising:

11. A control method executed in an imaging device including an imaging element, a step of converting pixel signals output from a plurality of pixels of the image sensor into digital signals by a conversion means by comparing the pixel signals with a slope voltage whose potential changes over time; a control step in which a control unit controls the conversion unit in a plurality of modes corresponding to operation conditions when the pixel signals are read out; In the control step, the control means In a first mode, the conversion of the pixel signal performed by the converting means is controlled by comparing the pixel signal with a slope voltage selected from a plurality of slope voltages; In a second mode, the conversion of the pixel signal performed by the conversion means is controlled by comparing the pixel signal with a predetermined slope voltage; The first or second mode is selected depending on the resolution at which the conversion means performs conversion.

10. A method for controlling an imaging device comprising:

12. A control method executed in an imaging device including an imaging element, a step of converting pixel signals output from a plurality of pixels of the image sensor into digital signals by a conversion means by comparing the pixel signals with a slope voltage whose potential changes over time; a control step in which a control unit controls the conversion unit in a plurality of modes corresponding to operation conditions when the pixel signals are read out; In the control step, the control means In a first mode, the conversion of the pixel signal performed by the converting means is controlled by comparing the pixel signal with a slope voltage selected from a plurality of slope voltages; In a second mode, the conversion of the pixel signal performed by the conversion means is controlled by comparing the pixel signal with a predetermined slope voltage; The first or second mode is selected depending on the number of vertical readout lines of the image sensor.

10. A method for controlling an imaging device comprising:

Images