Semiconductor Devices

Abstract

To provide a semiconductor device capable of suppressing a recovery loss and having high breakdown voltage characteristics.SOLUTION: A conductor layer of a semiconductor device has: a drift region of a first conductivity type; a pillar region of the first conductivity type in contact with a part of a top face of the drift region; a second conductivity type region in contact with the other part of the top face of the drift region, the second conductivity type region including an anode region of a second conductivity type arranged at a portion in contact with a lateral face of the pillar region, a base region of the second conductivity type in contact with a top face of the pillar region, and a contact region of the second conductivity type arranged at a position exposed to a top face of a semiconductor layer and electrically connected with a second main electrode; and a source region of the first conductivity type in contact with a top face of the base region of the second conductivity type region, arranged at a position exposed to the top face of the semiconductor layer, and electrically connected with the second main electrode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a semiconductor device. [Background technology]

[0002] When a forward bias is applied to a diode (including diodes built into MOSFETs), electrons are injected from the n-type cathode region into the n-type drift region, and holes are injected from the p-type anode region into the drift region. When the voltage applied to the diode changes from forward bias to reverse bias, the electrons and holes that were injected into the drift region during forward bias move in the opposite direction to when the diode was in forward bias. This reverse flow of electrons and holes is called recovery current, and is the main cause of recovery loss.

[0003] Patent Document 1 discloses a diode incorporating an npn transistor structure. In this diode, the npn transistor structure operates when forward biased. This can suppress the amount of holes injected from the anode region to the drift region. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-190838 Summary of the Invention [Problem to be solved by the invention]

[0005] The present specification provides a semiconductor device that suppresses recovery loss and has high breakdown voltage characteristics. [Means for solving the problem]

[0006] One embodiment of a semiconductor device disclosed herein may include a semiconductor layer, a first main electrode covering the lower surface of the semiconductor layer, and a second main electrode covering the upper surface of the semiconductor layer. The semiconductor layer may include a first conductivity type drift region, first conductivity type pillar regions in contact with a portion of the upper surface of the drift region, a second conductivity type region in contact with another portion of the upper surface of the drift region, a second conductivity type anode region in contact with a side surface of the pillar region, a second conductivity type base region in contact with the upper surface of the pillar region, and a second conductivity type contact region exposed at the upper surface of the semiconductor layer and electrically connected to the second main electrode. Additionally, a first conductivity type source region in contact with the upper surface of the base region in the second conductivity type region, exposed at the upper surface of the semiconductor layer, and electrically connected to the second main electrode. In this semiconductor device, the pillar regions, the base region, and the source region form a junction transistor structure. Because this junction transistor structure operates under forward bias, the current flowing through the diode formed by the anode region and the drift region is reduced, suppressing the amount of carriers injected from the anode region into the drift region and reducing recovery loss. Furthermore, in this semiconductor device, the anode region is disposed in contact with the side surface of the pillar region, so that the pillar region is depleted by the JFET effect under reverse bias. This reduces the electric field applied to the pn junction interface between the pillar region and the base region, thereby reducing reach-through between the pillar region and the base region. Thus, the semiconductor device of the above embodiment can suppress recovery loss and exhibit high breakdown voltage characteristics.

[0007] The anode region may include a pinch-off region in a part of the height range of the pillar region, the pinch-off region being in contact with the pillar region and having a higher impurity concentration than the remaining part. When the pinch-off region is provided, the pillar region is more effectively depleted under reverse bias, and reach-through between the pillar region and the base region is more effectively suppressed.

[0008] The pinch-off region may be in contact with the drift region. When the pinch-off region is provided at such a position, a high voltage is applied to the pinch-off region during reverse bias, and a depletion layer effectively extends from the pinch-off region to the pillar region. As a result, reach-through between the pillar region and the base region is more effectively suppressed.

[0009] The drift region, the pillar region, the anode region, the base region, and the source region may be configured such that the sum of a reach-through voltage between the source region and the base region and a voltage drop in the pillar region is less than a built-in voltage between the anode region and the pillar region, and a pinch-off voltage of the anode region and the pillar region is less than the reach-through voltage of the base region and the pillar region. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a schematic cross-sectional view of a main part of a semiconductor device. [Figure 2] FIG. 10 is a schematic cross-sectional view of a main part of a semiconductor device according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0011] 1, semiconductor device 1, which is a diode, includes a semiconductor layer 10, a cathode electrode 22 covering the lower surface of semiconductor layer 10, and an anode electrode 24 covering the upper surface of semiconductor layer 10. Note that cathode electrode 22 is an example of a first main electrode, and anode electrode 24 is an example of a second main electrode. Here, the thickness direction of semiconductor layer 10 is the z direction, the direction perpendicular to the thickness direction and in which unit cells are repeated is the x direction (hereinafter referred to as the lateral direction of semiconductor layer 10), and the direction perpendicular to both the z-axis direction and the x direction is the y direction.

[0012] The semiconductor layer 10 is not particularly limited, but may be made of, for example, silicon carbide (SiC). The semiconductor layer 10 has an n-type cathode region 11, an n-type drift region 12, an n-type pillar region, a p-type region 14, and an n-type source region 18.

[0013] The cathode region 11 is disposed at a position exposed on the lower surface of the semiconductor layer 10, and is in ohmic contact with the cathode electrode 22. The cathode region 11 is, for example, a silicon carbide substrate with a (0001) plane orientation.

[0014] The drift region 12 is in contact with the upper surface of the cathode region 11, and is disposed between the cathode region 11 and the pillar region 13, and between the cathode region 11 and the p-type region 14. The drift region 12 has a lower concentration of n-type impurities than the cathode region 11.

[0015] The pillar regions 13 are in contact with a portion of the upper surface of the drift region 12 and extend in the thickness direction (z direction) of the semiconductor layer 10. The concentration of n-type impurities in the pillar regions 13 may be the same as the concentration of n-type impurities in the drift region 12. Therefore, the pillar regions 13 can also be said to be part of the drift region 12. When viewed from the thickness direction (z direction) of the semiconductor layer 10, the pillar regions 13 are arranged within the range of the source region 18.

[0016] P-type region 14 is in contact with a portion of the upper surface of drift region 12, and includes an anode region 15, a base region 16, and a contact region 17. Note that p-type region 14 is an example of a second conductivity type region.

[0017] The anode region 15 is a portion of the p-type region 14 that is arranged adjacent to the pillar region 13 in the lateral direction (x direction) of the semiconductor layer 10, and is in contact with the side surfaces of the pillar region 13. A pair of anode regions 15 are arranged to face each other with the pillar region 13 between them, and cover both side surfaces of the pillar region 13.

[0018] The base region 16 is a portion of the p-type region 14 that is arranged adjacent to the pillar region 13 in the thickness direction (z direction) of the semiconductor layer 10, and is in contact with the upper surface of the pillar region 13. The base region 16 is interposed between the pillar region 13 and the source region 18, and separates the pillar region 13 from the source region 18. The concentration of p-type impurities in the base region 16 may be the same as the concentration of p-type impurities in the anode region 15.

[0019] The contact region 17 is in contact with the upper surface of the anode region 15, is disposed at a position exposed on the upper surface of the semiconductor layer 10, and is in ohmic contact with the anode electrode 24. The concentration of p-type impurities in the contact region 17 is higher than the concentrations of p-type impurities in the anode region 15 and the base region 16.

[0020] The source region 18 is in contact with the upper surface of the base region 16 of the p-type region 14, is located at a position exposed at the upper surface of the semiconductor layer 10, and is in ohmic contact with the anode electrode 24. The concentration of n-type impurities in the source region 18 is higher than the concentration of n-type impurities in the drift region 12. The depth of the source region 18 may be the same as the depth of the contact region 17.

[0021] In this way, the semiconductor device 1 is a diode incorporating an npn transistor structure that is configured by the pillar region 13, the base region 16, and the source region .

[0022] Next, the operation of the semiconductor device 1 will be described. When a forward bias is applied between the cathode electrode 22 and the anode electrode 24 so that the anode electrode 24 has a higher potential than the cathode electrode 22, a depletion layer spreads from the pn junction interface between the base region 16 and the source region 18 toward the base region 16, and this portion becomes reach-through, allowing current to flow. In other words, the npn transistor structure operates. As a result, the semiconductor device 1 can operate at a voltage lower than the built-in potential of a diode that does not incorporate an npn transistor structure, and therefore has low on-resistance when a low current is passing through it. Furthermore, the current flowing through the npn transistor structure is mainly electron current, and the amount of holes injected into the drift region 12 is suppressed. This allows the semiconductor device 1 to have low recovery loss characteristics.

[0023] As the forward bias current increases further, the reach-through voltage (V re ) and the voltage drop (V n ) increases. As shown in the following formula, the reach-through voltage (V re ) and voltage drop (V n ) is the built-in potential (V bi ), the semiconductor device 1 can suppress the amount of holes injected into the drift region 12 even when a high current is applied, and can have low recovery loss characteristics.

number

[0024] where: N n- : Concentration of n-type impurities in the drift region 12 N n : Concentration of n-type impurities in the pillar region 13 d n : Thickness of the pillar region 13 in the thickness direction (z direction) of the semiconductor layer 10 A n : Area of the pillar region 13 in the surface direction (xy plane direction) of the semiconductor layer 10 N pa : Concentration of p-type impurities in the anode region 15 d p : The thickness of the base region 16 in the thickness direction (z direction) of the semiconductor layer 10 N n+ : Concentration of n-type impurities in the source region 18 q: Elementary mass of electrons k: Boltzmann constant T: absolute temperature ε: Dielectric constant of semiconductor n i :Density of intrinsic semiconductor μ n : Electron mobility in pillar region 13 I: Current flowing through the pillar region 13 when forward biased Then, the reach-through voltage (V re ) and voltage drop (V n ) and built-in potential (V bi ) can be expressed by the following formulas, respectively.

number

number

number

[0025] The drift region 12, pillar region 13, base region 16, and source region 18 are designed to satisfy the above formula, thereby suppressing the amount of holes injected into the drift region 12 even when a high current is applied, enabling the semiconductor device 1 to have low recovery loss characteristics.

[0026] When a reverse bias is applied between the cathode electrode 22 and the anode electrode 24 so that the anode electrode 24 has a lower potential than the cathode electrode 22, the current is blocked by a depletion layer extending from the pn junction interface between the anode region 15 and the drift region 12, and the semiconductor device 1 is turned off.

[0027] As described above, in the semiconductor device 1, the base region 16 is formed thin so that the pn junction interface between the base region 16 and the source region 18 will experience reach-through under forward bias. Because the base region 16 is formed thin, there is concern that reach-through will occur at the pn junction interface between the base region 16 and the pillar region 13 even under reverse bias. Such reach-through may result in a decrease in breakdown voltage. However, in the semiconductor device 1, the anode region 15 is provided in contact with the side surface of the pillar region 13. Therefore, under reverse bias, the pillar region 13 is depleted by a depletion layer extending from the pn junction interface between the anode region 15 and the pillar region 13 (JFET effect). In this way, pinching off of the pillar region 13 under reverse bias reduces the electric field at the pn junction interface between the base region 16 and the pillar region 13, thereby preventing reach-through from occurring in that area. As a result, the semiconductor device 1 can exhibit high breakdown voltage characteristics. In other words, the semiconductor device 1 can increase the width of the pillar region 13 while maintaining the breakdown voltage, and therefore can more effectively suppress the amount of hole injection during forward bias and reduce recovery loss.

[0028] The above-mentioned action in the case of a reverse bias is expressed by the following formula: pi ) is the reach-through voltage (V re2 ) is effective.

number

[0029] where: W n : Width of the pillar region 13 in the lateral direction (x direction) of the semiconductor layer 10 N pa : Concentration of p-type impurities in the anode region 15 Then, the pinch-off voltage (V pi ) and reach-through voltage (V re2 ) can be expressed by the following formulas, respectively.

number

number

[0030] The pillar region 13, the anode region 15, and the base region 16 are designed to satisfy the above formula, thereby enabling the semiconductor device 1 to have high breakdown voltage characteristics.

[0031] The semiconductor device 2 of the modified example shown in FIG. 2 is characterized in that the anode region 15 includes a pinch-off region 15a. The pinch-off region 15a is a part of the anode region 15, and is a region having a higher concentration of p-type impurities than other parts of the anode region 15. The pinch-off region 15a is disposed in a part of the height range of the pillar region 13, and is in contact with the pillar region 13. As shown in the above formula 6, when the concentration of p-type impurities in the anode region 15 increases, the pinch-off voltage (V pi ) decreases. In this way, by providing the high-concentration pinch-off region 15a in part of the anode region 15, the pillar region 13 can be pinched off well when reverse bias is applied.

[0032] In the semiconductor device 2, the pinch-off region 15a is disposed in the lowest layer of the anode region 15 and is in contact with the drift region 12. When the pinch-off region 15a is disposed in such a position, a high voltage is applied to the pinch-off region 15a during reverse bias, and therefore the depletion layer can be effectively extended from the pinch-off region 15a to the pillar region 13.

[0033] Although the technology disclosed in this specification has been described above using a diode as an example, the technology disclosed in this specification can also be applied to a diode built into a MOSFET, for example.

[0034] Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. Furthermore, the technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0035] 1: semiconductor device, 10: semiconductor layer, 11: cathode region, 12: drift region, 13: pillar region, 14: p-type region, 15: anode region, 16: base region, 17: contact region, 18: source region, 22: cathode electrode, 24: anode electrode

Claims

1. a semiconductor layer; a first main electrode covering a lower surface of the semiconductor layer; a second main electrode coated on the upper surface of the semiconductor layer, The semiconductor layer is a drift region of a first conductivity type; a pillar region of a first conductivity type in contact with a portion of an upper surface of the drift region; a second conductivity type region in contact with another part of the upper surface of the drift region, the second conductivity type region including: an anode region of the second conductivity type arranged in a portion in contact with a side surface of the pillar region; a base region of the second conductivity type in contact with the upper surface of the pillar region; and a contact region of the second conductivity type arranged at a position exposed at the upper surface of the semiconductor layer and electrically connected to the second main electrode; a first conductivity type source region in contact with an upper surface of the base region of the second conductivity type region, disposed at a position exposed at an upper surface of the semiconductor layer, and electrically connected to the second main electrode; the drift region, the pillar region, the anode region, the base region, and the source region are configured such that a sum of a reach-through voltage between the source region and the base region and a voltage drop in the pillar region is smaller than a built-in voltage between the anode region and the drift region, and a pinch-off voltage of the anode region and the pillar region is smaller than the reach-through voltage of the base region and the pillar region.

2. 2. The semiconductor device according to claim 1, wherein said anode region includes, in a part of the height range of said pillar region, a pinch-off region that contacts said pillar region and has a higher impurity concentration than the remaining part.

3. The semiconductor device according to claim 2 , wherein the pinch-off region is in contact with the drift region.

Images