Transistors and Semiconductor Devices

Abstract

a first electrode, a second electrode, an oxide semiconductor connecting the first electrode and the second electrode, and a third electrode adjacent to but not in contact with the oxide semiconductor, wherein the first electrode and the second electrode are stacked with at least a first insulating film interposed therebetween, and the oxide semiconductor has a small cross-sectional area region between the first electrode and the second electrode, and the small cross-sectional area region has a cross-sectional area, when cut along a plane perpendicular to a channel length direction, that is smaller than the cross-sectional areas of each of the regions on both sides of the small cross-sectional area region in the channel length direction.

Description

[Technical Field]

[0001] The present invention relates to transistors and semiconductor devices. More specifically, the present invention relates to a transistor and a semiconductor device that can satisfactorily achieve normally-off operation. [Background technology]

[0002] Attempts have been made to apply a transistor having a channel made of an oxide semiconductor to a dynamic random access memory (DRAM) (Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-134077 Summary of the Invention [Problem to be solved by the invention]

[0004] However, the conventional techniques including Patent Document 1 have room for further improvement in terms of successfully realizing normally-off in transistors.

[0005] An object of the present invention is to provide a transistor and a semiconductor device that can satisfactorily achieve normally-off operation. [Means for solving the problem]

[0006] As a result of extensive investigations, the present inventors have found that normally-off can be satisfactorily achieved when the cross-sectional area of an oxide semiconductor satisfies specific conditions, and have completed the present invention. According to the present invention, the following transistors and the like can be provided. 1. a first electrode and a second electrode; an oxide semiconductor connecting the first electrode and the second electrode; a third electrode adjacent to but not in contact with the oxide semiconductor; Equipped with the first electrode and the second electrode are stacked with at least a first insulating film interposed therebetween; the oxide semiconductor has a small cross-sectional area region between the first electrode and the second electrode, and the small cross-sectional area region has a cross-sectional area, when cut along a plane perpendicular to a channel length direction, that is smaller than the cross-sectional areas of the regions on both sides of the small cross-sectional area region in the channel length direction; Transistor. 2. 2. The transistor according to 1, wherein the conditions of 1.1≦a / b≦20 and 1.1≦a / c≦20 are satisfied, where a is the cross-sectional area of the small cross-sectional area region, b is the cross-sectional area of one of the two side regions, and c is the cross-sectional area of the other of the two side regions. 3. The cross-sectional area of the small cross-sectional area region is 12 to 90,000 nm 2 3. The transistor according to 1 or 2, 4. 4. The transistor according to any one of 1 to 3, wherein the small cross-sectional area region is formed by providing a recess on a surface of the oxide semiconductor on the third electrode side or on a surface opposite to the third electrode side. 5. 4. The transistor according to any one of 1 to 3, wherein the oxide semiconductor penetrates at least the first insulating film to connect the first electrode and the second electrode. 6. 5. The transistor according to any one of 1 to 4, further comprising a second insulating film provided between the third electrode and the oxide semiconductor. 7. the first electrode and the second electrode are stacked with the first insulating film interposed therebetween, the oxide semiconductor has a cylindrical portion that penetrates the first insulating film, a second insulating film provided between the third electrode and the oxide semiconductor; the second insulating film has a cylindrical portion provided on an inner wall of the cylindrical portion of the oxide semiconductor; the third electrode has a portion provided inside the cylindrical portion of the second insulating film; 6. The transistor according to any one of 1 to 5. 8. 8. The transistor according to claim 7, wherein the oxide semiconductor has the small cross-sectional area region at a portion that penetrates the first insulating film. 9. 9. The transistor according to claim 7 or 8, wherein the oxide semiconductor penetrates the first insulating film while being in contact with the first insulating film, and the small cross-sectional area region is formed by providing a recess on a surface opposite to the surface in contact with the first insulating film. 10. 10. The transistor according to any one of 7 to 9, wherein the first insulating film is made of an insulating material having a lower electronegativity than each of the first electrode and the second electrode. 11. 11. The transistor according to any one of 7 to 10, wherein the electronegativity of the insulating material constituting the first insulating film is 1.54 or less. 12. 12. The transistor according to any one of items 7 to 11, wherein the first insulating film is made of SiOC (silicon oxycarbide), SiN (silicon nitride), or AlN (aluminum nitride). 13. the first electrode and the third electrode are stacked with the first insulating film interposed therebetween, the third electrode and the second electrode are stacked with a third insulating film interposed therebetween, the oxide semiconductor is provided in a columnar shape penetrating the first insulating film, the third electrode, and the third insulating film; a second insulating film provided between the third electrode and the oxide semiconductor; the second insulating film is provided so as to surround at least a part of the oxide semiconductor provided in the pillar shape; 6. The transistor according to any one of 1 to 5. 14. 14. The transistor according to any one of 1 to 13, wherein the channel length of the oxide semiconductor is 1 to 1000 nm. 15. 15. The transistor according to any one of 1 to 14, wherein the oxide semiconductor has a bixbyite structure. 16. 16. The transistor according to 15, wherein the oxide semiconductor is primarily composed of indium oxide. 17. 17. The transistor according to 15 or 16, wherein the ratio of indium atoms to all metal atoms contained in the oxide semiconductor is 80 atomic % or more. 18. 18. The transistor according to any one of 15 to 17, wherein the content of indium oxide in the oxide semiconductor is 55 mass % or more. 19. 19. The transistor according to any one of 15 to 18, wherein the oxide semiconductor further contains Ga or Al. 20. 19. The transistor according to any one of 15 to 18, wherein the oxide semiconductor further contains Ga. twenty one. 19. The transistor according to any one of 15 to 18, wherein the oxide semiconductor further contains Ga and Al. twenty two. 22. The transistor according to any one of 15 to 21, wherein the atomic ratio of Ga to all metal elements contained in the oxide semiconductor ([Ga] / ([Ga]+[all metal elements other than Ga])×100) is 0.5 to 25 at %. twenty three. 23. The transistor according to any one of 15 to 22, wherein the atomic ratio of Zn to all metal elements contained in the oxide semiconductor ([Zn] / ([Zn]+[all metal elements other than Zn])×100) is 0 to 3 at %. twenty four. 24. The transistor according to any one of 15 to 23, wherein the oxide semiconductor is substantially free of Zn. twenty five. 25. The transistor according to any one of 1 to 24, wherein at least one of the first electrode and the second electrode is at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), aluminum (Al), silicon (Si), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), germanium (Ge), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), tantalum (Ta), iridium (Ir), platinum (Pt), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum nitride (AlN), manganese nitride (MnN), molybdenum nitride (MoN), and nickel nitride (NiN). 26. 26. The transistor according to any one of 1 to 25, wherein the oxide semiconductor is a crystalline oxide semiconductor formed by atomic layer deposition. 27. A semiconductor device comprising the transistor according to any one of 1 to 26. 28. 28. The semiconductor device according to 27, which is a semiconductor memory device. 29. a first electrode and a second electrode; an oxide semiconductor connecting the first electrode and the second electrode; a third electrode adjacent to but not in contact with the oxide semiconductor; Equipped with the first electrode and the second electrode are stacked with at least a first insulating film interposed therebetween; the oxide semiconductor has a small cross-sectional area region between the first electrode and the second electrode, and a cross-sectional area of the small cross-sectional area region when cut along a plane orthogonal to a channel length direction is smaller than the cross-sectional areas of each of regions on both sides of the small cross-sectional area region in the channel length direction; the small cross-sectional area region is formed by providing a recess on a surface of the oxide semiconductor on the third electrode side or on a surface opposite to the third electrode side, the oxide semiconductor contains indium oxide as a main component and has a bixbyite structure; The channel length of the oxide semiconductor is 1 to 1000 nm. Transistor. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a transistor and a semiconductor device that can satisfactorily achieve normally-off operation. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic perspective view showing a cross section of a transistor according to a first embodiment. [Figure 2] 1 is a schematic cross-sectional view of a transistor according to a first embodiment. [Figure 3] 3A to 3C are diagrams illustrating an example of a method for manufacturing a transistor according to the first embodiment. [Figure 4] FIG. 10 is a schematic perspective view showing a cross section of a transistor according to a second embodiment. [Figure 5] FIG. 10 is a schematic cross-sectional view of a transistor according to a second embodiment. [Figure 6] FIG. 10 is a schematic perspective view showing a cross section of a transistor according to a third embodiment. [Figure 7] FIG. 10 is a schematic cross-sectional view of a transistor according to a third embodiment. [Figure 8] FIG. 1 is a diagram illustrating an example of a circuit configuration of a semiconductor memory device. DETAILED DESCRIPTION OF THE INVENTION

[0009] The transistor and semiconductor device of the present invention will be described in detail below. In this specification, "x to y" represents a numerical range of "not less than x and not more than y." The upper and lower limits of the numerical ranges can be combined in any way. Furthermore, among the individual embodiments of the aspects of the present invention described below, it is possible to combine two or more embodiments that are not mutually contradictory, and an embodiment that combines two or more embodiments is also an embodiment of an aspect of the present invention.

[0010] 1. Transistor A transistor according to one aspect of the present invention includes: a first electrode and a second electrode; an oxide semiconductor connecting the first electrode and the second electrode; a third electrode adjacent to but not in contact with the oxide semiconductor; Equipped with the first electrode and the second electrode are stacked with at least a first insulating film interposed therebetween; The oxide semiconductor has a small cross-sectional area region between the first electrode and the second electrode, and the small cross-sectional area region has a cross-sectional area, when cut along a plane perpendicular to a channel length direction, that is smaller than the cross-sectional areas of the regions on both sides of the small cross-sectional area region in the channel length direction. The transistor of this aspect has the effect of achieving a normally-off state in a satisfactory manner. More specifically, in the transistor of this embodiment, the oxide semiconductor has a small cross-sectional area region between the first electrode and the second electrode, and the cross-sectional area of the small cross-sectional area region, when cut along a plane perpendicular to the channel length direction, is smaller than the cross-sectional area of each of the regions on either side of the small cross-sectional area region in the channel length direction. This increases the resistance (which increases as the cross-sectional area decreases) in the channel region formed between the first electrode and the second electrode, preventing off-leakage and achieving a good normally-off state. On the other hand, the regions on either side of the small cross-sectional area region, which extend to the first electrode and the second electrode, have a larger cross-sectional area and lower resistance than the small cross-sectional area region, thereby ensuring good conduction between the oxide semiconductor and the first electrode and the second electrode. Furthermore, in the transistor of this aspect, the first electrode and the second electrode are stacked with at least a first insulating film interposed therebetween. By providing the transistor with such a structure (vertical structure), it is possible to densely arrange a plurality of transistors in, for example, a semiconductor memory device, which also contributes to miniaturization of the semiconductor memory device. When the channel length becomes shorter as the semiconductor memory device (or transistor) becomes smaller, it has been difficult to achieve a normally-off state with conventional technology. However, according to this aspect, even in such a case, it is possible to satisfactorily achieve a normally-off state as described above. Furthermore, when multiple transistors (especially those with a vertical structure) are arranged at high density in a semiconductor memory device, the transistors become susceptible to the influence of ambient noise. However, according to this embodiment, even in such a case, malfunctions can be prevented.

[0011] (First embodiment) An example (first embodiment) of a transistor according to this aspect will be described below with reference to FIGS. Fig. 1 is a schematic perspective view showing a cross section of a transistor according to a first embodiment, and Fig. 2 is a schematic cross-sectional view of the transistor. In the second embodiment, the transistor 10 includes a first electrode 11, a second electrode 12, a third electrode 13, an oxide semiconductor 15, a first insulating film 14, and a second insulating film 16. At least a portion of the third electrode 13 is located between the first electrode 11 and the second electrode 12. At least a portion of the third electrode 13 may be located on the opposite side of the first electrode 11 from the second electrode 12, or on the opposite side of the second electrode 12 from the first electrode 11. The first insulating film 14 is located between the first electrode 11 and the second electrode 12. Here, the first electrode 11 and the second electrode 12 are stacked with the first insulating film 14 interposed therebetween. As a result, the first electrode 11 and the second electrode 12 are electrically insulated by the first insulating film 14. Note that "stacking" here may mean that at least a part of the first electrode 11 and at least a part of the second electrode 12 are arranged along a direction perpendicular to the surface direction of a substrate (not shown) supporting the transistor 10, or may mean that at least a part of the first electrode 11 and at least a part of the second electrode 12 are arranged along a direction (Z direction) perpendicular to the surface direction in a case where a plurality of transistors 10 are arranged in a planar manner (XY direction) (a case where a plurality of transistors 10 form a transistor array), although not shown. At least a part of the first insulating film 14 may be interposed between the first electrode 11 and the second electrode 12.

[0012] The third electrode 13 is provided adjacent to but not in contact with the oxide semiconductor 15. Specifically, the third electrode 13 is adjacent to the oxide semiconductor 15 via a second insulating film 16. The second insulating film 16 may be provided between the third electrode 13 and the oxide semiconductor 15 to insulate the third electrode 13 from the oxide semiconductor 15.

[0013] The oxide semiconductor 15 is provided so as to penetrate at least the first insulating film 14 and connect the first electrode 11 and the second electrode 12 to each other. Here, the oxide semiconductor 15 is provided in a columnar shape, penetrating the first electrode 11 and the first insulating film 14 in this order. A recess is formed in the columnar oxide semiconductor 15 from one end side (the upper side in FIGS. 1 and 2) to the other end side (the lower side in FIGS. 1 and 2), and a second insulating film 16 is formed on the inner circumferential surface and bottom surface of the recess. The third electrode 13 is provided so as to fill the recess in which the second insulating film 16 is formed. From one point of view, it can also be said that the oxide semiconductor 15 has a cylindrical portion that penetrates the first insulating film 14, the second insulating film 16 has a cylindrical portion that is provided on the inner wall of the cylindrical portion of the oxide semiconductor 15, and the third electrode 13 has a portion that is provided inside the cylindrical portion of the second insulating film 16.

[0014] In the transistor 10, the first electrode 11 can function as a source electrode, and the second electrode 12 can function as a drain electrode. In another example, the first electrode 11 can function as a drain electrode, and the second electrode 12 can function as a source electrode. The third electrode 13 can function as a gate electrode. The oxide semiconductor 15 can function as a channel (current path) of the transistor 10. For example, when a gate voltage is applied to the third electrode 13, which is a gate electrode, the first electrode 11 and the second electrode 12 are electrically connected by the oxide semiconductor 15, and the transistor 10 is in an ON state. When no gate voltage is applied, the electrical connection between the first electrode 11 and the second electrode 12 by the oxide semiconductor 15 is released, and the transistor 10 is in an OFF state.

[0015] In this specification, "electrically connected" includes a case where the connection is made via "something that has some kind of electrical action." Here, the "something that has some kind of electrical action" is not particularly limited as long as it allows the exchange of electrical signals between the connected objects.

[0016] In the transistor 10, the oxide semiconductor 15 is provided so as to connect the first electrode 11 and the second electrode 12. "Provided so as to connect the first electrode 11 and the second electrode 12" means that the oxide semiconductor 15 is provided in a state in which the first electrode 11 and the second electrode 12 can be electrically connected. Therefore, the oxide semiconductor 15 does not need to be in physical contact with the first electrode 11 and the second electrode 12. For example, a conductive material (conductor) may be provided between the oxide semiconductor 15 and the first electrode 11 and / or the second electrode 12, and an insulating material (insulator) may be provided as long as conduction (electrical connection) is ensured.

[0017] As described above, in the transistor 10 of this embodiment, the oxide semiconductor 15 has a small cross-sectional area region 151 between the first electrode 11 and the second electrode 12. The cross-sectional area of the small cross-sectional area region 151, when cut along a plane perpendicular to the channel length direction, is smaller than the cross-sectional areas of the regions 152 and 153 on both sides of the small cross-sectional area region 151 in the channel length direction. This increases the resistance (which increases as the cross-sectional area decreases) in the channel region formed between the first electrode 11 and the second electrode 12, thereby preventing off-state leakage and achieving a favorable normally-off state. On the other hand, the regions 152 and 153 on both sides of the small cross-sectional area region, which extend to the first electrode 11 and the second electrode 12, have a larger cross-sectional area and a lower resistance than the small cross-sectional area region 151, thereby ensuring favorable conduction between the oxide semiconductor 15 and the first electrode 11 and the second electrode 12. Furthermore, in the transistor 10 of this embodiment, the first electrode 11 and the second electrode 12 are stacked with at least the first insulating film 14 interposed therebetween. By having the transistor 10 with such a structure (vertical structure), it is possible to arrange a plurality of transistors 10 at high density in, for example, a semiconductor memory device, which also contributes to the miniaturization of the semiconductor memory device. When the channel length becomes shorter as the semiconductor memory device (or transistor) becomes smaller, it has been difficult to achieve a normally-off state with conventional technology. However, according to this embodiment, even in such a case, it is possible to satisfactorily achieve a normally-off state as described above.

[0018] From one point of view, the small cross-sectional area region 151 in the oxide semiconductor 15 can be said to be the region between the first electrode 11 and the second electrode 12 where the cross-sectional area of the oxide semiconductor 15 (the cross-sectional area when cut along a plane perpendicular to the channel length direction, the same applies below) is the smallest, and may maintain a constant cross-sectional area over any length along the channel length direction. Moreover, the regions 152 and 153 on both sides of the small cross-sectional area region 151 have a cross-sectional area larger than that of the small cross-sectional area region 151, and may maintain a constant cross-sectional area over any length along the channel length direction.

[0019] The cross-sectional area of each region of the oxide semiconductor 15 may be measured by processing and exposing the relevant portion with a focused ion beam (FIB) and observing the cross section with a transmission electron microscope (TEM).

[0020] In the example of FIGS. 1 and 2 (first embodiment), the small cross-sectional area region 151 is located in a region where the oxide semiconductor 15 contacts the insulating film 14. In one embodiment, when the oxide semiconductor 15 is divided into three equal parts in the channel length direction, at least a part of the small cross-sectional area region 151 is located in the central region. In one embodiment, in a cross section of the oxide semiconductor 15 cut along a plane along the channel length direction (such as the cross sections shown in FIG. 2 or FIGS. 5 and 7 described later), the oxide semiconductor 15 is divided into three equal parts in the channel length direction, and the cross-sectional area of a central region in the cross section is smaller than the cross-sectional areas of the regions on both sides. Note that the "plane along the channel length direction" may be a plane along the channel length direction, and may be a plane that has the largest cross-sectional area when the oxide semiconductor 15 is cut along the plane. For example, if the oxide semiconductor 15 has a columnar shape, the "plane along the channel length direction" may be a plane that extends along the central axis of the column.

[0021] In one embodiment, when the cross-sectional area of small cross-sectional area region 151 is a, the cross-sectional area of one of the two side regions 152 is b, and the cross-sectional area of the other of the two side regions 153 is c, the conditions of 1.1≦a / b≦20 and 1.1≦a / c≦20 are satisfied. The value of a / b and / or a / c may be 1.2 or more and 15 or less, or 1.5 or more and 10 or less.

[0022] In one embodiment, the cross-sectional area of the small cross-sectional area region 151 is 12 to 90,000 nm 2 is. In one embodiment, the cross-sectional areas of the regions 152 and 153 on both sides of the small cross-sectional area region 151 are 15 to 300,000 nm 2 is.

[0023] The small cross-sectional area region 151 may be formed by providing a recess in a surface of the oxide semiconductor 15 facing the third electrode 13 or in a surface opposite to the third electrode 13. In the first embodiment, the small cross-sectional area region 151 is formed by providing a recess in the surface of the oxide semiconductor 15 facing the third electrode 13. Specifically, the small cross-sectional area region 151 is formed by providing a recess along the circumferential direction in the inner peripheral surface of the cylindrical portion of the oxide semiconductor 15. The second insulating film 16 and the third electrode 13 may have portions that protrude toward the recess. In this embodiment, the oxide semiconductor 15 has a small cross-sectional area region 151 in a portion that penetrates the first insulating film 14. More specifically, the oxide semiconductor 15 penetrates the first insulating film 14 while being in contact with the first insulating film 14, and a recess is provided on the surface opposite to the surface that is in contact with the first insulating film 14, thereby forming the small cross-sectional area region 151. The small cross-sectional area region 151 is preferably provided in a region of the oxide semiconductor 15 where carriers are induced by application of a voltage to the third electrode (gate electrode).

[0024] The dimensions of the transistor 10 may be appropriately designed depending on the application and the like. The channel length of the oxide semiconductor 15 is, for example, 1 nm or more and 10 μm or less, preferably 2 nm or more and 1000 nm or less. Such a small channel length allows the number of grain boundaries to be reduced (or made zero) when a crystalline oxide semiconductor (e.g., an oxide semiconductor having a bixbyite structure) is used as the oxide semiconductor 15. Because grain boundaries can serve as hydrogen diffusion paths, reducing the number of grain boundaries effectively suppresses hydrogen diffusion. Suppressing the diffusion of hydrogen, which can serve as a carrier, allows for a better normally-off state. The channel length of the oxide semiconductor 15 is the length of the oxide semiconductor 15 along the thickness direction (the vertical direction in Figures 1 and 2) of the stack in which the first electrode 11, the first insulating film 14, and the second electrode 12 are stacked in this order, and may be equal to the depth of the recess in the oxide semiconductor 15.

[0025] In one embodiment, the ratio of the channel length of the oxide semiconductor 15 to the cross-sectional area of the small cross-sectional area region 151 (channel length of the oxide semiconductor [nm] / cross-sectional area of the small cross-sectional area region [nm 2 ]) is 0.01 to 100.

[0026] The thickness of the second insulating film 16 is, for example, 1 Å to 500 nm, preferably 1 nm to 100 nm. In order to prevent the capacitance of the second insulating film 16 from becoming a parasitic component, the thickness of the second insulating film 16 may be 50 nm or less, 10 nm or less, or 2 nm or less.

[0027] The channel length of the oxide semiconductor 15 and the thickness of the second insulating film 16 may be measured by processing and exposing the relevant portions with a focused ion beam (FIB) and observing the cross section with a transmission electron microscope (TEM).

[0028] In one embodiment, the oxide semiconductor 15 has a bixbyite structure. The presence or absence of a bixbyite structure can be determined based on an X-ray diffraction pattern in X-ray diffractometry (XRD) or an electron diffraction spot in electron diffraction (particularly the above-mentioned TEM-ED).

[0029] In one embodiment, the oxide semiconductor 15 is primarily composed of indium oxide. "Containing indium oxide as a main component" means that more than 50 mass % of the material constituting the crystalline oxide semiconductor 15 is indium oxide.

[0030] In one embodiment, the ratio of indium atoms to all metal atoms contained in the oxide semiconductor 15 is 80 atomic % or more, 90 atomic % or more, or 95 atomic % or more. The content (atomic ratio) of each metal element in the oxide semiconductor 15 can be analyzed by TEM-EDS (Energy Dispersive X-ray Spectroscopy) measurement using an electron microscope.

[0031] In one embodiment, the oxide semiconductor 15 has a bixbyite structure containing indium oxide as a main component and may contain other metal atoms. For example, the oxide semiconductor 15 may contain, in addition to indium oxide (IO), indium gallium oxide (IGO) in which gallium is solid-dissolved in indium oxide as a main component, or indium gallium aluminum oxide (IGAO) in which gallium and aluminum are solid-dissolved in indium oxide as a main component. In one embodiment, the oxide semiconductor 15 may have an indium oxide content of 55% by mass or more, 60% by mass or more, 70% by mass or more, 80% by mass or more, 90% by mass or more, 95% by mass or more, 97% by mass or more, 98% by mass or more, or 99% by mass, or may be substantially 100% by mass. Note that "substantially 100% by mass" may include inevitable impurities.

[0032] In one embodiment, the oxide semiconductor 15 contains indium oxide and further contains a positive trivalent metal. The positive trivalent metal is preferably Ga or Al, and more preferably Ga. In one embodiment, the crystalline oxide semiconductor further contains Ga or Al, and may contain Ga, may contain Al, or may contain Ga and Al. In one embodiment, the atomic ratio of positive trivalent metals to all metal elements contained in oxide semiconductor 15 ([positive trivalent metals] / ([positive trivalent metals]+[total metal elements other than positive trivalent metals])×100) may be 0 to 30 at%, 0.5 to 25 at%, 1.0 to 22 at%, 1.5 to 20 at%, 2.0 to 15 at%, or 3.0 to 10 at%. Here, "positive trivalent metals" may be interpreted as Ga and Al. In one embodiment, the atomic ratio of Ga to all metal elements contained in the oxide semiconductor 15 ([Ga] / ([Ga]+[all metal elements other than Ga])×100) may be 0 to 30 at %, 0.5 to 25 at %, 1.0 to 22 at %, 1.5 to 20 at %, 2.0 to 15 at %, or 3.0 to 10 at %. In one embodiment, the atomic ratio of Al to all metal elements contained in the oxide semiconductor 15 ([Al] / ([Al]+[all metal elements other than Al])×100) may be 0 to 30 at%, 0.5 to 25 at%, 1.0 to 22 at%, 1.5 to 20 at%, 2.0 to 15 at%, or 3.0 to 10 at%.

[0033] When the oxide semiconductor 15 contains Ga, it is preferable because it tends to increase the crystal grain size of the oxide semiconductor 15 and reduce the number of crystal grain boundaries in the oxide semiconductor 15. This is because crystal grain boundaries can serve as paths for hydrogen diffusion.

[0034] In one embodiment, the oxide semiconductor 15 further contains one or more additive elements selected from B, Si, Sc, Zn, Ce, Y, Zr, Sn, Sm, Hf, Ta, and Yb. In one embodiment, the atomic ratio of the total amount of additive elements to all metal elements contained in the oxide semiconductor 15 ([total amount of additive elements] / ([total amount of additive elements]+[all metal elements other than additive elements])×100) is 0 to 10 at%, and may be 0.1 to 8 at%, 0.5 to 5 at%, or 1 to 3 at%.

[0035] In one embodiment, the oxide semiconductor 15 does not need to contain Zn. The atomic ratio of Zn to all metal elements contained in the oxide semiconductor 15 ([Amount of Zn] / ([Amount of Zn]+[Amount of all metal elements other than Zn])×100) is 0 to 3 at %, and may be 0 to 1 at %, 0 to 0.1 at %, 0 to 0.01 at %, or substantially 0 at %. In the case of "substantially 0 at %", the oxide semiconductor 15 may contain Zn as an inevitable impurity. Since Zn has the property of absorbing water molecules (including hydrogen and oxygen atoms), when the oxide semiconductor 15 has a low Zn content, and particularly when the oxide semiconductor 15 does not contain Zn, the hydrogen concentration and oxygen concentration of the oxide semiconductor 15 can be reduced, and the diffusion of hydrogen and oxygen into the oxide semiconductor 15 can be suppressed, thereby achieving a better normally-off state.

[0036] Each of the first electrode 11, the second electrode 12, and the third electrode 13 is not particularly limited as long as it is a conductor. Examples of the conductor include indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), aluminum (Al), silicon (Si), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), germanium (Ge), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), tantalum (Ta), iridium (Ir), platinum (Pt), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum nitride (AlN), manganese nitride (MnN), molybdenum nitride (MoN), and nickel nitride (NiN).

[0037] The first insulating film 14 and the second insulating film 16 are not particularly limited as long as they contain an insulator or are made of an insulator. Examples of insulators include aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The first insulating film 14 and the second insulating film 16 may each be a stacked film of the above materials. The insulating film may contain La, N, Zr, or the like. The insulators contained in the first insulating film 14a, the second insulating film 16, and the third insulating film 14b may be the same or different from one another. The material of the first insulating film 14 that is preferably used to form the recesses in the oxide semiconductor 15 will be described later.

[0038] An example of a method for manufacturing the transistor 10 according to this embodiment will be described below, but the manufacturing method is not limited to this example.

[0039] FIG. 3 is a diagram illustrating an example of a method for manufacturing the transistor 10 according to this embodiment. 3(a), a laminate of the second electrode 12, the first insulating film 14, and the first electrode 11 is formed, and then a through-hole is formed so as to penetrate the first electrode 11 and the first insulating film 14. Etching for forming the through-hole may be performed using various methods such as dry etching and wet etching. Furthermore, before etching, a resist may be formed on the first electrode 11 to define the region where the through-hole is to be formed. 3(a), this laminate may be formed on another substrate (not shown). Also, the second electrode 12 may be connected to an element other than the transistor according to this embodiment. The second electrode 12, the first insulating film 14, the first electrode 11, and the through-holes can be formed by known methods.

[0040] Next, as shown in FIG. 3(b), an oxide semiconductor 15 is formed in the through-hole. Examples of methods for forming the oxide semiconductor 15 include chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), sol-gel processes, and coating methods. CVD methods include metal organic CVD (MO-CVD), inductively coupled plasma CVD (ICP-CVD), and mist CVD. PVD methods include DC sputtering, AC sputtering, RF sputtering, ICP sputtering, reactive sputtering, and ion plating. The oxide semiconductor 15 may be formed as a crystalline oxide semiconductor by forming an amorphous oxide semiconductor and then performing post-annealing, which will be described later. A crystalline oxide semiconductor may be formed by performing post-annealing after forming an amorphous oxide semiconductor, or post-annealing may be performed after the oxide semiconductor is crystallized to form a crystalline oxide semiconductor. Alternatively, a crystalline oxide semiconductor may be formed without post-annealing, or the crystallinity of the crystalline oxide semiconductor may be adjusted by performing post-annealing after forming the crystalline oxide semiconductor.

[0041] The small cross-sectional area region 151 (and the regions 152, 153 on both sides thereof) in the oxide semiconductor 15 may be formed, for example, by forming an oxide semiconductor 15 without a recess and then forming a recess by surface treatment. Another example is a method of forming an oxide semiconductor 15 having recesses by utilizing a difference in deposition rate in the ALD method. In this method, the deposition rate can be controlled to be slower on the first insulating film 14 than on the first electrode 11 and the second electrode 12. This makes it possible to form an oxide semiconductor 15 that is thick on the first electrode 11 and the second electrode 12, where the deposition rate is relatively fast, and thin on the first insulating film 14, where the deposition rate is relatively slow (i.e., an oxide semiconductor 15 having recesses). In one embodiment, the first insulating film 14 is made of an insulating material that has a lower electronegativity than each of the first electrode 11 and the second electrode 12. This allows the deposition rate on the first insulating film 14 to be slowed down. In one embodiment, the electronegativity of the insulating material constituting the first insulating film 14 is 1.54 or less, which can slow down the deposition rate on the first insulating film 14. The electronegativity can be, for example, 0.80 to 1.54, 0.90 to 1.50, or 1.00 to 1.45. In one embodiment, the first insulating film 14 is made of SiOC (silicon oxycarbide, electronegativity: 1.10), SiN (silicon nitride, electronegativity: 1.14), or AlN (aluminum nitride, electronegativity: 1.43), which can slow down the deposition rate on the first insulating film 14.

[0042] 3(b), post-annealing is preferably performed on the oxide semiconductor 15. Post-annealing can be performed after the oxide semiconductor is formed, for example, after the subsequent formation of the first electrode 11 or before the formation of the first electrode 11. The oxide semiconductor before post-annealing may be in an amorphous or crystalline state. The annealing atmosphere may contain nitrogen or oxygen and may be in a vacuum or in air. The annealing temperature is preferably 250° C. to 600° C., more preferably 300° C. to 500° C., and even more preferably 350° C. to 450° C. The annealing time is 5 minutes to 2 hours, preferably 30 minutes to 1 hour. The oxide semiconductor 15 can be formed by atomic layer deposition (ALD), which will be described later.

[0043] Next, as shown in FIG. 3(c), a second insulating film 16 is formed. The second insulating film 16 can be formed by various methods such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), sol-gel method, coating method, etc.

[0044] 3(d), the third electrode 13 is formed. At this time, as will be described later, the third electrode 13 may be formed so as to be connected to a word line. Alternatively, the third electrode 13 itself may serve as the word line. The third electrode 13 can be formed by a known method.

[0045] In this manner, the transistor 10 shown in FIGS. 1 and 2 is obtained.

[0046] In the above-described manufacturing method, the oxide semiconductor 15 is formed in the through-hole. Therefore, atomic layer deposition (ALD) is a preferred method for forming the oxide semiconductor 15. Atomic layer deposition (ALD) is a thin film formation method in which a process of alternately exposing a substrate surface to a raw material (sometimes referred to as a precursor) containing a metal element constituting the film-forming target (here, the oxide semiconductor 15) and an oxidizing agent constitutes one cycle, forming one atomic layer in one cycle, and repeating this cycle until a desired film thickness is reached. Therefore, by using ALD, a dense oxide semiconductor 15 can be formed even in a region near the second electrode 12, away from the opening, in the through-hole where the second insulating film 16 is formed.

[0047] One ALD atomic layer deposition cycle may include the following four steps: (1) The precursor (precursor), which is the raw material, is vaporized in a container and introduced into a chamber, where it is reacted with OH groups on the substrate surface or film surface under a predetermined system pressure for a predetermined time, resulting in monomolecular adsorption. If the vapor pressure of the precursor is low, the container containing the precursor may be heated to promote vaporization, and if the vapor pressure of the precursor is high, the container containing the precursor may be cooled to suppress vaporization. (2) Unreacted raw materials and by-product gases are removed from the chamber by purging with an inert gas, and one atomic layer is deposited. (3) A reactive gas is introduced into the chamber, and the precursor metal is oxidized using heat, plasma, or the like. (4) Unreacted oxidant and by-product gases are removed by purging with an inert gas. After step (4), the process may return to step (1), and steps (1) to (4) may be repeated until the desired film thickness is achieved.

[0048] Various ALD devices can be used when performing ALD. Specific examples include devices that can supply a precursor by bubbling and devices with a vaporization chamber. Other examples include devices that can perform plasma processing on a reactive gas (oxidizer). The ALD device is not limited to a single-wafer device equipped with a deposition chamber, and devices that can process multiple wafers simultaneously using a batch furnace may also be used.

[0049] Types of ALD precursors include organometallics (e.g., AlMe3), metal hydrides (e.g., AsH3), metal alkoxides (e.g., Ti(OCHMe2)4), metal amides (e.g., Ti(NMe2)4), β-diketonates (e.g., Co(acac)2), metallocenes (e.g., MgCp2), metal amidinates, and others. Various metal compounds that can be used as ALD precursors are commercially available, and it is sufficient to select a precursor and an oxidizing agent that can form the target film to be formed.

[0050] Examples of the precursor include compounds of silicon or a metal with one or more compounds selected from the group consisting of compounds used as organic ligands, such as alkyl compounds, alcohol compounds, glycol compounds, β-diketone compounds, cyclopentadiene compounds, and organic amine compounds.

[0051] Examples of metal species of the precursor include lithium, sodium, potassium, magnesium, calcium, strontium, barium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, manganese, iron, ruthenium, cobalt, rhodium, iridium, nickel, palladium, platinum, copper, silver, gold, zinc, boron, aluminum, silicon, indium, gallium, germanium, tin, lead, antimony, bismuth, scandium, ruthenium, yttrium, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium.

[0052] When the oxide semiconductor 15 contains an indium atom (In), a precursor containing In may be used. When the oxide semiconductor 15 contains another metal, a precursor containing that metal may be used. When forming an oxide semiconductor using two or more metals, there are two methods: a method in which each component is vaporized and supplied independently (sometimes referred to as the "single-source method"), and a method in which a multi-component raw material is mixed in advance to a desired composition and a mixed raw material is vaporized and supplied (sometimes referred to as the "cocktail source method"). In the single-source method, the precursors used preferably have similar thermal and / or oxidative decomposition behavior. In the cocktail source method, the precursors preferably have similar thermal and / or oxidative decomposition behavior and are not subject to deterioration due to chemical reactions or the like when mixed.

[0053] Compounds that can be used as organic ligands for the precursor include the following. Depending on the valence of the central metal, multiple ligands selected from the following may be coordinated. When multiple ligands are coordinated to the central metal in the precursor, these multiple ligands may be the same, or two or more types of ligands may be combined.

[0054] Examples of alkyl compounds used as organic ligands of the precursor include methyl, ethyl, propyl, isopropyl, butyl, sec-butyl, isobutyl, tert-butyl, pentyl, isopentyl, and tert-pentyl.

[0055] Alcohol compounds usable as organic ligands of the precursor include alkyl alcohols such as methanol, ethanol, propanol, isopropyl alcohol, butanol, sec-butyl alcohol, isobutyl alcohol, tert-butyl alcohol, pentyl alcohol, isopentyl alcohol, and tert-pentyl alcohol; 2-methoxyethanol, 2-ethoxyethanol, 2-butoxyethanol, 2-(2-methoxyethoxy)ethanol, 2-methoxy-1-methylethanol, 2-methoxy-1,1-dimethylethanol, 2-ethoxy-1,1-dimethylethanol, 2-isopropoxy-1,1-dimethylethanol, and 2-butoxyethanol; ether alcohols such as 2-(2-methoxyethoxy)-1,1-dimethylethanol, 2-propoxy-1,1-diethylethanol, 2-s-butoxy-1,1-diethylethanol, and 3-methoxy-1,1-dimethylpropanol; and dialkylamino alcohols such as dimethylaminoethanol, ethylmethylaminoethanol, diethylaminoethanol, dimethylamino-2-pentanol, ethylmethylamino-2-pentanol, dimethylamino-2-methyl-2-pentanol, ethylmethylamino-2-methyl-2-pentanol, and diethylamino-2-methyl-2-pentanol.

[0056] Examples of glycol compounds used as organic ligands for the precursor include 1,2-ethanediol, 1,2-propanediol, 1,3-propanediol, 2,4-hexanediol, 2,2-dimethyl-1,3-propanediol, 2,2-diethyl-1,3-propanediol, 1,3-butanediol, 2,4-butanediol, 2,2-diethyl-1,3-butanediol, 2-ethyl-2-butyl-1,3-propanediol, 2,4-pentanediol, 2-methyl-1,3-propanediol, 2-methyl-2,4-pentanediol, 2,4-hexanediol, and 2,4-dimethyl-2,4-pentanediol.

[0057] The β-diketone compounds used as organic ligands for the precursors include acetylacetone, hexane-2,4-dione, 5-methylhexane-2,4-dione, heptane-2,4-dione, 2-methylheptane-3,5-dione, 5-methylheptane-2,4-dione, 6-methylheptane-2,4-dione, 2,2-dimethylheptane-3,5-dione, 2,6-dimethylheptane-3,5-dione, 2,2,6-trimethylheptane-3,5-dione, 2,2,6,6-tetramethylheptane-3,5-dione, octane-2,4-dione, 2,2,6-trimethyloctane-3,5-dione, 2,6-dimethyloctane-3,5-dione, 2,9-dimethylnonane-4,6-dione, and 2-methyl-6-ethyl alkyl-substituted β-diketones such as decane-3,5-dione and 2,2-dimethyl-6-ethyldecane-3,5-dione; fluorine-substituted alkyl β-diketones such as 1,1,1-trifluoropentane-2,4-dione, 1,1,1-trifluoro-5,5-dimethylhexane-2,4-dione, 1,1,1,5,5,5-hexafluoropentane-2,4-dione and 1,3-diperfluorohexylpropane-1,3-dione; and ether-substituted β-diketones such as 1,1,5,5-tetramethyl-1-methoxyhexane-2,4-dione, 2,2,6,6-tetramethyl-1-methoxyheptane-3,5-dione and 2,2,6,6-tetramethyl-1-(2-methoxyethoxy)heptane-3,5-dione.

[0058] Examples of cyclopentadiene compounds used as organic ligands of the precursor include cyclopentadiene, methylcyclopentadiene, ethylcyclopentadiene, propylcyclopentadiene, isopropylcyclopentadiene, butylcyclopentadiene, sec-butylcyclopentadiene, isobutylcyclopentadiene, tert-butylcyclopentadiene, dimethylcyclopentadiene, and tetramethylcyclopentadiene.

[0059] Examples of organic amine compounds used as organic ligands of the precursor include methylamine, ethylamine, propylamine, isopropylamine, butylamine, sec-butylamine, tert-butylamine, isobutylamine, dimethylamine, diethylamine, dipropylamine, diisopropylamine, ethylmethylamine, propylmethylamine, and isopropylmethylamine.

[0060] Alternatively, metal halide compounds (e.g., InCl3, InBr3, InF3, etc.) may be used as precursors. When multiple halogens are coordinated to a metal, these halogens may be the same or two or more halogens may be combined. In addition, some of the halogens may be replaced with hydrogen.

[0061] Examples of indium-containing precursors include InCl3, TMIn (trimethyl indium), TEIn (triethyl indium), InCp (cyclopentadienyl indium(I)), InEtCp (ethylcyclopentadienyl indium(I)), In(acac)3 (indium acetylacetonate), In(tmhd)3 (indium 2,2,6,6-tetramethyl-3,5-heptanedionate), In[( iPrN)2CNR2]3(R=Me)(indium-tris-guanidinates), Et2InN(TMS)2(diethyl[bis-(trimethylsilyl)amido]indium), INCA(diethyl[1,1,1-trimethyl-N-(trimethylsilyl)silanaminato]indium), DADI([3-(dimethylamino)propyl]dimethyl In(dmamp)3((1-dimethylamino-2-methyl-2-propoxy)indium), Me2In(EDPA)(dimethyl(N-ethoxy-2,2-dimethylpropanamido)indium), tris(N,N'-diisopropylacetamidinato)indium(III), and the like.

[0062] These ALD precursors may be used alone or in combination of two or more.

[0063] The precursors described above can be produced according to known production methods. For example, when an alcohol compound is used as the organic ligand, the precursor can be produced by reacting the inorganic salt of the metal or a hydrate thereof described above with an alkali metal alkoxide of the alcohol compound. Examples of inorganic salts of metals or hydrates thereof include metal halides and nitrates. Examples of alkali metal alkoxides include sodium alkoxides, lithium alkoxides, and potassium alkoxides.

[0064] Examples of oxidizing agents used in ALD include H2O, O2, O3, O2 plasma, H2O plasma, hydrogen peroxide (H2O2), etc. These oxidizing agents may be used alone or in combination of two or more.

[0065] When two or more oxidizing agents are used, they may be used simultaneously or individually while changing the oxidizing agents. For example, by using two oxidizing agents, O2 plasma and H2O plasma, it is possible to take advantage of both the high mobility obtained by using O2 plasma and the carbon concentration reduction and improved stability of mobility against heat treatment obtained by using H2O plasma. By using two or more oxidizing agents, it is possible to adjust the high mobility and low carbon concentration. Depending on the desired effect, the ratio of O2 plasma and H2O plasma used, the order of use, the number of cycles, etc. can be appropriately selected.

[0066] The pressure of the system (inside the film formation chamber) in step (1) may be set appropriately depending on the type of precursor, the substrate temperature, etc., and is, for example, preferably 1 to 10,000 Pa, more preferably 10 to 1,000 Pa, even more preferably 50 to 500 Pa, and particularly preferably 80 to 120 Pa.

[0067] In one embodiment, H2O plasma is used as an oxidizing agent in the film formation process. In one embodiment, O2 plasma is used as an oxidizing agent in the film formation process. In one embodiment, O3 is used as the oxidizing agent in the deposition process. Use of these oxidizing agents provides an effect of enabling the electrical characteristics of the oxide semiconductor film to be controlled to a favorable state.

[0068] To vaporize the precursor, the vessel containing the precursor may be heated to a temperature sufficient to vaporize the precursor, or, if a precursor with a high vapor pressure is used, the vessel may be cooled. In one embodiment, a container containing the indium-containing precursor (for example, triethylindium) is heated to a temperature in the range of 25 to 150°C. The temperature is preferably in the range of 50 to 150°C, more preferably 75 to 125°C.

[0069] In the above-mentioned production method, the substrate temperature during film formation is usually within the range of 50 to 600°C, preferably 85 to 500°C, more preferably 80 to 350°C, and even more preferably 100 to 250°C.

[0070] The growth amount of the oxide semiconductor film per cycle of the ALD process varies depending on the precursor and reactive gas used during film formation, as well as the substrate temperature during film formation.

[0071] The growth amount per cycle of the ALD process is called the growth per cycle (GPC), and can be calculated by measuring the film thickness of the oxide semiconductor after repeating, for example, 30 ALD cycles. Here, the GPC varies depending on the combination of precursor, oxidant, and substrate temperature, and also varies depending on the type of substrate. Therefore, the number of cycles varies depending on many factors such as the types and combinations of precursors and oxidizing agents used, the type of substrate, the substrate temperature during film formation, and the desired film thickness, and can be set appropriately taking these factors into consideration.

[0072] When O3 is used as the oxidizing agent, the substrate temperature during film formation is preferably above 100°C, more preferably 110 to 250°C, 120 to 230°C, or 130 to 220°C. When H2O plasma and O2 plasma are used as the oxidizing agent, the substrate temperature during film formation is preferably 100 to 150°C.

[0073] Examples of inert gases that can be used to purge unreacted raw materials and unreacted oxidizing agent include argon and nitrogen, and in the method of this embodiment, argon or nitrogen is preferred.

[0074] In the above step (3), it is preferable to generate plasma of the reactive gas (oxidant).

[0075] (Second embodiment) Next, another example (second embodiment) of the transistor according to this aspect will be described with reference to FIGS. Fig. 4 is a schematic perspective view showing a cross section of a transistor according to the second embodiment, and Fig. 5 is a schematic cross-sectional view of the transistor. 4 and 5, the same reference numerals as in FIGS. 1 and 2 indicate the same components, and unless otherwise specified, the explanation given in relation to FIGS. 1 and 2 is applicable.

[0076] In the second embodiment, the transistor 10 includes a first electrode 11, a second electrode 12, a third electrode 13, an oxide semiconductor 15, a first insulating film 14a, a third insulating film 14b, and a second insulating film 16. The first electrode 11 and the second electrode 12 are stacked with at least the first insulating film 14a (here, the first insulating film 14a and the third insulating film 14b) interposed therebetween. At least a part of the first insulating film 14a (here, the first insulating film 14a and the third insulating film 14b) may be interposed between the first electrode 11 and the second electrode 12. The third electrode 13 is located between the first electrode 11 and the second electrode 12 .

[0077] Of the first insulating film 14a and the third insulating film 14b, the first insulating film 14a is located between the first electrode 11 and the third electrode 13. As a result, the first electrode 11 and the third electrode 13 are electrically insulated from each other by the first insulating film 14a. Furthermore, the third insulating film 14b is located between the second electrode 12 and the third electrode 13. As a result, the second electrode 12 and the third electrode 13 are electrically insulated from each other by the third insulating film 14b.

[0078] 2, the third electrode 13 is disposed between the first insulating film 14a and the third insulating film 14b, but the first insulating film 14a and the third insulating film 14b may be in contact with each other and form a single layer outside the region shown in Fig. 2. In this case, the third electrode 13 does not need to be disposed between the first insulating film 14a and the third insulating film 14b in that region.

[0079] The oxide semiconductor 15 is provided so as to penetrate at least the first insulating film 14a and connect the first electrode 11 and the second electrode 12. The oxide semiconductor 15 may penetrate the third electrode 13 in addition to the first insulating film 14a and the third insulating film 14b. Here, the oxide semiconductor 15 is provided in a columnar shape, penetrating the first insulating film 14a, the third electrode 13, and the third insulating film 14b in this order. In this case, the third electrode 13 preferably surrounds the entire periphery of the side of the oxide semiconductor 15 (the periphery in the direction perpendicular to the length direction) in a portion of the oxide semiconductor 15 in the length direction (the central portion in the example of FIG. 2 ), via the second insulating film 16 described below. This makes it easier to prevent leakage current even if the channel length of the oxide semiconductor 15, described below, is shortened. At the same time, this is advantageous in terms of miniaturization. The length direction of the oxide semiconductor 15 referred to here may be the vertical direction in FIG. 2 (the direction connecting the first electrode and the second electrode), may be the direction along the channel length described later, may be the thickness direction of a stack in which the first insulating film 14a, the third electrode 13, and the third insulating film 14b are stacked in this order, or may be the height direction of the columnar structure when the oxide semiconductor 15 is columnar.

[0080] The second insulating film 16 is provided between the third electrode 13 and the oxide semiconductor 15. The oxide semiconductor 15, the second insulating film 16, and the third electrode 13 are arranged in this order. The second insulating film 16 may be provided between the third electrode 13 and the oxide semiconductor 15 to insulate the third electrode 13 from the oxide semiconductor 15. The second insulating film 16 may also be provided, for example, between the first insulating film 14a and / or the third insulating film 14b and the oxide semiconductor 15, in addition to between the third electrode 13 and the oxide semiconductor 15. The second insulating film 16 is provided so as to surround the entire side surface of the pillar-shaped oxide semiconductor 15 .

[0081] From one perspective, the transistor 10 can also be said to have a through-hole that penetrates a stack in the thickness direction (the vertical direction in Figures 1 and 2) of the stack, in which the first insulating film 14a, the third electrode 13, and the third insulating film 14b are stacked in this order, the inner surface of the through-hole is covered with a cylindrical second insulating film 16, and the inside of the cylindrical second insulating film 16 is filled with an oxide semiconductor 15.

[0082] In the second embodiment, the transistor 10 also has a small cross-sectional area region 151 between the first electrode 11 and the second electrode 12 (a region laterally surrounded by the third electrode 13 in the second embodiment). The cross-sectional area of the small cross-sectional area region 151, when cut along a plane perpendicular to the channel length direction, is smaller than the cross-sectional areas of the regions 152 and 153 on both sides of the small cross-sectional area region 151 in the channel length direction. This increases the resistance (which increases as the cross-sectional area decreases) in the channel region formed between the first electrode 11 and the second electrode 12, thereby preventing off-leakage and achieving a favorable normally-off state. On the other hand, the regions 152 and 153 on both sides of the small cross-sectional area region, which extend to the first electrode 11 and the second electrode 12, have a larger cross-sectional area and a lower resistance than the small cross-sectional area region 151, thereby ensuring favorable conduction between the oxide semiconductor 15 and the first electrode 11 and the second electrode 12. Also, in the transistor 10 of the second embodiment, the first electrode 11 and the second electrode 12 are stacked with at least the first insulating film 14 interposed therebetween. By having such a structure (vertical structure) for the transistor 10, it is possible to arrange a plurality of transistors 10 at high density in, for example, a semiconductor memory device, which also contributes to miniaturization of the semiconductor memory device. When the channel length becomes shorter as the semiconductor memory device (or transistor) becomes smaller, it has been difficult to achieve a normally-off state with conventional technology. However, according to the present embodiment, even in such a case, it is possible to satisfactorily achieve a normally-off state as described above.

[0083] In the example of FIGS. 4 and 5 (second embodiment), the small cross-sectional area region 151 is located in a region where the oxide semiconductor 15 is adjacent to the third electrode 13 with the insulating film 16 interposed therebetween.

[0084] In the second embodiment, a small cross-sectional area region 151 is formed by providing a recess in the surface of the oxide semiconductor 15 facing the third electrode 13. Specifically, the small cross-sectional area region 151 is formed by providing a recess along the circumferential direction in a region facing the third electrode 13 on the outer peripheral surface of the columnar oxide semiconductor 15. The second insulating film 16 may have a portion that protrudes toward this recess. The third electrode 13 may also have a portion that protrudes toward this recess. In one embodiment, when the cross-sectional area of small cross-sectional area region 151 is a, the cross-sectional area of one of the two side regions 152 is b, and the cross-sectional area of the other of the two side regions 153 is c, the conditions of 1.1≦a / b≦20 and 1.1≦a / c≦20 are satisfied. The value of a / b and / or a / c may be 1.2 or more and 15 or less, or 1.5 or more and 10 or less. In one embodiment, the cross-sectional area of the small cross-sectional area region 151 is 12 to 90,000 nm 2 is. In one embodiment, the cross-sectional areas of the regions 152 and 153 on both sides of the small cross-sectional area region 151 are 15 to 300,000 nm 2 is.

[0085] The method for manufacturing the transistor 10 according to the second embodiment is not particularly limited, and the transistor 10 can be manufactured by a known method while referring to the manufacturing method according to the first embodiment. For example, the transistor 10 according to the second embodiment may be manufactured as follows. An oxide semiconductor 15, a second electrode 12, and an insulating film 19 supporting the second electrode 12 are formed. Next, a third insulating film 14b, a third electrode 13, and a first insulating film 14a are formed in this order. Next, a through-hole is formed by etching so as to penetrate the first insulating film 14a, the third electrode 13, and the third insulating film 14b. Next, a second insulating film 16 is formed. Next, an oxide semiconductor 15 is formed in the through-hole in which the second insulating film 16 has been formed. Next, a first electrode 11 is formed on the oxide semiconductor 15. Here, the small cross-sectional area region 151 can be formed, for example, by etching a through-hole that penetrates the first insulating film 14a, the third electrode 13, and the third insulating film 14b, using an etching gas whose etching rate for the third electrode 13 is slower than that for the first insulating film 14a and the third insulating film 14b. As a result, the third electrode 13 is formed in a convex shape that protrudes toward the center of the through-hole, and the second insulating film 16 formed on the inner surface of the through-hole also has a convex portion that protrudes toward the center of the through-hole. By forming an oxide semiconductor 15 in the through-hole with such second insulating film 16 formed therein, the small cross-sectional area region 151 can be formed at a position corresponding to the convex portion of the second insulating film 16.

[0086] In the second embodiment, the second insulating film 16 entirely surrounds the side surfaces of the oxide semiconductor 15 provided in a columnar shape. However, this is not necessarily limited to this. For example, the second insulating film 16 may surround at least a portion of the oxide semiconductor 15 provided in a columnar shape.

[0087] In the second embodiment, the dimensions of the transistor 10 may also be designed appropriately depending on the application and the like. The channel length of the oxide semiconductor 15 is, for example, 1 nm to 10 μm, preferably 2 to 1000 nm, more preferably 3 to 100 nm, even more preferably 4 to 50 nm, still more preferably 5 to 30 nm, and still more preferably 6 to 20 nm. The channel length of the oxide semiconductor 15 is the length of the oxide semiconductor 15 along the thickness direction (the vertical direction in FIGS. 4 and 5 ) of the stack in which the first insulating film 14a, the third electrode 13, and the third insulating film 14b are stacked in this order, and may be equal to the distance between the first electrode 11 and the second electrode 12. When the oxide semiconductor 15 is columnar, the channel length of the oxide semiconductor 15 corresponds to the height of the columnar structure. The channel length of the oxide semiconductor 15 may be measured in the same manner as in the first embodiment.

[0088] The channel length of the oxide semiconductor 15 is not particularly limited, but is preferably 1 to 1000 nm, more preferably 1 to 500 nm, and even more preferably 2 to 500 nm. The "channel length" of the oxide semiconductor 15 is the distance (length) between the first electrode 11 and the second electrode 12 connected by the oxide semiconductor 15, which is the channel.

[0089] The thickness of the second insulating film 16 is, for example, 1 Å to 500 nm, preferably 1 nm to 100 nm. In order to prevent the capacitance of the second insulating film 16 from becoming a parasitic component, the thickness of the second insulating film 16 may be set to 50 nm or less, 10 nm or less, or 2 nm or less within the above range. The thickness of the second insulating film 16 of the oxide semiconductor 15 may be measured in the same manner as the channel length of the oxide semiconductor 15 .

[0090] The descriptions in the first embodiment may be used for the first electrode 11, the second electrode 12, the third electrode 13, and the oxide semiconductor 15. The descriptions in the first embodiment for the first insulating film 14 may be used for the first insulating film 14a and the third insulating film 14b.

[0091] (Third embodiment) Next, still another example (third embodiment) of the transistor according to this aspect will be described with reference to FIGS. Fig. 6 is a schematic perspective view showing a cross section of a transistor according to the third embodiment, and Fig. 7 is a schematic cross-sectional view of the transistor. 6 and 7, the same reference numerals as in FIGS. 1 and 2 indicate the same components, and unless otherwise specified, the explanation given in relation to FIGS. 1 and 2 is applicable.

[0092] In the third embodiment, a transistor 10 includes a first electrode 11, a second electrode 12, a third electrode 13, oxide semiconductors 15 and 15′, and a first insulating film 14. The third electrode 13 is located between the first electrode 11 and the second electrode 12 . The first insulating film 14 is located between the first electrode 11 and the third electrode 13. Here, the first electrode 11 and the second electrode 12 are stacked with the first insulating film 14 interposed therebetween. As a result, the first electrode 11 and the second electrode 12 are electrically insulated by the first insulating film 14. The third electrode 13 is provided adjacent to the oxide semiconductors 15, 15' without contacting them. Specifically, the third electrode 13 is adjacent to the oxide semiconductors 15, 15' via the first insulating film 14 located between the third electrode 13 and the oxide semiconductors 15, 15'. In this sense, it can be said that the first insulating film 14 in the third embodiment also plays the role of the second insulating film 16 in the first and second embodiments.

[0093] The oxide semiconductors 15 and 15' connect the first electrode 11 and the second electrode 12, respectively.

[0094] In the third embodiment, the transistor 10 also has an oxide semiconductor 15 having a small cross-sectional area region 151 between the first electrode 11 and the second electrode 12. The cross-sectional area of the small cross-sectional area region 151, when cut along a plane perpendicular to the channel length direction, is smaller than the cross-sectional areas of regions 152 and 153 on both sides of the small cross-sectional area region 151 in the channel length direction. Similarly, the oxide semiconductor 15′ has a small cross-sectional area region 151′ between the first electrode 11 and the second electrode 12. The cross-sectional area of the small cross-sectional area region 151′, when cut along a plane perpendicular to the channel length direction, is smaller than the cross-sectional areas of regions 152′ and 153′ on both sides of the small cross-sectional area region 151′ in the channel length direction. This increases the resistance (which increases as the cross-sectional area decreases) in the channel region formed between the first electrode 11 and the second electrode 12, thereby preventing off-leakage and achieving a normally-off state. On the other hand, the regions 152, 153 (152', 153') on both sides of the small cross-sectional area region, which continue to the first electrode 11 and the second electrode 12, have a larger cross-sectional area and a lower resistance value than the small cross-sectional area region 151 (151'), thereby ensuring good conductivity between the oxide semiconductor 15 (15') and the first electrode 11 and the second electrode 12. Also, in the transistor 10 of the second embodiment, the first electrode 11 and the second electrode 12 are stacked with at least the first insulating film 14 interposed therebetween. By having such a structure (vertical structure) for the transistor 10, it is possible to arrange a plurality of transistors 10 at high density in, for example, a semiconductor memory device, which also contributes to miniaturization of the semiconductor memory device. When the channel length becomes shorter as the semiconductor memory device (or transistor) becomes smaller, it has been difficult to achieve a normally-off state with conventional technology. However, according to the present embodiment, even in such a case, it is possible to satisfactorily achieve a normally-off state as described above.

[0095] In the examples of FIGS. 6 and 7 (third embodiment), the small cross-sectional area regions 151, 151' are located in regions where the oxide semiconductors 15, 15' are adjacent to the third electrode 13 with the insulating film 14 interposed therebetween.

[0096] In the third embodiment, a small cross-sectional area region 151 is formed by providing a recess in the surface of the oxide semiconductor 15 facing the third electrode 13. Specifically, the small cross-sectional area region 151 is formed by providing a recess in the region of the plate-shaped oxide semiconductor 15, 15′ facing the third electrode 13. The first insulating film 14 may have a portion that protrudes toward the recess. In one embodiment, when the cross-sectional area of the small cross-sectional area region 151 (151') is a, the cross-sectional area of one of the two regions 152 (152') is b, and the cross-sectional area of the other of the two regions 153 (153') is c, the conditions of 1.1≦a / b≦20 and 1.1≦a / c≦20 are satisfied. The value of a / b and / or a / c may be 1.2 or more and 15 or less, or 1.5 or more and 10 or less. In one embodiment, the cross-sectional area of the small cross-sectional area region 151 (151') is 12 to 90,000 nm 2 is. In one embodiment, the cross-sectional areas of the regions 152 (152') and 153 (153') on both sides of the small cross-sectional area region 151 (151') are each 15 to 300,000 nm 2 is.

[0097] The dimensions of the transistor 10 may be appropriately designed depending on the application and the like. The channel length of the oxide semiconductors 15, 15′ is, for example, 1 nm to 10 μm, preferably 2 nm to 1000 nm. The channel length of the oxide semiconductor 15 is the length of the oxide semiconductors 15, 15′ in the thickness direction (the vertical direction in FIGS. 6 and 7 ) of the stack in which the first electrode 11, the first insulating film 14, and the second electrode 12 are stacked in this order, and may be equal to the distance between the first electrode 11 and the second electrode 12.

[0098] The thickness of the first insulating film 14 is, for example, 1 Å to 500 nm, preferably 1 nm to 100 nm. In order to prevent the capacitance of the first insulating film 14 from becoming a parasitic component, the thickness of the first insulating film 14 may be 50 nm or less, 10 nm or less, or 2 nm or less.

[0099] The channel lengths of the oxide semiconductors 15 and 15' and the thickness of the first insulating film 14 may be measured by the same method as in the first embodiment.

[0100] The descriptions in the first and second embodiments may be used for the first electrode 11, the second electrode 12, the third electrode 13, the first insulating film 14, and the oxide semiconductor 15. The descriptions in the first and second embodiments for the second insulating film 16 may be used for the first insulating film 14.

[0101] The manufacturing method of the transistor 10 according to the third embodiment is not particularly limited, and it can be manufactured by referring to the manufacturing method according to the first embodiment and by referring to known methods (for example, the methods described in International Publication No. 2020 / 076850, etc.). The descriptions in the first and second embodiments may be used to refer to the methods for forming the first electrode 11, the second electrode 12, the third electrode 13, the first insulating film 14, and the oxide semiconductor 15. The descriptions in the first and second embodiments for the method for forming the first insulating film 14 may be used to refer to the method for forming the second insulating film 16. Here, the small cross-sectional area regions 151, 151' can be formed, for example, by forming a portion of the oxide semiconductor 15, 15' (a portion of the oxide semiconductor 15, 15' that does not include the upper region 152 and does not yet have the notches for forming the small cross-sectional area regions 151, 151') and then forming trenches by etching. The notches for forming the small cross-sectional area regions 151, 151' are formed along with the trench formation. The lower regions 153, 153' of the portion of the oxide semiconductor 15, 15' are the deepest portions, and therefore the inner diameter of the trench is relatively small. As a result, the cross-sectional area of the lower regions 153, 153', when cut along a plane perpendicular to the channel length direction, is larger than that of the small cross-sectional area regions 151, 151'. Next, the first insulating film 14 (a portion not including the upper region) and the third electrode 13 are formed in this order. Next, an additional oxide semiconductor is formed on the portion of the oxide semiconductors 15, 15', the first insulating film 14 (excluding the upper region), and the third electrode 13, and a trench having a smaller diameter than the trench (the trench used to form the small cross-sectional area regions 151, 151') is formed in the additional oxide semiconductor. This cuts out the additional oxide semiconductor, forming upper regions 152, 152' of the oxide semiconductors 15, 15'. By forming the small trenches as described above, the cross-sectional area of the upper regions 152, 152' when cut along a plane perpendicular to the channel length direction becomes larger than that of the small cross-sectional area regions 151, 151'. Next, an upper region of the first insulating film 14 is formed in the trench. In this manner, the small cross-sectional area regions 151, 151' can be formed.

[0102] 2. Semiconductor devices A semiconductor device according to an aspect of the present invention includes a transistor according to an aspect of the present invention. The semiconductor device according to this embodiment has high reliability because it includes a transistor that can satisfactorily achieve normally-off operation. The type of semiconductor device is not particularly limited, but from the viewpoint of significantly exhibiting the above-mentioned effects, semiconductor memory devices such as volatile memories such as DRAM (Dynamic Random Access Memory) and SRAM (Static RAM) and nonvolatile memories such as mask ROM (Read Only Memory), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), flash memory (NOR flash memory, NAND flash memory), MRAM (Magnetoresistive RAM), FeRAM (Ferroelectric RAM), ReRAM (Resistive RAM) are preferred. Alternatively, the semiconductor device according to this embodiment may be a logic device such as TTL (Transistor-Transistor Logic), CMOS (Complementary Metal-Oxide-Semiconductor), BiCMOS, PLD (Programmable Logic Device), FPGA (Field Programmable Gate Array), CPU (Central Processing Unit), or MPU (Microprocessor Unit). Furthermore, since a transistor according to one aspect of the present invention can have a vertical structure as shown in each embodiment, it is suitable for arranging multiple transistors at high density in a semiconductor memory device, which also contributes to miniaturization of the semiconductor memory device. Furthermore, the transistor according to one embodiment of the present invention tends to have a small leakage current because an oxide semiconductor is used for the channel. Therefore, by using the transistor according to one embodiment of the present invention in a semiconductor memory device, the capacitance of a capacitor can be reduced or the capacitor can be omitted. As a result, the use of the transistor according to one embodiment of the present invention enables miniaturization of the semiconductor memory device.

[0103] A semiconductor device may include a large number of transistors. For example, a DRAM includes hundreds of millions of memory cells, and the number of transistors that make up the memory cells is also hundreds of millions. Furthermore, a DRAM also uses multiple transistors in addition to the memory cells. According to this aspect, it is possible to suppress variations in the performance of each transistor, and it is also possible to effectively suppress variations in the operation of the semiconductor device.

[0104] FIG. 8 is a diagram illustrating an example of a circuit configuration of a semiconductor memory device including a transistor according to one embodiment of the present invention. As shown in FIG. 8, a semiconductor memory device 50 includes a transistor 10, a capacitor 51, a word line WL, and a bit line BL. The source electrode of the transistor 10 is connected to a bit line BL. The drain electrode of the transistor 10 is connected to one end of a capacitor 51. The gate electrode of the transistor 10 is connected to a word line WL. The other end of the capacitor 51 is grounded. The bit line BL may be connected to a first electrode 11 of the transistor 10 and may be connected to a second electrode 12. The word line WL may be connected to a third electrode 13 of the transistor 10. One end of the capacitor 51 may be connected to the first electrode 11 of the transistor 10 and may be connected to the second electrode 12.

[0105] 8, one memory cell 52 is formed by the transistor 10 and a capacitor 51. The memory cell 52 can store data based on the charge held by the capacitor 51. Note that the configuration of the memory cell 52 is not limited to this example, and in other examples, the capacitor 51 is omitted. When the capacitor 51 is omitted, data can be stored based on the charge held in the transistor 10 itself. Also, the memory cell 52 may be configured by combining two or more transistors. When the transistor 10 itself is to have the function of retaining charge, for example, one or more of the configurations described below can be applied. (1) For the second insulating film, a high dielectric constant insulator such as hafnium oxide (HfO2) or zirconium oxide (ZrO2) is used. (2) For the second insulating film, a ferroelectric material such as (Pb,La)(Zr,Ti)O3 (PLZT), SrTiO3 (STO), or yttria-stabilized zirconia (YSZ) is used. (3) An element that forms a level in the gap of an oxide semiconductor is added to the oxide semiconductor, and hysteresis is utilized. (4) A parasitic capacitance is utilized when a part of the source electrode and / or drain electrode and a part of the gate electrode are arranged so as to face each other with an insulating film interposed therebetween. In the above (4), for example, a parasitic capacitance can be utilized when a part of one of the source electrode and the drain electrode is disposed so as to face a part of the gate electrode via an insulating film. In this case, the other of the source electrode and the drain electrode can be disposed away from the gate electrode (for example, the distance between the other of the source electrode and the drain electrode and the gate electrode can be longer than the distance between the one of the source electrode and the drain electrode and the gate electrode).

[0106] The semiconductor memory device 50 can read data stored in the memory cells 52 onto the bit lines BL by controlling the word lines WL, and can also write data transferred to the bit lines BL into the memory cells 52. The semiconductor memory device 50 includes a memory cell array (not shown) made up of a plurality of memory cells 52. [Explanation of symbols]

[0107] 10: Transistor 11: 1st electrode 12:Second electrode 13: Third electrode 14, 14a: first insulating film 14b: third insulating film 15, 15': oxide semiconductor 151, 151': Small cross-sectional area area 152, 152', 153, 153': Areas (on both sides of the small cross-sectional area) 16: Second insulating film 19: insulating film 50: Semiconductor memory device 51: Capacitor 52: Memory cell WL: Word line BL: bit line

Claims

1. a first electrode and a second electrode; an oxide semiconductor connecting the first electrode and the second electrode; a third electrode adjacent to but not in contact with the oxide semiconductor; Equipped with the first electrode and the second electrode are stacked with at least a first insulating film interposed therebetween, the oxide semiconductor has a small cross-sectional area region between the first electrode and the second electrode, and a cross-sectional area of the small cross-sectional area region when cut along a plane orthogonal to a channel length direction is smaller than the cross-sectional areas of each of the regions on both sides of the small cross-sectional area region in the channel length direction; Transistor.

2. 2. The transistor according to claim 1, wherein when the cross-sectional area of the small cross-sectional area region is a, the cross-sectional area of one of the two side regions is b, and the cross-sectional area of the other of the two side regions is c, the conditions of 1.1≦a / b≦20 and 1.1≦a / c≦20 are satisfied.

3. The cross-sectional area of the small cross-sectional area region is 12 to 90,000 nm ２ 3. The transistor according to claim 1, wherein:

4. 3 . The transistor according to claim 1 , wherein the small cross-sectional area region is formed by providing a recess in a surface of the oxide semiconductor on the third electrode side or on a surface opposite to the third electrode side.

5. The transistor according to claim 1 , wherein the oxide semiconductor penetrates at least the first insulating film to connect the first electrode and the second electrode.

6. The transistor according to claim 1 , further comprising a second insulating film provided between the third electrode and the oxide semiconductor.

7. the first electrode and the second electrode are stacked with the first insulating film interposed therebetween, the oxide semiconductor has a cylindrical portion that penetrates the first insulating film, a second insulating film provided between the third electrode and the oxide semiconductor; the second insulating film has a cylindrical portion provided on an inner wall of the cylindrical portion of the oxide semiconductor; the third electrode has a portion provided inside the cylindrical portion of the second insulating film; 3. The transistor according to claim 1 or 2.

8. The transistor according to claim 7 , wherein the oxide semiconductor has the small cross-sectional area region in a portion that penetrates the first insulating film.

9. 8. The transistor according to claim 7, wherein the oxide semiconductor penetrates the first insulating film while being in contact with the first insulating film, and the small cross-sectional area region is formed by providing a recess on a surface of the oxide semiconductor opposite to a surface in contact with the first insulating film.

10. 8. The transistor according to claim 7, wherein the first insulating film is made of an insulating material having a lower electronegativity than each of the first electrode and the second electrode.

11. 8. The transistor according to claim 7, wherein the insulating material constituting the first insulating film has an electronegativity of 1.54 or less.

12. 8. The transistor according to claim 7, wherein the first insulating film is made of SiOC (silicon oxycarbide), SiN (silicon nitride), or AlN (aluminum nitride).

13. the first electrode and the third electrode are stacked with the first insulating film interposed therebetween, the third electrode and the second electrode are stacked with a third insulating film interposed therebetween, the oxide semiconductor is provided in a columnar shape penetrating the first insulating film, the third electrode, and the third insulating film; a second insulating film provided between the third electrode and the oxide semiconductor; the second insulating film is provided so as to surround at least a part of the oxide semiconductor provided in the pillar shape; 3. The transistor according to claim 1 or 2.

14. 3. The transistor according to claim 1, wherein the channel length of the oxide semiconductor is 1 to 1000 nm.

15. The transistor according to claim 1 , wherein the oxide semiconductor has a bixbyite structure.

16. The transistor according to claim 15 , wherein the oxide semiconductor is primarily composed of indium oxide.

17. 16. The transistor according to claim 15, wherein a ratio of indium atoms to all metal atoms contained in the oxide semiconductor is 80 atomic % or more.

18. The transistor according to claim 15 , wherein the oxide semiconductor contains indium oxide at a content of 55 mass % or more.

19. The transistor of claim 15 , wherein the oxide semiconductor further comprises Ga or Al.

20. The transistor of claim 15 , wherein the oxide semiconductor further comprises Ga.

21. The transistor of claim 15 , wherein the oxide semiconductor further comprises Ga and Al.

22. 16. The transistor according to claim 15, wherein the atomic ratio of Ga to all metal elements contained in the oxide semiconductor ([Ga] / ([Ga]+[all metal elements other than Ga])×100) is 0.5 to 25 at %.

23. 16. The transistor according to claim 15, wherein the atomic ratio of Zn to all metal elements contained in the oxide semiconductor ([Zn] / ([Zn]+[all metal elements other than Zn])×100) is 0 to 3 at %.

24. The transistor of claim 15 , wherein the oxide semiconductor is substantially free of Zn.

25. 3. The transistor according to claim 1, wherein at least one of the first electrode and the second electrode is at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), aluminum (Al), silicon (Si), iron (Fe), cobalt (Co), nickel (Ni), copper (Cu), germanium (Ge), molybdenum (Mo), ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), tantalum (Ta), iridium (Ir), platinum (Pt), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum nitride (AlN), manganese nitride (MnN), molybdenum nitride (MoN), and nickel nitride (NiN).

26. The transistor according to claim 1 , wherein the oxide semiconductor is a crystalline oxide semiconductor formed by atomic layer deposition.

27. A semiconductor device comprising the transistor of claim 1 or 2.

28. 28. The semiconductor device of claim 27, which is a semiconductor memory device.

29. a first electrode and a second electrode; an oxide semiconductor connecting the first electrode and the second electrode; a third electrode adjacent to but not in contact with the oxide semiconductor; Equipped with the first electrode and the second electrode are stacked with at least a first insulating film interposed therebetween, the oxide semiconductor has a small cross-sectional area region between the first electrode and the second electrode, and a cross-sectional area of the small cross-sectional area region when cut along a plane orthogonal to a channel length direction is smaller than the cross-sectional areas of each of regions on both sides of the small cross-sectional area region in the channel length direction; the small cross-sectional area region is formed by providing a recess on a surface of the oxide semiconductor on the third electrode side or on a surface opposite to the third electrode side, the oxide semiconductor contains indium oxide as a main component and has a bixbyite structure; the channel length of the oxide semiconductor is 1 to 1000 nm; Transistor.

Images