Pixel acquisition circuit and image sensor

Abstract

The present invention discloses a pixel acquisition circuit and an image sensor. [Solution] The image sensor includes a pixel acquisition circuit array, a global control unit, a global time signal generation unit, and a readout unit, where the pixel acquisition circuit array includes a plurality of pixel acquisition circuits, the global control unit is coupled to the pixel acquisition circuit array via a global reset signal line and is suitable for resetting the pixel acquisition circuit array when the image sensor is powered, the global time signal generation unit is coupled to the pixel acquisition circuit array via the global time signal line and is suitable for generating a global time signal representing time information, and the readout unit is coupled to the pixel acquisition circuit array via a row selection line, a row event reset signal line, a column flag bit signal line and a column time signal line and is suitable for reading out event information of the event sequence generated by the pixel acquisition circuit array.

Description

[Technical Field]

[0001] The present invention relates to the technical field of image sensors, and more particularly to new types of image sensors. [Background technology]

[0002] In many application fields of image sensors, detecting moving objects is an important point, and in this application field, dynamic vision image sensors (hereinafter referred to as dynamic vision sensors) have attracted more and more attention due to their unique advantages over traditional image sensors (such as active pixel sensors).

[0003] The pixel unit (also called the pixel acquisition circuit) designed based on bionic principles allows the dynamic visual sensor to continuously respond to changes in light intensity in the field of view in real time, without requiring any exposure time, making it easy to detect fast-moving objects. Furthermore, the dynamic visual sensor only responds to and outputs position information of the pixel unit corresponding to areas of light intensity changes in the field of view, and automatically blocks unnecessary background information, resulting in advantages such as low output data volume and low bandwidth usage. The above characteristics of the dynamic visual sensor allow the back-end image processing system to directly acquire and process useful dynamic information in the field of view, thereby significantly reducing the requirements for storage and computing power and achieving good real-time performance. Summary of the Invention [Problem to be solved by the invention]

[0004] In a typical dynamic vision sensor, a pixel unit generates an event when it detects a change in light intensity that meets a predetermined condition. Before the event is read out to the surrounding control unit, the pixel unit remains in a reset state and does not respond to changes in external light intensity. Once the event is read out, the pixel unit's reset state is released, and it becomes responsive to changes in external light intensity again. The time between the generation of an event in the pixel unit and its readout to the surrounding control unit is called the event readout delay. The readout delay causes the pixel unit to stop responding to changes in external light intensity, resulting in the dynamic vision sensor losing event information that should have been detected. This situation becomes more serious with the accelerating movement speed of objects in the field of view and the limited event processing and readout speed of the dynamic vision sensor. For the detection of some high-speed motion, the object's movement speed is fast, which is reflected as a rapid change in light intensity in the field of view. The existence of a readout delay causes the pixel unit to be unable to respond to such rapid changes, resulting in the loss of some event output. On the other hand, as the resolution of dynamic visual sensors increases, the transmission delay time of the internal wiring of the chip also increases, which fundamentally limits the speed at which the dynamic visual sensors can process and read events, resulting in a large event readout delay, making it impossible for the event information output by the dynamic visual sensors to accurately represent the true motion information, especially for high-speed motion.

[0005] In view of this, a new image sensor is needed to solve the above problems. [Means for solving the problem]

[0006] The present invention provides a novel pixel acquisition circuit and image sensor that solves or at least alleviates at least one of the problems that exist and are discussed above.

[0007] According to one aspect of the present invention, there is provided a pixel acquisition circuit, the pixel acquisition circuit including: an event generation module; a state latch; a self-timing logic; an event sequence storage module; and a readout module, wherein the event generation module is adapted to generate a trigger signal indicating an event generation when a change in intensity of light irradiated thereto satisfies a certain condition; the state latch is adapted to be set upon receiving the trigger signal; the self-timing logic is coupled to the state latch and adapted to be activated when the state latch is set, and after a predetermined period in the activated state, the event generation module is again responsive to a change in external light intensity by resetting the state latch; the event sequence storage module is coupled to the state latch and adapted to store event information of an event sequence consisting of a plurality of generated events when the state latch is set; and the readout module is coupled to the event sequence storage module and adapted to read out the event information of the event sequence stored in the event sequence storage module when a row select line is enabled.

[0008] Preferably, in the pixel acquisition circuit according to the present invention, the event information includes status information and time information of the generated event, and the event sequence storage module includes an event register group including a plurality of event registers and a time sampling group including a plurality of sampling sub-modules, wherein the event register is suitable for storing the status information of one event generated by the pixel acquisition circuit, each sampling sub-module corresponds one-to-one to each event register, and the sampling sub-module is suitable for recording the time information of the event indicated by the corresponding event register.

[0009] Preferably, in the pixel acquisition circuit according to the present invention, the readout module is coupled to the peripheral readout unit via a row selection line, a plurality of column flag bit signal lines and a plurality of column time information signal lines, and the readout module is further adapted to output status information of each event respectively via the plurality of column flag bit signal lines, and output time information of each event respectively via the plurality of column time information signal lines when the row selection line is enabled.

[0010] Preferably, in the pixel sampling circuit according to the present invention, the readout module is coupled to peripheral readout units via a row select line, a readout gate signal line, a column flag bit signal line and a column time information signal line, and the readout module is further adapted to output status information of each event via the column flag bit signal line and time information of each event via the column time information signal line under the action of the readout gate signal line when the row select line is enabled.

[0011] Preferably, in the pixel acquisition circuit according to the present invention, the sampling sub-module is coupled to a peripheral global time signal generating unit via a global time signal line, and samples the instantaneous amplitude value of the global time signal at the event generation time as the time information of the event.

[0012] Preferably, in the pixel acquisition circuit according to the present invention, the event register group includes N event registers connected in series, where N is greater than or equal to 2, the input terminal of the first event register is connected to a power supply voltage, the input terminal of each of the second to Nth event registers is connected to the output terminal of the previous event register, the clock signal of each event register is the output of the state latch, and each event register is connected to a row event reset signal line, so that it is reset when it receives a row event reset signal.

[0013] Preferably, in the pixel acquisition circuit according to the present invention, the sampling sub-module includes a first switch and a first capacitor, the first switch having a control end connected to the output end of a corresponding event register, a first end connected to the global time signal line, a second end connected to the first end of the first capacitor, and a second end of the first capacitor grounded.

[0014] Preferably, in the pixel sampling circuit according to the present invention, the event register is further adapted to indicate status information of a corresponding event through its output signal, and when the event register is reset, its output signal is at a low level, and when the event register is set, its output signal is at a high level; and when the event register is set, the sampling sub-module samples the instantaneous amplitude value of the global time signal when the first switch is turned off by the first capacitor, as the time information of the corresponding event.

[0015] Preferably, in the pixel acquisition circuit according to the present invention, the sampling sub-module includes a pulse shaper, a second switch, and a first transistor and a second capacitor connected in parallel, wherein the second switch has a control end connected to the output end of a corresponding event register via the pulse shaper, a first end connected to a global time signal line, and a second end connected to the drain of the first transistor and the first end of the second capacitor respectively, the source of the first transistor and the second end of the second capacitor being grounded, and the gate of the first transistor being connected to the row event reset signal line.

[0016] Preferably, in the pixel acquisition circuit according to the present invention, the sampling sub-module is further adapted to, when an event is generated, output a narrow pulse signal to a second switch via a pulse shaper to turn on the second switch, and sample the instantaneous amplitude value of the global time signal via a second capacitor as time information of the event.

[0017] Preferably, in the pixel acquisition circuit according to the present invention, the readout module includes a plurality of buffer sub-modules, each of which is composed of a second transistor and a third switch connected in series, and each buffer sub-module outputs the status information or time information of an event correspondingly, wherein the source of the second transistor is connected to one end of the third switch, the gate of the second transistor is connected to the output end of the event sequence storage module, the drain of the second transistor is connected to the power supply, and the control end of the third switch is connected to the row selection line, and the other end of the third switch is connected to the column flag bit signal line or the column time information signal line.

[0018] Preferably, in the pixel acquisition circuit according to the present invention, the readout module includes a plurality of buffer sub-modules each consisting of one third transistor and one fourth switch connected in series, wherein the source of the third transistor is connected to one end of the fourth switch, the gate of the third transistor is connected to the output end of the event sequence storage module, the drain of the third transistor is connected to the power supply, the control end of the fourth switch is connected to the readout gate signal line, the other end of the fourth switch is connected to one end of the fifth switch or the sixth switch, one end of the fifth switch is connected to the other end of some of the fourth switches and the other end is connected to the column flag bit signal line, and one end of the sixth switch is connected to the other end of some of the other fourth switches and the other end is connected to the column time information signal line.

[0019] Preferably, in the pixel acquisition circuit according to the present invention, the event generation module includes a photoelectric detection sub-module and a trigger generation sub-module, the photoelectric detection sub-module is adapted to monitor an optical signal irradiated thereto in real time and output a corresponding electrical signal, and the trigger generation sub-module is coupled to the photoelectric detection module and is adapted to generate a trigger signal indicating the generation of an event when the electrical signal meets a threshold condition.

[0020] According to another aspect of the present invention, there is provided an image sensor, the image sensor comprising: a pixel acquisition circuit array; a global control unit; a global time signal generation unit; and a readout unit, wherein the pixel acquisition circuit array comprises a plurality of the above-mentioned pixel acquisition circuits; the global control unit is coupled to the pixel acquisition circuit array via a global reset signal line and is adapted to reset the pixel acquisition circuit array when the image sensor is energized; the global time signal generation unit is coupled to the pixel acquisition circuit array via the global time signal line and is adapted to generate a global time signal representing time information; and the readout unit is coupled to the pixel acquisition circuit array via a row select line, a row event reset signal line, a column flag bit signal line and a column time signal line and is adapted to read out event information of the event sequence generated by the pixel acquisition circuit array.

[0021] Preferably, in the image sensor according to the present invention, the readout unit includes a row selection subunit, a column selection subunit, and a readout control subunit, wherein the row selection subunit is coupled to the pixel acquisition circuit array via a row selection line and a row event reset signal line, and the column selection subunit is coupled to the pixel acquisition circuit array via a column flag bit signal line and a column time signal line, and the readout control subunit is suitable for controlling the row selection subunit and the column selection subunit.

[0022] Preferably, in the image sensor according to the present invention, the event information includes status information and time information of the event, and the column selection subunit includes a column flag bit reading subunit and a column time information reading subunit, the column flag bit reading subunit is suitable for reading out the status information of the event via a column flag bit signal line, and the column time information reading subunit is suitable for reading out the time information of the event via a column time signal line. [Effects of the Invention]

[0023] The pixel acquisition circuit of the present invention employs self-timing logic instead of the handshake protocol control logic used in typical dynamic vision sensors. After the pixel acquisition circuit enters a trigger state, the self-timing logic is activated, and after the timing ends, the pixel acquisition circuit automatically releases the trigger state, allowing the pixel acquisition circuit to immediately respond to changes in external light intensity. In this way, the operation of the pixel acquisition circuit does not depend on the peripheral readout control logic, and it can continuously detect and generate events.

[0024] In addition, an event sequence storage module is further added to the pixel acquisition circuit, which is used to temporarily store the status information and time information of multiple events generated by the pixel acquisition circuit, and when the pixel acquisition circuit is selected by a peripheral readout unit, the event sequence information temporarily stored therein can be read out to an external unit.

[0025] An image sensor based on this pixel acquisition circuit does not miss any event detection due to readout delays, and because it is not sensitive to readout delays, the operating speed of the readout units around the pixel acquisition circuit array can be correspondingly reduced, thereby further reducing the power consumption of the image sensor. [Brief explanation of the drawings]

[0026] To the accomplishment of the foregoing and related ends, certain illustrative aspects are described herein in conjunction with the following description and the annexed drawings, which illustrate various forms in which the principles disclosed herein may be practiced; all aspects and equivalents thereof are intended to be within the scope of the claimed subject matter. The foregoing and other objects, features, and advantages of the present disclosure will become more apparent from the following detailed description read in conjunction with the accompanying drawings. Throughout this disclosure, like reference numerals generally refer to like parts or elements. [Figure 1] 1 shows a schematic diagram of an image sensor 100 according to some embodiments of the present invention. [Figure 2]2 shows a schematic diagram of a pixel capture circuit 200 according to some embodiments of the present invention. [Figure 3] 2 shows a schematic diagram of a pixel capture circuit 200 according to some other embodiments of the present invention. [Figure 4A] 2 shows a schematic diagram of an event sequence storage module 240 according to some embodiments of the present invention. [Figure 4B] 2 shows a schematic diagram of an event sequence storage module 240 according to some embodiments of the present invention. [Figure 5] 2 shows a time sequence diagram of the output signals of the state latch 220 and the event sequence storage module 240 according to one embodiment of the present invention. [Figure 6] 10 shows a schematic diagram of a sampling sub-module according to another embodiment of the present invention. [Figure 7A] 2 shows a schematic diagram of a readout module 250 according to one embodiment of the present invention. [Figure 7B] 2 shows a schematic diagram of a readout module 250 according to another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0027]

[0023] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While the accompanying drawings illustrate exemplary embodiments of the present disclosure, it should be understood that the present disclosure can be embodied in various forms and should not be limited to the embodiments described herein. On the contrary, these embodiments are provided to provide a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0028] FIG. 1 shows a schematic diagram of an image sensor 100 according to some embodiments of the present invention.

[0029] As shown in FIG. 1, the image sensor 100 includes a pixel acquisition circuit array 110 , a global control unit 120 , a global time signal generation unit 130 and a readout unit 140 .

[0030] The pixel acquisition circuit array 110 is composed of a plurality of identical pixel acquisition circuits 200 (i.e., pixel units) arranged two-dimensionally (FIG. 1 shows a single 3×3 pixel acquisition circuit array, but is not limited to this). According to an embodiment of the present invention, the pixel acquisition circuit 200 monitors changes in light intensity in the field of view in real time, and when the change in light intensity meets a certain condition, it enters a trigger state, i.e., triggers and generates an event, thereby indicating the occurrence of a motion event at a corresponding position in the field of view at that time. The pixel acquisition circuit 200 of the present invention can store event information for multiple events, and the event information includes status information and time information for the generated event.

[0031] In addition, the readout unit 140 further includes a row selection subunit 142, a column selection subunit 144, and a readout control subunit 146. The column selection subunit 144 also includes a column flag bit readout subunit 1442 and a column time information readout subunit 1444. The readout control subunit 146 is respectively coupled to the row selection subunit 142 and the column selection subunit 144, thereby controlling the row selection subunit 142 and the column selection subunit 144.

[0032] 1, the pixel acquisition circuit array 110 is respectively coupled to a global control unit 120, a global time signal generation unit 130, and a readout unit 140. Specifically, the global control unit 120 is coupled to the pixel acquisition circuit array 110 via a global reset signal line. The global time signal generation unit 130 is coupled to the pixel acquisition circuit array 110 via a global time signal line. The readout unit 140 is coupled to the pixel acquisition circuit array 110 via a row select line, a row event reset signal line, a column flag bit signal line, and a column time signal line. Furthermore, the row selection subunit 142 is coupled to the pixel acquisition circuit array 110 via a row selection line and a row event reset signal line, and the column selection subunit 144 is coupled to the pixel acquisition circuit array 110 via a column flag bit signal line and a column time signal line (specifically, the column flag bit readout subunit 1442 is coupled to the pixel acquisition circuit array 110 via a column flag bit signal line, and the column time information readout subunit 1444 is coupled to the pixel acquisition circuit array 110 via a column time signal line).

[0033] In one embodiment, the global control unit 120 resets the entire pixel acquisition circuit array 110 when the image sensor 100 is powered on to ensure that each pixel acquisition circuit 200 has a stable initial state.

[0034] The global time signal generating unit 130 generates a global time signal representing time information. The global time signal may be a periodically varying analog voltage signal, such as a ramp signal, a triangular signal, or an exponential signal, or may be a coded periodic digital signal, such as a multi-bit Gray code signal. This embodiment of the present invention is not limited thereto. According to this embodiment of the present invention, the pixel sampling circuit 200 samples the instantaneous amplitude value information of the global time signal at the time when the pixel sampling circuit 200 is triggered, and uses this as the time information of the event.

[0035] The global time signal generating unit 130 can be realized as a ramp signal generator, a triangular wave signal generator, an exponential signal generator, etc. Some of the circuit modules mentioned above are general-purpose basic modules, so they will not be repeated here.

[0036] The readout unit 140 reads out the event information generated by the pixel acquisition circuit array 110. Unlike a general dynamic vision sensor, the readout unit 140 is only used to read out the event information stored in the pixel acquisition circuit array 110, and is not used to control the operating state of the pixel acquisition circuit array 110.

[0037] In one embodiment according to the present invention, the row selection sub-unit 142 and the column flag bit readout sub-unit 1442 may be a random scanning decider or a sequential scanning selection scanning circuit, which will not be repeated here.

[0038] According to one embodiment, when the global time signal line provides a periodically changing analog voltage signal, the column time information readout sub-unit 1444 corresponding to each column pixel acquisition circuit includes one or more analog-to-digital converters to convert the event time information (i.e., the instantaneous voltage amplitude value of the global time signal) stored in the pixel acquisition circuit 200 into a digital code and output it, so that the back-end processing unit can recover the true time information generated by the event based on it. When the global time signal line provides a coded multi-bit periodic digital signal, the column time information readout sub-unit 1444 is implemented as a multi-bit digital scanning circuit.

[0039] In one embodiment, the readout control subunit 146 first controls the row selection subunit 142 to select one row of pixel acquisition circuits 200, and then the readout control subunit 146 controls the column selection subunit 144 to read the status information (e.g., "0" indicates untriggered and "1" indicates triggered) and time information stored in the pixel acquisition circuits 200 of this row, and output them to an external module of the image sensor 100. The status information, for example, "0" indicates an untriggered event and "1" indicates a triggered event.

[0040] Unlike the pixel acquisition circuit in a typical dynamic vision sensor, this pixel acquisition circuit not only generates and stores multiple event information, but also completes its reset operation independently and does not depend on the peripheral readout control logic. That is, the trigger (i.e., event generation) and release of the trigger state of the pixel acquisition circuit 200 are both completed within the pixel acquisition circuit 200.

[0041] To further explain the pixel acquisition circuit 200, the internal configuration and operation principle of the pixel acquisition circuit 200 will be described in detail below in conjunction with the drawings.

[0042] 2 shows a schematic diagram of a pixel capture circuit 200 according to one embodiment of the present invention. The pixel capture circuit 200 includes at least an event generation module 210, a state latch 220, a self-timing logic 230, an event sequence storage module 240, and a readout module 250. The event generation module 210 is coupled to the state latch 220, while the state latch 220 and the self-timing logic 230 are coupled to each other. The state latch 220 is also coupled to the event sequence storage module 240, which is also coupled to the readout module 250.

[0043] When the change in the intensity of the light irradiated onto it (e.g., the amount and rate of change of the illuminance) satisfies a certain condition (e.g., the amount and rate of change of the illuminance both exceed their respective thresholds), the event generation module 210 generates a trigger signal indicating the generation of an event, sends it to the state latch 220 coupled thereto, and sets the state latch 220.

[0044] In one embodiment, the event generation module 210 includes a photoelectric detection sub-module 212 and a trigger generation sub-module 214 coupled to each other. The trigger generation sub-module 214 also includes a high pass filter amplifier 2142 and a threshold comparison sub-module 2144.

[0045] The photoelectric detection sub-module 212 monitors the optical signal irradiated onto it in real time and outputs a corresponding electrical signal.

[0046] The trigger generation sub-module 214 generates a trigger signal indicating the generation of an event when the electrical signal satisfies a threshold condition. Specifically, the high-pass filter amplifier 2142 is coupled to the photoelectric detection sub-module 212 and performs a pre-processing operation on the electrical signal to generate a processed electrical signal, where the pre-processing operation includes at least one of an amplification operation and a filtering operation. The threshold comparison sub-module 2144 determines whether the processed electrical signal satisfies a threshold condition (e.g., greater than a first threshold and less than a second threshold, but not limited to this), and generates a trigger signal if the threshold condition is met. According to one embodiment of the present invention, during the pre-processing operation, the amplification operation is performed to improve the sensitivity of the pixel acquisition circuit to detect light intensity, but this is not required. The filtering operation is typically high-pass filtering, i.e., it responds only to high-frequency, i.e., sufficiently fast, changes in light intensity, thereby filtering out slow changes in light intensity.

[0047] 2 exemplarily shows one implementation of each part of the event generation module 210. The photoelectric detection sub-module 212 is, for example, a logarithmic photoelectric detector, the high-pass filter amplifier 2142 can employ various well-known filtering and amplification techniques, and the threshold comparison sub-module 2144 can be implemented by, but is not limited to, a voltage comparator. The function of the event generation module 210 is no different from that of a general dynamic visual sensor, and therefore will not be repeated here.

[0048] When the state latch 220 receives a trigger signal, it is set and the pixel capture circuit 200 enters the trigger state. At the same time, the state latch 220 sends a signal to the self-timing logic 230 and the event sequence storage module 240, respectively.

[0049] On the other hand, the self-timing logic 230 is activated when the state latch 220 is set, and automatically resets the state latch 220 after a predetermined period of time in the activated state (i.e., local reset in FIG. 2), thereby automatically releasing the trigger state of the pixel acquisition circuit 200. As shown in FIG. 2, when the state latch 220 is reset, it sends a signal to the high-pass filter amplifier 2142, thereby resetting the high-pass filter amplifier 2142, and thus the event generation module 210 can again respond to changes in external light intensity.

[0050] According to an embodiment of the present invention, the predetermined period of time (i.e., the self-timing time) is generally on the order of microseconds, and only needs to ensure that the pixel acquisition circuit 200 can be stably reset. The cooperation of the self-timing logic 230 and the state latch 220 allows the pixel acquisition circuit 200 to constantly detect changes in external light intensity. In other words, during one acquisition process, the pixel acquisition circuit 200 can be triggered multiple times to generate multiple events.

[0051] In a typical dynamic vision sensor, a triggered pixel acquisition circuit is selected by a peripheral readout unit after a certain readout delay. Its handshake protocol control logic resets the state latch, releasing the trigger state of the pixel acquisition circuit and allowing it to respond to changes in external light intensity again. The readout delay is limited by the image sensor's event processing and readout speed, typically on the order of hundreds of microseconds or even milliseconds. When there is a lot of dynamic information in the field of view, the readout delay becomes even longer due to a large number of events being blocked. During this period, the pixel acquisition circuit does not respond to changes in external light intensity, and does not generate new events even when the light intensity change meets the above-mentioned certain conditions. As a result, typical dynamic vision sensors lose some event information. In contrast, the pixel acquisition circuit 200 of this embodiment replaces the existing handshake protocol control logic with self-timing logic, ensuring that the pixel acquisition circuit 200 continuously detects and generates events.

[0052] Meanwhile, each time the state latch 220 is set, the event sequence storage module 240 stores the event information of the generated event. An event sequence is formed from this at least one event (usually multiple events), and the event sequence storage module 240 stores the event information of the event sequence. When a peripheral readout unit selects the pixel acquisition circuit, it reads out all of the event information of the event sequence stored therein at once.

[0053] In one embodiment, the event information includes state information and time information of the event, where the state information indicates whether the event is triggered, and the time information records the time when the event is triggered.

[0054] According to one embodiment, the event sequence storage module 240 includes an event register group 242 and a time sampling group 244. The event register group 242 also includes a plurality of event registers (preferably, N is the number of the event registers, where N>1), and each event register stores the status information of one event generated by the pixel acquisition circuit 200.

[0055] The time sampling group 244 includes a plurality of sampling sub-modules, each of which corresponds to one of the event registers (i.e., the number of sampling sub-modules is also N). The sampling sub-modules are used to record the time information of the events indicated by the corresponding event registers. In one embodiment, the sampling sub-modules are coupled to the peripheral global time signal generating unit 130 via a global time signal line, and sample the instantaneous amplitude value of the global time signal at the event generation time to obtain the time information of the event.

[0056] 2, the readout module 250 is implemented as a parallel readout module, and is coupled to the peripheral readout units 140 via one row selection line, a plurality of column flag bit signal lines, and a plurality of column time information signal lines. In one embodiment, the number of column flag bit signal lines and the number of column time information signal lines may be equal to the number of event registers (sampling sub-modules), i.e., N. As shown in FIG. 2, the plurality of column flag bit signal lines and the plurality of column time information signal lines are referred to as column flag bit signal lines[1:N] and column time information signal lines[1:N], respectively.

[0057] When the row where the pixel acquisition circuit 200 is located is selected by the row selection subunit 142, the row selection line is enabled, and the readout module 250 reads out the event information of the event sequence stored in the event sequence storage module 240. Specifically, the readout module 250 outputs the status information of each event via the column flag bit signal lines [1:N] respectively, and outputs the time information of each event via the column time information signal lines [1:N] respectively.

[0058] 3 shows a schematic diagram of a pixel acquisition circuit 200 according to some other embodiments of the present invention. Compared with the pixel acquisition circuit 200 shown in FIG. 2, the pixel acquisition circuit 200 in FIG. 3 uses a serial method to implement a readout module 250 (i.e., a serial readout module). Specifically, compared with a parallel readout module, the serial readout module has an additional readout gate signal line in the row direction and only one column flag bit signal line and one column time information signal line in the column direction.

[0059] Since the event generation module 210, state latch 220, self-timing logic 230, and event sequence storage module 240 have each been described above with respect to FIG. 2, only the read module 250 will now be described.

[0060] In the embodiment shown in FIG. 3, the readout module 250 is coupled to the peripheral readout units 140 via row select lines, readout gate signal lines, column flag bit signal lines, and column time information signal lines.

[0061] When the row where the pixel acquisition circuit 200 is located is selected by the row selection subunit 142, the row selection line is enabled, and the readout module 250, under the influence of the readout gate signal line, serially outputs the status information of the event sequence through the column flag bit signal line and serially outputs the time information of the event sequence through the column time information signal line.

[0062] 2 and 3 show schematic diagrams of the pixel sampling circuit 200 according to an embodiment of the present invention, but the present invention is not limited thereto.

[0063] Additionally, Figures 4A and 4B each illustrate a schematic diagram of an event sequence storage module 240 according to some embodiments of the present invention.

[0064] 4A and 4B, the value of N is 3. That is, the event register group 242 includes three event registers and three sampling sub-modules, and each event register corresponds to one sampling sub-module. As described above, each event register stores the status information of one event, and each sampling sub-module stores the time information of one event.

[0065] In the embodiment shown in FIG. 4A, the global time signal line provides a periodically varying analog voltage signal, such as a ramp signal, a triangle signal, or an exponential signal.

[0066] The event register group 242 includes N event registers connected in series, where N is typically 2, as described above. The input terminal of the first event register (i.e., event register 1 in FIG. 4A) is connected to the power supply voltage, and the input terminals of the second to Nth event registers are connected to the output terminal of the previous event register, i.e., these N event registers form a register chain. The clock signal for each event register is the output of the state latch 220, and each event register is connected to a row event reset signal line, thereby providing a reset signal.

[0067] The N sampling sub-modules in the time sampling group 244 are independent of each other and are coupled only to the corresponding event registers, and each sampling sub-module has the same configuration. In the embodiment shown in Figure 4A, the sampling sub-module is an analog sampling module, including a first switch S1 and a first capacitor C1. The control terminal of the first switch S1 is connected to the output terminal of the corresponding event register, and the first terminal of the first switch S1 is connected to the global time signal line, the second terminal of the first switch S1 is connected to the first terminal of the first capacitor C1, and the second terminal of the first capacitor C1 is grounded.

[0068] 4A shows a case where N=3, but of course, this is not limiting. Hereinafter, the event sequence storage module 240 will be further described assuming N=3. As shown in FIG. 4A, the output of event register 1 is connected to the input of event register 2, the output of event register 2 is connected to the input of event register 3, and the input of event register 1 is connected to the power supply voltage.

[0069] When the row event reset signal is active, all event registers are reset, indicating that no events are generated in the pixel acquisition circuit. Take the event register 1 and sampling submodule 1 as an example. Sampling submodule 1 is composed of a first switch S1a and a first capacitor C1a. The control signal for the first switch S1a is the output signal Q1 of the event register 1. When the event register 1 is reset, its output signal Q1 is low. At this time, the first switch S1a is turned on, and the first capacitor C1a follows the global time signal provided by the global time signal line. When an event is generated, the event register 1 is set, its output signal Q1 is high, the first switch S1a is turned off, and the first capacitor C1a samples the instantaneous amplitude value information of the global time signal at the time the first switch S1a is turned off, which is used as the time information for the event.

[0070] In this way, the output signals Q1, Q2, and Q3 of the three event registers indicate the state information of the event sequence in the pixel acquisition circuit 200, and the output signals T1, T2, and T3 of the three sampling sub-modules indicate the time information of the event sequence in the pixel acquisition circuit 200.

[0071] In the embodiment shown in Figure 4B, the global time signal line provides a coded periodic digital signal, for example, a multi-bit Gray code signal, and the sampling sub-module is still an analog sampling module, and of course, a digital storage module such as a latch may also be used, without any limitation here.

[0072] In Figure 4B, the global time signal line [1:3] transmits a 3-bit digital signal. This is merely an example, and the present invention is not limited to this example. Correspondingly, each sampling sub-module also includes three sub-units to sample each of these 3-bit digital signals. Specifically, each sub-module includes a first switch S1 and a first capacitor C1. The connection method between these sub-modules can be referenced in the description of Figure 4A above. The same content as in Figure 4A will not be described one by one here.

[0073] Taking sampling submodule 1 as an example, the first switch S1a1 and the first capacitor C1a1 constitute the first submodule, which is connected to the global time signal line [1] and outputs the signal T1a. The first switch S1a2 and the first capacitor C1a2 constitute the second submodule, which is connected to the global time signal line [2] and outputs the signal T1b. The first switch S1a3 and the first capacitor C1a3 constitute the third submodule, which is connected to the global time signal line [3] and outputs the signal T1c. Then, T1a, T1b, and T1c are combined to obtain the time information of the first event. Based on similar configurations and connections, sampling submodules 2 and 3 sample and output the time information of the second and third events, respectively.

[0074] Based on the description of Figures 4A and 4B, those skilled in the art should understand that the pixel acquisition circuit 200 according to an embodiment of the present invention is realized by adjusting the event sequence storage module 240 (especially the time sampling group 244) based on the global time signal provided by the global time signal generation unit 130.

[0075] The operation flow of the event sequence storage module 240 will now be described with reference to Figure 5. Figure 5 shows a time sequence diagram of the output signals of the state latch 220 and the event sequence storage module 240 according to one embodiment of the present invention (i.e., the embodiment shown in Figure 4A), where the global time signal is a ramp voltage signal.

[0076] Initially, all three event registers are reset, and their corresponding output signals Q1, Q2, and Q3 are all 0, indicating that no events are generated in this pixel acquisition circuit. The first switches of the three sampling sub-modules are all on, and their corresponding output signals T1, T2, and T3 follow the global time signal.

[0077] At time A, the pixel acquisition circuit is triggered to generate the first event. At this time, the output of the state latch becomes high, event register 1 is set, and its output signal Q1 becomes 1. In sampling submodule 1, the first switch is turned off, and the first capacitor samples the instantaneous voltage amplitude value V1 of the global time signal at this time, which is used as the time information of the first event. When the state latch is set, the self-timing logic in the pixel acquisition circuit is activated, which automatically resets the state latch after the timing is completed, so the output of the state latch is a pulse signal. When the state latch is reset, the pixel acquisition circuit continues to detect changes in external light intensity.

[0078] At time B, the pixel acquisition circuit triggers again to generate a second event, and the output of the status latch goes high again. Because event register 1 has already been set, the output signal Q2 of event register 2 goes high at this time, indicating that the pixel acquisition circuit has detected two events. The first switch in sampling submodule 2 turns off, and the first capacitor samples the instantaneous voltage amplitude value V2 of the global time signal at this time as the time information of the second event. Then, the self-timing logic is activated, and the status latch is reset after the timing ends, allowing the pixel acquisition circuit to continue detecting changes in external light intensity.

[0079] At time C, when the pixel sampling circuit detects the third event, Q3 goes high, the first switch in the sampling submodule 3 turns off, and the first capacitor samples the amplitude value V3 of the instantaneous voltage of the global time signal at this time, which is used as the time information of the third event.

[0080] At time D, the row selection subunit selects this row, and the row selection line is enabled. The readout module (which may be a parallel readout module or a serial readout module) in the pixel acquisition circuit transmits the event sequence status information Q1, Q2, and Q3 output by the event sequence storage module to the column selection subunit via the column flag bit signal lines and the event sequence time information T1, T2, and T3 to the column selection subunit via the column time information signal lines. The column flag bit readout subunit in the column selection subunit reads Q1, Q2, and Q3. In this example, they are all 1, so the pixel acquisition circuit generates three events. The column time information readout subunit in the column selection subunit obtains the time information corresponding to the three events and converts the instantaneous amplitude values V1, V2, and V3 of the global time signal stored in each sampling submodule into digital codes for output. Because there is a one-to-one correspondence between the voltage amplitude values of the ramp voltages and the time, the back-end processing unit can use this to recover the time information of the actual trigger of each event. After the event information stored in the pixel acquisition circuit is read out, the row selection sub-unit activates the row event reset signal, at which time the event registers are all reset, the switches in the sampling sub-module are all turned on again, and the event information previously stored in the pixel acquisition circuit is all cleared. After that, the operation flow of the pixel acquisition circuit is consistent with that described above.

[0081] According to some other embodiments, the sampling sub-module in the event sequence storage module 240 may also be implemented in other ways. FIG. 6 shows a schematic diagram of a sampling sub-module according to another embodiment of the present invention. In some embodiments, a new event sequence storage module may be configured using the sampling sub-module shown in FIG. 6 instead of the sampling sub-module in FIG. 4A or 4B. Here, sampling sub-module 1 will be taken as an example. This sampling sub-module 1 is connected to event register 1, and other sampling sub-modules may be connected to other event registers in a similar manner.

[0082] 6, the sampling submodule includes a second switch S2 and a second capacitor C2, as well as a pulse shaper and a first transistor M1. The control terminal of the second switch S2 is connected to the output terminal of the corresponding event register via the pulse shaper (i.e., the control signal of the second switch S2 is the signal processed by the pulse shaper Q1). The first terminal of the second switch S2 is connected to the global time signal line, and the second terminal is connected to the drain of the first transistor M1 and the first terminal of the second capacitor C2, respectively. The first transistor M1 and the second capacitor C2 are connected in parallel, and the source of the first transistor M1 and the second terminal of the second capacitor C2 are grounded. The gate of the first transistor M1 is connected to the row event reset signal line.

[0083] When the row event reset signal is valid, the first transistor M1 is conductive and the second capacitor C2 is discharged to ground potential, i.e., T1 is initialized to ground potential. When the pixel acquisition circuit generates an event, Q1 goes high, and the sampling submodule outputs a narrow pulse signal to the second switch S2 through the pulse shaper. During this period, the second switch S2 is turned on, and the second capacitor C2 samples the instantaneous amplitude value of the global time signal as the time information of the event.

[0084] Compared with the sampling sub-modules shown in Figures 4A and 4B, in the sampling sub-module shown in Figure 6, for an untriggered event register, the second switch S2 is always in an off state, and T1 is always at ground potential, so that the external processing module can also indirectly determine the event status information based on the width value information of T1 (i.e., if T1 is at ground potential, it indicates that the event status is untriggered; conversely, if T1 is not at ground potential, it indicates that the event status is triggered), and there is no need to output the event status information stored in the event register through the column flag bit signal line.

[0085] FIG. 7A shows a schematic diagram of a readout module 250 according to one embodiment of the present invention, and FIG. 7B shows a schematic diagram of a readout module 250 according to another embodiment of the present invention.

[0086] 2 and 3, the read module 250 can be implemented as a parallel read module or a serial read module. Also, FIG. 7A shows a parallel read module, and FIG. 7B shows a serial read module.

[0087] In the parallel readout module shown in FIG. 7A, the readout module 250 includes a plurality of buffer sub-modules, each of which is configured with a second transistor M2 and a third switch S3 connected in series, and each buffer sub-module outputs the status information or time information of one corresponding event. For ease of understanding, FIG. 7A also assumes that N=3. That is, the three event registers output Q1, Q2, and Q3, respectively, and the three sampling sub-modules output T1, T2, and T3, respectively. Thus, there are a total of six buffer sub-modules (enclosed in dashed lines in FIG. 7A), each corresponding to one event register and one sampling sub-module.

[0088] Take one of the buffer sub-modules 710 as an example. The source of the second transistor M2a is connected to one end of the third switch S3a, the gate of the second transistor M2a is connected to the output end of the event sequence storage module (i.e., Q1), and the drain of the second transistor M2a is connected to the power supply. The control end of the third switch S3a is connected to the row selection line (therefore, the third switch is also called a row selection switch), and the other end of the third switch S3a is connected to the column flag bit signal line or the column time information signal line. For other buffer modules, please refer to the buffer sub-module 710; for space reasons, they will not be described one by one here.

[0089] The event status information Q1, Q2, Q3 and event time information T1, T2, T3 output by the event sequence storage module are sent to the corresponding column flag bit signal line and column time information signal line through the buffer sub-module. When this row is selected, its row selection line is enabled, all row selection switches are conductive, and Q1, Q2, Q3 and T1, T2, T3 are sent to the column flag bit signal line [1:3] and column time signal line [1:3] respectively.

[0090] In the serial readout module shown in Figure 7B, the readout module 250 includes a buffer sub-module consisting of a third transistor M3 and a fourth switch S4 connected in series, a fifth switch S5, and a sixth switch S6. As above, the number of buffer sub-modules is equal to the sum of the number of event registers and sampling sub-modules. Similarly, in Figure 7B, N = 3, so there are a total of six buffer sub-modules (also enclosed in a dashed box in Figure 7B).

[0091] Taking the buffer sub-module 720 connected to one of the event registers as an example, the source of the third transistor M3a is connected to one end of the fourth switch S4a, the gate of the third transistor M3a is connected to the output end of the event sequence storage module (i.e., Q1), and the drain of the third transistor M3a is connected to the power supply. The control end of the fourth switch S4a is connected to the read gate signal line, and the other end of the fourth switch S4a is connected to one end of the fifth switch S5. One end of the fifth switch S5 is connected to the other end of some of the fourth switches S4 (for "some of the fourth switches," that is, the fourth switches of all the buffer sub-modules connected to the event register), and the other end is connected to the column flag bit signal line.

[0092] Similarly, for the buffer sub-module connected to the sampling sub-module, the other end of its fourth switch S4 is connected to one end of the sixth switch S6. For the fifth switch S5, one end of the sixth switch S6 is connected to the other ends of some of the other fourth switches S4 (for "some of the other fourth switches," that is, the fourth switches of all the buffer sub-modules connected to the sampling sub-module), and the other end is connected to the column time information signal line.

[0093] The fourth switches S4a through S4f in the buffer submodule are controlled by read gate signal lines, and the fifth and sixth switches S5 and S6 are controlled by row select lines. The outputs of Q1, Q2, and Q3 share a single column flag bit signal line, and the outputs of T1, T2, and T3 share a single column time information signal line. When a row is selected, the row select line is enabled, and the fifth and sixth switches S5 and S6 are both turned on. At this time, the read gate signal line sequentially controls the fourth switches S4a, S4b, and S4c to conduct, and event status information Q1, Q2, and Q3 is serially output via the column flag bit signal line. Similarly, the read gate signal line sequentially controls the fourth switches S4d, S4e, and S4f to conduct, and event time information T1, T2, and T3 is serially output via the column time signal line.

[0094] To summarize, the pixel acquisition circuit of the present invention employs self-timing logic instead of the handshake protocol control logic used in typical dynamic vision sensors. After the pixel acquisition circuit 200 enters a trigger state, the self-timing logic is activated, which automatically releases the trigger state of the pixel acquisition circuit after the timing expires, allowing the pixel acquisition circuit to immediately respond to changes in external light intensity. This allows the operation of the pixel acquisition circuit to operate independently of the peripheral readout control logic and to continuously detect and generate events. An event sequence storage module is also added to the pixel acquisition circuit, which temporarily stores the status and time information of multiple events generated by the pixel acquisition circuit. When the pixel acquisition circuit is selected by the peripheral readout unit, the temporarily stored event sequence information is read out to the external unit.

[0095] By using the above-described measures, the image sensor 100 of the present invention does not miss any event detection due to readout delays. Furthermore, because it is not sensitive to readout delays, the operating speed of the readout units around the pixel acquisition circuit array can be correspondingly reduced, thereby further reducing the power consumption of the image sensor.

[0096] In the specification provided herein, many specific details have been set forth. However, it will be understood that embodiments of the present invention may be practiced without these specific details. In some embodiments, well-known methods, structures, and techniques have not been shown in detail in order to avoid obscuring the understanding of this specification.

[0097] Similarly, in the foregoing description of exemplary embodiments of the invention, features of the invention may be grouped together in a single embodiment, drawing, or description thereof for the purpose of simplifying the disclosure and facilitating understanding of one or more of the individual inventive aspects. However, this method of disclosure is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, inventive aspects require fewer than all features of a single foregoing disclosed embodiment. Thus, the claims following a specific embodiment are hereby expressly incorporated into that specific embodiment, with each claim therein being itself a separate embodiment of the invention.

[0098] Those skilled in the art will understand that the modules, units, or assemblies of the devices described in the examples disclosed herein can be arranged in the devices described in the examples, or can be interchangeably positioned in one or more devices different from the devices in the examples. The modules in the examples can be combined into one module or otherwise divided into multiple sub-modules.

[0099] As will be understood by those skilled in the art, modules in the devices of the embodiments can be adaptively modified and installed in one or more devices different from the embodiments. Modules, units, or assemblies in the embodiments can be combined into a single module, unit, or assembly, and can also be divided into multiple sub-modules, sub-units, or sub-assemblies. All features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all steps or units of any method or device so disclosed can be combined in any combination, except that at least some of such features and / or steps or units are mutually exclusive. Unless otherwise specified, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) can be replaced by alternative features serving the same, equivalent, or similar purpose.

[0100] It should be understood by those skilled in the art that some of the embodiments described above may include certain features that are included in other embodiments but not other features, and that a combination of features from different embodiments is within the scope of the present invention and forms a different embodiment. For example, in the following claims, any one of the embodiments claimed for protection may be used in any combination.

[0101] It should be noted that some of the embodiments are described herein as methods or combinations of method components that can be implemented by a processor in a computer system or other device that performs the functions. Thus, a processor with the necessary instructions used to implement the method or method elements forms an apparatus that can be used to implement the method or method components. It should be noted that the components described herein of the apparatus embodiments are examples of the apparatus that can be used to implement the functions performed by the components for the purpose of implementing the invention.

[0102] As used herein, unless otherwise specified, the use of ordinal numbers such as "first," "second," "third," etc. to describe generic objects is meant only to refer to different instances of similar objects and does not imply that the objects so described must have a predetermined order in time, space, sequence, or in any other way.

[0103] While the present invention has been described with reference to a limited number of embodiments, those skilled in the art, having benefited from the foregoing description, will appreciate that other embodiments are possible within the scope of the invention described herein. It should also be noted that the terminology used herein has been selected primarily for ease of reading and instruction, and not to interpret or limit the subject matter of the present invention. Accordingly, many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the appended claims. With respect to the scope of the invention, the disclosure made herein is illustrative and not limiting, and the scope of the invention is limited by the appended claims.

Claims

1. A pixel acquisition circuit, an event generation module, a state latch, self-timing logic, an event sequence storage module, and a readout module; The event generating module is adapted to generate a trigger signal indicating an event generation when a change in the intensity of light irradiated thereto satisfies a certain condition; the state latch is adapted to be set upon receiving the trigger signal; the self-timing logic is coupled to the state latch and adapted to be activated when the state latch is set, and after a predetermined period of time in the activated state, resets the state latch, thereby causing the event generation module to again respond to changes in external light intensity; the event sequence storage module is coupled to the state latch and is adapted to store event information of an event sequence consisting of a plurality of generated events when the state latch is set; the readout module is coupled to the event sequence storage module and is suitable for reading out the event information of the event sequence stored in the event sequence storage module when a row select line is enabled.

2. The event information includes state information and time information of the generated event, and the event sequence storage module includes an event register group including a plurality of event registers and a time sampling group including a plurality of sampling sub-modules; the event register is adapted to store status information of one event generated by the pixel capture circuit; 2. The pixel acquisition circuit according to claim 1, wherein each of the sampling sub-modules corresponds one-to-one with each of the event registers, and each of the sampling sub-modules is adapted to record time information of an event indicated by a corresponding event register.

3. The readout module is coupled to a peripheral readout unit via a row selection line, a plurality of column flag bit signal lines and a plurality of column time information signal lines, and the readout module is further adapted to output, when the row selection line is enabled, state information of each event via the plurality of column flag bit signal lines respectively, and output time information of each event via the plurality of column time information signal lines respectively; Or, 3. The pixel sampling circuit according to claim 2, wherein the readout module is coupled to a peripheral readout unit through a row selection line, a readout gate signal line, a column flag bit signal line and a column time information signal line, and the readout module is further adapted to output status information of each event through the column flag bit signal line and time information of each event through the column time information signal line under the action of the readout gate signal line when the row selection line is enabled.

4. The pixel acquisition circuit according to claim 2 or 3, characterized in that the sampling sub-module is coupled to a peripheral global time signal generation unit via a global time signal line, and is suitable for sampling the instantaneous amplitude value of the global time signal at the time when the event is generated, to obtain the time information of the event.

5. the event register group includes N event registers connected in series, where N≧2, the input terminal of the first event register is connected to a power supply voltage, and the input terminal of each of the second to Nth event registers is connected to the output terminal of the previous event register; 5. The pixel acquisition circuit according to claim 2, wherein the clock signal of each event register is the output of the state latch, and each event register is connected to a row event reset signal line, and is reset when it receives a row event reset signal.

6. the sampling sub-module includes a first switch and a first capacitor; the first switch has a control end connected to the output end of a corresponding event register, a first end connected to a global time signal line, and a second end connected to a first end of a first capacitor, the second end of which is grounded; The event register is further adapted to indicate the status information of the corresponding event by its output signal, and when the event register is reset, the output signal is at a low level, and when the event register is set, the output signal is at a high level; 6. The pixel acquisition circuit according to claim 5, wherein the sampling sub-module is further adapted to sample an instantaneous amplitude value of the global time signal when the first switch is turned off by the first capacitor when the event register is set, and use the instantaneous amplitude value as time information of the corresponding event.

7. the sampling sub-module includes a pulse shaper, a second switch, and a first transistor and a second capacitor connected in parallel; a second switch, a control end of which is connected to the output end of a corresponding event register via the pulse shaper, a first end of which is connected to a global time signal line, a second end of which is connected to the drain of the first transistor and the first end of the second capacitor, the source of the first transistor and the second end of the second capacitor are grounded, and the gate of the first transistor is connected to a row event reset signal line; 6. The pixel acquisition circuit of claim 5, wherein the sampling sub-module is further adapted to: when an event is generated, output a narrow pulse signal to a second switch via the pulse shaper to turn on the second switch; and sample an instantaneous amplitude value of the global time signal via a second capacitor to obtain time information of the event.

8. The readout module includes a plurality of buffer sub-modules, each of which is composed of a second transistor and a third switch connected in series, and each buffer sub-module outputs the status information or time information of an event correspondingly, the source of the second transistor is connected to one end of the third switch, the gate of the second transistor is connected to the output end of the event sequence storage module, the drain of the second transistor is connected to a power supply, and the control end of the third switch is connected to a row selection line, and the other end of the third switch is connected to a column flag bit signal line or a column time information signal line; Or, 4. The pixel acquisition circuit of claim 3, wherein the readout module includes a plurality of buffer sub-modules, each of which is composed of a third transistor and a fourth switch connected in series, wherein a source of the third transistor is connected to one end of the fourth switch, a gate of the third transistor is connected to the output end of the event sequence storage module, a drain of the third transistor is connected to a power supply, a control end of the fourth switch is connected to a readout gate signal line, and the other end of the fourth switch is connected to one end of a fifth switch or a sixth switch, wherein one end of the fifth switch is connected to the other ends of some of the fourth switches and the other end is connected to a column flag bit signal line, and one end of the sixth switch is connected to the other ends of other some of the fourth switches and the other end is connected to a column time information signal line.

9. 1. An image sensor, comprising: a pixel acquisition circuit array, a global control unit, a global time signal generating unit, and a readout unit; The pixel acquisition circuit array includes a plurality of pixel acquisition circuits according to any one of claims 1 to 8, the global control unit is coupled to the pixel acquisition circuit array via a global reset signal line and is adapted to reset the pixel acquisition circuit array when the image sensor is energized; the global time signal generating unit is coupled to the pixel acquisition circuit array via a global time signal line, and is adapted to generate a global time signal representing time information; the readout unit is coupled to the pixel acquisition circuit array via a row select line, a row event reset signal line, a column flag bit signal line, and a column time signal line, and is adapted to read out event information of the event sequence generated by the pixel acquisition circuit array; the readout unit includes a row selection subunit, a column selection subunit, and a readout control subunit; the row select subunit is coupled to the pixel acquisition circuit array via a row select line and a row event reset signal line; the column selection subunit is coupled to the pixel acquisition circuit array via a column flag bit signal line and a column time signal line; 10. An image sensor, wherein the readout control subunit is adapted to control the row selection subunit and the column selection subunit.

10. The event information includes event status information and time information; and the column selection subunit includes a column flag bit read subunit and a column time information read subunit; the column flag bit read sub-unit is adapted to read out status information of an event via the column flag bit signal line; 10. The image sensor of claim 9, wherein the column time information readout sub-unit is adapted to read out time information of events via the column time signal lines.

Images