Semiconductor Devices

Abstract

To provide a semiconductor device in which current in a termination region can be suppressed.SOLUTION: A semiconductor device includes first and second electrodes, first to fourth semiconductor regions, and a conductive portion. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The second electrode is provided on the second and third semiconductor regions. The conductive portion includes first and second conductive regions. The first conductive region is opposed to the first semiconductor region and the second and third semiconductor regions via an insulating film. The second conductive region is arranged around the second electrode. The fourth semiconductor region is provided around and electrically connected with the second semiconductor region. The fourth semiconductor region has a lateral end portion in contact with the first semiconductor region. At least a part of the end portion is located at a position more the first electrode side than the second conductive region in a direction along a first direction.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] A semiconductor device includes a cell region having elements such as an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), or a diode, and a termination region outside the cell region. In the termination region, a semiconductor region electrically connected to some of the elements may be provided for reasons such as voltage resistance. Excessive current may flow through such a semiconductor region into the termination region. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-9728 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device capable of suppressing current in a termination region. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a second electrode, a conductive portion, and a fourth semiconductor region. The first semiconductor region is provided on the first electrode and is of a first conductivity type. The second semiconductor region is provided on the first semiconductor region and is of a second conductivity type. The third semiconductor region is provided on the second semiconductor region and is of the first conductivity type. The second electrode is provided on the second semiconductor region and the third semiconductor region and is electrically connected to the second semiconductor region and the third semiconductor region. The conductive portion includes a first conductive region and a second conductive region. The first conductive region faces the first semiconductor region, the second semiconductor region, and the third semiconductor region via an insulating film. The second conductive region is disposed around the second electrode. The fourth semiconductor region is provided around the second semiconductor region, is electrically connected to the second semiconductor region, and is of the second conductivity type. The fourth semiconductor region has an end in a direction perpendicular to a first direction from the first electrode to the second electrode, the end being in contact with the first semiconductor region, and at least a part of the end is located closer to the first electrode than the second conductive region in the first direction. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic plan view illustrating a semiconductor device according to an embodiment. [Figure 2] 1 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment. [Figure 3] 1 is a schematic plan view illustrating a semiconductor device according to an embodiment; [Figure 4] 1 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment. [Figure 5] 1 is a schematic cross-sectional view illustrating a semiconductor device according to a reference example. [Figure 6] FIG. 10 is a graph illustrating simulation results of the characteristics of the semiconductor device. [Figure 7] FIG. 10 is a graph illustrating simulation results of the characteristics of the semiconductor device. [Figure 8]10A and 10B are graphs illustrating simulation results of the characteristics of the semiconductor device according to the embodiment. [Figure 9] 9A and 9B are graphs illustrating simulation results of the characteristics of the semiconductor device according to the embodiment. [Figure 10] 10A and 10B are graphs illustrating simulation results of the characteristics of the semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In the present specification and the drawings, elements similar to those already explained are given the same reference numerals and detailed explanations will be omitted as appropriate. In each of the embodiments described below, the p-type (an example of the second conductivity type) and n-type (an example of the first conductivity type) of each semiconductor region may be reversed to implement each embodiment.

[0008] FIG. 1 is a schematic plan view showing a semiconductor device according to an embodiment. FIG. 2 is a schematic cross-sectional view illustrating the semiconductor device according to the embodiment. 1 illustrates a portion of a semiconductor device 100 according to an embodiment. The semiconductor device 100 according to the embodiment includes a cell region RC and a termination region RE surrounding the cell region RC. The cell region RC includes elements such as an IGBT, a MOSFET, or a diode.

[0009] 1 shows the layout of the underlying layers, omitting the electrodes, wiring, insulating films, etc. provided on the surface of the semiconductor device 100 as appropriate. However, the position of a second electrode 12, which will be described later, is indicated by a dashed line, and the position of a contact 70 is indicated by a solid line.

[0010] FIG. 2 is a cross-sectional view corresponding to the cross section taken along line AA shown in FIG. 2, the semiconductor device 100 includes a first electrode 11 (e.g., a collector electrode or a cathode), a semiconductor region 27 provided on the first electrode 11, and a first semiconductor region 21 provided on the semiconductor region 27. The semiconductor region 27 is in contact with and electrically connected to the first electrode 11 and the first semiconductor region 21. The semiconductor region 27 and the first semiconductor region 21 are each of a first conductivity type (e.g., n-type). The impurity concentration of the first conductivity type in the semiconductor region 27 is higher than the impurity concentration of the first conductivity type in the first semiconductor region 21.

[0011] The cell region RC (e.g., IGBT region R1) further includes a semiconductor region 28 (e.g., a collector region), a second semiconductor region 22 (e.g., a base region or an anode region), a plurality of third semiconductor regions 23 (e.g., emitter regions), a plurality of first conductive regions 31 (e.g., gate electrodes), a plurality of insulating films 51 (e.g., gate insulating films), and a second electrode 12 (e.g., an emitter electrode or an anode).

[0012] In the description of the embodiments, a first direction D1, a second direction D2, and a third direction D3 are used. The direction from the first electrode 11 to the second electrode 12 is defined as the first direction D1. A direction perpendicular to the first direction D1 is defined as the second direction D2. A direction perpendicular to the first direction D1 and perpendicular to the second direction D2 is defined as the third direction D3. For ease of explanation, the direction from the first electrode 11 to the second electrode 12 is referred to as "up," and the opposite direction is referred to as "down." These directions are based on the relative positional relationship between the first electrode 11 and the second electrode 12 and are unrelated to the direction of gravity.

[0013] The semiconductor region 28 is provided between the first electrode 11 and the semiconductor region 27. The semiconductor region 28 is in contact with and electrically connected to both the first electrode 11 and the semiconductor region 27. The semiconductor region 28 is of a second conductivity type (for example, p-type).

[0014] The second semiconductor region 22 is provided on a part of the first semiconductor region 21 and is electrically connected to the first semiconductor region 21. The second semiconductor region 22 is of the second conductivity type.

[0015] The third semiconductor region 23 is provided on a portion of the second semiconductor region 22 and is electrically connected to the second semiconductor region 22. The third semiconductor region 23 is of the first conductivity type. The impurity concentration of the first conductivity type in the third semiconductor region 23 is higher than the impurity concentration of the first conductivity type in the first semiconductor region 21 and higher than the impurity concentration of the first conductivity type in the semiconductor region 27.

[0016] The first conductive region 31 faces the side surfaces of the first semiconductor region 21, the second semiconductor region 22, and the third semiconductor region 23 via the insulating film 51. That is, the first conductive region 31 is aligned with the first to third semiconductor regions 21 to 23 in the second direction D2. The multiple first conductive regions 31 are aligned in the second direction D2, and each first conductive region 31 extends in the third direction D3.

[0017] 2, a semiconductor substrate W including first to third semiconductor regions 21 to 23 is provided with a plurality of trenches T1. The trenches T1 are recesses provided in the surface Wf of the semiconductor substrate W. The trenches T1 reach from the surface Wf to the first semiconductor region 21. That is, the trenches T1 are located on the first semiconductor region 21 and are aligned with the second semiconductor region 22 and the third semiconductor region 23 in the second direction D2. The plurality of trenches T1 are aligned in the second direction D2, and each trench T1 extends in a third direction D3 (extension direction).

[0018] Each first conductive region 31 and each insulating film 51 is provided inside each trench T1. Specifically, the insulating film 51 is provided on the inner wall (bottom and side surfaces) of the trench T1, and the first conductive region 31 is provided inside the insulating film 51. A part of the second semiconductor region 22 and two third semiconductor regions 23 are arranged between adjacent trenches T1.

[0019] The second electrode 12 is provided on the second semiconductor region 22 and the third semiconductor region 23, and is electrically connected to each of the second semiconductor region 22 and the third semiconductor region 23. An insulating film 55a is disposed between the second electrode 12 and the first conductive region 31. The second electrode 12 is electrically insulated from the first conductive region 31 (conductive portion 30).

[0020] The second electrode 12 includes a plurality of contacts 70. The contacts 70 are portions of the second electrode 12 that are in contact with the second semiconductor region 22 and the third semiconductor region 23. For example, as shown in FIG. 2, the contacts 70 are portions of the second electrode 12 that are disposed inside holes 55h that penetrate the insulating film 55a. The plurality of contacts 70 are aligned in the second direction D2 and extend in the third direction D3. When viewed from above, one contact 70 is disposed between two adjacent first conductive regions 31 (trench T1).

[0021] The semiconductor device 100 may be a reverse-conducting IGBT in which an IGBT and a diode are integrated into a single chip. In this case, for example, as shown in FIG. 2, an IGBT region R1 and a diode region R2 are defined in the cell region RC. The diode region R2 is aligned with the IGBT region R1 in a direction perpendicular to the first direction D1 (e.g., a second direction D2). Compared to the IGBT region R1, the diode region R2 includes a semiconductor region 29 (e.g., a cathode region) instead of the semiconductor region 28, and does not include the third semiconductor region 23. The first conductive region 31 in the diode region R2 may be electrically connected to the second electrode 12.

[0022] The semiconductor region 29 is aligned with the semiconductor region 28 in the second direction D2 and is located between the first electrode 11 and the semiconductor region 27. The semiconductor region 29 is in contact with and electrically connected to both the first electrode 11 and the semiconductor region 27. The semiconductor region 29 is of the first conductivity type. The impurity concentration of the first conductivity type in the semiconductor region 29 is higher than the impurity concentration of the first conductivity type in the semiconductor region 27.

[0023] For example, as shown in FIG. 2, the semiconductor device 100 includes, in the termination region RE, a fourth semiconductor region 24, a sixth semiconductor region 26a (e.g., a guard ring), semiconductor regions 26b to 26d (e.g., guard rings), a semiconductor region 26e (e.g., an EQPR (EQuivalent-Potential Ring) region), a second conductive region 32, a wiring portion 60 (e.g., a gate wiring), and conductive layers 61 to 65.

[0024] 2, the second conductive region 32 is aligned with the second electrode 12 in a direction perpendicular to the first direction D1. The second conductive region 32 is disposed around the second electrode 12. When viewed from above, the second conductive region 32 has a substantially rectangular ring shape that surrounds the outer periphery (entire periphery) of the second electrode 12.

[0025] The second conductive region 32 is continuous with the first conductive region 31 and is electrically connected to the first conductive region 31. As shown in Fig. 1, both ends of the first conductive region 31 in the third direction D3 are connected to both ends (regions extending in the second direction D2) of the second conductive region 32 that are spaced apart in the third direction D3.

[0026] For example, the first conductive region 31 and the second conductive region 32 are integrally formed of the same material. The first conductive region 31 and the second conductive region 32 may each be part of one continuous conductive portion 30. The second conductive region 32 is a portion of the conductive portion 30 that is located above the surface Wf of the semiconductor substrate W. The first conductive region 31 is a portion that is located below the surface Wf of the semiconductor substrate W and inside the trench T1.

[0027] As shown in FIG. 2, the fourth semiconductor region 24 is aligned with the second semiconductor region 22 in a direction perpendicular to the first direction D1. The fourth semiconductor region 24 is disposed around the second semiconductor region 22. When viewed from above, the fourth semiconductor region 24 has a substantially rectangular ring shape that surrounds the outer periphery (entire periphery) of the second semiconductor region 22. The fourth semiconductor region 24 is electrically connected to the second semiconductor region 22. The fourth semiconductor region 24 is of the second conductivity type. The impurity concentration of the second conductivity type in the fourth semiconductor region 24 may be the same as the impurity concentration of the second conductivity type in the second semiconductor region 22.

[0028] In the embodiments, "the same" includes not only completely identical but also substantially identical. For example, the range of "the same" includes cases where there are differences to a certain extent due to variations in process conditions.

[0029] The fourth semiconductor region 24 has ends (an inner end 24r and an outer end 24s) in a direction perpendicular to the first direction D1. The end 24r is located between the end 24s and the second semiconductor region 22. In other words, the end 24r is the inner peripheral side surface of the annular fourth semiconductor region 24, and the end 24s is the outer peripheral side surface of the annular fourth semiconductor region 24. The end 24s is surrounded by the first semiconductor region 21 and is in contact with the first semiconductor region 21.

[0030] 2, the fourth semiconductor region 24 is located below the second conductive region 32. More specifically, at least a part of the end 24s and at least a part of the end 24r are each below the second conductive region 32 and overlap with the second conductive region 32 in the first direction D1. At least a part of the end 24s and at least a part of the end 24r are each closer to the first electrode 11 than the second conductive region 32 in the direction along the first direction D1. Note that an insulating film 55b is provided between the fourth semiconductor region 24 and the second conductive region 32, and the fourth semiconductor region 24 and the second conductive region 32 are electrically insulated from each other.

[0031] Furthermore, for example, the width W32 of the second conductive region 32 is wider than the width W24 of the fourth semiconductor region 24. As a result, the entire fourth semiconductor region 24 is located below the second conductive region 32 and overlaps with the second conductive region 32 in the first direction D1. Furthermore, in the example of Fig. 2, the end 24s and the end 24r of the fourth semiconductor region 24 overlap with the wiring portion 60 in the first direction D1.

[0032] The depth of the fourth semiconductor region 24 may be the same as the depth of the second semiconductor region 22. The trench T1 is deeper than the fourth semiconductor region 24. For example, the fourth semiconductor region 24 can be formed by the same process (such as an ion implantation process and a thermal process) as the second semiconductor region 22.

[0033] In this example, a fifth semiconductor region 25 is further provided between the second semiconductor region 22 and the fourth semiconductor region 24. When viewed from above, the fifth semiconductor region 25 has a substantially rectangular ring shape that surrounds the outer periphery (e.g., the entire periphery) of the second semiconductor region 22. The fifth semiconductor region 25 contacts the outer periphery of the second semiconductor region 22 and the inner periphery of the fourth semiconductor region 24. In this manner, the fourth semiconductor region 24 is electrically connected to the second semiconductor region 22 via the fifth semiconductor region 25. For example, the outer periphery of the fifth semiconductor region 25 is located below the second conductive region 32, and the inner periphery of the fifth semiconductor region 25 is located below the second electrode 12.

[0034] The fifth semiconductor region 25 is of the second conductivity type. The impurity concentration of the second conductivity type in the fifth semiconductor region 25 is lower than the impurity concentration of the second conductivity type in the second semiconductor region 22 and lower than the impurity concentration of the second conductivity type in the fourth semiconductor region 24. The resistivity of the fifth semiconductor region 25 is higher than the resistivity of the second semiconductor region 22 and higher than the resistivity of the fourth semiconductor region 24. The sheet resistance of the fifth semiconductor region 25 is higher than the sheet resistance of the second semiconductor region 22 and higher than the sheet resistance of the fourth semiconductor region 24. The fifth semiconductor region 25 is shallower than the second semiconductor region 22 and shallower than the fourth semiconductor region 24.

[0035] For example, the total amount of impurities of the second conductivity type in the second semiconductor region 22 and the total amount of impurities of the second conductivity type in the fourth semiconductor region 24 are each 1×10 13 atoms / cm 2 Over 4×10 13 atoms / cm 2 For example, the total amount of impurities of the second conductivity type in the fifth semiconductor region 25 is 1×10 12 atoms / cm 2 Over 4×10 12 atoms / cm 2 The following is the result. The total amount of impurities is the number of impurities per unit area in a plane perpendicular to the first direction D1. The total amount of impurities is, for example, the integral of the number of impurities per unit volume in the first direction D1. The impurity concentration is the effective impurity concentration that contributes to the conduction of the semiconductor, and when a certain region contains both impurities that act as donors and impurities that act as acceptors, this is the concentration excluding the offset amounts.

[0036] The sixth semiconductor region 26a and the semiconductor regions 26b to 26e are each provided on the first semiconductor region 21. When viewed from above, the sixth semiconductor region 26a and the semiconductor regions 26b to 26e have a substantially rectangular ring shape that surrounds the outer periphery (entire perimeter) of the fourth semiconductor region 24. The sixth semiconductor region 26a and the semiconductor regions 26b to 26e are provided concentrically and spaced apart from each other.

[0037] That is, the sixth semiconductor region 26a surrounds the periphery of the fourth semiconductor region 24, the semiconductor region 26b surrounds the periphery of the sixth semiconductor region 26a, the semiconductor region 26c surrounds the periphery of the semiconductor region 26b, the semiconductor region 26d surrounds the periphery of the semiconductor region 26c, and the semiconductor region 26e surrounds the periphery of the semiconductor region 26d. Parts of the first semiconductor region 21 are arranged between these semiconductor regions (i.e., between the fourth semiconductor region 24 and the sixth semiconductor region 26a, between the sixth semiconductor region 26a and the semiconductor region 26b, between the semiconductor region 26b and the semiconductor region 26c, between the semiconductor region 26c and the semiconductor region 26d, and between the semiconductor region 26d and the semiconductor region 26e).

[0038] The sixth semiconductor region 26a is of the second conductivity type. The concentration of the second conductivity type impurities in the sixth semiconductor region 26a is higher than the concentration of the second conductivity type impurities in the fourth semiconductor region 24. The sixth semiconductor region 26a is deeper than the fourth semiconductor region 24 and deeper than the trench T1. The width W26 of the sixth semiconductor region 26a may be wider than the width W24 of the fourth semiconductor region 24. For example, the total amount of the second conductivity type impurities in the sixth semiconductor region 26a is 1×10 17 atoms / cm 2 More than 1×10 18 atoms / cm 2 The same applies to the semiconductor regions 26b to 26d. The semiconductor region 26e is of the first conductivity type.

[0039] 2, the wiring portion 60 is provided on the second conductive region 32 and is in contact with the second conductive region 32. An insulating film 55c is disposed in a portion between the wiring portion 60 and the second conductive region 32.

[0040] The conductive layer 61 is provided on and in contact with the sixth semiconductor region 26a. Similarly, the conductive layers 62 to 65 are provided on and in contact with the semiconductor regions 26b to 26e, respectively. An insulating film 55d is disposed below the conductive layers 61 to 65.

[0041] FIG. 3 is a schematic plan view illustrating the semiconductor device according to the embodiment. Fig. 3 is a diagram in which the conductive portion 30 is further omitted from Fig. 1. In Fig. 3, the position of the trench T1 (first conductive region 31) is indicated by a dashed line. As shown in FIG. 3, the fourth semiconductor region 24 has four extension portions B1 to B4 corresponding to the four sides. The extension portions B1 and B2 extend in a third direction D3. The extension portions B3 and B4 extend in a second direction D2. The fourth semiconductor region 24 also has corner portions C1 to C4 that connect the extension portions together. The corner portion C1 connects the extension portion B1 to the extension portion B3. The corner portion C2 connects the extension portion B1 to the extension portion B4. The corner portion C3 connects the extension portion B2 to the extension portion B4. The corner portion C4 connects the extension portion B2 to the extension portion B3.

[0042] The extension portion B1 and the extension portion B2 are aligned in the second direction D2 with the multiple contacts 70. No contact 70 is arranged between the extension portion B1 and the trench T11, which is the closest of the multiple trenches T1 to the extension portion B1. Similarly, no contact 70 is arranged between the extension portion B2 and the trench T12, which is the closest of the multiple trenches T1 to the extension portion B2.

[0043] Furthermore, the center of the trench T1 (first conductive region 31) in the third direction D3 is located in the cell region RC, and both ends of the trench T1 (first conductive region 31) in the third direction D3 extend to the termination region RE. More specifically, one end tg1 of the trench T1 in the third direction D3 extends to the extension portion B3, and the other end tg2 of the trench T1 (first conductive region 31) in the third direction D3 extends to the extension portion B4. The ends tg1 and tg2 are each located outside the inner periphery of the fourth semiconductor region 24 and inside the outer periphery of the fourth semiconductor region 24.

[0044] The width W25 of the fifth semiconductor region 25 may be wider or narrower than the width W24 of the fourth semiconductor region 24.

[0045] FIG. 4 is a schematic cross-sectional view illustrating a semiconductor device according to the embodiment. FIG. 4 is a cross-sectional view corresponding to the cross section taken along line BB shown in FIG. The fourth semiconductor region 24 is in contact with the end tg1 of the trench T1. A distance L1 (the shortest distance along the third direction D3) between the end 24s of the fourth semiconductor region 24 and the end tg1 of the trench T1 is greater than zero, for example, not less than 5.0 μm (micrometers) and not more than 25 μm.

[0046] The depth of the trench T1 (the length along the first direction D1) is, for example, not less than 4.0 μm and not more than 6.0 μm. The distance L2 along the first direction D1 between the bottom end ts1 of the trench T1 and the bottom end 24t of the fourth semiconductor region 24 is, for example, not less than 0.5 μm and not more than 4.0 μm.

[0047] An example of the material of each component of the semiconductor device 100 will be described. The first to fifth semiconductor regions 21 to 25, the sixth semiconductor region 26a, and the semiconductor regions 26b to 26e, 27 to 29 contain silicon, silicon carbide, gallium nitride, or gallium arsenide as semiconductor materials. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as n-type impurities. Boron can be used as p-type impurities. The conductive portion 30 (first conductive region 31 and second conductive region 32) includes a conductive material such as polysilicon. Impurities may be added to the conductive material. The insulating films 51 and 55a to 55d contain an insulating material such as silicon oxide or silicon nitride. The first electrode 11, the second electrode 12, the wiring portion 60, and the conductive layers 61 to 65 are conductive portions containing a metal such as aluminum or copper.

[0048] The operation of the semiconductor device 100 will now be described. The cell region RC of the semiconductor device 100 operates as an IGBT when, for example, a positive potential is applied to the first electrode 11 and a negative potential is applied to the second electrode 12. On the other hand, the cell region RC operates as a diode when a negative potential is applied to the first electrode 11 and a positive potential is applied to the second electrode 12.

[0049] More specifically, while a positive voltage relative to the second electrode 12 is applied to the first electrode 11, a voltage equal to or greater than the threshold is applied to the first conductive region 31. As a result, a channel is formed in the second semiconductor region 22 in the IGBT region R1, and the IGBT region R1 enters an ON state. When electrons flow through the channel to the first semiconductor region 21, holes are injected from the semiconductor region 28 into the first semiconductor region 21. As a result of conductivity modulation occurring in the first semiconductor region 21, the electrical resistance of the semiconductor device 100 decreases significantly. Thereafter, when the voltage applied to the first conductive region 31 becomes lower than the threshold, the channel in the third semiconductor region 23 disappears, and the IGBT region R1 enters an OFF state.

[0050] When a positive voltage is applied to the first electrode 11 with respect to the second electrode 12, the pn junction between the first semiconductor region 21 and the second semiconductor region 22 in the diode region R2 is reverse biased. Conversely, when a positive voltage is applied to the second electrode 12 with respect to the first electrode 11, the pn junction is forward biased.

[0051] Next, the effects of the embodiment will be described with reference to a semiconductor device according to a reference example. FIG. 5 is a schematic cross-sectional view illustrating a semiconductor device according to a reference example. 5 shows a cross section of a portion of a semiconductor device 190 according to a reference example, similar to Fig. 2. Compared to the semiconductor device 100 according to the embodiment, the semiconductor device 190 does not include the fourth semiconductor region 24 and the fifth semiconductor region 25, and instead includes a semiconductor region 26z and a conductive layer 69.

[0052] The semiconductor region 26z has a substantially rectangular ring shape that surrounds the outer periphery of the second semiconductor region 22. The semiconductor region 26z is of the second conductivity type. The semiconductor region 26z contacts the outer periphery of the second semiconductor region 22 and is electrically connected to the second semiconductor region 22.

[0053] A wiring portion 60 (gate wiring) is provided on the semiconductor region 26z. Furthermore, a conductive layer 69 is provided on the semiconductor region 26z. An outer periphery 26zs of the semiconductor region 26z is located below the conductive layer 69. For example, when viewed from above, the conductive layer 69 has a ring shape that overlaps with the outer periphery 26zs of the semiconductor region 26z. The conductive layer 69 is in contact with the semiconductor region 26z and is electrically connected to the semiconductor region 26z. By providing the conductive layer 69, for example, it is possible to suppress the electric field near the outer periphery 26zs of the semiconductor region 26z.

[0054] As described above, the semiconductor region 26z is disposed below the wiring portion 60 and the conductive layer 69 outside the wiring portion 60. Therefore, the width W26z of the semiconductor region 26z is relatively wide. Considering a forward bias state (the first electrode 11 is at a negative potential and the second electrode 12 is at a positive potential), hole current (current I in FIG. 5) may flow from the second electrode 12 to the termination region below the semiconductor region 26z via the second semiconductor region 22 and the semiconductor region 26z. When the width of the semiconductor region 26z is relatively wide, excessive hole current tends to flow. For example, as the cell region RC becomes smaller, the proportion of the termination region RE (e.g., an ineffective region that does not directly contribute to device characteristics) becomes relatively larger. In such cases, the hole current flowing through the semiconductor region 26z may not be negligible.

[0055] In contrast, the semiconductor device 100 according to the embodiment does not include the semiconductor region 26z, but includes a fourth semiconductor region 24 instead. As described with reference to FIG. 2 and other figures, the end 24s of the fourth semiconductor region 24 is located below the second conductive region 32. At least a portion of the end 24s is located closer to the first electrode 11 than the second conductive region 32 in the direction along the first direction D1. This allows the width of the fourth semiconductor region 24 to be formed relatively narrow. Therefore, in the semiconductor device 190, the hole current flowing into the termination region via the fourth semiconductor region 24 can be suppressed compared to the hole current flowing via the semiconductor region 26z. Furthermore, since the second conductive region 32 is located above the end 24s, the electric field near the end 24s can be suppressed, for example.

[0056] As described above, the first conductive region 31 is disposed inside the trench T1. This allows the cell region RC to be miniaturized and the on-resistance to be lowered compared to a planar transistor. In this way, even when the cell region RC is made smaller and the proportion of the termination region RE is relatively large, according to the embodiment, it is possible to suppress the hole current flowing in via the fourth semiconductor region 24. However, the semiconductor device according to the embodiment may include a planar transistor.

[0057] The depth of the semiconductor region 26z in the reference example is, for example, deeper than the trench T1 and the same as the depth of the sixth semiconductor region 26a. The impurity concentration of the second conductivity type in the semiconductor region 26z is higher than the impurity concentration of the second conductivity type in the second semiconductor region 22 and the same as the impurity concentration of the second conductivity type in the sixth semiconductor region 26a. In contrast, in the semiconductor device 100 according to the embodiment, the impurity concentration of the second conductivity type in the fourth semiconductor region 24 is lower than the impurity concentration of the second conductivity type in the sixth semiconductor region 26a. The total amount of impurities of the second conductivity type in the fourth semiconductor region 24 is less than the total amount of impurities of the second conductivity type in the sixth semiconductor region 26a. This increases the electrical resistance of the fourth semiconductor region 24, thereby suppressing hole current flowing in through the fourth semiconductor region 24.

[0058] The semiconductor device 100 further includes the fifth semiconductor region 25 described above. The total amount of impurities of the second conductivity type in the fifth semiconductor region 25 is less than the total amount of impurities of the second conductivity type in the fourth semiconductor region 24. The concentration of impurities of the second conductivity type in the fifth semiconductor region 25 is lower than the concentration of impurities of the second conductivity type in the fourth semiconductor region 24. The electrical resistivity of the fifth semiconductor region 25 is higher than the electrical resistivity of the fourth semiconductor region 24. This makes it possible to further suppress hole current flowing in via the fifth semiconductor region 25 and the fourth semiconductor region 24.

[0059] Furthermore, under a reverse bias (the first electrode 11 is at a positive potential and the second electrode 12 is at a negative potential), a depletion layer spreads from the pn junction surface between the fourth semiconductor region 24 and the first semiconductor region 21 and the interface between the trench T1 and the first semiconductor region 21 toward the first semiconductor region 21. When the depletion layer spreads into the first semiconductor region 21, carriers (electrons and holes) generated by impact ionization or the like are accelerated in the depletion layer, which may cause an avalanche breakdown.

[0060] 4, the distance L1 between the end 24s of the fourth semiconductor region 24 and the end tg1 of the trench T1 is, for example, 25 μm or less. When the distance L1 is shortened and the end 24s of the fourth semiconductor region 24 approaches the end tg1 of the trench T1, the electric field is likely to be stronger near the lower end of the end tg1 of the trench T1 than near the end 24s of the fourth semiconductor region 24. As a result, avalanche breakdown is more likely to occur near the lower end of the end tg1 of the trench T1 than near the fourth semiconductor region 24, resulting in a lower breakdown voltage.

[0061] Furthermore, the trench T1 is deeper than the fourth semiconductor region 24. As described above with reference to FIG. 4 , the distance L2 between the lower end 24t of the fourth semiconductor region 24 and the lower end ts1 of the trench T1 is greater than zero, for example, 0.5 μm to 4.0 μm. If the distance L2 is increased and the lower end ts1 of the trench T1 is spaced apart from the fourth semiconductor region 24, the electric field near the lower end of the end tg1 of the trench T1 is likely to be stronger than near the end 24s of the fourth semiconductor region 24, for example. As a result, avalanche breakdown is more likely to occur near the end tg1 of the trench T1 than near the fourth semiconductor region 24, resulting in a lower breakdown voltage.

[0062] For example, if avalanche breakdown occurs near the extension B1, extension B2, or corners C1 to C4 of the fourth semiconductor region 24 described with reference to FIG. 3, current may concentrate in areas of the extension B1, extension B2, or corners C1 to C4 where the breakdown voltage is particularly low. In response to this, in the semiconductor device 100, by adjusting at least one of the distance L1 and the distance L2 as described above, avalanche breakdown can be more likely to occur near the lower end of the end tg1 of the trench T1 than near the extension B1, extension B2, or corners C1 to C4. When multiple trenches T1 are provided, avalanche breakdown is more likely to occur near the end of each trench T1. This allows the locations where avalanche breakdown occurs (avalanche points) to be distributed to multiple locations, thereby suppressing current concentration. For example, element breakdown can be suppressed.

[0063] For example, in the semiconductor device 100, the breakdown voltage of the corners (for example, the breakdown voltage between the corner C1 and a part of the first semiconductor region 21 adjacent to the corner C1) is lower than the breakdown voltage of the extensions (for example, the breakdown voltage between the extension B3 and a part of the first semiconductor region 21 adjacent to the extension B3). This makes it possible to suppress current concentration at the corners. For example, when avalanche breakdown occurs due to a reverse bias, the current flowing through each of the corners C1 to C4 is smaller than the current flowing through the extension B3 or the extension B4.

[0064] As described above with reference to FIG. 3 , when viewed from above, the contact 70 is not disposed between the extension B1 and the trench T11, which is the trench T11 closest to the extension B1. That is, the second semiconductor region 22 does not contact the second electrode 12 in the region between the trench T11 and the extension B1. If avalanche breakdown occurs near the extension B1, holes will flow from near the extension B1 around the trench T11 to the contact 70. Because the current flows around the trench T11, the current path from the extension B1 to the contact 70 becomes longer, increasing the resistance. This suppresses the current flowing through the extension B1 and suppresses current concentration in the extension B1. Similarly, current concentration in the extension B2 can be suppressed.

[0065] FIG. 6 is a graph illustrating the simulation results of the characteristics of the semiconductor device. Fig. 6 shows the IV characteristics when a forward bias is applied. That is, Fig. 6 shows the relationship between the voltage of the second electrode 12 relative to the first electrode 11 and the current flowing from the second electrode 12 to the first electrode 11. The current I100 represents the IV characteristics of the semiconductor device 100, and the current I190 represents the IV characteristics of the semiconductor device 190.

[0066] 6, the current I100 is lower than the current I190. In the semiconductor device 100, the semiconductor region 26z of the semiconductor device 190 is not provided, and therefore, as described above, it is possible to suppress the inflow of excessive hole current from the semiconductor region 26z.

[0067] FIG. 7 is a graph illustrating the simulation results of the characteristics of the semiconductor device. The horizontal axis (x) in FIG. 7 represents the position of the semiconductor device in the second direction D2. Specifically, the horizontal axis in FIG. 7 corresponds to the position on line LN1 shown in FIG. 2 or the position on line LN2 shown in FIG. 5. The vertical axis on the left side of FIG. 7 represents the doping concentration of the second conductivity type impurity. Concentration C100 represents the doping concentration of the semiconductor device 100, and concentration C190 represents the doping concentration of the semiconductor device 190. In the semiconductor device 190, since the semiconductor region 26z is provided, the doping concentration is high in a wide range (near -110≦x≦0) corresponding to the semiconductor region 26z. On the other hand, in the semiconductor device 100, a fourth semiconductor region 24 (near -50≦x≦-20) and a fifth semiconductor region 25 (near -20≦x≦0) having a low doping concentration and a narrow width are provided instead of the semiconductor region 26z.

[0068] 7 also shows a concentration C101. The concentration C101 represents the doping concentration in a semiconductor device 101 obtained by omitting the fifth semiconductor region 25 from the semiconductor device 100 and instead extending the fourth semiconductor region 24 to the second semiconductor region 22.

[0069] 7 represents the hole current density. Current density D100 represents the hole current density of semiconductor device 100, current density D101 represents the hole current density of semiconductor device 101, and current density D190 represents the current density of semiconductor device 190.

[0070] 7, the current density D100 and the current density D101 are each lower than the current density D190 over a wide range in the semiconductor region 26z. In the semiconductor device 100 (and the semiconductor device 101), the semiconductor region 26z of the semiconductor device 190 is not provided, and therefore, as described above, the inflow of excessive hole current from the semiconductor region 26z can be suppressed.

[0071] FIG. 8 is a graph illustrating the simulation results of the characteristics of the semiconductor device according to the embodiment. Fig. 8 shows the IV characteristics when a reverse bias is applied. That is, Fig. 8 shows the relationship between the voltage of the first electrode 11 with respect to the second electrode 12 and the current flowing from the first electrode 11 to the second electrode 12. In Fig. 8, the depth of the trench T1 in the semiconductor device 100 is changed to 4.5 μm, 5.0 μm, and 5.5 μm.

[0072] As shown in Figure 8, when the trench T1 is shallower, the current value is 2 × 10 -9 The voltage value increases when it suddenly rises from near A. That is, for example, by making the trench T1 shallower and bringing the bottom end ts1 of the trench T1 closer to the bottom end 24t of the fourth semiconductor region 24, the breakdown voltage can be improved.

[0073] On the other hand, when the trench T1 is shallowed to a depth of 4.5 μm or 5.0 μm, the current value becomes 2×10 -9 Negative resistance occurs when the voltage rises sharply from near A. For example, if the trench T1 is shallower, the lower end ts1 of the trench T1 approaches the fourth semiconductor region 24, which is thought to make avalanche breakdown less likely to occur near the lower end tg1 of the trench T1. In this case, it is presumed that avalanche breakdown is relatively likely to occur near the extension portion B1, extension portion B2, or corner portions C1 to C4, and current tends to concentrate particularly in areas with low breakdown voltage, resulting in negative resistance. By deepening the trench T1, avalanche breakdown is more likely to occur near the end of each trench T1, which disperses the avalanche points and suppresses current concentration. In this embodiment, the trench T1 is preferably, for example, 5.5 μm or more.

[0074] 9A and 9B are graphs illustrating simulation results of the characteristics of the semiconductor device according to the embodiment. 9(a) and 9(b) show IV characteristics when a reverse bias is applied to a semiconductor device similar to the semiconductor device 100. That is, FIGS. 9(a) and 9(b) show the relationship between the voltage of the first electrode 11 relative to the second electrode 12 and the current flowing from the first electrode 11 to the second electrode 12. FIG. 9(a) shows the case where the distance L1 shown in FIG. 4 is 17 μm, and FIG. 9(b) shows the case where the distance L1 is 37 μm. In FIGS. 9(a) and 9(b), the amount of second conductivity type impurities per unit area of ​​the fifth semiconductor region 25 is 2×10 12 atoms / cm 2 It states that:

[0075] 9(a) and 9(b) show simulation results for a trench orthogonal cross section and a trench longitudinal cross section, respectively. The trench orthogonal cross section is a cross section parallel to the second direction D2 passing through the multiple trenches T1 and corresponds to the cross section taken along line AA in FIG. 1. The trench longitudinal cross section is a cross section parallel to the third direction D3 passing through the trenches T1 and corresponds to the cross section taken along line BB in FIG. 1.

[0076] In the example of FIG. 9(a), the current value rises sharply when the voltage is around 1370 V. After that, the current value in the trench longitudinal cross section becomes larger than the current value in the trench perpendicular cross section. This is presumably because avalanche breakdown is more likely to occur near the bottom end of the end tg1 of the trench T1 than near the extension B1 (or extension B2) of the fourth semiconductor region 24. Therefore, the current value in the trench longitudinal cross section including the end tg1 of the trench T1 is considered to be relatively large.

[0077] On the other hand, in the example of FIG. 9(b), the current value rises sharply when the voltage is around 1365V. After that, the current value at the trench longitudinal cross section becomes larger than the current value at the trench perpendicular cross section. This is presumably because avalanche breakdown is more likely to occur near the extension portion B1 (or extension portion B2) than near the bottom end of the end tg1 of the trench T1. Therefore, the current value at the trench perpendicular cross section including the extension portion B1 is considered to be relatively large.

[0078] By shortening the distance L1 in this way, avalanche breakdown is more likely to occur near the end tg1 of the trench T1.

[0079] FIG. 10 is a graph illustrating the simulation results of the characteristics of the semiconductor device according to the embodiment. 10 shows the conditions under which avalanche breakdown occurs at the end of trench T1 when a reverse bias is applied in a semiconductor device similar to semiconductor device 100. The horizontal axis of FIG. 10 represents the amount of impurities of the second conductivity type per unit area of ​​fifth semiconductor region 25 (total amount of impurities) atoms / cm 2 The vertical axis of Fig. 10 indicates the upper limit distance L1 at which avalanche breakdown occurs at the end of trench T1 for each impurity amount. In other words, the value on the vertical axis of Fig. 10 is the upper limit distance L1 at which the magnitude of the current is larger, for example, in the longitudinal cross section of the trench than in the perpendicular cross section of the trench.

[0080] For example, the amount of second conductivity type impurities per unit area of ​​the fifth semiconductor region 25 is 5×10 11 atoms / cm 2 , avalanche breakdown occurs at the end of trench T1 when distance L1 is 12 μm or less. For example, the amount of second conductivity type impurities per unit area of ​​the fifth semiconductor region 25 is 1×10 12 atoms / cm 2 , avalanche breakdown occurs at the end of trench T1 when distance L1 is 25 μm or less. For example, the amount of second conductivity type impurities per unit area of ​​the fifth semiconductor region 25 is 2×10 12 atoms / cm 2 , avalanche breakdown occurs at the end of trench T1 when distance L1 is 25 μm or less.

[0081] In the embodiment, the distance L1 is preferably, for example, 25 μm or less. This makes it easier for avalanche breakdown to occur near the end tg1 of the trench T1. When a plurality of trenches T1 are provided, avalanche breakdown is easier to occur near the end of each trench T1. This makes it possible to distribute the locations where avalanche breakdown occurs, thereby suppressing current concentration. In this case, the amount of impurities of the second conductivity type per unit area of ​​the fifth semiconductor region 25 is, for example, 1×10 12 atoms / cm 2 The following applies.

[0082] The amount of second conductivity type impurities per unit area of ​​the fifth semiconductor region 25 is 5×10 11 atoms / cm 2 In this case, the amount of impurities of the second conductivity type per unit volume of the fifth semiconductor region 25 is, for example, 2.5×10 15 atoms / cm 3 is. The amount of second conductivity type impurities per unit area of ​​the fifth semiconductor region 25 is 1×10 12 atoms / cm 2 In this case, the amount of impurities of the second conductivity type per unit volume of the fifth semiconductor region 25 is, for example, 5.0×10 15 atoms / cm 3 is. The amount of second conductivity type impurities per unit area of ​​the fifth semiconductor region 25 is 2×10 12 atoms / cm 2 In this case, the amount of impurities of the second conductivity type per unit volume of the fifth semiconductor region 25 is, for example, 1.0×10 16 atoms / cm 3 is.

[0083] According to the embodiment, a semiconductor device capable of suppressing current in the termination region can be provided.

[0084] In each of the embodiments described above, the relative level of the impurity concentration between each semiconductor region can be confirmed using, for example, a scanning capacitance microscope (SCM). Note that the carrier concentration in each semiconductor region can be considered to be equal to the concentration of activated impurities in each semiconductor region. Therefore, the relative level of the carrier concentration between each semiconductor region can also be confirmed using an SCM. Furthermore, the impurity concentration in each semiconductor region can be measured using, for example, SIMS (secondary ion mass spectrometry).

[0085] In this specification, "electrically connected" includes not only connection through direct contact but also connection via other conductive members.

[0086] Although several embodiments of the present invention have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other. [Explanation of symbols]

[0087] 11 first electrode, 12 second electrode, 21 to 25 first to fifth semiconductor regions, 24r end, 24s end, 24t lower end, 26a sixth semiconductor region, 26b to 26e, 26z semiconductor region, 26zs outer periphery, 30 conductive part, 31 first conductive region, 32 second conductive region, 51, 55a~55d insulating film, 55h hole, 60 wiring part, 61~65, 69 conductive layer, 70 contact, 100, 190 semiconductor device, B1~B4 extension part, C1~C4 corner part, C100, C101, C190 concentration, D100, D101, D190 current density, I100, I190 current, L1, L2 distance, LN1, LN2 Line, R1 IGBT region, R2 Diode region, RC Cell region, RE Termination region, T1, T11, T12 Trench, W Semiconductor substrate, W24, W26, W26z, W32 Width, Wf Surface, tg1, tg2 End, ts1 Bottom

Claims

1. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a second electrode provided on the second semiconductor region and the third semiconductor region and electrically connected to the second semiconductor region and the third semiconductor region; a conductive portion including a first conductive region that faces the first semiconductor region, the second semiconductor region, and the third semiconductor region via an insulating film, and a second conductive region that is disposed around the second electrode; a fourth semiconductor region of a second conductivity type provided around the second semiconductor region and electrically connected to the second semiconductor region, the fourth semiconductor region having an end in a direction perpendicular to a first direction from the first electrode to the second electrode and in contact with the first semiconductor region, at least a part of the end being located closer to the first electrode than the second conductive region in a direction along the first direction and overlapping with the second conductive region in the first direction; A semiconductor device comprising:

2. a fifth semiconductor region of the second conductivity type provided between the second semiconductor region and the fourth semiconductor region; the fourth semiconductor region is electrically connected to the second semiconductor region via the fifth semiconductor region; The semiconductor device according to claim 1 , wherein the resistivity of said fifth semiconductor region is higher than the resistivity of said fourth semiconductor region.

3. 3. The semiconductor device according to claim 2, wherein a total amount of impurities of the second conductivity type in said fifth semiconductor region is less than a total amount of impurities of the second conductivity type in said fourth semiconductor region.

4. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a second electrode provided on the second semiconductor region and the third semiconductor region and electrically connected to the second semiconductor region and the third semiconductor region; a conductive portion including a first conductive region that faces the first semiconductor region, the second semiconductor region, and the third semiconductor region via an insulating film, and a second conductive region that is disposed around the second electrode; a fourth semiconductor region of a second conductivity type provided around the second semiconductor region and electrically connected to the second semiconductor region, the fourth semiconductor region having an end in a direction perpendicular to a first direction from the first electrode to the second electrode and in contact with the first semiconductor region, and a distance along the first direction between the fourth semiconductor region and the first electrode being shorter than a distance along the first direction between the second conductive region and the first electrode; a fifth semiconductor region of the second conductivity type provided between the second semiconductor region and the fourth semiconductor region; Equipped with the fourth semiconductor region is electrically connected to the second semiconductor region via the fifth semiconductor region; the resistivity of the fifth semiconductor region is higher than the resistivity of the fourth semiconductor region; a total amount of impurities of the second conductivity type in the fifth semiconductor region is less than a total amount of impurities of the second conductivity type in the fourth semiconductor region; A semiconductor device, wherein the total amount of impurities of the second conductivity type in the fifth semiconductor region is 1×10 12 atoms / cm 2 or more.

5. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a second electrode provided on the second semiconductor region and the third semiconductor region and electrically connected to the second semiconductor region and the third semiconductor region; a conductive portion including a first conductive region that faces the first semiconductor region, the second semiconductor region, and the third semiconductor region via an insulating film, and a second conductive region that is disposed around the second electrode; a fourth semiconductor region of a second conductivity type provided around the second semiconductor region and electrically connected to the second semiconductor region, the fourth semiconductor region having an end in a direction perpendicular to a first direction from the first electrode to the second electrode and in contact with the first semiconductor region, and a distance along the first direction between the fourth semiconductor region and the first electrode being shorter than a distance along the first direction between the second conductive region and the first electrode; Equipped with the insulating film and the first conductive region are disposed inside a trench provided on the first semiconductor region, A semiconductor device, wherein the distance between the end of the fourth semiconductor region and the end of the trench in the extension direction is 25 μm or less.

6. The semiconductor device according to claim 5 , wherein the trench is deeper than the fourth semiconductor region.

7. The trench is provided in plurality, The plurality of trenches are aligned in a second direction perpendicular to the extending direction, the second electrode includes a contact in contact with the second semiconductor region; the fourth semiconductor region has an extension aligned with the contact in the second direction when viewed from above, 7. The semiconductor device according to claim 5, wherein when viewed from above, the contact is not disposed between the extending portion and a trench among the plurality of trenches that is closest to the extending portion.

8. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; a second electrode provided on the second semiconductor region and the third semiconductor region and electrically connected to the second semiconductor region and the third semiconductor region; a conductive portion including a first conductive region that faces the first semiconductor region, the second semiconductor region, and the third semiconductor region via an insulating film, and a second conductive region that is disposed around the second electrode; a fourth semiconductor region of a second conductivity type provided around the second semiconductor region and electrically connected to the second semiconductor region, the fourth semiconductor region having an end in a direction perpendicular to a first direction from the first electrode to the second electrode and in contact with the first semiconductor region, and a distance along the first direction between the fourth semiconductor region and the first electrode being shorter than a distance along the first direction between the second conductive region and the first electrode; a sixth semiconductor region of the second conductivity type surrounding the fourth semiconductor region; Equipped with a total amount of impurities of the second conductivity type in the fourth semiconductor region is less than a total amount of impurities of the second conductivity type in the sixth semiconductor region.

9. A semiconductor device as described in Claim 8, wherein the depth of the fourth semiconductor region is shallower than the depth of the sixth semiconductor region.

10. A semiconductor device described in any one of claims 4 to 9, wherein at least a portion of the end of the fourth semiconductor region overlaps with the second conductive region in the first direction.

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