Semiconductor device and manufacturing method

Abstract

Provided is a semiconductor device which is equipped with: a semiconductor substrate which has a top surface and a bottom surface and is provided with a drift region of a first conductive type; a transistor section which has a collector region of a second conductive type which contacts the bottom surface of the semiconductor substrate and an emitter region of the first conductive type which has a higher doping concentration than does the drift region and is provided adjacent to the top surface of the semiconductor substrate; and a diode section which has a cathode region of the first conductive type which contacts the bottom surface of the semiconductor substrate. Therein, the avalanche breakdown in the diode section is at least 0.7 times and less than 1 time the avalanche breakdown in the transistor section.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method. [Background technology]

[0002] BACKGROUND ART Conventionally, a reverse conducting IGBT (RC-IGBT) is known in which a transistor section such as an IGBT (Insulated Gate Bipolar Transistor) and a diode section are provided on a single semiconductor substrate (see, for example, Patent Documents 1 and 2). [Prior art document] [Patent Documents] [Patent Document 1] JP 2018-78230 A [Patent Document 2] JP 2015-135954 A Problem to be Solved

[0003] In semiconductor devices such as reverse conducting IGBTs, it is preferable that breakdown is less likely to occur.

[0004] To solve the above problems, a first aspect of the present invention provides a semiconductor device. The semiconductor device may include a semiconductor substrate having an upper surface and a lower surface, and having a first conductivity type drift region provided therein. The semiconductor device may include a transistor section having a second conductivity type collector region in contact with the lower surface of the semiconductor substrate, and a first conductivity type emitter region in contact with the upper surface of the semiconductor substrate and having a doping concentration higher than that of the drift region. Any of the above semiconductor devices may include a diode section having a first conductivity type cathode region in contact with the lower surface of the semiconductor substrate. In any of the above semiconductor devices, the avalanche breakdown voltage of the diode section may be 0.7 times or more and less than 1 time the avalanche breakdown voltage of the transistor section.

[0005] In any of the above semiconductor devices, the cathode voltage at which the diode section reaches a negative resistance region may be equal to or higher than the collector voltage at which the transistor section reaches a negative resistance region.

[0006] In any of the above semiconductor devices, the diode section and the transistor section may have a plurality of trench sections arranged at intervals along an arrangement direction on the upper surface of the semiconductor substrate.

[0007] In any of the above semiconductor devices, at least some of the trench portions in the transistor section may be arranged at a first interval in the arrangement direction. In any of the above semiconductor devices, at least some of the trench portions in the diode section may be arranged at a second interval in the arrangement direction that is larger than the first interval.

[0008] Any of the above semiconductor devices may include an intermediate region disposed between the diode portion and the transistor portion, the intermediate region having a plurality of the trench portions and at least one of the cathode region and the collector region. In any of the above semiconductor devices, the intermediate region may include a transistor-side region. In any of the above semiconductor devices, the transistor-side region may be in contact with the transistor portion, and one or more of the trench portions may be arranged at the first interval.

[0009] Any of the above semiconductor devices may include an intermediate region disposed between the diode portion and the transistor portion, the intermediate region including a plurality of the trench portions and the cathode region and the collector region. In any of the above semiconductor devices, the intermediate region may include a transistor-side region. In any of the above semiconductor devices, the transistor-side region may be in contact with the transistor portion, and one or more of the trench portions may be disposed at intervals smaller than the first interval.

[0010] In any of the above semiconductor devices, a boundary position between the cathode region and the collector region in the intermediate region may be located in the transistor-side region.

[0011] In any of the above semiconductor devices, the boundary position may be located below the trench portion closest to the diode portion among the one or more trench portions in the transistor-side region.

[0012] In any of the above semiconductor devices, the transistor-side region may include the first trench portion and the second trench portion, the distance between which in the arrangement direction is smallest in the intermediate region. In any of the above semiconductor devices, the boundary position may be located in a region from below the first trench portion to below the second trench portion.

[0013] In any of the above semiconductor devices, the intervals between the plurality of trench portions in the arrangement direction in the intermediate region may be greater as the trench portions are closer to the diode portion.

[0014] In any of the above semiconductor devices, the second distance may be at least twice the first distance.

[0015] In any of the semiconductor devices described above, at least a portion of the trench portion in the transistor portion may have a first length in a depth direction of the semiconductor substrate, and at least a portion of the trench portion in the diode portion may have a second length in the depth direction that is greater than the first length.

[0016] Any of the above semiconductor devices may include an intermediate region disposed between the diode portion and the transistor portion, the intermediate region having a plurality of the trench portions and the cathode region and the collector region. In any of the above semiconductor devices, the intermediate region may have a transistor-side region in contact with the transistor portion. In any of the above semiconductor devices, the transistor-side region may have the trench portion of the first length.

[0017] Any of the above semiconductor devices may include an intermediate region disposed between the diode portion and the transistor portion, the intermediate region having the cathode region and the collector region, the intermediate region having a plurality of the trench portions, and the transistor portion. In any of the above semiconductor devices, the intermediate region may have a transistor-side region in contact with the transistor portion. In any of the above semiconductor devices, the transistor-side region may have the trench portion having a length shorter than the first length.

[0018] In any of the above semiconductor devices, a boundary position between the cathode region and the collector region in the intermediate region may be located in the transistor-side region.

[0019] In any of the above semiconductor devices, the lengths of the plurality of trench portions in the intermediate region in the depth direction may be greater as they approach the diode portion.

[0020] In any of the above semiconductor devices, the transistor section may have a first lower end region of the second conductivity type provided in contact with a lower end of at least one of the trench sections. In any of the above semiconductor devices, the lower end of at least one of the trench sections of the diode section may not be in contact with a region of the second conductivity type.

[0021] In any of the above semiconductor devices, the lower ends of all the trench portions of the diode portion may not be in contact with the second conductivity type region.

[0022] In any of the above semiconductor devices, the diode section may be provided in contact with a lower end of at least one of the trench sections and may have a second lower end region of the first conductivity type having a doping concentration higher than that of the drift region. In any of the above semiconductor devices, the lower end of at least one of the trench sections of the transistor section may not be in contact with a region of the first conductivity type having a doping concentration higher than that of the drift region.

[0023] In any of the above semiconductor devices, the transistor section may have a base region of a second conductivity type provided between the emitter region and the drift region. In any of the above semiconductor devices, the transistor section may have an accumulation region of a first conductivity type provided between the base region and the drift region and having a doping concentration higher than that of the drift region. In any of the above semiconductor devices, the doping concentration of the second lower end region may be lower than that of the accumulation region.

[0024] In any of the above semiconductor devices, the diode section may have a lifetime adjusting section that adjusts a lifetime of carriers on the upper surface side of the semiconductor substrate.

[0025] A second aspect of the present invention provides a semiconductor device. The semiconductor device may include a semiconductor substrate having an upper surface and a lower surface and provided with a drift region of a first conductivity type. The semiconductor device may include a transistor section including a collector region of a second conductivity type in contact with the lower surface of the semiconductor substrate and an emitter region of the first conductivity type in contact with the upper surface of the semiconductor substrate and having a doping concentration higher than that of the drift region. Any of the above semiconductor devices may include a diode section having a cathode region of the first conductivity type in contact with the lower surface of the semiconductor substrate. In any of the above semiconductor devices, the diode section and the transistor section may have a plurality of trench sections arranged at intervals along an arrangement direction on the upper surface of the semiconductor substrate. The transistor section may have a first lower end region of the second conductivity type provided in contact with a lower end of at least one of the trench sections. In any of the above semiconductor devices, the lower end of at least one of the trench sections of the diode section may not be in contact with a region of the second conductivity type.

[0026] A third aspect of the present invention provides a method for manufacturing a semiconductor device having a transistor portion and a diode portion on a semiconductor substrate. In the manufacturing method, a maximum non-destructive energy density at which the semiconductor device is not destroyed may be obtained by an unclamped dielectric switching test for a first semiconductor device having the same breakdown voltage as the transistor portion. In the manufacturing method, the ratio of the avalanche breakdown voltages of the diode portion and the transistor portion may be set using the first semiconductor device as a reference so that the maximum non-destructive energy density is greater than that of the first semiconductor device. In any of the above manufacturing methods, the transistor portion and the diode portion of the second semiconductor device may be designed to satisfy the set ratio of the avalanche breakdown voltages. In any of the above manufacturing methods, the second semiconductor device may be manufactured based on the design.

[0027] The above summary of the invention does not list all of the necessary features of the present invention. In addition, subcombinations of these features may also constitute inventions. [Brief explanation of the drawings]

[0028] [Figure 1] 1 is a top view illustrating an example of a semiconductor device 100 according to an embodiment of the present invention. [Figure 2] FIG. 2 is an enlarged view of an area D in FIG. [Figure 3] FIG. 3 is a diagram showing an example of an ee cross section in FIG. 2. [Figure 4] 10 is an example of current density-voltage characteristics of a transistor section 70 and a diode section 80 according to a reference example. [Figure 5] 10 is an example of current density-voltage characteristics of a transistor section 70 and a diode section 80 according to an embodiment. [Figure 6] FIG. 2 is a diagram showing an example of an ee cross section according to an embodiment. [Figure 7] FIG. 10 is a diagram showing another example of an ee cross section according to the embodiment. [Figure 8] FIG. 10 is a diagram showing another example of an ee cross section according to the embodiment. [Figure 9] FIG. 10 is a diagram showing another example of an ee cross section according to the embodiment. [Figure 10] FIG. 10 is a diagram showing another example of an ee cross section according to the embodiment. [Figure 11] FIG. 10 is a diagram showing another example of an ee cross section according to the embodiment. [Figure 12] FIG. 10 is a diagram showing another example of an ee cross section according to the embodiment. [Figure 13] FIG. 10 is a diagram showing another example of an ee cross section according to the embodiment. [Figure 14] FIG. 10 is a diagram showing another example of an ee cross section according to the embodiment. [Figure 15] FIG. 10 is a diagram showing another example of an ee cross section according to the embodiment. [Figure 16] FIG. 10 is a diagram showing another example of an ee cross section according to the embodiment. [Figure 17] FIG. 10 is a diagram showing another example of an ee cross section according to the embodiment. [Figure 18] 10 is a diagram showing the relationship between the trench spacing in the transistor section 70 and the diode section 80 and the avalanche breakdown voltage in the transistor section 70 and the diode section 80. FIG. [Figure 19] 10 is a diagram showing the relationship between the trench length in the transistor section 70 and the diode section 80 and the avalanche breakdown voltage in the transistor section 70 and the diode section 80. FIG. [Figure 20] 10 is a diagram showing the relationship between the trench spacing in the transistor section 70 and the diode section 80 and the avalanche breakdown voltage in the transistor section 70 and the diode section 80. FIG. [Figure 21] 10 is a diagram showing the relationship between the dose (or doping concentration) in the second lower end region 204 of the diode section 80 and the avalanche breakdown voltage of the diode section 80. FIG. [Figure 22] 2 is a diagram illustrating the maximum non-destructive energy density of the semiconductor device 100. FIG. [Figure 23] 1 shows the relationship between the avalanche withstand voltage Va_d in the diode section 80 and the maximum non-destructive energy density. [Figure 24]2A to 2C are diagrams illustrating an example of a method for manufacturing the semiconductor device 100. DETAILED DESCRIPTION OF THE INVENTION

[0029] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0030] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0031] In this specification, technical matters may be explained using the Cartesian coordinate axes of the X-axis, Y-axis, and Z-axis. The Cartesian coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is written without specifying positive or negative, it means the direction parallel to the +Z-axis and -Z-axis.

[0032] In this specification, orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0033] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate may be referred to as the top surface side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate may be referred to as the bottom surface side.

[0034] In this specification, when we say "same" or "equal," it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0035] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting N-type conductivity or a semiconductor exhibiting P-type conductivity.

[0036] In this specification, the doping concentration refers to the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration refers to the net concentration obtained by adding together the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account the polarity of the charge. As an example, the donor concentration is N D , acceptor concentration N A Then, the net doping concentration at any point is N D -N A In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0037] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, a VOH defect in a semiconductor, in which a vacancy (V), oxygen (O), and hydrogen (H) are bonded, functions as a donor that supplies electrons. In this specification, a VOH defect may be referred to as a hydrogen donor. A hydrogen donor may be a donor in which at least a vacancy (V) and hydrogen (H) are bonded.

[0038] In this specification, the semiconductor substrate has N-type bulk donors distributed throughout. The bulk donors are donors due to dopants that are uniformly contained in the ingot that is the base of the semiconductor substrate when it is manufactured. In this example, the bulk donors are elements other than hydrogen. The dopants of the bulk donors are, for example, phosphorus, antimony, arsenic, selenium, or sulfur, but are not limited to these. In this example, the bulk donor is phosphorus. The bulk donors are also contained in the P-type region. The semiconductor substrate may be a wafer cut from a semiconductor ingot, or may be a chip obtained by dividing the wafer. The semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), the magnetic field-applied Czochralski method (MCZ method), or the float zone method (FZ method). The ingot in this example is manufactured by the MCZ method. The oxygen concentration in the substrate manufactured by the MCZ method is 1×10 17 ~7×10 17 / cm 3 The oxygen concentration in the substrate manufactured by the FZ method is 1×10 15 ~5×10 16 / cm 3 The higher the oxygen concentration, the easier it is to generate hydrogen donors. The bulk donor concentration may be the chemical concentration of bulk donors distributed throughout the semiconductor substrate, and may be between 90% and 100% of that chemical concentration. Alternatively, a non-doped substrate that does not contain dopants such as phosphorus may be used as the semiconductor substrate. In this case, the bulk donor concentration (D0) of the non-doped substrate is, for example, 1×10 10 / cm 3 That's it, 5 x 10 12 / cm 3 The bulk donor concentration (D0) of the non-doped substrate is preferably 1×10 11 / cm 3 The bulk donor concentration (D0) of the non-doped substrate is preferably 5×10 12 / cm 3 The concentrations in the present invention may be values at room temperature, for example, values at 300 K (Kelvin) (approximately 26.9° C.).

[0039] In this specification, when P+ type or N+ type is used, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is used, it means that the doping concentration is lower than that of P type or N type. Furthermore, when P++ type or N++ type is used in this specification, it means that the doping concentration is higher than that of P+ type or N+ type. The unit system used in this specification is the SI unit system unless otherwise specified. The unit of length may be expressed in cm, but various calculations may be performed after converting to meters (m).

[0040] As used herein, chemical concentration refers to the atomic density of an impurity measured regardless of its electrical activation state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration can be measured by voltage-capacitance (CV) measurement. The carrier concentration measured by spreading resistance (SR) measurement may also be used as the net doping concentration. The carrier concentration measured by CV or SR may be used as the value in a thermal equilibrium state. In addition, since the donor concentration in an N-type region is significantly greater than the acceptor concentration, the carrier concentration in that region may also be used as the donor concentration. Similarly, in a P-type region, the carrier concentration in that region may also be used as the acceptor concentration. In this specification, the doping concentration in an N-type region may also be referred to as the donor concentration, and the doping concentration in a P-type region may also be referred to as the acceptor concentration.

[0041] When the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be taken as the concentration of the donor, acceptor, or net doping in that region. When the concentration of the donor, acceptor, or net doping is almost uniform, the average value of the concentration of the donor, acceptor, or net doping in that region may be taken as the concentration of the donor, acceptor, or net doping. In this specification, the concentration per unit volume is expressed in atoms / cm. 3 , or / cm 3This unit is used for donor or acceptor concentration or chemical concentration in a semiconductor substrate. The atom notation may be omitted.

[0042] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. In the range where current flows when measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state. The decrease in carrier mobility occurs when carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc.

[0043] The donor or acceptor concentration calculated from the carrier concentration measured by the CV or SR method may be lower than the chemical concentration of the element that represents the donor or acceptor. As an example, the donor concentration of phosphorus or arsenic, which act as donors in silicon semiconductors, or the acceptor concentration of boron, which acts as an acceptor, is approximately 99% of the chemical concentration. On the other hand, the donor concentration of hydrogen, which acts as a donor in silicon semiconductors, is approximately 0.1% to 10% of the chemical concentration of hydrogen.

[0044] Fig. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Fig. 1 shows the positions of each component projected onto the top surface of a semiconductor substrate 10. Fig. 1 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0045] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate made of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has edges 162 in a top view. In this specification, the term "top view" simply refers to a view from the top surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two pairs of edges 162 facing each other in a top view. In FIG. 1, the X-axis and Y-axis are parallel to either edge 162. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10.

[0046] An active portion 160 is provided in the semiconductor substrate 10. The active portion 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160, but is omitted from FIG. 1 . The active portion 160 may refer to a region that overlaps with the emitter electrode in a top view. The active portion 160 may also include a region sandwiched between the active portions 160 in a top view.

[0047] The active section 160 is provided with a transistor section 70 including a transistor element such as an IGBT (Insulated Gate Bipolar Transistor). The active section 160 may further be provided with a diode section 80 including a diode element such as a free wheel diode (FWD). In the example of FIG. 1, the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 of this example is a reverse conducting IGBT (RC-IGBT).

[0048] In FIG. 1, the region where the transistor section 70 is arranged is marked with the symbol "I," and the region where the diode section 80 is arranged is marked with the symbol "F." In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (the Y-axis direction in FIG. 1). The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. In other words, the length of the transistor section 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than the width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section, which will be described later.

[0049] The diode section 80 has an N+ type cathode region in a region in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A P+ type collector region may be provided in a region of the lower surface of the semiconductor substrate 10 other than the cathode region. In this specification, an extension region 81 in which the diode section 80 is extended in the Y-axis direction to a gate wiring (described later) may also be included in the diode section 80. A collector region is provided on the lower surface of the extension region 81.

[0050] The transistor section 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. In addition, the transistor section 70 has a gate structure periodically arranged on the upper surface side of the semiconductor substrate 10, the gate structure having an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film.

[0051] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed near an edge 162. The vicinity of the edge 162 refers to the region between the edge 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0052] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to a conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 164 and the gate trench portion. In FIG. 1, the gate wiring is indicated by diagonal hatching.

[0053] The gate wiring in this example has a peripheral gate wiring 130 and an active-side gate wiring 131. The peripheral gate wiring 130 is disposed between the active portion 160 and an edge 162 of the semiconductor substrate 10 in a top view. The peripheral gate wiring 130 in this example surrounds the active portion 160 in a top view. The region surrounded by the peripheral gate wiring 130 in a top view may be the active portion 160. In addition, a well region is formed below the gate wiring. The well region is a P-type region with a higher concentration than a base region, which will be described later, and is formed from the top surface of the semiconductor substrate 10 to a position deeper than the base region. In a top view, the region surrounded by the well region may be the active portion 160.

[0054] The peripheral gate wiring 130 is connected to the gate pad 164. The peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The peripheral gate wiring 130 may be a metal wiring containing aluminum or the like.

[0055] The active side gate wiring 131 is provided in the active section 160. By providing the active side gate wiring 131 in the active section 160, it is possible to reduce variations in wiring length from the gate pad 164 for each region of the semiconductor substrate 10.

[0056] The peripheral gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active section 160. The peripheral gate wiring 130 and the active side gate wiring 131 are arranged above the semiconductor substrate 10. The peripheral gate wiring 130 and the active side gate wiring 131 may be wiring formed of a semiconductor such as polysilicon doped with impurities.

[0057] The active-side gate wiring 131 may be connected to the peripheral gate wiring 130. In this example, the active-side gate wiring 131 extends in the X-axis direction from one peripheral gate wiring 130 to the other peripheral gate wiring 130 that sandwich the active section 160, crossing the active section 160 at approximately the center in the Y-axis direction. When the active section 160 is divided by the active-side gate wiring 131, the transistor sections 70 and the diode sections 80 may be arranged alternately in the X-axis direction in each divided region.

[0058] The semiconductor device 100 may include a temperature sensing section (not shown) that is a PN junction diode formed of polysilicon or the like, and a current detecting section (not shown) that simulates the operation of a transistor section provided in the active section 160.

[0059] In the present example, semiconductor device 100 includes an edge termination structure 90 between active section 160 and edge 162 when viewed from above. Edge termination structure 90 in the present example is disposed between peripheral gate wiring 130 and edge 162. Edge termination structure 90 alleviates electric field concentration on the top surface side of semiconductor substrate 10. Edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf, which are arranged in an annular shape surrounding active section 160.

[0060] FIG. 2 is an enlarged view of region D in FIG. 1. Region D includes a transistor section 70, a diode section 80, and an active-side gate wiring 131. The semiconductor device 100 of this example includes a connection region 190 between the transistor section 70 and the diode section 80. The semiconductor device 100 of this example includes a gate trench section 40, a dummy trench section 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface side of the semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are each an example of a trench section. The semiconductor device 100 of this example also includes an emitter electrode 52 and an active-side gate wiring 131 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate wiring 131 are provided separately from each other.

[0061] An interlayer insulating film is provided between the emitter electrode 52 and the active-side gate wiring 131 and the upper surface of the semiconductor substrate 10, but is not shown in Fig. 2. In this example, contact holes 54 are provided in the interlayer insulating film so as to penetrate the interlayer insulating film. In Fig. 2, each contact hole 54 is hatched with diagonal lines.

[0062] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to the dummy conductive portion of the dummy trench portion 30 at the tip of the dummy trench portion 30 in the Y-axis direction. The dummy conductive portion of the dummy trench portion 30 does not need to be connected to the emitter electrode 52 and the gate conductive portion, and may be controlled to a potential different from the potential of the emitter electrode 52 and the potential of the gate conductive portion.

[0063] The active side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active side gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active side gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0064] The emitter electrode 52 is made of a material containing metal. FIG. 2 shows the area where the emitter electrode 52 is provided. For example, at least a portion of the emitter electrode 52 is made of aluminum or an aluminum-silicon alloy, such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal made of titanium, a titanium compound, or the like below the region made of aluminum or the like. Furthermore, the contact hole may have a plug formed by embedding tungsten or the like so as to contact the barrier metal and aluminum or the like.

[0065] The well region 11 is provided so as to overlap with the active side gate wiring 131. The well region 11 is also provided so as to extend by a predetermined width in an area where it does not overlap with the active side gate wiring 131. In this example, the well region 11 is provided away from the end of the contact hole 54 in the Y-axis direction toward the active side gate wiring 131. The well region 11 is a region of the second conductivity type having a doping concentration higher than that of the base region 14. The well region 11 may be formed from the upper surface of the semiconductor substrate 10 to a depth deeper than the lower end of the trench portion. In this example, the base region 14 is P type and the well region 11 is of P+ type.

[0066] The transistor section 70, the connection region 190, and the diode section 80 each have a plurality of trenches arranged in the arrangement direction. In the transistor section 70 of this example, one or more gate trenches 40 and one or more dummy trenches 30 are alternately provided along the arrangement direction. In the connection region 190 of this example, a plurality of dummy trenches 30 are provided along the arrangement direction. In the diode section 80 of this example, a plurality of dummy trenches 30 are provided along the arrangement direction. In this example, the connection region 190 and the diode section 80 are not provided with gate trenches 40, but the connection region 190 and the diode section 80 may be provided with gate trenches 40.

[0067] The gate trench portion 40 in this example may have two straight line portions 39 (portions of the trench portion that are linear along the extension direction) that extend along an extension direction perpendicular to the arrangement direction, and a tip portion 41 that connects the two straight line portions 39. The extension direction in FIG. 2 is the Y-axis direction.

[0068] At least a part of the tip portion 41 is preferably curved in a top view. By connecting the ends of the two straight portions 39 in the Y-axis direction with each other by the tip portion 41, electric field concentration at the ends of the straight portions 39 can be alleviated.

[0069] In the transistor section 70, the dummy trench section 30 is provided between each of the linear portions 39 of the gate trench section 40. One or more dummy trench sections 30 may be provided between each of the linear portions 39. The dummy trench section 30 may have a linear shape extending in the extension direction, and may have a linear section 29 and an end portion 31, similar to the gate trench section 40. The semiconductor device 100 shown in FIG. 2 includes both linear dummy trench sections 30 without end portions 31 and dummy trench sections 30 with end portions 31.

[0070] The diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 when viewed from above. In other words, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 11. This makes it possible to alleviate electric field concentration at the bottom of each trench portion.

[0071] A mesa portion is provided between each trench portion in the arrangement direction. The mesa portion refers to a region inside the semiconductor substrate 10 that is sandwiched between the trench portions. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of the mesa portion is the same as the depth position of the lower end of the trench portion. In this example, the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending in the extension direction (Y-axis direction) along the trench. In this example, a mesa portion 60 is provided in the transistor portion 70, a mesa portion 61 is provided in the diode portion 80, and a mesa portion 62 is provided in the connection region 190. In this specification, the mesa portion simply referred to as a mesa portion refers to each of the mesa portion 60, mesa portion 61, and mesa portion 62.

[0072] A base region 14 is provided in each mesa portion. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region closest to the active-side gate wiring 131 is referred to as the base region 14-e. While FIG. 2 shows the base region 14-e at one end of each mesa portion in the extension direction, a base region 14-e is also provided at the other end of each mesa portion. Each mesa portion may be provided with at least one of a first-conductivity-type emitter region 12 and a second-conductivity-type contact region 15 in a region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0073] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may be provided with a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0074] The contact regions 15 and the emitter regions 12 in the mesa portion 60 are each provided from one trench portion to the other trench portion in the X-axis direction. As an example, the contact regions 15 and the emitter regions 12 in the mesa portion 60 are alternately arranged along the extension direction of the trench portions (the Y-axis direction).

[0075] In another example, the contact region 15 and the emitter region 12 of the mesa portion 60 may be provided in a stripe shape along the extension direction (Y-axis direction) of the trench portion. For example, the emitter region 12 is provided in a region in contact with the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.

[0076] The mesa portion 61 of the diode portion 80 and the mesa portion 62 of the connection region 190 are not provided with an emitter region 12. A base region 14 and a contact region 15 may be provided on the upper surfaces of the mesa portion 61 and the mesa portion 62. A contact region 15 may be provided in contact with each base region 14-e in a region sandwiched between the base regions 14-e on the upper surfaces of the mesa portion 61 and the mesa portion 62. A base region 14 may be provided in a region sandwiched between the contact regions 15 on the upper surface of the mesa portion 61. The base region 14 may be disposed in the entire region sandwiched between the contact regions 15.

[0077] A contact hole 54 is provided above each mesa portion. The contact hole 54 is arranged in a region sandwiched between the base regions 14-e. In this example, the contact holes 54 are provided above the contact region 15, the base region 14, and the emitter region 12. The contact holes 54 are not provided in regions corresponding to the base region 14-e and the well region 11. The contact hole 54 may be arranged in the center of the arrangement direction (X-axis direction) of the mesa portions 60.

[0078] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. A P+ type collector region 22 may be provided in a region of the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided. In the connection region 190, the cathode region 82, the collector region 22, or both the cathode region 82 and the collector region 22 may be provided in a region adjacent to the lower surface of the semiconductor substrate 10. The cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. In FIG. 2, the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.

[0079] The cathode region 82 is disposed away from the well region 11 in the Y-axis direction. This ensures a distance between the cathode region 82 and a P-type region (well region 11) that has a relatively high doping concentration and is formed deep, thereby improving the breakdown voltage. In this example, the end of the cathode region 82 in the Y-axis direction is disposed farther from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In another example, the end of the cathode region 82 in the Y-axis direction may be disposed between the well region 11 and the contact hole 54.

[0080] 3 is a diagram showing an example of an ee cross section in FIG. 2. FIG. 3 shows a structure according to a reference example. The ee cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. The ee cross section includes the transistor section 70, the connection region 190, and the diode section 80. In this cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.

[0081] The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with the contact hole 54 described with reference to FIG. 2.

[0082] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 passes through a contact hole 54 in the interlayer insulating film 38 and contacts the upper surface 21 of the semiconductor substrate 10. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metal material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (the Z-axis direction) is referred to as the depth direction.

[0083] The semiconductor substrate 10 has an N-type or N-type drift region 18. The drift region 18 is provided in each of the transistor section 70, the diode section 80, and the connection region 190.

[0084] The mesa portion 60 of the transistor portion 70 includes an N+ type emitter region 12 and P type The base region 14 is provided in this order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+ type accumulation region 16 may be provided in the mesa portion 60. The accumulation region 16 is disposed between the base region 14 and the drift region 18.

[0085] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The emitter region 12 has a higher doping concentration than the drift region 18. In the XZ plane passing through the contact region 15, the contact region 15 is provided in place of the emitter region 12.

[0086] The base region 14 is provided below the emitter region 12. In this example, the base region 14 is provided in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 60.

[0087] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+ type region with a higher doping concentration than the drift region 18. That is, the accumulation region 16 has a higher donor concentration than the drift region 18. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.

[0088] The mesa portion 61 of the diode portion 80 is in contact with the upper surface 21 of the semiconductor substrate 10. P type A base region 14 is provided in the mesa portion 61. A drift region 18 is provided below the base region 14. An accumulation region 16 may be provided below the base region 14 in the mesa portion 61. A contact region 15 may be provided below the contact hole 54 on the upper surface 21 of the mesa portion 61. By providing the contact region 15, the contact resistance between the mesa portion 61 and the emitter electrode 52 can be reduced.

[0089] The mesa portion 62 of the connection region 190 is in contact with the upper surface 21 of the semiconductor substrate 10. P type A base region 14 is provided on the mesa portion 62. A drift region 18 is provided below the base region 14. An accumulation region 16 may be provided below the base region 14 in the mesa portion 62. A contact region 15 may be provided below the contact hole 54 on the upper surface 21 of the mesa portion 62.

[0090] In each of the transistor section 70, the diode section 80, and the connection region 190, an N+ type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may have a concentration peak with a higher doping concentration than the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. The doping concentration of the drift region 18 may be the average value of the doping concentration in a region where the doping concentration distribution is approximately flat.

[0091] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peaks of the buffer region 20 may be located at the same depth as the chemical concentration peaks of hydrogen (protons) or phosphorus, for example. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0092] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than the acceptor concentration of the base region 14. The collector region 22 may contain the same acceptor as the base region 14, or may contain a different acceptor. The acceptor of the collector region 22 is, for example, boron.

[0093] In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. In the connection region 190, either a collector region 22 or a cathode region 82 may be provided below the buffer region 20. In this example, the collector regions 22 are provided below all of the mesa sections 62.

[0094] The donor concentration of the cathode region 82 is higher than the donor concentration of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements that serve as the donor and acceptor in each region are not limited to the above-mentioned examples. The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0095] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the upper surface 21 of the semiconductor substrate 10 at intervals in the X-axis direction. Each trench extends from the upper surface 21 of the semiconductor substrate 10, penetrating the base region 14, to below the base region 14. In regions where at least one of the emitter region 12, the contact region 15, and the accumulation region 16 is provided, each trench also penetrates these doped regions. The trenches penetrating the doped regions do not necessarily mean that the trenches are formed after the doped regions are formed. The trenches penetrating the doped regions also include trenches formed after the trenches are formed.

[0096] As described above, the transistor section 70 is provided with the gate trench section 40 and the dummy trench section 30. The diode section 80 and the connection region 190 are provided with the dummy trench section 30, but are not provided with the gate trench section 40.

[0097] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench and on the inner side of the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0098] The gate conductive portion 44 may be provided to be longer in the depth direction than the base region 14. The gate trench portion 40 in this cross section is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0099] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 covers the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length in the depth direction as the gate conductive portion 44.

[0100] In this example, the gate trench 40 and the dummy trench 30 are covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench 30 and the gate trench 40 may have a downwardly convex curved shape (a curved shape in cross section). In this specification, the depth position of the lower end of the gate trench 40 is defined as Zt.

[0101] In the reference example of FIG. 3 , the spacing between the trenches in the X-axis direction (i.e., the width of each mesa portion) is the same. The depth of each trench in the Z-axis direction (i.e., the bottom end position Zt) is also the same. In the semiconductor device 100 having trenches like this example, when a high voltage is applied, avalanche breakdown is likely to occur near the bottom end of the trench where the electric field concentrates. A P-type collector region 22 is provided on the bottom surface 23 of the transistor portion 70, and a PNP transistor composed of, for example, the base region 14, the drift region 18, and the collector region 22 is formed. If the transistor portion 70 and the diode portion 80 have the same trench structure, such as the spacing and depth, the avalanche breakdown voltage of the transistor portion 70 will be lower than that of the diode portion 80 due to the influence of current amplification of the PNP transistor. The avalanche breakdown voltage refers to the voltage at which avalanche breakdown first occurs at one of the points when the voltage between the collector electrode 24 and the emitter electrode 52 is gradually increased and each voltage is applied for a sufficiently long time. In other words, the avalanche breakdown voltage refers to the static breakdown voltage.

[0102] 4 shows an example of current density-voltage characteristics of the transistor section 70 and the diode section 80 according to the reference example. FIG. 4 shows the change in collector current when the collector voltage of the transistor section 70 is gradually increased while the gate voltage is set to 0 V or less, and the change in cathode current when the cathode voltage of the diode section 80 is gradually increased. The collector voltage and the cathode voltage are voltages between the collector electrode 24 and the emitter electrode 52. The collector current and the cathode current are currents flowing through the collector electrode 24.

[0103] When the collector voltage of the transistor section 70 reaches the avalanche breakdown voltage Va_t of the transistor section 70, avalanche breakdown occurs in a portion of the transistor section 70 where the breakdown voltage is low, causing a sudden increase in collector current. Similarly, when the cathode voltage of the diode section 80 reaches the avalanche breakdown voltage Va_d of the diode section 80, avalanche breakdown occurs in the diode section 80, causing a sudden increase in cathode current. The semiconductor device 100 is designed so that both the avalanche breakdown voltage Va_t of the transistor section 70 and the avalanche breakdown voltage Va_d of the diode section 80 are greater than the specified value V0 of the breakdown voltage of the semiconductor device 100.

[0104] The avalanche breakdown voltage Va_t of the transistor section 70 may be defined as the minimum voltage among the voltages in the portion where the collector voltage remains almost constant (flat) with respect to an increase in collector current in the current density-voltage characteristics shown in FIG. 5. The current density-voltage characteristics may be measured in an ambient temperature environment of room temperature (25°C). The avalanche breakdown voltage Va_d of the diode section 80 may be defined as the minimum voltage among the voltages in the portion where the cathode voltage remains almost constant (flat) in the current density-voltage characteristics shown in FIG. "Almost flat" means, for example, that the voltage fluctuates by 20 V or less while the current fluctuates by 100 times.

[0105] As another example of a definition method, the avalanche breakdown voltage Va_t of the transistor section 70 may be defined as the value of the collector voltage at a preset collector current value among the voltages in the portion where the collector voltage waveform is almost constant (flat) with respect to an increase in the collector current in the current density-voltage characteristics shown in FIG. 5. The avalanche breakdown voltage Va_d of the diode section 80 may be defined as the value of the cathode voltage at a preset cathode current value among the voltages in the portion where the cathode voltage is almost constant (flat) with respect to an increase in the cathode current in the current density-voltage characteristics shown in FIG. As an example, in the current density-voltage characteristics shown in FIG. 5, when the collector current or cathode current is 1×10 -3 (A / cm 2 ) is the collector voltage or cathode voltage when or avalanche breakdown voltage Va_d The preset collector current or cathode current value may be set to 1×10 in the current density-voltage characteristics shown in FIG. -4 (A / cm 2 ) or more, and may be 1 × 10 0 (A / cm 2 ) or less.

[0106] When avalanche breakdown occurs in the transistor section 70 and the current density of the collector current increases and reaches a negative resistance region, the current increase cannot be suppressed, resulting in destruction of the semiconductor device 100. Similarly, in the diode section 80, when the current density of the cathode current reaches a negative resistance region (omitted in FIG. 4), the current increase cannot be suppressed, resulting in destruction of the semiconductor device 100.

[0107] In the transistor section 70, the voltage (Vn_t-Va_t) that can rise from the voltage Va_t at which avalanche breakdown occurs to the voltage Vn_t at which the negative resistance region is reached is only a few volts, and the collector current that can be increased is also small. If the temperature of the semiconductor substrate 10 rises, the voltage Vn_t at which the negative resistance region is reached can also rise, but in the transistor section 70, the voltage and current that can rise from the avalanche breakdown to the negative resistance region are small, so the temperature of the semiconductor substrate 10 cannot be increased sufficiently, and the negative resistance region is easily reached.

[0108] On the other hand, in the diode section 80, the voltage that can rise from the voltage Va_d at which avalanche breakdown occurs to the voltage Vn_d at which the negative resistance region is reached (ΔV=Vn_d−Va_d) is relatively large, and the cathode current that can rise is also relatively large. Therefore, compared to the transistor section 70, the diode section 80 is less likely to reach the negative resistance region even when an avalanche breakdown occurs, and breakdown of the semiconductor device 100 can be suppressed.

[0109] The voltage Vn_d at which the diode section 80 reaches the negative resistance region is the voltage at which the cathode voltage changes from increasing to decreasing when the cathode current of the diode section 80 increases. The voltage Vn_d may be the maximum value of the cathode voltage in the characteristics shown in FIG. 5. The voltage Vn_t at which the transistor section 70 reaches the negative resistance region is the voltage at which the collector voltage (collector-emitter voltage) changes from increasing to decreasing when the collector current of the transistor section 70 increases. The voltage Vn_t may be the maximum value of the collector voltage in the characteristics shown in FIG. 5.

[0110] 4, the avalanche breakdown voltage Va_t of the transistor section 70 is smaller than the avalanche breakdown voltage Va_d of the diode section 80. Therefore, the transistor section 70 undergoes avalanche breakdown first. When the transistor section 70 undergoes avalanche breakdown, the semiconductor device 100 instantly reaches a negative resistance region, and is destroyed.

[0111] 5 shows an example of current density-voltage characteristics of the transistor section 70 and the diode section 80 according to the embodiment. The avalanche breakdown voltage Va_d in the diode section 80 of this embodiment is smaller than the avalanche breakdown voltage Va_t in the transistor section 70. This allows avalanche breakdown to occur in the diode section 80 before it occurs in the transistor section 70. Therefore, when avalanche breakdown occurs, it is possible to prevent the diode section 80 from instantly reaching a negative resistance region.

[0112] In this example, the avalanche breakdown voltage Va_d of the diode section 80 is 0.7 times or more and less than 1 time the avalanche breakdown voltage Va_t of the transistor section 70. By reducing the avalanche breakdown voltage Va_d of the diode section 80, it becomes easier to suppress avalanche breakdown in the transistor section 70. The avalanche breakdown voltage Va_d may be 0.98 times or less, 0.96 times or less, or even 0.9 times or less of the avalanche breakdown voltage Va_t. If the avalanche breakdown voltage Va_d of the diode section 80 is made too small, the avalanche breakdown voltage of the semiconductor device 100 will be reduced. The avalanche breakdown voltage Va_d may be 0.75 times or more, 0.8 times or more, or 0.85 times or more of the avalanche breakdown voltage Va_t.

[0113] The avalanche withstand voltage Va_d of the diode section 80 is greater than the specification value of the avalanche withstand voltage V0 of the semiconductor device 100. The avalanche withstand voltage Va_d may be greater than the average value of the specification value V0 of the avalanche withstand voltage and the avalanche withstand voltage Va_t of the transistor section 70. The avalanche withstand voltage Va_d of the diode section 80 can be adjusted by the spacing in the X-axis direction of the trench sections in the diode section 80 (or the width in the X-axis direction of the mesa section 61), the depth of the trench sections in the diode section 80, etc.

[0114] The voltage Vn_d at which the diode section 80 reaches the negative resistance region may be equal to or greater than the avalanche withstand voltage Va_t of the transistor section 70. The voltage Vn_d at which the diode section 80 reaches the negative resistance region may be equal to or greater than the voltage Vn_t at which the transistor section 70 reaches the negative resistance region. This prevents the transistor section 70 from reaching the negative resistance region first. The voltage Vn_d at which the diode section 80 reaches the negative resistance region may be equal to or smaller than the voltage Vn_t at which the transistor section 70 reaches the negative resistance region.

[0115] The current density-voltage characteristics of the transistor section 70 and the diode section 80 may be calculated using a general device simulation. The device simulation may be performed by solving Poisson's equation and the current continuity equation for electrons and holes under predetermined boundary conditions and initial conditions. The current density-voltage characteristics of the transistor section 70 may be calculated for a structure that simulates only the transistor section 70. Alternatively, calculations may be performed for a structure that simulates both the transistor section 70 and the diode section 80, and the current density-voltage characteristics of only the transistor section 70 may be extracted. The current density-voltage characteristics of the diode section 80 may be calculated for a structure that simulates only the diode section 80. Alternatively, calculations may be performed for a structure that simulates both the transistor section 70 and the diode section 80, and the current density-voltage characteristics of only the diode section 80 may be extracted.

[0116] FIG. 6 is a diagram showing an example of an ee cross section according to an embodiment. In this example, the spacing between trench portions in the diode section 80 is different from that of the reference example shown in FIG. 3. In this example, an intermediate region 200 may be provided instead of the connection region 190 in the reference example shown in FIG. 3. The intermediate region 200 and the connection region 190 differ in the spacing between trench portions in the X-axis direction. The other structures are similar to those of the examples described with reference to FIGS. 1 to 3. The intermediate region 200 is disposed between the diode section 80 and the transistor section 70 in the X-axis direction. A plurality of trench portions are provided in the intermediate region 200.

[0117] When viewed from above, the transistor section 70 is a region including the mesa section 60 in which the emitter region 12 is provided and the trench section adjacent to the mesa section 60. The collector region 22 is provided on the lower surface of the transistor section 70.

[0118] In top view, the diode section 80 is a region including the mesa section 61 where the emitter region 12 is not provided and the trench section adjacent to the mesa section 61. A cathode region 82 is provided on the lower surface of the diode section 80. The interval between the multiple trench sections in the diode section 80 in the X-axis direction is a constant value Xd. The length in the Z-axis direction of the multiple trench sections in the diode section 80 is also constant (depth position Zt of the bottom end). The avalanche breakdown voltage Va_d in the diode section 80 is smaller than the avalanche breakdown voltage Va_t in the transistor section 70.

[0119] In a top view, the intermediate region 200 is a region including the mesa portion 62 without the emitter region 12 and the trench portion adjacent to the mesa portion 62. At least one of the collector region 22 and the cathode region 82 is provided on the lower surface 23 of the intermediate region 200. One of the collector region 22 and the cathode region 82 may be provided on the lower surface 23 of the intermediate region 200 from the position in contact with the transistor portion 70 to the position in contact with the diode portion 80. In another example, the collector region 22 may be provided in the region in contact with the transistor portion 70 on the lower surface of the intermediate region 200, and the cathode region 82 may be provided in the region in contact with the diode portion 80. In this case, the boundary between the collector region 22 and the cathode region 82 is located in the intermediate region 200.

[0120] The boundary between the intermediate region 200 and the transistor section 70 is the center in the X-axis direction of the trench section (dummy trench section 30-1 in this example) that is closest to the diode section 80 among the trench sections that contact the emitter region 12. The trench section of the intermediate region 200 has a different structure from the trench section of the diode section 80. For example, the trench section of the intermediate region 200 differs from the trench section of the diode section 80 in at least one of the spacing between adjacent trench sections and the depth of the trench section. Alternatively, the trench section of the intermediate region 200 and the trench section of the diode section 80 may differ in the presence or absence of a first lower end region 202 (see FIG. 11) or a second lower end region 204 (see FIG. 13). The boundary between the intermediate region 200 and the diode section 80 is the center in the X-axis direction of the boundary trench section where the structure changes (dummy trench section 30-4 in this example). The avalanche breakdown voltage of the intermediate region 200 may be greater than the avalanche breakdown voltage of the diode section 80 and less than the avalanche breakdown voltage of the transistor section 70. In each example of this specification, the intermediate region 200 does not have to be provided. In this case, the transistor section 70 and the diode section 80 are provided in contact with each other.

[0121] Each of the diode section 80, the transistor section 70, and the intermediate region 200 has a plurality of trench sections arranged at intervals along the arrangement direction (X-axis direction) on the upper surface 21 of the semiconductor substrate 10.

[0122] At least some of the trench portions in the transistor portion 70 are arranged at a first interval Xt in the X-axis direction. The first interval Xt may be the maximum interval among the intervals between the trench portions in the transistor portion 70. In this example, all of the trench portions in the transistor portion 70 are arranged at the first interval Xt.

[0123] At least some of the trench portions in the diode portion 80 are arranged at a second interval Xd in the X-axis direction, which is larger than the first interval Xt. In this example, all of the trench portions in the diode portion 80 are arranged at the second interval Xd.

[0124] By increasing the second distance Xd between the trench portions in the diode portion 80, carriers from a wider area flow toward one trench portion. This makes it easier for an electric field to concentrate in one trench portion in the diode portion 80, reducing the avalanche breakdown voltage. In this example, the second distance Xd between the trench portions in the diode portion 80 is set so that the avalanche breakdown voltage Va_d in the diode portion 80 is less than 1 time but not less than 70% of the avalanche breakdown voltage Va_t in the transistor portion 70.

[0125] The second spacing Xd between the trench portions in the diode section 80 may be larger than the first spacing Xt between the trench portions in the transistor section 70, and may be 1.2 times or more, 2 times or more, 3 times or more, or 5 times or more the first spacing Xt. As an example, the first spacing Xt is 2.5 μm or less, and the second spacing Xd is 5 μm or more. However, if the second spacing Xd is made too large, the breakdown voltage of the diode section 80 becomes too low, so the second spacing Xd may be 50 μm or less, or may be 30 μm or less.

[0126] The intermediate region 200 has a plurality of trench portions. In this example, the intermediate region 200 has a plurality of dummy trench portions 30. As described above, the dummy trench portion 30-1 is disposed at the boundary between the transistor portion 70 and the intermediate region 200. The center of the dummy trench portion 30-1 in the X-axis direction is defined as the boundary position between the transistor portion 70 and the intermediate region 200. As described above, the dummy trench portion 30-4 is disposed at the boundary between the diode portion 80 and the intermediate region 200. The center of the dummy trench portion 30-4 in the X-axis direction is defined as the boundary position between the diode portion 80 and the intermediate region 200. One or more dummy trench portions 30 may be disposed between the dummy trench portion 30-1 and the dummy trench portion 30-4, and no other dummy trench portions 30 may be disposed between the dummy trench portion 30-1 and the dummy trench portion 30-4. In the example of FIG. 6, dummy trench portion 30-2 and dummy trench portion 30-3 are disposed between dummy trench portion 30-1 and dummy trench portion 30-4.

[0127] The intermediate region 200 has one or more mesa portions 62. In this example, the mesa portion 62-1 is disposed adjacent to the transistor portion 70, and the mesa portion 62-3 is disposed adjacent to the diode portion 80. One or more mesa portions 62 may be disposed between the mesa portion 62-1 and the mesa portion 62-3, and other mesa portions 62 may not be disposed. In the example of FIG. 6, the mesa portion 62-2 is disposed between the mesa portion 62-1 and the mesa portion 62-3.

[0128] In the intermediate region 200 of this example, the trench spacing increases monotonically from the dummy trench portion 30-1 to the dummy trench portion 30-4 as it approaches the diode portion 80. That is, in the intermediate region 200 of this example, the mesa width increases monotonically from the mesa portion 62-1 to the mesa portion 62-3 as it approaches the diode portion 80. The trench spacing is the distance between the centers of adjacent trench portions in the X-axis direction. The mesa width is the width of the region sandwiched between two adjacent trench portions in the X-axis direction. A monotonically increasing trench spacing means that the trench spacing increases in at least one location in the direction from the dummy trench portion 30-1 to the dummy trench portion 30-4, and there is no location where the trench spacing decreases. That is, a region where the trench spacing does not change may be included in the direction from the dummy trench portion 30-1 to the dummy trench portion 30-4.

[0129] In the example of FIG. 6, the trench spacing between dummy trench portion 30-k and dummy trench portion 30-k+1 is designated Xk, where k is an integer greater than or equal to 1. Dummy trench portion 30-k+1 is disposed adjacent to dummy trench portion 30-k on the diode portion 80 side. Trench spacing Xk may monotonically increase as k increases. By monotonically increasing trench spacing Xk, the avalanche breakdown voltage in one mesa portion 62 can be gradually changed in the X-axis direction. This prevents electric field intensity from concentrating in the intermediate region 200.

[0130] The intermediate region 200 has a transistor-side region 201 that contacts the transistor portion 70. In the transistor-side region 201, one or more trench portions (in this example, dummy trench portions 30) are arranged at the same first interval Xt as the trench interval in the transistor portion 70. In the example of FIG. 6, the trench interval X1 is equal to the first interval Xt. That is, the region from the dummy trench portion 30-1 to the dummy trench portion 30-2 is the transistor-side region 201. The boundary positions in the X-axis direction of the cathode region 82 and the collector region 22 in the intermediate region 200 may be arranged in the transistor-side region 201.

[0131] The trench interval X3 at the location closest to the diode portion 80 is larger than the trench interval X1. The trench interval X3 is smaller than the second interval Xd in the diode portion 80.

[0132] In the intermediate region 200, the trench interval may increase at one location, or may increase at a plurality of locations. In this example, Xt = X1 < X2 < X3 < Xd. That is, the trench intervals in the X-axis direction of the plurality of trench portions in the intermediate region 200 of this example are larger the closer they are to the diode portion 80. X3 may be equal to Xd. In this case, up to the dummy trench portion 30-3 is the diode portion 80.

[0133] FIG. 7 is a diagram showing another example of the e-e cross section according to the embodiment. In this example, the trench interval X1 in the transistor-side region 201 is different from the example of FIG. 6. Other structures may be the same as the example of FIG. 6. The trench interval X1 of the transistor-side region 201 in this example is smaller than the first interval Xt in the transistor portion 70. In the example of FIG. 7, the transistor-side region 201 has two trench portions, but may have more trench portions. Even in this case, each trench interval Xk in the transistor-side region 201 is smaller than the first interval Xt. Each trench interval Xk in the transistor-side region 201 may be constant, or may increase monotonically toward the diode portion 80.

[0134] In the intermediate region 200, a relatively large current flows in the portion adjacent to the transistor portion 70. Therefore, by reducing the trench pitch in the transistor-side region 201 at this location, the breakdown voltage at this location can be increased, and the destruction of the semiconductor device 100 can be suppressed.

[0135] In the intermediate region 200, the trench pitch X2 of the trench portion adjacent to the transistor-side region 201 is larger than the trench pitch X1 of the transistor-side region 201. The trench pitch X2 may be the same as the first pitch Xt, may be smaller than the first pitch Xt, or may be larger. The trench pitch X1 of the transistor-side region 201 is the smallest trench pitch in the intermediate region 200. In this example, Xt > X1 < X2 < X3 < Xd. X3 may be equal to Xd. The boundary position in the X-axis direction between the collector region 22 and the cathode region 8two may be arranged in the region from below the dummy trench portion 30-1 to below the dummy trench portion 30-2.

[0136] FIG. 8 is a diagram showing another example of the e-e cross section according to the embodiment. In this example, the configuration of the transistor-side region 201 is different from that in the example of FIG. 6. Other structures may be the same as those in the example of FIG. 6. The transistor-side region 201 in this example includes three or more trench portions. In FIG. 8, the dummy trench portions from 30-1 to 30-4 are the transistor-side region 201. Similar to the example of FIG. 6, the trench pitches (X1, X2, X3 in this example) in the transistor-side region 201 may be the same as the first pitch Xt, or may be smaller than the first pitch Xt. The boundary position between the cathode region 8two and the collector region 22 is arranged below the dummy trench portion 30-4, which is the dummy trench portion closest to the diode portion 80 side, among the trench portions of the transistor-side region 201.

[0137] FIG. 9 is a diagram showing another example of an ee cross section according to an embodiment. In this example, the length in the Z-axis direction of the trench portion of the diode section 80 differs from the examples described in FIGS. 3 to 8. Furthermore, this example has an intermediate region 200 instead of the connection region 190 in the reference example shown in FIG. 3. The intermediate region 200 in this example differs from the examples described in FIGS. 6 to 8 in the length in the Z-axis direction of the trench portion. Other structures in the intermediate region 200 (for example, trench spacing Xk) may be similar to any of the examples described in FIGS. 6 to 8, or may be the same as the connection region 190 described in FIG. 3.

[0138] At least some of the trench portions in the transistor portion 70 are arranged with a first length Ztt in the Z-axis direction. The first length Ztt may be the maximum length among the lengths of the trench portions in the transistor portion 70. In this example, all of the trench portions in the transistor portion 70 have the first length Ztt.

[0139] At least some of the trench portions in the diode portion 80 have a second length Ztd in the Z-axis direction that is greater than the first length Ztt. In this example, all of the trench portions in the diode portion 80 have the second length Ztd.

[0140] Increasing the second length Ztd of the trench portion in the diode portion 80 makes it easier for current to concentrate at the bottom end of the trench portion in the diode portion, thereby reducing the avalanche breakdown voltage. In this example, the second length Ztd of the trench portion in the diode portion 80 is set so that the avalanche breakdown voltage Va_d in the diode portion 80 is less than 1 time but not less than 70% of the avalanche breakdown voltage Va_t in the transistor portion 70. As described with reference to FIGS. 6 to 8 , when the trench spacing Xd of the diode portion 80 and the trench spacing Xt of the transistor portion 70 are made to be further different, the lengths of the trench portions and the trench spacing are set so that the avalanche breakdown voltage Va_d in the diode portion 80 is less than 1 time but not less than 70% of the avalanche breakdown voltage Va_t in the transistor portion 70.

[0141] The second length Ztd may be 1.5 times or more, or may be 2 times or more, the first length Ztt. However, if the second length Ztd is made too large, the breakdown voltage of the diode section 80 becomes too small, so the second length Ztd may be 5 times or less, or may be 4 times or less, the first length Ztt.

[0142] The intermediate region 200 has a plurality of trench portions. In this example, the intermediate region 200 has a plurality of dummy trench portions 30. In this example, the dummy trench portion 30-1 is disposed at the boundary between the transistor portion 70 and the intermediate region 200, and the dummy trench portion 30-5 is disposed at the boundary between the diode portion 80 and the intermediate region 200. One or more dummy trench portions 30 may be disposed between the dummy trench portion 30-1 and the dummy trench portion 30-5, and other dummy trench portions 30 may not be disposed. In the example of FIG. 9, the dummy trench portion 30-2, the dummy trench portion 30-3, and the dummy trench portion 30-4 are disposed between the dummy trench portion 30-1 and the dummy trench portion 30-5.

[0143] In the intermediate region 200 of this example, the length of the trench portion in the Z-axis direction monotonically increases from dummy trench portion 30-1 to dummy trench portion 30-5 as it approaches the diode portion 80. A monotonically increasing length of the trench portion means that in the direction from dummy trench portion 30-1 to dummy trench portion 30-5, the length of the trench portion increases at least in one location and there is no location where the length of the trench portion decreases. In other words, in the direction from dummy trench portion 30-1 to dummy trench portion 30-5, there may be a region where the length of the trench portion does not change.

[0144] In the example of FIG. 9, let the length in the Z-axis direction of the dummy trench portion 30-k be Ztk. Here, k is an integer of 1 or more. Also, the dummy trench portion 30-k+1 is arranged adjacent to the dummy trench portion 30-k on the side of the diode portion 80. The length Ztk may increase monotonically as k increases. By the monotonic increase of the trench length Ztk, the avalanche breakdown voltage can be gradually changed in the X-axis direction.

[0145] The intermediate region 200 has a transistor-side region 201 that contacts the transistor portion 70. In the transistor-side region 201, one or more trench portions (in this example, dummy trench portions 30) are arranged with the same first length Ztt as the transistor portion 70. In the example of FIG. 9, the trench lengths Zt1 and Zt2 are equal to the first length Ztt. That is, the region from the dummy trench portion 30-1 to the dummy trench portion 30-2 is the transistor-side region 201. The boundary positions in the X-axis direction of the cathode region 82 and the collector region 22 in the intermediate region 200 may be arranged in the transistor-side region 201.

[0146] The trench length Zt4 at the location closest to the diode portion 80 is larger than the trench length Zt1. The trench length Zt4 is smaller than the second length Ztd in the diode portion 80.

[0147] In the intermediate region 200, the trench length may increase at one location, or may increase at a plurality of locations. In this example, Ztt = Zt1 = Zt2 < Zt3 = Zt4 < Ztd. In other examples, the trenches in the X-axis direction of the plurality of trench portions in the intermediate region 200 length may be larger the closer they are to the diode portion 80. That is, Ztt = Zt1 < Zt2 < Zt3 < Zt4 < Ztd may also be possible.

[0148] FIG. 10 is a diagram showing another example of the e-e cross section according to the embodiment. In this example, the trench length of any one of the trench portions in the transistor-side region 201 is different from that in the example of FIG. 9. Other structures may be the same as those in the example of FIG. 9. The trench length (Zt2 in FIG. 10) of any one of the trench portions in the transistor-side region 201 of this example is smaller than the first length Ztt in the transistor portion 70.

[0149] In the example of FIG. 10, the trench length Zt2 of one dummy trench portion 30-2 in the transistor-side region 201 is smaller than the first length Ztt. In other examples, the transistor-side region 201 may include a plurality of dummy trench portions 30 having trench lengths smaller than the first length Ztt. The trench lengths of these dummy trench portions 30 may be constant or may increase monotonically toward the diode portion 80.

[0150] In the middle region 200, the current flows relatively easily in the portion adjacent to the transistor portion 70. Therefore, by reducing the trench length of the transistor-side region 201, the breakdown voltage at this location can be increased, and the destruction of the semiconductor device 100 can be suppressed.

[0151] The trench length Zt3 of the trench portion adjacent to the transistor-side region 201 is larger than the trench length Zt2. The trench length Zt3 may be the same as the first interval Xt or may be larger than the first interval Xt. The trench length Zt2 of the transistor-side region 201 is the smallest trench interval in the middle region 200. In this example, Ztt = Zt1 > Zt2 < Zt3 = Zt4 < Ztd. The boundary position in the X-axis direction between the collector region 22 and the cathode region 82 may be arranged in the region from below the dummy trench portion 30-1 to below the dummy trench portion 30-2.

[0152] FIG. 11 is a diagram showing another example of an ee cross section according to an embodiment. This example differs from the examples described with reference to FIGS. 3 to 10 in that a first lower end region 202 is provided in the transistor section 70 and the intermediate region 200. As with the example described with reference to FIG. 3, the trench spacing Xt and trench length may be constant in the transistor section 70, the diode section 80, and the intermediate region 200. The transistor section 70, the diode section 80, and the intermediate region 200 may have the same trench spacing as the examples described with reference to FIGS. 6 to 8 and may have the same trench length as the examples described with reference to FIGS. 9 and 10.

[0153] The transistor section 70 has a P-type first lower end region 202 provided in contact with a lower end 212 of at least one trench section. The first lower end region 202 is provided to cover from the lower end 212 of the trench section to a part of the sidewall 213 of the trench section. In this example, the first lower end region 202 of the transistor section 70 is in contact with the accumulation region 16. By providing the first lower end region 202, electric field concentration at the lower end 212 of the trench section of the transistor section 70 can be alleviated. The doping concentration of the first lower end region 202 may be lower or higher than the doping concentration of the base region 14. The doping concentration of the first lower end region 202 may be lower than the collector region 22 and may be lower than the contact region 15.

[0154] The first lower end region 202 may be provided in all trench portions of the transistor portion 70. The first lower end regions 202 provided at the lower ends 212 of the respective trench portions may be separated from each other in the X-axis direction as shown in FIG. 11 , or may be connected to each other in the X-axis direction.

[0155] The first lower end region 202 is not provided at the lower end 212 of at least one trench portion of the diode portion 80. In other words, the lower end 212 of the trench portion is not in contact with a P-type region. In this example, the lower end 212 of the trench portion is in contact with the drift region 18. The first lower end region 202 does not have to be provided at the lower ends 212 of all trench portions of the diode portion 80.

[0156] By providing the first lower end region 202 in the transistor section 70 and not providing the first lower end region 202 in the diode section 80, the avalanche breakdown voltage of the transistor section 70 can be increased and the avalanche breakdown voltage of the diode section 80 can be relatively reduced. Even with this structure, as shown in FIG. 5, the avalanche breakdown voltage of the diode section 80 can be adjusted to less than 1 time but 70% or more of the avalanche breakdown voltage of the transistor section 70. The avalanche breakdown voltage of the transistor section 70 can be adjusted by the doping concentration of the first lower end region 202, etc. Furthermore, the avalanche breakdown voltage of the diode section 80 may be adjusted to less than 1 time but 70% or more of the avalanche breakdown voltage of the transistor section 70 by combining two or more of the adjustment of the trench spacing Xk as described with reference to FIGS. 6 to 8, the adjustment of the trench length as described with reference to FIGS. 9 and 10, and the adjustment using the first lower end region 202 as described with reference to FIG. 11.

[0157] The trench portions of the intermediate region 200 are provided with first lower end regions 202, except for the dummy trench portion 30-3 located at the boundary with the diode portion 80. In the example of FIG. 11 , the first lower end regions 202 are provided in contact with the lower ends 212 of the dummy trench portions 30-1 and 30-2. The doping concentration of each first lower end region 202 of the intermediate region 200 is the same as the doping concentration of the first lower end region 202 of the transistor portion 70. In another example, the doping concentration of the first lower end region 202 of the intermediate region 200 may monotonically decrease the closer to the diode portion 80. The boundary position in the X-axis direction between the collector region 22 and the cathode region 82 may be located in a region from below the dummy trench portion 30-1 to below the dummy trench portion 30-2.

[0158] FIG. 12 is a diagram showing another example of an ee cross section according to an embodiment. In this example, the number of trench portions in the intermediate region 200 is different from the example in FIG. 11. The other structures are similar to the example in FIG. 11. The intermediate region 200 in this example has three or more trench portions each provided with a first lower end region 202. In FIG. 12, the first lower end region 202 is provided in four dummy trench portions 30, from dummy trench portion 30-1 to dummy trench portion 30-4.

[0159] FIG. 13 is a diagram showing another example of an ee cross section according to an embodiment. This example differs from the examples described with reference to FIGS. 3 to 12 in that a second lower end region 204 is provided in the diode section 80. As with the example described with reference to FIG. 3, the trench spacing Xt and trench length may be constant in the transistor section 70, the diode section 80, and the intermediate region 200. The transistor section 70, the diode section 80, and the intermediate region 200 may have a trench spacing similar to that in the examples described with reference to FIGS. 6 to 8 and a trench length similar to that in the examples described with reference to FIGS. 9 and 10. Furthermore, as with the examples described with reference to FIGS. 11 and 12, the transistor section 70 and the intermediate region 200 may be provided with a first lower end region 202.

[0160] The diode section 80 has an N-type second lower end region 204 provided in contact with a lower end 212 of at least one trench section. The second lower end region 204 is provided to cover from the lower end 212 of the trench section to a part of the sidewall 213 of the trench section. The lower end of the second lower end region 204 is located closer to the lower surface 23 than the lower end of the accumulation region 16. The doping concentration of the second lower end region 204 is higher than the doping concentration of the drift region 18. The doping concentration of the second lower end region 204 may be two or more times, five or more times, or ten or more times the doping concentration of the drift region 18. The doping concentration of the second lower end region 204 may be lower than the doping concentration of the accumulation region 16. The doping concentration of the second lower end region 204 may be lower than the doping concentration of the cathode region 82. By providing the second lower end region 204, the electric field concentration at the lower end 212 of the trench portion of the diode portion 80 is promoted, and the avalanche breakdown voltage of the diode portion 80 can be reduced.

[0161] The second lower end region 204 may be provided in half or more of the trench portions of the diode section 80, may be provided in 90% or more of the trench portions, or may be provided in all of the trench portions. The second lower end regions 204 provided at the lower ends 212 of the respective trench portions may be separated from each other in the X-axis direction as shown in FIG. 13 , or may be connected to each other in the X-axis direction.

[0162] The second lower end region 204 is not provided at the lower end 212 of at least one trench portion of the transistor portion 70. In other words, the lower end 212 of the trench portion is not in contact with an N-type region having a higher doping concentration than the drift region 18. In this example, the lower end 212 of the trench portion is in contact with the drift region 18. The second lower end region 204 does not have to be provided at the lower ends 212 of all trench portions of the transistor portion 70. The second lower end region 204 is not provided at the lower ends 212 of all trench portions of the intermediate region 200.

[0163] The doping concentration of each second lower end region 204 may be uniform. In another example, the doping concentrations of the multiple second lower end regions 204 may be different from one another. As an example, the doping concentration of the second lower end region 204 at the center of the diode section 80 in the X-axis direction may be higher than the doping concentration of the second lower end region 204 at the end of the diode section 80 in the X-axis direction. This makes it easier for avalanche breakdown to occur near the center of the diode section 80, which is away from the transistor section 70.

[0164] The boundary position between the collector region 22 and the cathode region 82 is located closer to the transistor section 70 than the second lower end region 204. This allows the P+ type collector region 22 and the N type second lower end region 204 to be located apart from each other, thereby suppressing the movement of carriers between the collector region 22 and the second lower end region 204.

[0165] With the structure of this example, the avalanche breakdown voltage of the diode section 80 can also be adjusted to less than 1 time and 70% or more of the avalanche breakdown voltage of the transistor section 70, as shown in FIG. Diode section 80 The avalanche breakdown voltage of the diode section 80 can be adjusted by the doping concentration of the second lower end region 204, etc. The avalanche breakdown voltage of the diode section 80 may be adjusted to less than 1 time but not less than 70% of the avalanche breakdown voltage of the transistor section 70 by combining two or more of the adjustment of the trench interval Xk as described with reference to Figures 6 to 8, the adjustment of the trench length as described with reference to Figures 9 and 10, the adjustment using the first lower end region 202 as described with reference to Figures 11 and 12, and the adjustment using the second lower end region 204 as described with reference to Figure 13.

[0166] FIG. 14 is a diagram showing another example of an ee cross section according to an embodiment. This example differs from the examples described with reference to FIGS. 3 to 13 in that a lifetime adjusting section 208 is provided in the diode section 80. As with the example described with reference to FIG. 3, the trench spacing Xt and trench length may be constant in the transistor section 70, the diode section 80, and the intermediate region 200. The transistor section 70, the diode section 80, and the intermediate region 200 may have a trench spacing similar to that of the examples described with reference to FIGS. 6 to 8 and a trench length similar to that of the examples described with reference to FIGS. 9 and 10. As with the examples described with reference to FIGS. 11 and 12, the transistor section 70 and the intermediate region 200 may be provided with a first lower end region 202. As with the example described with reference to FIG. 13, the diode section 80 may be provided with a second lower end region 204.

[0167] The lifetime adjustment portion 208 is disposed on the upper surface 21 of the semiconductor substrate 10, below the lower end of the trench portion. The lifetime adjustment portion 208 is a region where the carrier lifetime exhibits a minimum value in the depth direction of the semiconductor substrate 10. In regions where many lattice defects 206 remain, carriers are captured by the lattice defects 206, shortening the carrier lifetime. By adjusting the carrier lifetime, characteristics such as the turn-off time of the semiconductor device 100 can be adjusted. In this example, a charged particle beam such as a helium ion beam is irradiated to a predetermined depth position to form lattice defects 206 near the depth position, thereby forming the lifetime adjustment portion 208. In this example, the lifetime adjustment portion 208 is provided over the entire diode portion 80 in the X-axis direction. The lifetime adjustment portion 208 may be provided extending over the entire intermediate region 200 in the X-axis direction. The lifetime adjustment portion 208 may also be provided extending over a portion of the transistor portion 70 in the X-axis direction.

[0168] The carrier lifetime in the region where the lifetime adjustment unit 208 is provided may be less than 10% and not less than 0.001% compared to the region where the lifetime adjustment unit 208 is not provided. For example, compared to a reference carrier lifetime at the center in the depth direction of the drift region 18 of the transistor unit 70, the carrier lifetime in the lifetime adjustment unit 208 is less than 10% and not less than 0.001%. The carrier lifetime in the lifetime adjustment unit 208 may be not more than 1% of the reference carrier lifetime, or may be not more than 0.1%. The carrier lifetime in the lifetime adjustment unit 208 may be not less than 0.01% of the reference carrier lifetime.

[0169] 3 to 13, when lifetime adjusting section 208 is not provided, the carrier lifetime in drift region 18 is approximately uniform. "Almost uniform" means, for example, that the carrier lifetime in the entire drift region 18 is distributed within a range of 100% or less and 10% or more of the maximum value of the carrier lifetime in drift region 18. When lifetime adjusting section 208 is not provided, the carrier lifetime in the entire drift region 18 may be distributed within a range of 100% or less and 50% or more of the maximum value of the carrier lifetime in drift region 18.

[0170] Fig. 15 is a diagram showing another example of the ee cross section according to the embodiment. In this example, a lifetime adjusting section 208 is provided in the configuration shown in Fig. 9. The lifetime adjusting section 208 may also be provided in the configuration shown in Fig. 10.

[0171] Fig. 16 is a diagram showing another example of the ee cross section according to the embodiment. In this example, a lifetime adjusting section 208 is provided in the configuration shown in Fig. 11. The lifetime adjusting section 208 may also be provided in the configuration shown in Fig. 12.

[0172] 17 is a diagram showing another example of the ee cross section according to the embodiment. In this example, a lifetime adjusting section 208 is provided in the configuration shown in FIG.

[0173] FIG. 18 shows the relationship between the trench spacing in the transistor section 70 and the diode section 80 and the avalanche breakdown voltage in the transistor section 70 and the diode section 80. In FIG. 18, the measured values for each sample are plotted as squares and circles. In both the transistor section 70 and the diode section 80, increasing the trench spacing reduces the avalanche breakdown voltage. In other words, adjusting the trench spacing can adjust the avalanche breakdown voltage. In this example, when the trench spacing in the transistor section 70 is 1 μm, the breakdown voltage of the transistor section 70 is 1425 V. In contrast, when the trench spacing in the diode section 80 is 5.5 μm or greater, the breakdown voltage of the diode section 80 can be reduced to less than 1425 V. The trench spacing in the diode section 80 may be 5.5 times or greater, 6 times or greater, or 10 times or greater than the trench spacing in the transistor section 70.

[0174] FIG. 19 shows the relationship between the trench length in the transistor section 70 and the diode section 80 and the avalanche breakdown voltage in the transistor section 70 and the diode section 80. In FIG. 19, the measured values for each sample are plotted as squares and circles. In both the transistor section 70 and the diode section 80, increasing the trench length reduces the avalanche breakdown voltage. In other words, adjusting the trench length can adjust the avalanche breakdown voltage. In this example, when the trench length in the transistor section 70 is 5 μm, the breakdown voltage of the transistor section 70 is 1425 V. In contrast, when the trench spacing in the diode section 80 is 12 μm or greater, the breakdown voltage of the diode section 80 can be reduced to less than 1425 V. The trench length in the diode section 80 may be 2.4 times or more, 3 times or more, or 5 times or more the trench length of the transistor section 70.

[0175] FIG. 20 is a diagram showing the relationship between the trench spacing in the transistor section 70 and the diode section 80 and the avalanche breakdown voltage in the transistor section 70 and the diode section 80. The diode section 80 of this example is the same as the diode section 80 of the example of FIG. 18. The transistor section 70 of the example of FIG. 18 does not have a first lower end region 202, but the transistor section 70 of this example has a first lower end region 202. The transistor section 70 of this example is the same as the transistor section 70 of the example of FIG. 18 except for the provision of the first lower end region 202. As shown in FIGS. 18 and 20 , the provision of the first lower end region 202 increases the avalanche breakdown voltage of the transistor section 70. In other words, the provision of the first lower end region 202 makes it possible to adjust the avalanche breakdown voltage.

[0176] 21 is a diagram showing the relationship between the dose (or doping concentration) in the second lower end region 204 of the diode section 80 and the avalanche breakdown voltage in the diode section 80. In FIG. 21, the avalanche breakdown voltage when the second lower end region 204 is not provided is plotted as squares. Increasing the dose in the second lower end region 204 reduces the avalanche breakdown voltage. In other words, the avalanche breakdown voltage can be adjusted by adjusting the dose in the second lower end region 204.

[0177] 22 is a diagram illustrating the maximum non-destructive energy density of the semiconductor device 100. The maximum non-destructive energy density refers to the energy density applied immediately before the semiconductor device 100 is destroyed when the energy applied to the semiconductor device 100 is gradually increased in an unclamped dielectric switching test (UIS test).

[0178] When the semiconductor device 100 is transitioned from the on state to the off state at time t1, the current density of the main current flowing through the semiconductor device 100 gradually decreases, and the collector-emitter voltage of the semiconductor device 100 increases. 22 As shown in the lower graph, the energy applied is the time integral of the product of the main current density and the collector-emitter voltage (V × J).

[0179] When the current density of the main current flowing when semiconductor device 100 is in the on state is gradually increased and the turn-off operation is repeated, semiconductor device 100 is destroyed at time t2 during the turn-off operation at a certain current density, and the main current increases rapidly. The maximum non-destructive energy density is an energy slightly smaller than the energy applied from time t1 to time t2 during the turn-off operation. The maximum non-destructive energy density may be the energy applied during the turn-off operation, or may be the energy applied during the turn-off operation subtracted by a predetermined margin, or the energy applied during the turn-off operation immediately before the turn-off operation.

[0180] Fig. 23 shows the relationship between the avalanche withstand voltage Va_d and the maximum non-destructive energy density in the diode section 80. The horizontal axis in Fig. 23 shows the avalanche withstand voltage Va_d normalized by the avalanche withstand voltage Va_t in the transistor section 70 (i.e., Va_d / Va_t).

[0181] The maximum non-destructive energy density when the avalanche withstand voltage Va_d in the diode section 80 is the same as the avalanche withstand voltage Va_t in the transistor section 70 (Va_d / Va_t=1) is defined as a reference value S0.

[0182] The semiconductor device 100 may have an avalanche withstand voltage ratio between the diode section 80 and the transistor section 70 such that the maximum non-destructive energy density is greater than a reference value S. As an example, the semiconductor device 100 has an avalanche withstand voltage Va_d of the diode section 80 that is 70% or more but less than 100% of the avalanche withstand voltage Va_t of the transistor section 70.

[0183] The semiconductor device 100 has a maximum non-destructive maximum energy density of S max The semiconductor device 100 may have an avalanche breakdown voltage ratio of the diode section 80 and the transistor section 70 that is 80% or more of the maximum non-destructive energy density S maxThe semiconductor device 100 may have an avalanche breakdown voltage ratio of the diode section 80 and the transistor section 70 that is 90% or more of the reference value S0 and the maximum value S1. max The semiconductor device 100 may have an avalanche withstand voltage ratio of the diode section 80 and the transistor section 70 that is equal to or greater than the intermediate value between the avalanche withstand voltage Va_t and the avalanche withstand voltage Va_d of the diode section 80. The semiconductor device 100 may have an avalanche withstand voltage Va_d of the diode section 80 that is equal to or greater than 75% of the avalanche withstand voltage Va_t of the transistor section 70, or may be equal to or greater than 80%. The semiconductor device 100 may have an avalanche withstand voltage Va_d of the diode section 80 that is less than 100%, or may be equal to or less than 95%, or may be equal to or less than 90% of the avalanche withstand voltage Va_t of the transistor section 70.

[0184] 24 is a diagram showing an example of a method for manufacturing the semiconductor device 100. First, in a reference value acquisition step S302, one or more semiconductor devices are used to acquire the reference value S0 of the non-destructive maximum energy density described in FIGS. 22 and 23. In S302, the reference value S0 is acquired by an unclamped dielectric switching test. The one or more semiconductor devices used to acquire the reference value S0 are referred to as the first semiconductor device.

[0185] Next, in setting step S304, as explained in FIG. 23, the avalanche withstand voltage ratios of the diode section 80 and the transistor section 70 are set so that the non-destructive maximum energy density is greater than the reference value S0.

[0186] Next, in design stage S306, the structures of the diode section 80 and the transistor section 70 are designed so as to satisfy the avalanche breakdown voltage ratio set in S304. In S306, as described with reference to FIGS. 5 to 17 , the avalanche breakdown voltage ratio of the diode section 80 and the transistor section 70 is adjusted by adjusting the spacing between the trench sections, the depth of the trench sections, the arrangement of the first lower end region 202, the arrangement of the second lower end region 204, the arrangement of the lifetime adjusting section 208, and the like. The semiconductor device in which the avalanche breakdown voltage ratios of the diode section 80 and the transistor section 70 have been adjusted is referred to as a second semiconductor device.

[0187] Next, in manufacturing stage S308, the semiconductor device 100 is manufactured based on the design in S306. The semiconductor device 100 is a second semiconductor device. In this way, the semiconductor device 100 can be manufactured. The semiconductor device 100 has the avalanche breakdown voltage described with reference to FIG. 5.

[0188] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0189] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0190] 10 semiconductor substrate, 11 well region, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 18 drift region, 20 buffer region, 21 upper surface, 22 collector region, 23 lower surface, 24 collector electrode, 29 straight portion, 30 dummy trench portion, 31 tip portion, 32 dummy insulating film, 34 dummy conductive portion, 38 interlayer insulating film, 39 straight portion, 40 gate trench portion, 41 tip portion, 42 gate insulating film, 44 gate conductive portion, 52 emitter electrode, 5 4 contact hole, 60, 61, 62 mesa portion, 70 transistor portion, 80 diode portion, 81 extension region, 82 cathode region, 90 edge termination structure portion, 100 semiconductor device, 130 peripheral gate wiring, 131 active side gate wiring, 160 active portion, 162 edge, 164 gate pad, 190 connection region, 200 intermediate region, 201 transistor side region, 202 first lower end region, 204 second lower end region, 206 lattice defect, 208 lifetime adjusting portion, 212 lower end, 213 sidewall

Claims

1. A semiconductor substrate having an upper surface and a lower surface and having a first conductivity type drift region provided therein; a transistor section including a collector region of a second conductivity type in contact with the lower surface of the semiconductor substrate, and an emitter region of a first conductivity type provided in contact with the upper surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a diode portion having a cathode region of a first conductivity type in contact with the lower surface of the semiconductor substrate; Equipped with an avalanche breakdown voltage in the diode section is 0.7 times or more and less than 1 time the avalanche breakdown voltage in the transistor section; the diode section and the transistor section have a plurality of trench sections arranged at intervals along an arrangement direction on the upper surface of the semiconductor substrate, At least some of the trench portions in the transistor portion are arranged at a first interval in the arrangement direction, At least some of the trench portions in the diode portion are arranged at second intervals in the arrangement direction that are larger than the first intervals. Semiconductor device.

2. A semiconductor substrate having an upper surface and a lower surface and having a first conductivity type drift region provided therein; a transistor section including a collector region of a second conductivity type in contact with the lower surface of the semiconductor substrate, and an emitter region of a first conductivity type provided in contact with the upper surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a diode portion having a cathode region of a first conductivity type in contact with the lower surface of the semiconductor substrate; Equipped with an avalanche breakdown voltage in the diode section is 0.7 times or more and less than 1 time the avalanche breakdown voltage in the transistor section; the diode section and the transistor section have a plurality of trench sections arranged at intervals along an arrangement direction on the upper surface of the semiconductor substrate, At least a part of the trench portion in the transistor portion has a first length in a depth direction of the semiconductor substrate, At least a part of the trench portion in the diode portion has a second length in the depth direction that is greater than the first length, an intermediate region disposed between the diode portion and the transistor portion, the intermediate region having a plurality of trench portions and including the cathode region and the collector region; the intermediate region has a transistor side region in contact with the transistor portion, The transistor-side region has the trench portion of the first length. Semiconductor device.

3. A semiconductor substrate having an upper surface and a lower surface and having a first conductivity type drift region provided therein; a transistor section including a collector region of a second conductivity type in contact with the lower surface of the semiconductor substrate, and an emitter region of a first conductivity type provided in contact with the upper surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a diode portion having a cathode region of a first conductivity type in contact with the lower surface of the semiconductor substrate; Equipped with an avalanche breakdown voltage in the diode section is 0.7 times or more and less than 1 time the avalanche breakdown voltage in the transistor section; the diode section and the transistor section have a plurality of trench sections arranged at intervals along an arrangement direction on the upper surface of the semiconductor substrate, At least a part of the trench portion in the transistor portion has a first length in a depth direction of the semiconductor substrate, At least a part of the trench portion in the diode portion has a second length in the depth direction that is greater than the first length, an intermediate region disposed between the diode portion and the transistor portion, the intermediate region having a plurality of trench portions and including the cathode region and the collector region; the intermediate region has a transistor side region in contact with the transistor portion, The transistor-side region has the trench portion having a length smaller than the first length. Semiconductor device.

4. A semiconductor substrate having an upper surface and a lower surface and having a first conductivity type drift region provided therein; a transistor section including a collector region of a second conductivity type in contact with the lower surface of the semiconductor substrate, and an emitter region of a first conductivity type provided in contact with the upper surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a diode portion having a cathode region of a first conductivity type in contact with the lower surface of the semiconductor substrate; Equipped with an avalanche breakdown voltage in the diode section is 0.7 times or more and less than 1 time the avalanche breakdown voltage in the transistor section; the diode section and the transistor section have a plurality of trench sections arranged at intervals along an arrangement direction on the upper surface of the semiconductor substrate, At least a part of the trench portion in the transistor portion has a first length in a depth direction of the semiconductor substrate, At least a part of the trench portion in the diode portion has a second length in the depth direction that is greater than the first length, an intermediate region disposed between the diode portion and the transistor portion, the intermediate region having a plurality of trench portions and including the cathode region and the collector region; the intermediate region has a transistor side region in contact with the transistor portion, The transistor-side region has the trench portion with a length greater than the first length. Semiconductor device.

5. A semiconductor substrate having an upper surface and a lower surface and having a first conductivity type drift region provided therein; a transistor section including a collector region of a second conductivity type in contact with the lower surface of the semiconductor substrate, and an emitter region of a first conductivity type provided in contact with the upper surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a diode portion having a cathode region of a first conductivity type in contact with the lower surface of the semiconductor substrate; Equipped with an avalanche breakdown voltage in the diode section is 0.7 times or more and less than 1 time the avalanche breakdown voltage in the transistor section; the diode section and the transistor section have a plurality of trench sections arranged at intervals along an arrangement direction on the upper surface of the semiconductor substrate, the transistor portion has a first lower end region of a second conductivity type provided in contact with a lower end of at least one of the trench portions; A lower end of at least one of the trench portions of the diode portion is not in contact with a region of the second conductivity type. Semiconductor device.

6. A semiconductor substrate having an upper surface and a lower surface and having a first conductivity type drift region provided therein; a transistor section including a collector region of a second conductivity type in contact with the lower surface of the semiconductor substrate, and an emitter region of a first conductivity type provided in contact with the upper surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a diode portion having a cathode region of a first conductivity type in contact with the lower surface of the semiconductor substrate; Equipped with an avalanche breakdown voltage in the diode section is 0.7 times or more and less than 1 time the avalanche breakdown voltage in the transistor section; the diode section and the transistor section have a plurality of trench sections arranged at intervals along an arrangement direction on the upper surface of the semiconductor substrate, the diode section is provided in contact with a lower end of at least one of the trench sections and has a second lower end region of a first conductivity type having a doping concentration higher than that of the drift region; A lower end of at least one of the trench portions of the transistor portion is not in contact with a region of the first conductivity type having a doping concentration higher than that of the drift region. Semiconductor device.

7. A semiconductor substrate having an upper surface and a lower surface and having a first conductivity type drift region provided therein; a transistor section including a collector region of a second conductivity type in contact with the lower surface of the semiconductor substrate, and an emitter region of a first conductivity type provided in contact with the upper surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a diode portion having a cathode region of a first conductivity type in contact with the lower surface of the semiconductor substrate; Equipped with an avalanche breakdown voltage in the diode section is 0.7 times or more and less than 1 time the avalanche breakdown voltage in the transistor section; the diode section and the transistor section have a plurality of trench sections arranged at intervals along an arrangement direction on the upper surface of the semiconductor substrate, an intermediate region disposed between the diode portion and the transistor portion, the intermediate region having a plurality of trench portions and including at least one of the cathode region and the collector region; The avalanche breakdown voltage of the intermediate region is higher than the avalanche breakdown voltage of the diode section and lower than the avalanche breakdown voltage of the transistor section. Semiconductor device.

8. A semiconductor substrate having an upper surface and a lower surface and having a first conductivity type drift region provided therein; a transistor section including a collector region of a second conductivity type in contact with the lower surface of the semiconductor substrate, and an emitter region of a first conductivity type provided in contact with the upper surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a diode portion having a cathode region of a first conductivity type in contact with the lower surface of the semiconductor substrate; Equipped with an avalanche breakdown voltage in the diode section is 0.7 times or more and less than 1 time the avalanche breakdown voltage in the transistor section; The cathode voltage at which the diode section reaches a negative resistance region is lower than the collector voltage at which the transistor section reaches a negative resistance region. Semiconductor device.

9. The cathode voltage at which the diode section reaches a negative resistance region is equal to or higher than the collector voltage at which the transistor section reaches a negative resistance region. The semiconductor device according to claim 1 .

10. an intermediate region disposed between the diode portion and the transistor portion, the intermediate region having a plurality of trench portions and including at least one of the cathode region and the collector region; The intermediate region has a transistor-side region, the transistor-side region contacting the transistor portion, and one or more of the trench portions are arranged at the first interval. The semiconductor device according to claim 1 .

11. an intermediate region disposed between the diode portion and the transistor portion, the intermediate region having a plurality of trench portions and including at least one of the cathode region and the collector region; The intermediate region has a transistor-side region, the transistor-side region contacting the transistor portion, and one or more of the trench portions are arranged at intervals smaller than the first interval. The semiconductor device according to claim 1 .

12. a boundary between the cathode region and the collector region in the intermediate region being located in the transistor side region; The semiconductor device according to claim 10.

13. The boundary position is disposed below the trench portion closest to the diode portion among the one or more trench portions in the transistor-side region. The semiconductor device according to claim 12.

14. the transistor-side region includes the first trench portion and the second trench portion, the distance between which in the arrangement direction is smallest in the intermediate region; The boundary position is located in a region from below the first trench portion to below the second trench portion. The semiconductor device according to claim 12.

15. The intervals between the plurality of trench portions in the arrangement direction in the intermediate region are larger as they are closer to the diode portion. The semiconductor device according to claim 10 .

16. The second interval is at least twice the first interval. The semiconductor device according to claim 1 or any one of claims 10 to 14.

17. a boundary between the cathode region and the collector region in the intermediate region being located in the transistor side region; The semiconductor device according to claim 2 .

18. The lengths of the plurality of trench portions in the intermediate region in the depth direction are greater as they approach the diode portion.

18. The semiconductor device according to claim 2, wherein the semiconductor device is a semiconductor substrate.

19. The bottom ends of all the trench portions of the diode portion are not in contact with the second conductivity type region. The semiconductor device according to claim 5 .

20. The transistor section a base region of a second conductivity type provided between the emitter region and the drift region; an accumulation region of a first conductivity type provided between the base region and the drift region and having a doping concentration higher than that of the drift region; and The doping concentration of the second lower end region is lower than the doping concentration of the accumulation region. The semiconductor device according to claim 6.

21. The diode section has a lifetime adjusting section that adjusts the lifetime of carriers on the upper surface side of the semiconductor substrate. The semiconductor device according to claim 1 .

22. The avalanche breakdown voltage of the diode section is 0.75 to 0.95 times the avalanche breakdown voltage of the transistor section. The semiconductor device according to claim 1 .

23. a semiconductor substrate having an upper surface and a lower surface and provided with a drift region of a first conductivity type; a transistor section including a collector region of a second conductivity type in contact with the lower surface of the semiconductor substrate, and an emitter region of a first conductivity type provided in contact with the upper surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a diode portion having a cathode region of a first conductivity type in contact with the lower surface of the semiconductor substrate; Equipped with the diode section and the transistor section each have a plurality of trench sections arranged at intervals along an arrangement direction on the upper surface of the semiconductor substrate, the transistor portion has a first lower end region of a second conductivity type provided in contact with a lower end of at least one of the trench portions; A lower end of at least one of the trench portions of the diode portion is not in contact with a region of the second conductivity type. Semiconductor device.

24. A semiconductor substrate having an upper surface and a lower surface and having a first conductivity type drift region provided therein; a transistor section including a collector region of a second conductivity type in contact with the lower surface of the semiconductor substrate, and an emitter region of a first conductivity type provided in contact with the upper surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a diode portion having a cathode region of a first conductivity type in contact with the lower surface of the semiconductor substrate; Equipped with The semiconductor device has an avalanche breakdown voltage in the diode section that is 0.75 to 0.95 times the avalanche breakdown voltage in the transistor section.

25. The avalanche breakdown voltage of the diode section is 0.8 to 0.9 times the avalanche breakdown voltage of the transistor section.

25. The semiconductor device according to claim 24.

26. A method for manufacturing a semiconductor device having a transistor portion and a diode portion on a semiconductor substrate, comprising: For a first semiconductor device having the same breakdown voltage of the transistor portion and the diode portion, a non-destructive maximum energy density is obtained in an unclamped dielectric switching test at which the semiconductor device is not destroyed; a ratio of avalanche withstand voltages of the diode section and the transistor section is set so that the non-destructive maximum energy density is greater than that of the first semiconductor device, based on the first semiconductor device; designing the transistor section and the diode section in the second semiconductor device so as to satisfy the set ratio of avalanche breakdown voltages; A manufacturing method for manufacturing the second semiconductor device based on the design.

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