Solid-state imaging device, manufacturing method thereof, and electronic device

Abstract

Provided is a solid-state imaging device that makes it possible to achieve further improvements in the quality and reliability of a solid-state imaging device.　This solid-state imaging device comprises: a first substrate; a second substrate that is layered on the first substrate by being directly bonded thereto on the side opposite from the light incident side of the first substrate, and that has a different size than that of the first substrate; a third substrate that is provided on the side opposite from the light incident side of the second substrate; and an insulating layer that is formed between the first substrate and the third substrate. The third substrate includes a well that is formed on the light incident side of the third substrate.

Description

[Technical Field]

[0001] The present technology relates to a solid-state imaging device, a method for manufacturing a solid-state imaging device, and an electronic device. [Background technology]

[0002] In general, solid-state imaging devices such as complementary metal oxide semiconductor (CMOS) image sensors and charge coupled devices (CCDs) are widely used in digital still cameras, digital video cameras, and the like.

[0003] In recent years, there has been active development of Chip on Wafer (CoW) or Chip on Chip (CoC), which directly bonds a chip to a wafer or chip, as a bonding technology that reduces the cost of image sensors for large-format cameras and enables the combined mounting of multiple types of logic and memory chips (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2019 / 087764 Summary of the Invention [Problem to be solved by the invention]

[0005] However, the technique proposed in Patent Document 1 may not be able to further improve the quality and reliability of solid-state imaging devices.

[0006] Therefore, the present technology has been developed in consideration of such circumstances, and its main purpose is to provide a solid-state imaging device that can achieve further improvements in the quality and reliability of the solid-state imaging device, a manufacturing method for the solid-state imaging device, and an electronic device equipped with the solid-state imaging device. [Means for solving the problem]

[0007] As a result of intensive research conducted by the inventors to achieve the above object, they have succeeded in further improving the quality and reliability of solid-state imaging devices, and have completed the present technology.

[0008] That is, in the present technology, as a first aspect, a first substrate; a second substrate that is laminated on the first substrate by direct bonding on the opposite side of the first substrate from the light incident side, and has a size different from that of the first substrate; a third substrate provided on the opposite side of the second substrate with respect to the light incident side; an insulating layer formed between the first substrate and the third substrate; The third substrate has a well formed on the light incident side of the third substrate.

[0009] In a solid-state imaging device according to a first aspect of the present technology, The third substrate may be in contact with the second substrate, The third substrate may be in contact with the insulating layer.

[0010] The well of the third substrate may be formed so as to separate different potential regions of the second substrate.

[0011] In a solid-state imaging device according to a first aspect of the present technology, The well of the third substrate may be formed up to an area corresponding to the edge surface of the second substrate facing the insulating layer, and the edge surface of the well may be approximately flush with the edge surface of the second substrate.

[0012] In a solid-state imaging device according to a first aspect of the present technology, The well of the third substrate may be formed up to an area corresponding to the outside of the edge surface of the second substrate facing the insulating layer, the edge surface of the well may not be flush with the edge surface of the second substrate, and the edge surface of the well may be located in an area corresponding to the insulating layer.

[0013] In a solid-state imaging device according to a first aspect of the present technology, The second substrate may have a well formed on the opposite side to the light incident side of the second substrate.

[0014] In a solid-state imaging device according to a first aspect of the present technology, The third substrate may be composed of a well formed on a light incident side of the third substrate and a substrate, At least one of at least a portion of the well and at least a portion of the substrate may be electrically connected to the second substrate.

[0015] In a solid-state imaging device according to a first aspect of the present technology, At least a partial area of ​​the surface of the third substrate that contacts the second substrate may have a resistance of 1 Ωcm or more.

[0016] In a solid-state imaging device according to a first aspect of the present technology, A surface of the second substrate in contact with the third substrate and a surface of the insulating layer in contact with the third substrate may be substantially flush with each other.

[0017] In a solid-state imaging device according to a first aspect of the present technology, The insulating layer may include at least one of an inorganic oxide film and an organic film.

[0018] In addition, as a second aspect, the present technology: a first substrate; a second substrate that is laminated on the first substrate by direct bonding on the opposite side of the first substrate from the light incident side, and has a size different from that of the first substrate; a third substrate provided on the opposite side of the second substrate with respect to the light incident side; an insulating layer formed between the first substrate and the third substrate; the third substrate is in contact with the second substrate; The third substrate is in contact with the insulating layer.

[0019] In a solid-state imaging device according to a second aspect of the present technology, The third substrate may have a well formed on the light incident side of the third substrate.

[0020] In a solid-state imaging device according to a second aspect of the present technology, The well of the third substrate may be formed so as to separate different potential regions of the second substrate.

[0021] In a solid-state imaging device according to a second aspect of the present technology, The well of the third substrate may be formed up to an area corresponding to the edge surface of the second substrate facing the insulating layer, and the edge surface of the well may be approximately flush with the edge surface of the second substrate.

[0022] In a solid-state imaging device according to a second aspect of the present technology, The well of the third substrate may be formed up to an area corresponding to the outside of the edge surface of the second substrate facing the insulating layer, the edge surface of the well may not be flush with the edge surface of the second substrate, and the edge surface of the well may be located in an area corresponding to the insulating layer.

[0023] In a solid-state imaging device according to a second aspect of the present technology, The second substrate may have a well formed on the opposite side to the light incident side of the second substrate.

[0024] In a solid-state imaging device according to a second aspect of the present technology, The third substrate may be composed of a well formed on a light incident side of the third substrate and a substrate, At least one of at least a portion of the well and at least a portion of the substrate may be electrically connected to the second substrate.

[0025] In a solid-state imaging device according to a second aspect of the present technology, At least a partial area of ​​the surface of the third substrate that contacts the second substrate may have a resistance of 1 Ωcm or more.

[0026] In a solid-state imaging device according to a second aspect of the present technology, A surface of the second substrate in contact with the third substrate and a surface of the insulating layer in contact with the third substrate may be substantially flush with each other.

[0027] In a solid-state imaging device according to a second aspect of the present technology, The insulating layer may include at least one of an inorganic oxide film and an organic film.

[0028] Furthermore, in this technology, as a third aspect, a first substrate; a second substrate that is laminated on the first substrate by direct bonding on the opposite side of the first substrate from the light incident side, and has a size different from that of the first substrate; a third substrate provided on the opposite side of the second substrate with respect to the light incident side; an insulating layer formed between the first substrate and the third substrate; at least one film formed between the first substrate and the third substrate and made of a material different from a material constituting the insulating layer; the insulating layer and the at least one film are formed in this order from the light incident side, the at least one film contacting the second substrate; the at least one film contacts the insulating layer; The at least one film is in contact with the third substrate.

[0029] In a solid-state imaging device according to a third aspect of the present technology, A surface of the second substrate in contact with the at least one film and a surface of the insulating layer in contact with the at least one film may be substantially flush with each other.

[0030] In a solid-state imaging device according to a third aspect of the present technology, a surface of the second substrate in contact with the at least one film and a surface of the insulating layer in contact with the at least one film may not be flush with each other; The surface of the insulating layer that contacts the at least one film may be located closer to the first substrate than the surface of the second substrate that contacts the at least one film.

[0031] In a solid-state imaging device according to a third aspect of the present technology, The insulating layer may include at least one of an inorganic oxide film and an organic film.

[0032] A solid-state imaging device according to a third aspect of the present technology, It may further include a metal diffusion prevention film, The metal diffusion preventing film may be formed so as to cover a surface of the insulating layer that is not in contact with the at least one film, The metal diffusion barrier film may be disposed between the second substrate and the insulating layer, and between the first substrate and the insulating layer.

[0033] In a solid-state imaging device according to a third aspect of the present technology, The at least one film may include at least one selected from the group consisting of a heat dissipation member, a member having a film stress greater than that of Si, and a member having a linear expansion coefficient greater than that of Si.

[0034] In a solid-state imaging device according to a third aspect of the present technology, The heat dissipation member may contain at least one selected from the group consisting of SiC, AlN, SiN, Cu, Al, and C.

[0035] In a solid-state imaging device according to a third aspect of the present technology, The member having a film stress greater than that of Si may contain at least one selected from the group consisting of SiO2, SiN, Cu, Al, and C.

[0036] Furthermore, in the present technology, as a fourth aspect, a first substrate; a second substrate that is laminated on the first substrate by direct bonding on the opposite side of the first substrate from the light incident side, and has a size different from that of the first substrate; a third substrate provided on the opposite side of the second substrate with respect to the light incident side; a cavity formed between the first substrate and the third substrate; the third substrate is in contact with the second substrate; The third substrate is in contact with the cavity.

[0037] In a solid-state imaging device according to a fourth aspect of the present technology, The solid-state imaging device according to

[20] is provided, wherein the third substrate has a well formed on a light incident side of the third substrate.

[0038] In a solid-state imaging device according to a fourth aspect of the present technology, The well of the third substrate may be formed so as to separate different potential regions of the second substrate.

[0039] In a solid-state imaging device according to a fourth aspect of the present technology, The well of the third substrate may be formed up to an area corresponding to the edge surface of the second substrate facing the cavity, and the edge surface of the well may be approximately flush with the edge surface of the second substrate.

[0040] In a solid-state imaging device according to a fourth aspect of the present technology, The well of the third substrate may be formed up to an area corresponding to the outside of the edge surface of the second substrate facing the cavity, the edge surface of the well may not be flush with the edge surface of the second substrate, and the edge surface of the well may be located in an area corresponding to the cavity.

[0041] In a solid-state imaging device according to a fourth aspect of the present technology, The second substrate may have a well formed on the opposite side to the light incident side of the second substrate.

[0042] In a solid-state imaging device according to a fourth aspect of the present technology, The third substrate may be composed of a well formed on a light incident side of the third substrate and a substrate, At least one of at least a portion of the well and at least a portion of the substrate may be electrically connected to the second substrate.

[0043] In a solid-state imaging device according to a fourth aspect of the present technology, At least a partial area of ​​the surface of the third substrate that contacts the second substrate may have a resistance of 1 Ωcm or more.

[0044] In a solid-state imaging device according to a fourth aspect of the present technology, A surface of the second substrate that contacts the third substrate and a surface of the cavity that contacts the third substrate may be substantially flush with each other.

[0045] Furthermore, as a fifth aspect, this technology: a first substrate; a second substrate that is laminated on the first substrate by direct bonding on the opposite side of the first substrate from the light incident side, and has a size different from that of the first substrate; a third substrate provided on the opposite side of the second substrate with respect to the light incident side; a cavity formed between the first substrate and the third substrate; at least one film formed between the first substrate and the third substrate; the cavity and the at least one film are formed in this order from the light incident side, the at least one film contacting the second substrate; the at least one membrane contacts the cavity; The at least one film is in contact with the third substrate.

[0046] In a solid-state imaging device according to a fifth aspect of the present technology, A surface of the second substrate in contact with the at least one film and a surface of the cavity in contact with the at least one film may be substantially flush with each other.

[0047] In a solid-state imaging device according to a fifth aspect of the present technology, a surface of the second substrate in contact with the at least one film and a surface of the cavity in contact with the at least one film may not be flush with each other; A surface of the cavity that contacts the at least one film may be located closer to the first substrate than a surface of the second substrate that contacts the at least one film.

[0048] A solid-state imaging device according to a fifth aspect of the present technology, It may further include a metal diffusion prevention film, The metal diffusion prevention film may be formed so as to cover a surface of the cavity that is not in contact with the at least one film, The metal diffusion barrier film may be disposed between the second substrate and the cavity, and between the first substrate and the cavity.

[0049] In a solid-state imaging device according to a fifth aspect of the present technology, The at least one film may include at least one selected from the group consisting of a heat dissipation member, a member having a film stress greater than that of Si, and a member having a linear expansion coefficient greater than that of Si.

[0050] In a solid-state imaging device according to a fifth aspect of the present technology, The heat dissipation member may contain at least one selected from the group consisting of SiC, AlN, SiN, Cu, Al, and C.

[0051] In a solid-state imaging device according to a fifth aspect of the present technology, The member having a film stress greater than that of Si may contain at least one selected from the group consisting of SiO2, SiN, Cu, Al, and C.

[0052] According to a sixth aspect of the present technology, there is provided an electronic device equipped with any one of the solid-state imaging devices according to the first to fifth aspects of the present technology.

[0053] The seventh aspect of this technology is: a first substrate; a second substrate that is laminated on the first substrate by direct bonding on the opposite side of the first substrate from the light incident side, and has a size different from that of the first substrate; a third substrate provided on the opposite side of the second substrate with respect to the light incident side; an insulating layer formed between the first substrate and the third substrate; the third substrate is in contact with the second substrate; the third substrate is in contact with the insulating layer, the first substrate formed by a semiconductor process; bonding the second substrate formed by the semiconductor process to the second substrate that has been determined to be a non-defective product by an electrical inspection; After the bonding, an insulating layer is formed on the first substrate and the second substrate from the second substrate side; After the film formation, the second substrate and the insulating layer are thinned until the second substrate is exposed.

[0054] In a method for manufacturing a solid-state imaging device according to a seventh aspect of the present technology, The surface of the second substrate obtained by the thinning process and the surface of the insulating layer obtained by the thinning process may be substantially flush with each other.

[0055] In a method for manufacturing a solid-state imaging device according to a seventh aspect of the present technology, The surface of the second substrate obtained by the thinning process and the surface of the insulating layer obtained by the thinning process may not be flush with each other, The surface of the insulating layer may be located closer to the first substrate than the surface of the second substrate.

[0056] According to the present technology, it is possible to further improve the quality and reliability of solid-state imaging devices. Note that the effects described herein are not necessarily limited to those described herein, and may be any of the effects described in the present disclosure. [Brief explanation of the drawings]

[0057] [Figure 1] 1 is a block diagram showing an example of the configuration of a solid-state imaging device to which the present technology is applied. [Figure 2] 1 is a block diagram showing an example of the configuration of a solid-state imaging device to which the present technology is applied. [Figure 3] 1 is a block diagram showing an example of the configuration of a solid-state imaging device to which the present technology is applied. [Figure 4] 1 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to a first embodiment to which the present technology is applied. [Figure 5] 1 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to a first embodiment to which the present technology is applied. [Figure 6] 1 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to a first embodiment to which the present technology is applied. [Figure 7] 1 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to a first embodiment to which the present technology is applied. [Figure 8] 1 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to a first embodiment to which the present technology is applied. [Figure 9] 1 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to a first embodiment to which the present technology is applied. [Figure 10] 1 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to a first embodiment to which the present technology is applied. [Figure 11] 1 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to a first embodiment to which the present technology is applied. [Figure 12] 1 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to a first embodiment to which the present technology is applied. [Figure 13] 1 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to a first embodiment to which the present technology is applied. [Figure 14]1 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to a first embodiment to which the present technology is applied. [Figure 15] 1 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to a first embodiment to which the present technology is applied. [Figure 16] 10A and 10B are diagrams for explaining that the solid-state imaging device according to the first embodiment to which the present technology is applied can prevent leakage current. [Figure 17] 10A and 10B are diagrams for explaining that the solid-state imaging device according to the first embodiment to which the present technology is applied can prevent leakage current. [Figure 18] 10A and 10B are diagrams for explaining that the solid-state imaging device according to the first embodiment to which the present technology is applied can prevent leakage current. [Figure 19] 10A and 10B are diagrams for explaining that the solid-state imaging device according to the first embodiment to which the present technology is applied can prevent leakage current. [Figure 20] 10A and 10B are diagrams for explaining that the solid-state imaging device according to the first embodiment to which the present technology is applied can prevent leakage current. [Figure 21] 10A and 10B are diagrams for explaining that the solid-state imaging device according to the first embodiment to which the present technology is applied can prevent leakage current. [Figure 22] 10A and 10B are diagrams for explaining that the solid-state imaging device according to the first embodiment to which the present technology is applied can prevent leakage current. [Figure 23] 10A and 10B are diagrams for explaining that the solid-state imaging device according to the first embodiment to which the present technology is applied can prevent leakage current. [Figure 24] 10 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to a second embodiment to which the present technology is applied. [Figure 25] FIG. 10 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to a third embodiment to which the present technology is applied. [Figure 26] FIG. 10 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to a fourth embodiment to which the present technology is applied. [Figure 27] 3A to 3C are diagrams for explaining an example of a manufacturing method for the solid-state imaging device according to the first embodiment to which the present technology is applied. [Figure 28] 3A to 3C are diagrams for explaining an example of a manufacturing method for the solid-state imaging device according to the first embodiment to which the present technology is applied. [Figure 29] 1 is a cross-sectional view showing a first example of the configuration of a solid-state imaging device. [Figure 30] 1 is a cross-sectional view showing a configuration example of a solid-state imaging device to which the present technology is applied. [Figure 31] FIG. 10 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to a fifth embodiment to which the present technology is applied. [Figure 32] FIG. 10 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to a sixth embodiment to which the present technology is applied. [Figure 33] FIG. 10 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to a sixth embodiment to which the present technology is applied. [Figure 34] FIG. 10 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to a sixth embodiment to which the present technology is applied. [Figure 35] FIG. 10 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to a sixth embodiment to which the present technology is applied. [Figure 36] FIG. 10 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to a sixth embodiment to which the present technology is applied. [Figure 37] FIG. 10 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to a sixth embodiment to which the present technology is applied. [Figure 38] FIG. 10 is a cross-sectional view showing an example of the configuration of a solid-state imaging device according to a sixth embodiment to which the present technology is applied. [Figure 39] 13A to 13C are diagrams for explaining a method for manufacturing a solid-state imaging device according to a seventh embodiment to which the present technology is applied. [Figure 40] 1A to 1C are diagrams illustrating an example of a method for manufacturing a solid-state imaging device. [Figure 41] FIG. 10 is a cross-sectional view showing a second example of the configuration of the solid-state imaging device. [Figure 42] 1A to 1C are diagrams illustrating examples of use of solid-state imaging devices according to first to sixth embodiments to which the present technology is applied. [Figure 43] FIG. 13 is a functional block diagram of an example of an electronic device according to an eighth embodiment to which the present technology is applied. [Figure 44]FIG. 1 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. [Figure 45] FIG. 2 is a block diagram showing an example of the functional configuration of a camera head and a CCU. [Figure 46] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Figure 47] FIG. 2 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit. DETAILED DESCRIPTION OF THE INVENTION

[0058] Preferred embodiments for implementing the present technology will be described below. The embodiments described below are examples of typical embodiments of the present technology, and the scope of the present technology will not be narrowed by them. Unless otherwise specified, in the drawings, "upper" means the upper direction or upper side in the drawing, "lower" means the lower direction or lower side in the drawing, "left" means the left direction or left side in the drawing, and "right" means the right direction or right side in the drawing. Furthermore, in the drawings, the same or equivalent elements or components are denoted by the same reference numerals, and redundant explanations will be omitted.

[0059] The explanation will be given in the following order. 1. Overview of this technology 2. First Embodiment (Example 1 of Solid-State Imaging Device) 3. Second Embodiment (Second Example of Solid-State Imaging Device) 4. Third Embodiment (Example 3 of Solid-State Imaging Device) 5. Fourth Embodiment (Fourth Example of Solid-State Imaging Device) 6. Fifth Embodiment (Fifth Example of Solid-State Imaging Device) 7. Sixth Embodiment (Sixth Example of Solid-State Imaging Device) 8. Seventh Embodiment (First Example of Manufacturing Method of Solid-State Imaging Device) 9. Eighth embodiment (example of electronic device) 10. Example of use of solid-state imaging device using this technology 11. Application example to endoscopic surgery system 12. Mobile application examples

[0060] <1. Overview of this technology> An overview of this technology will be explained.

[0061] First, a solid-state imaging device according to the first technical example will be described with reference to Fig. 29. Fig. 29 is a cross-sectional view showing the configuration of the solid-state imaging device according to the first technical example.

[0062] 29 includes a first substrate 1250-1, second substrates 1250-2a and 1250-2b that are stacked on the first substrate 1250-1 by direct bonding on the opposite side (lower side of FIG. 29) from the light incident side (upper side of FIG. 29) of the first substrate 1250-1 and have a size different from that of the first substrate 1250-1, a third substrate 1250-3 that is provided on the opposite side (lower side of FIG. 29) from the light incident side (upper side of FIG. 29) of the second substrates 1250-2a and 1250-2b, and an insulating layer 50 (sometimes referred to as an insulating film 50) formed between the first substrate 1250-1 and the third substrate 1250-3. In the solid-state imaging device 1250, the third substrate 1250-3 is in contact only with the insulating layer 50.

[0063] The first substrate 1250-1 is a sensor substrate on which photodiodes and multiple transistors that constitute pixels are formed. The second substrate 1250-2a is, for example, any one of an analog circuit substrate on which an analog circuit is formed, a logic circuit substrate on which a logic circuit is formed, and a memory circuit substrate on which a memory circuit is formed, and the second substrate 1250-2b is, for example, any one of an analog circuit substrate on which an analog circuit is formed, a logic circuit substrate on which a logic circuit is formed, and a memory circuit substrate on which a memory circuit is formed. The third substrate 1250-3 is a support substrate.

[0064] In the solid-state imaging device 1250, singulated second substrates 1250-2a and 1250-2b are bonded below the first substrate 1250-1 (lower side in FIG. 29). After the space between the second substrates 1250-2a and 1250-2b is filled with an insulating film 50 and planarized, they are bonded to a support substrate 1250-3, and then a structure (for example, a structure relating to the on-chip lens 13-1 and the color filter 13-2) is constructed on the light incident surface side (upper side in FIG. 29) of the first substrate 1250-1.

[0065] When heat is generated in the circuits of the second substrates 1250-2a and 1250-2b, the semiconductor substrate (silicon (Si) substrate) is covered with an insulating film 50, which has poor thermal conductivity and can cause variations in pixel characteristics due to localized uneven heat distribution.

[0066] Furthermore, if the insulating layer (insulating film) between the second substrates 1250-2a and 1250-2b and the support substrate 1250-3 is made extremely thin or eliminated in order to improve the heat dissipation between the second substrates 1250-2a and 1250-2b and the support substrate 1250-3, the second substrates 1250-2a and 1250-2b may become electrically connected via the support substrate 1250-3. This can also occur between different potentials within the same second substrate (i.e., within the second substrate 1250-2a or 1250-2b).

[0067] Next, a solid-state imaging device according to the second technical example and a method for manufacturing the solid-state imaging device according to the second technical example will be described with reference to Figures 40 and 41. Figure 41 is a cross-sectional view showing the configuration of the solid-state imaging device according to the second technical example, and Figure 40 is a diagram for explaining the method for manufacturing the solid-state imaging device according to the second technical example.

[0068] As shown in FIG. 40A, the semiconductor substrate 12K is bonded to the semiconductor substrates 9-1K and 9-2K via the wiring layers 11, 10-1, and 10-2. As shown in FIG. 40B, the semiconductor substrates 9-1K and 9-2K are thinned (to become the semiconductor substrates 9-1 and 9-2). As shown in FIG. 40C, the temperature is raised to form an insulating film (oxide film) 50 so as to embed it above the semiconductor substrates 9-1K and 9-2K and the semiconductor substrate 12K (below in FIG. 40C). As shown in FIG. 40D, the insulating film (oxide film) 50 is formed and cooled. As shown in FIG. 40E, the support substrate 1360-3 is bonded. As shown in FIG. 40F, the semiconductor substrate 12K is thinned (to become the semiconductor substrate 12), and is customized by forming on-chip lenses, color filters (not shown), etc., to manufacture the solid-state imaging device 1360.

[0069] As described above, after bonding substrates (or chips), the substrates (or chips) are thinned and embedded with an oxide film, and then a support substrate is bonded to the thinned substrate after a planarization process, thereby achieving the CoW process.

[0070] 41 includes a first substrate 1370-1, second substrates 1370-2a and 1370-2b that are stacked on the first substrate 1370-1 by direct bonding on the opposite side (lower side in FIG. 41) from the light incident side (upper side in FIG. 29) of the first substrate 1370-1 and have a size different from that of the first substrate 1370-1, a third substrate 1370-3 that is provided on the opposite side (lower side in FIG. 41) from the light incident side (upper side in FIG. 41) of the second substrates 1370-2a and 1370-2b, and an insulating layer 50 formed between the first substrate 1370-1 and the third substrate 1370-3. In the solid-state imaging device 1370, the third substrate 1370-3 is in contact only with the insulating layer 50.

[0071] The first substrate 1370-1 is a sensor substrate on which photodiodes and multiple transistors that constitute pixels are formed. The second substrate 1370-2a is, for example, one of an analog circuit substrate on which an analog circuit is formed, a logic circuit substrate on which a logic circuit is formed, and a memory circuit substrate on which a memory circuit is formed. The second substrate 1370-2b is, for example, one of an analog circuit substrate on which an analog circuit is formed, a logic circuit substrate on which a logic circuit is formed, and a memory circuit substrate on which a memory circuit is formed. The third substrate 1370-3 is a support substrate.

[0072] As shown in FIG. 41, the solid-state imaging device 1370 is completely covered with an oxide film (insulating film) 50, including the lower surfaces of the second substrates 1370-2a and 1370-2b (the lower surface of FIG. 41, facing the support 1370-3). Therefore, the stress and strain caused by the embedding cannot be alleviated (arrow P41 shown in FIG. 41), which may result in fluctuations in the transistor (Tr) characteristics within the second substrates 1370-2a and 1370-2b and misalignment of the on-chip lens (OCL) on the first substrate 1370-1 side during installation. Furthermore, there is concern that the thermal conductivity is low, leaving no escape route for the heat generated within the second substrates 1370-2a and 1370-2b (arrow Q41 shown in FIG. 41). Regarding the fluctuations in transistor (Tr) characteristics, it has been confirmed that the mobility of electrons and holes fluctuates specifically at the chip edge due to the influence of stress.

[0073] The present technology has been made in consideration of the above circumstances. A solid-state imaging device according to the present technology includes a first substrate, a second substrate that is stacked on the first substrate by direct bonding on the opposite side of the first substrate from the light incident side and has a size different from the size of the first substrate, a third substrate that is provided on the opposite side of the second substrate from the light incident side, and an insulating layer that is formed between the first substrate and the third substrate, and the third substrate has a well formed on the light incident side of the third substrate.

[0074] In addition, the solid-state imaging device according to the present technology may be a solid-state imaging device including a first substrate, a second substrate stacked on the first substrate by direct bonding on the side opposite to the light incident side of the first substrate and having a size different from that of the first substrate, a third substrate provided on the side opposite to the light incident side of the second substrate, and an insulating layer formed between the first substrate and the third substrate, wherein the third substrate is in contact with the second substrate and the third substrate is in contact with the insulating layer.

[0075] According to the solid-state imaging device of the present technology, it is possible to further improve the quality and reliability of the solid-state imaging device. More specifically, according to the solid-state imaging device of the present technology, it is possible to relieve stress on the substrate (particularly the second substrate) and improve thermal conductivity. Furthermore, according to the solid-state imaging device of the present technology, by adopting a structure in which the substrate (particularly the second substrate) and the semiconductor substrate (silicon (Si) substrate) of the support substrate are thin or in contact with each other, heat generated in the circuit of the substrate (particularly the second substrate) is released to the package (PKG) via the semiconductor substrate (silicon (Si) substrate) of the support substrate, thereby suppressing heat transfer to the first substrate (sensor substrate, etc.), and reducing variations in pixel characteristics and noise due to heat. In the solid-state imaging device according to the present technology, by forming an electrically isolated well structure in the support substrate or by increasing the resistance of the entire support substrate, it is possible to reduce variations in pixel characteristics and noise caused by heat, while electrically isolating areas of different potential between substrates (particularly the second substrate) or within a substrate (particularly the second substrate), for example on the support substrate surface side, thereby preventing leakage current through the support substrate.

[0076] The solid-state imaging device according to the present technology will be further described with reference to Fig. 1 to Fig. 3 and Fig. 30. Fig. 1 to Fig. 3 are block diagrams showing configuration examples of the solid-state imaging device according to the present technology. Fig. 30 is a cross-sectional view showing the configuration example of the solid-state imaging device according to the present technology.

[0077] The solid-state imaging device 1001 shown in Fig. 1A has a three-layer structure. Specifically, the solid-state imaging device 1001 includes, in order from the light incident side (the upper side of Fig. 1A), a sensor substrate 1001-1 as a first substrate as a first layer, an analog circuit substrate 1001-2a, a logic circuit substrate 1001-2b, and a memory circuit substrate 1001-2c as three second substrates having a different size from the first substrate (i.e., in Fig. 1A, smaller than the first substrate), as a second layer (i.e., a total of three second substrates are formed on the same layer), and a support substrate 1001-3 as a third substrate as a third layer.

[0078] The solid-state imaging device 1002 shown in Fig. 1B has a three-layer structure. Specifically, the solid-state imaging device 1002 is composed of, in order from the light incident side (upper side in Fig. 1B), a sensor substrate 1002-1, which is a first substrate, as a first layer; a circuit substrate 1002-2, which is a second substrate, having a size different from that of the first substrate (i.e., in Fig. 1B, it is smaller than the first substrate); and a support substrate 1002-3, which is a third substrate, as a third layer. An analog circuit 1002-2a, a logic circuit 1002-2b, and a memory circuit 1002-2c (i.e., a total of three circuits) are formed on the second substrate 1002-2.

[0079] The solid-state imaging device 1003 shown in Fig. 2A has a four-layer structure. Specifically, the solid-state imaging device 1003 includes, in order from the light incident side (upper side in Fig. 2A), a sensor substrate 1003-4, which is a fourth substrate, as a first layer, a circuit substrate 1003-1, which is a first substrate and has approximately the same size as the fourth substrate (i.e., in Fig. 2A, its size is approximately equal to that of the fourth substrate), as a second layer, two second substrates, a logic circuit substrate 1003-2b and a memory circuit substrate 1003-2c, which are different in size from the first substrate (i.e., in Fig. 2A, their size is smaller than that of the first substrate), as a third layer (i.e., two second substrates in total are formed on the same layer), and a support substrate 1003-3, which is a third substrate, as a fourth layer. An analog circuit 1003-1a and a logic circuit 1003-1b (that is, two circuits in total) are formed on the first substrate (circuit substrate) 1003-1.

[0080] The solid-state imaging device 1004 shown in Fig. 2B has a four-layer structure. Specifically, the solid-state imaging device 1004 includes, in order from the light incident side (the upper side of Fig. 2B), a sensor substrate 1004-4, which is a fourth substrate, as a first layer, a circuit substrate 1004-1, which is a first substrate having a size different from that of the fourth substrate (i.e., in Fig. 2B, its size is smaller than that of the fourth substrate), as a second layer, a logic circuit substrate 1004-2b and a memory circuit substrate 1004-2c, which are two second substrates having a size different from that of the first substrate (i.e., in Fig. 2B, its size is smaller than that of the first substrate), as a third layer (i.e., two second substrates in total are formed on the same layer), and a support substrate 1004-3, which is a third substrate, as a fourth layer. An analog circuit 1004-1a and a logic circuit 1004-1b (that is, two circuits in total) are formed on the first substrate (circuit substrate) 1004-1.

[0081] The solid-state imaging device 1005 shown in Fig. 3 has a four-layer structure. Specifically, the solid-state imaging device 1005 includes, in order from the light incident side (the upper side of Fig. 3), a sensor substrate 1005-1 as a first substrate as a first layer, an analog circuit substrate 1005-2a and a logic circuit substrate 1005-2b-1 as two second substrates having a size different from that of the first substrate (i.e., in Fig. 3, they are smaller than the first substrate) as a second layer (i.e., two second substrates in total are formed on the same layer as the second layer), a logic circuit substrate 1005-2b-2 and a memory circuit substrate 1005-2c as two second substrates having a size different from that of the first substrate (i.e., in Fig. 3, they are smaller than the first substrate) as a third layer (i.e., two second substrates in total are formed on the same layer as the third layer), and a support substrate 1005-3 as a third substrate as a fourth layer. In the solid-state imaging device 1005, four second substrates are configured in the second and third layers, forming a stacked structure.

[0082] In the above description, examples of the solid-state imaging device according to the present technology having a three-layer structure or a four-layer structure have been described, but the solid-state imaging device according to the present technology may have a five-layer or more structure.

[0083] 30 includes a first substrate 126-1, a second substrate 126-2 that is stacked on the first substrate 126-1 by direct bonding on the opposite side (lower side in FIG. 30) of the first substrate 126-1 from the light incident side (upper side in FIG. 30) of the first substrate 126-1 and has a size different from that of the first substrate 126-1, a third substrate 126-3 that is provided on the opposite side (lower side in FIG. 30) of the second substrate 126-2 from the light incident side (upper side in FIG. 30) of the second substrate 126-2, and two insulating layers 50 formed between the first substrate 126-1 and the third substrate 126-3 (it can also be said that insulating layers 50 are formed on each of the left and right side sides of the second substrate 126-2). In the solid-state imaging device 126, the third substrate 126-3 is in contact with the second substrate 126-2 and also in contact with the two insulating layers 50.

[0084] The first substrate 126-1 is a sensor substrate on which photodiodes, multiple transistors, and the like that constitute pixels are formed. Specifically, the first substrate 126-1 (sensor substrate) includes, in order from the light incident side (upper side in FIG. 30), an on-chip lens 13-1, a color filter 13-2, a semiconductor substrate 12, and a wiring layer 11. A photodiode (PD) (not shown) is formed on the semiconductor substrate 12. Furthermore, transistors and the like (not shown) that constitute pixel circuits are formed on the semiconductor substrate 12 (at the interface between the semiconductor substrate 12 and the wiring layer 11).

[0085] The second substrate 126-2 is, for example, any one of an analog circuit substrate on which an analog circuit is formed, a logic circuit substrate on which a logic circuit is formed, and a memory circuit substrate on which a memory circuit is formed. Specifically, the second substrate 126-2 includes, in order from the light incident side, a wiring layer 10 and a semiconductor substrate 9. One of an analog circuit, a logic circuit, and a memory circuit is formed on the semiconductor substrate 9 (the interface between the semiconductor substrate 9 and the wiring layer 10). The third substrate 127-3 is a support substrate.

[0086] An example of direct bonding between the first substrate 126-1 and the second substrate 126-2 is bonding between an electrode made of Cu (copper) formed on the wiring layer 11 of the first substrate 126-1 and an electrode made of Cu (copper) formed on the wiring layer 10 of the second substrate 126-2 (CuCu bonding, inter-substrate electrode bonding structure).

[0087] Hereinafter, preferred embodiments for carrying out the present technology will be described in detail with reference to the drawings. The embodiments described below are examples of typical embodiments of the present technology, and the scope of the present technology should not be interpreted as being narrow.

[0088] 2. First Embodiment (First Example of Solid-State Imaging Device) A solid-state imaging device according to a first embodiment (first example of a solid-state imaging device) of the present technology will be described with reference to FIGS. 4 to 23 and 27 to 28. FIG.

[0089] 4 to 15 are cross-sectional views showing configuration examples of the solid-state imaging device according to the first embodiment of the present technology, and FIGS. 16 to 23 are diagrams for explaining that the solid-state imaging device according to the first embodiment of the present technology can prevent leakage current. FIGS. 27 and 28 are diagrams for explaining an example of a manufacturing method for the solid-state imaging device according to the first embodiment of the present technology.

[0090] First, a description will be given with reference to FIGS.

[0091] The solid-state imaging device 101 shown in Figure 4 comprises a first substrate 101-1, second substrates 101-2a and 101-2b that are stacked on the first substrate 101-1 by direct bonding (for example, CuCu bonds 1200a and 1210a, and CuCu bonds 1200a and 1220a, as shown in Figure 4) on the opposite side (lower side of Figure 4) of the light incident side of the first substrate 101-1, and have a size different from that of the first substrate 101-1, a third substrate 101-3 that is provided on the opposite side (lower side of Figure 4) of the light incident side (upper side of Figure 4) of the second substrates 101-2a and 101-2b, and an insulating layer 50 that is formed between the first substrate 101-1 and the third substrate 101-3. In the solid-state imaging device 101, the third substrate 101-3 is in contact with the second substrates 101-2a and 101-2b, and also in contact with the insulating layer 50.

[0092] The first substrate 101-1 is a sensor substrate on which photodiodes and multiple transistors that constitute pixels are formed. The second substrate 101-2a is, for example, any one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The second substrate 101-2b is, for example, any one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The third substrate 101-3 is a support substrate.

[0093] An N-type well 210Na is formed in the semiconductor substrate 9-1 included in the second substrate 101-2a, and an N-type well 210Nb is formed in the semiconductor substrate 9-2 included in the second substrate 101-2b.

[0094] The third substrate 101-3 has an N-type substrate 21NS and P-type wells 21Pa and 21Pb (floating) formed therein, thereby electrically isolating areas of different potential between the second substrate 101-2a and the second substrate 101-2b or within the second substrate 101-2a or the second substrate 101-2b, thereby preventing leakage current through the support substrate 101-3.

[0095] The P-type well 21Pa is formed up to a region corresponding to the outside of the end face of the second substrate 101-2a facing the insulating layer 50, and the end face of the P-type well 21Pa and the end face of the second substrate 101-2a are not flush with each other in the vertical direction, and the right end face of the P-type well 21a is located in a region corresponding to the insulating layer 50.

[0096] On the other hand, the P-type well 21Pb is formed up to a region corresponding to the outside of the end face of the second substrate 101-2b facing the insulating layer 50, and the end face of the P-type well 21Pb and the end face of the second substrate 101-2b are not flush with each other in the vertical direction, and the left end face of the P-type well 21b is located in a region corresponding to the insulating layer 50.

[0097] 5 includes a first substrate 102-1, second substrates 102-2a and 102-2b that are stacked on the first substrate 102-1 by direct bonding on the opposite side (lower side in FIG. 5) from the light incident side (upper side in FIG. 5) of the first substrate 102-1 and have a size different from that of the first substrate 102-1, a third substrate 102-3 that is provided on the opposite side (lower side in FIG. 5) from the light incident side (upper side in FIG. 5) of the second substrates 102-2a and 102-2b, and an insulating layer 50 formed between the first substrate 102-1 and the third substrate 102-3. In the solid-state imaging device 102, the third substrate 102-3 is in contact with the second substrates 102-2a and 102-2b and also in contact with the insulating layer 50.

[0098] The first substrate 102-1 is a sensor substrate on which photodiodes and multiple transistors that constitute pixels are formed. The second substrate 102-2a is, for example, any one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The second substrate 102-2b is, for example, any one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The third substrate 102-3 is a support substrate.

[0099] An N-type well 220Na is formed in the semiconductor substrate 9-1 included in the second substrate 102-2a, and an N-type well 220Nb is formed in the semiconductor substrate 9-2 included in the second substrate 102-2b.

[0100] The third substrate 102-3 has an N-type substrate 22NS and P-type wells 22Pa and 22Pb (floating) formed therein, thereby electrically isolating areas of different potential between the second substrate 102-2a and the second substrate 101-2b or within the second substrate 102-2a or the second substrate 102-2b, thereby preventing leakage current through the support substrate 102-3.

[0101] The P-type well 22Pa is formed up to a region corresponding to the end face of the second substrate 102-2a facing the insulating layer 50, and the end face of the P-type well 22Pa and the end face of the second substrate 102-2a are flush in the vertical direction.

[0102] On the other hand, the P-type well 22Pb is formed up to a region corresponding to the end surface of the second substrate 102-2b facing the insulating layer 50, and the end surface of the P-type well 22Pb and the end surface of the second substrate 102-2b are flush in the vertical direction.

[0103] 6 includes a first substrate 103-1, second substrates 103-2a and 103-2b that are stacked on the first substrate 103-1 by direct bonding on the opposite side (lower side in FIG. 6) from the light incident side (upper side in FIG. 6) of the first substrate 103-1 and have a size different from that of the first substrate 103-1, a third substrate 103-3 that is provided on the opposite side (lower side in FIG. 6) from the light incident side (upper side in FIG. 6) of the second substrates 103-2a and 103-2b, and an insulating layer 50 formed between the first substrate 103-1 and the third substrate 103-3. In the solid-state imaging device 103, the third substrate 103-3 is in contact with the second substrates 103-2a and 103-2b and also in contact with the insulating layer 50.

[0104] The first substrate 103-1 is a sensor substrate on which photodiodes and multiple transistors that constitute pixels are formed. The second substrate 103-2a is, for example, any one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The second substrate 103-2b is, for example, any one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The third substrate 103-3 is a support substrate.

[0105] In the semiconductor substrate 9-1 included in the second substrate 103-2a, an N-type well 230Na, a P-type well 230Pa, and an N-type well 230Nb are formed in order from the left side of Fig. 6. In the semiconductor substrate 9-2 included in the second substrate 103-2b, an N-type well 230Nc and a P-type well 230Pb are formed in order from the left side of Fig. 6.

[0106] The third substrate 103-3 has an N-type substrate 23NS and P-type wells 23Pa and 23Pb formed therein, thereby electrically isolating different potential locations between the second substrates 103-2a and 103-2b or within the second substrates 103-2a and 103-2b, and preventing leakage current through the support substrate 103-3. Furthermore, the N-type substrate 23NS and the N-type well 230Na are electrically connected, the P-type well 23Pa and the P-type well 230Pa are electrically connected, and the P-type well 23Pb and the P-type well 230Pb are electrically connected, and the third substrate (support substrate) 103-3 is at a fixed potential, thereby more reliably preventing leakage current.

[0107] The P-type well 23Pa is formed up to a region corresponding to the outside of the end face of the second substrate 103-2a facing the insulating layer 50, and the end face of the P-type well 23Pa and the end face of the second substrate 103-2a are not flush with each other in the vertical direction, and the right end face of the P-type well 23a is located in a region corresponding to the insulating layer 50.

[0108] On the other hand, the P-type well 23Pb is formed up to a region corresponding to the outside of the end face of the second substrate 103-2b facing the insulating layer 50, and the end face of the P-type well 23Pb and the end face of the second substrate 103-2b are not flush with each other in the vertical direction, and the left end face of the P-type well 23b is located in a region corresponding to the insulating layer 50.

[0109] 7 includes a first substrate 104-1, second substrates 104-2a and 104-2b that are stacked on the first substrate 104-1 by direct bonding on the opposite side (lower side in FIG. 7) from the light incident side (upper side in FIG. 7) of the first substrate 104-1 and have a size different from that of the first substrate 104-1, a third substrate 104-3 that is provided on the opposite side (lower side in FIG. 7) from the light incident side (upper side in FIG. 7) of the second substrates 104-2a and 104-2b, and an insulating layer 50 formed between the first substrate 104-1 and the third substrate 104-3. In the solid-state imaging device 104, the third substrate 104-3 is in contact with the second substrates 104-2a and 104-2b and also in contact with the insulating layer 50.

[0110] The first substrate 104-1 is a sensor substrate on which photodiodes and multiple transistors that constitute pixels are formed. The second substrate 104-2a is, for example, any one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The second substrate 104-2b is, for example, any one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The third substrate 104-3 is a support substrate.

[0111] In the semiconductor substrate 9-1 included in the second substrate 104-2a, an N-type well 240Na, a P-type well 240Pa, and an N-type well 240Nb are formed, in that order from the left in Fig. 6. In the semiconductor substrate 9-2 included in the second substrate 104-2b, an N-type well 240Nc and a P-type well 240Pb are formed, in that order from the left in Fig. 6.

[0112] The third substrate 104-3 has an N-type substrate 24NS and P-type wells 24Pa and 24Pb formed therein, thereby electrically isolating different potential locations between the second substrates 104-2a and 104-2b or within the second substrates 104-2a and 104-2b, and preventing leakage current through the support substrate 104-3. Furthermore, the N-type substrate 24NS and the N-type well 240Na are electrically connected, the P-type well 24Pa and the P-type well 240Pa are electrically connected, and the P-type well 24Pb and the P-type well 240Pb are electrically connected, and the third substrate (support substrate) 104-3 is at a fixed potential, thereby more reliably preventing leakage current.

[0113] The P-type well 24Pa is formed up to a region corresponding to the end face of the second substrate 104-2a facing the insulating layer 50, and the end face of the P-type well 24Pa and the end face of the second substrate 104-2a are flush in the vertical direction.

[0114] On the other hand, the P-type well 24Pb is formed up to a region corresponding to the end surface of the second substrate 104-2b facing the insulating layer 50, and the end surface of the P-type well 24Pb and the end surface of the second substrate 104-2b are flush in the vertical direction.

[0115] 8 includes a first substrate 105-1, second substrates 105-2a and 105-2b that are stacked on the first substrate 105-1 by direct bonding on the opposite side (lower side in FIG. 8) from the light incident side (upper side in FIG. 8) of the first substrate 105-1 and have a size different from that of the first substrate 105-1, a third substrate 105-3 that is provided on the opposite side (lower side in FIG. 8) from the light incident side (upper side in FIG. 8) of the second substrates 105-2a and 105-2b, and an insulating layer 50 formed between the first substrate 105-1 and the third substrate 105-3. In the solid-state imaging device 105, the third substrate 105-3 is in contact with the second substrates 105-2a and 105-2b and also in contact with the insulating layer 50.

[0116] The first substrate 105-1 is a sensor substrate on which photodiodes and multiple transistors that constitute pixels are formed. The second substrate 105-2a is, for example, any one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The second substrate 105-2b is, for example, any one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The third substrate 105-3 is a support substrate.

[0117] An N-type well 250Na is formed in the semiconductor substrate 9-1 of the second substrate 105-2a, and an N-type well 250Nb is formed in the semiconductor substrate 9-2 of the second substrate 105-2b.

[0118] The third substrate 105-3 has N-type wells 25Na and 25Nb (floating) formed therein and has a P-type substrate 25PS, thereby electrically isolating areas of different potential between the second substrate 105-2a and the second substrate 105-2b or within the second substrate 105-2a or the second substrate 105-2b, thereby preventing leakage current through the support substrate 105-3.

[0119] The N-type well 25Na is formed up to a region corresponding to the end surface of the second substrate 105-2a facing the insulating layer 50, and the right end surface of the N-type well 25Na and the end surface of the second substrate 105-2a are flush in the vertical direction.

[0120] On the other hand, the N-type well 25Nb is formed up to a region corresponding to the end surface of the second substrate 105-2b facing the insulating layer 50, and the left end surface of the N-type well 25Nb and the end surface of the second substrate 105-2b are flush in the vertical direction.

[0121] 9 includes a first substrate 106-1, second substrates 106-2a and 106-2b that are stacked on the first substrate 106-1 by direct bonding on the opposite side (lower side in FIG. 9) from the light incident side (upper side in FIG. 9) of the first substrate 106-1 and have a size different from that of the first substrate 106-1, a third substrate 106-3 that is provided on the opposite side (lower side in FIG. 9) from the light incident side (upper side in FIG. 9) of the second substrates 106-2a and 106-2b, and an insulating layer 50 formed between the first substrate 106-1 and the third substrate 106-3. In the solid-state imaging device 106, the third substrate 106-3 is in contact with the second substrates 106-2a and 106-2b and also in contact with the insulating layer 50.

[0122] The first substrate 106-1 is a sensor substrate on which photodiodes and multiple transistors that constitute pixels are formed. The second substrate 106-2a is, for example, one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The second substrate 106-2b is, for example, one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The third substrate 106-3 is a support substrate.

[0123] An N-type well 260Na is formed in the semiconductor substrate 9-1 of the second substrate 106-2a, and an N-type well 260Nb is formed in the semiconductor substrate 9-2 of the second substrate 106-2b.

[0124] The third substrate 106-3 has N-type wells 26Na and 26Nb (floating) formed therein and has a P-type substrate 26PS, thereby electrically isolating areas of different potential between the second substrate 106-2a and the second substrate 106-2b or within the second substrate 106-5a or the second substrate 106-2b, and preventing leakage current through the support substrate 106-3.

[0125] The N-type well 26Na is formed up to a region corresponding to the outside of the end face of the second substrate 106-2a facing the insulating layer 50, and the end face of the N-type well 26Na and the end face of the second substrate 106-2a are not flush with each other in the vertical direction, and the right end face of the N-type well 26a is located in a region corresponding to the insulating layer 50.

[0126] On the other hand, the N-type well 26Nb is formed up to a region corresponding to the outside of the end face of the second substrate 106-2b facing the insulating layer 50, and the end face of the N-type well 26Nb and the end face of the second substrate 106-2b are not flush with each other in the vertical direction, and the left end face of the N-type well 26b is located in a region corresponding to the insulating layer 50.

[0127] 10 includes a first substrate 107-1, second substrates 107-2a and 107-2b that are stacked on the first substrate 107-1 by direct bonding on the opposite side (lower side in FIG. 10) from the light incident side (upper side in FIG. 10) of the first substrate 107-1 and have a size different from that of the first substrate 107-1, a third substrate 107-3 that is provided on the opposite side (lower side in FIG. 10) from the light incident side (upper side in FIG. 10) of the second substrates 107-2a and 107-2b, and an insulating layer 50 formed between the first substrate 107-1 and the third substrate 107-3. In the solid-state imaging device 107, the third substrate 107-3 is in contact with the second substrates 107-2a and 107-2b and also in contact with the insulating layer 50.

[0128] The first substrate 107-1 is a sensor substrate on which photodiodes and multiple transistors that constitute pixels are formed. The second substrate 107-2a is, for example, any one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The second substrate 107-2b is, for example, any one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The third substrate 107-3 is a support substrate.

[0129] In the semiconductor substrate 9-1 included in the second substrate 107-2a, a P-type well 270P and an N-type well 270Na are formed in this order from the left in Fig. 10. In the semiconductor substrate 9-2 included in the second substrate 107-2b, an N-type well 270Nb is formed.

[0130] The third substrate 107-3 has an N-type well 27Na formed therein and a P-type substrate 27PS, which electrically isolates different potential locations between the second substrates 107-2a and 107-2b or within the second substrates 107-2a and 107-2b, thereby preventing leakage current through the support substrate 107-3. Furthermore, the N-type substrate 27PS and the P-type well 270P are electrically connected, and the potential of the third substrate (support substrate) 107-3 is fixed, thereby more reliably preventing leakage current.

[0131] The N-type well 27Na is formed up to a region corresponding to the end surface of the second substrate 107-2a facing the insulating layer 50, and the right end surface of the N-type well 27Na and the end surface of the second substrate 107-2a are flush in the vertical direction.

[0132] On the other hand, the N-type well 27Nb is formed up to a region corresponding to the end surface of the second substrate 107-2b facing the insulating layer 50, and the left end surface of the N-type well 27Nb and the end surface of the second substrate 107-2b are flush in the vertical direction.

[0133] 11 includes a first substrate 108-1, second substrates 108-2a and 108-2b that are stacked on the first substrate 108-1 by direct bonding on the opposite side (lower side in FIG. 11) from the light incident side (upper side in FIG. 11) of the first substrate 108-1 and have a size different from that of the first substrate 108-1, a third substrate 108-3 that is provided on the opposite side (lower side in FIG. 11) from the light incident side (upper side in FIG. 11) of the second substrates 108-2a and 108-2b, and an insulating layer 50 formed between the first substrate 108-1 and the third substrate 108-3. In the solid-state imaging device 108, the third substrate 108-3 is in contact with the second substrates 108-2a and 108-2b and also in contact with the insulating layer 50.

[0134] The first substrate 108-1 is a sensor substrate on which photodiodes and multiple transistors that constitute pixels are formed. The second substrate 108-2a is, for example, any one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The second substrate 108-2b is, for example, any one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The third substrate 108-3 is a support substrate.

[0135] 11, a P-type well 280P and an N-type well 280Na are formed in the semiconductor substrate 9-1 included in the second substrate 108-2a, and an N-type well 280Nb is formed in the semiconductor substrate 9-2 included in the second substrate 108-2b.

[0136] The third substrate 108-3 has the N-type well 28Na formed therein and the P-type substrate 28PS, which electrically isolates different potential locations between the second substrates 108-2a and 108-2b or within the second substrates 108-2a and 108-2b, thereby preventing leakage current through the support substrate 108-3. Furthermore, the N-type substrate 28PS and the P-type well 280P are electrically connected, and the potential of the third substrate (support substrate) 108-3 is fixed, thereby more reliably preventing leakage current.

[0137] The N-type well 28Na is formed up to a region corresponding to the outside of the end face of the second substrate 108-2a facing the insulating layer 50, and the end face of the N-type well 28Na and the end face of the second substrate 108-2a are not flush with each other in the vertical direction, and the right end face of the N-type well 28a is located in a region corresponding to the insulating layer 50.

[0138] On the other hand, the N-type well 28Nb is formed up to a region corresponding to the outside of the end face of the second substrate 108-2b facing the insulating layer 50, and the end face of the N-type well 28Nb and the end face of the second substrate 108-2b are not flush with each other in the vertical direction, and the left end face of the N-type well 28b is located in a region corresponding to the insulating layer 50.

[0139] 12 includes a first substrate 109-1, second substrates 109-2a and 109-2b that are stacked on the first substrate 109-1 by direct bonding on the opposite side (lower side in FIG. 12) from the light incident side (upper side in FIG. 12) of the first substrate 109-1 and have a size different from that of the first substrate 109-1, a third substrate 109-3 that is provided on the opposite side (lower side in FIG. 12) from the light incident side (upper side in FIG. 12) of the second substrates 109-2a and 109-2b, and an insulating layer 50 formed between the first substrate 109-1 and the third substrate 109-3. In the solid-state imaging device 109, the third substrate 109-3 is in contact with the second substrates 109-2a and 109-2b and also in contact with the insulating layer 50.

[0140] The first substrate 109-1 is a sensor substrate on which photodiodes and multiple transistors that constitute pixels are formed. The second substrate 109-2a is, for example, any one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The second substrate 109-2b is, for example, any one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The third substrate 109-3 is a support substrate.

[0141] A P-type well 290Pa is formed in the semiconductor substrate 9-1 of the second substrate 109-2a, and a P-type well 290Pb is formed in the semiconductor substrate 9-2 of the second substrate 109-2b.

[0142] The third substrate 109-3 is N-type (reference symbol 29NS), and at least a portion of the surface in contact with the second substrates 109-2a and 109-2b has a resistance of 1 Ωcm or more (high resistance), thereby electrically isolating areas of different potential between the second substrates 109-2a and 109-2b or within the second substrates 109-2a or 109-2b, and preventing leakage current through the support substrate 109-3.

[0143] 13 includes a first substrate 110-1, second substrates 110-2a and 110-2b that are stacked on the first substrate 110-1 by direct bonding on the opposite side (lower side in FIG. 13) from the light incident side (upper side in FIG. 13) of the first substrate 110-1 and have a size different from that of the first substrate 110-1, a third substrate 110-3 that is provided on the opposite side (lower side in FIG. 13) from the light incident side (upper side in FIG. 13) of the second substrates 110-2a and 110-2b, and an insulating layer 50 formed between the first substrate 110-1 and the third substrate 110-3. In the solid-state imaging device 110, the third substrate 110-3 is in contact with the second substrates 110-2a and 110-2b and also in contact with the insulating layer 50.

[0144] The first substrate 110-1 is a sensor substrate on which photodiodes and multiple transistors that constitute pixels are formed. The second substrate 110-2a is, for example, any one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The second substrate 110-2b is, for example, any one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The third substrate 110-3 is a support substrate.

[0145] In the semiconductor substrate 9-1 included in the second substrate 110-2a, a P-type well 300Pa, an N-type well 300N, and a P-type well 300Pb are formed, in this order from the left in Fig. 13. In the semiconductor substrate 9-2 included in the second substrate 110-2b, a P-type well 300Pc is formed.

[0146] The third substrate 110-3 is N-type (reference symbol 30NS), and at least a portion of the surface in contact with the second substrates 110-2a and 110-2b has a resistance of 1 Ωcm or more (high resistance). This electrically isolates different potential locations between the second substrates 110-2a and 110-2b or within the second substrates 110-2a and 110-2b, thereby preventing leakage current through the support substrate 110-3. Furthermore, the N-type third substrate 110-3 and the N-type well 300N are electrically connected, and the third substrate (support substrate) 110-3 is fixed in potential, thereby more reliably preventing leakage current.

[0147] 14 includes a first substrate 111-1, second substrates 111-2a and 111-2b that are stacked on the first substrate 111-1 by direct bonding on the opposite side (lower side in FIG. 14) from the light incident side (upper side in FIG. 14) of the first substrate 111-1 and have a size different from that of the first substrate 111-1, a third substrate 111-3 that is provided on the opposite side (lower side in FIG. 14) from the light incident side (upper side in FIG. 14) of the second substrates 111-2a and 111-2b, and an insulating layer 50 that is formed between the first substrate 111-1 and the third substrate 111-3. In the solid-state imaging device 111, the third substrate 111-3 is in contact with the second substrates 111-2a and 111-2b and also in contact with the insulating layer 50.

[0148] The first substrate 111-1 is a sensor substrate on which photodiodes and multiple transistors that constitute pixels are formed. The second substrate 111-2a is, for example, any one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The second substrate 111-2b is, for example, any one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The third substrate 111-3 is a support substrate.

[0149] An N-type well 310Na is formed in the semiconductor substrate 9-1 included in the second substrate 111-2a, and an N-type well 310Nc is formed in the semiconductor substrate 9-2 included in the second substrate 111-2b.

[0150] The third substrate 111-3 is P-type (reference symbol 31PS), and at least a portion of the surface in contact with the second substrates 111-2a and 111-2b has a resistance of 1 Ωcm or more (high resistance), thereby electrically isolating areas of different potential between the second substrates 111-2a and 111-2b or within the second substrate 111-2a or 111-2b, and preventing leakage current through the support substrate 111-3.

[0151] 15 includes a first substrate 112-1, second substrates 112-2a and 112-2b that are stacked on the first substrate 112-1 by direct bonding on the opposite side (lower side in FIG. 15) from the light incident side (upper side in FIG. 15) of the first substrate 112-1 and have a size different from that of the first substrate 112-1, a third substrate 112-3 that is provided on the opposite side (lower side in FIG. 15) from the light incident side (upper side in FIG. 15) of the second substrates 112-2a and 112-2b, and an insulating layer 50 that is formed between the first substrate 112-1 and the third substrate 112-3. In the solid-state imaging device 112, the third substrate 112-3 is in contact with the second substrates 112-2a and 112-2b and also in contact with the insulating layer 50.

[0152] The first substrate 112-1 is a sensor substrate on which photodiodes and multiple transistors that constitute pixels are formed. The second substrate 112-2a is, for example, any one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The second substrate 112-2b is, for example, any one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The third substrate 112-3 is a support substrate.

[0153] In the semiconductor substrate 9-1 included in the second substrate 112-2a, an N-type well 320Na, a P-type well 320P, and an N-type well 320Nb are formed, from the left side of Fig. 15. In the semiconductor substrate 9-2 included in the second substrate 112-2b, an N-type well 310Nc is formed.

[0154] The third substrate 112-3 is P-type (reference symbol 32PS), and at least a portion of the surface in contact with the second substrates 112-2a and 112-2b has a resistance of 1 Ωcm or more (high resistance). This electrically isolates different potential locations between the second substrates 112-2a and 112-2b or within the second substrates 112-2a and 112-2b, thereby preventing leakage current through the support substrate 112-3. Furthermore, the P-type third substrate 112-3 and the P-type well 320P are electrically connected, and the third substrate (support substrate) 112-3 is fixed in potential, thereby more reliably preventing leakage current.

[0155] Next, prevention of leakage current will be described with reference to FIGS.

[0156] In the semiconductor substrate 113A-2a of the second substrate on the left side constituting the solid-state imaging device 113A shown in FIG. 16A, a P-well 330Pa-1 (0V) (the P-well 330Pa-1 and the P-support substrate 113A-3 are in contact), an N+ well 330Na (+1V), and a P+ well 330Pa-2 (0V) are formed, in that order from the P-support substrate 113A-3 side, and in the semiconductor substrate 113A-2b of the second substrate on the right side constituting the solid-state imaging device 113A, a P-well 330Pb-1 (-1V) (the P-well 330Pb-1 and the P-support substrate 113A-3 are in contact), an N+ well 330Nb (+3V), and a P+ well 330Pb-2 (0V) are formed, in that order from the P-support substrate 113A-3 side. A leakage current flows from P-well 330Pa-1 (0V) through P-support substrate 113A-3 to P-well 330Pb-1 (-1V), resulting in conduction.

[0157] In FIG. 16B, the third substrate (support substrate) 113B-3 constituting the solid-state imaging device 113B has an N+ well 33N-B (floating) in contact with the P-well 330Pa-1 (0V) and the P-well 330Pb-1 (-1V), thereby preventing leakage current.

[0158] In FIG. 16C, a third substrate (support substrate) 113C-3 constituting a solid-state imaging device 113C is N-type, thereby preventing leakage current.

[0159] In the semiconductor substrate 114A-2a of the second substrate on the left side constituting the solid-state imaging device 114A shown in Figure 17A, a P-well 340Pa-1 (0V) (the P-well 340Pa-1 and the P-support substrate 114A-3 are in contact), an N+ well 340Na (+1V), and a P+ well 340Pa-2 (0V) are formed, in that order from the P-support substrate 114A-3 side, and in the semiconductor substrate 114A-2b of the second substrate on the right side constituting the solid-state imaging device 114A, a P-well 340Pb-1 (-1V) (the P-well 340Pb-1 and the P-support substrate 114A-3 are in contact), an N+ well 340Nb (+3V), and a P+ well 340Pb-2 (0V) are formed, in that order from the P-support substrate 114A-3 side. A leakage current flows from P-well 340Pa-1 (0V) through P-support substrate 114A-3 to P-well 340Pb-1 (-1V), resulting in conduction.

[0160] In FIG. 17B, a third substrate (support substrate) 114B-3 constituting a solid-state imaging device 114B has an N+ well 34N-B (floating) in contact with a P- well 340Pb-1 (-1V), thereby preventing leakage current.

[0161] 17C, the third substrate (support substrate) 114C-3 constituting the solid-state imaging device 113C has an N+ well 34N-C (floating) in contact with a part of the P-well 340Pa-1 (0V) and a part of the P-well 340Pb-1 (-1V), thereby preventing leakage current. Note that the N+ well 34N-C (floating) of the third substrate (support substrate) 114C-3 constituting the solid-state imaging device 113C may be in contact with the entire P-well 340Pa-1 (0V) and the entire P-well 340Pb-1 (-1V) to prevent leakage current.

[0162] In the semiconductor substrate 115A-2a of the second substrate on the left side constituting the solid-state imaging device 115A shown in FIG. 18A, an N+ well 350Na(+1V) (the N+ well 350Na and the P-support substrate 115A-3 are in contact) and a P+ well 350Pa-2(0V) are formed, in that order from the P-support substrate 115A-3 side, and to the left of the N+ well 350Na(+1V) a P-well 350Pa-1(0V) is formed in contact with the P-support substrate 115A-3, and to the right of the N+ well 350Na(+1V) a P-well 350Pa-3(0V) is formed in contact with the P-support substrate 115A-3.

[0163] In the semiconductor substrate 115A-2b of the second substrate on the right side constituting the solid-state imaging device 115A, an N+ well 350Nb(+1V) (the N+ well 350Nb and the P- support substrate 115A-3 are in contact) and a P+ well 350Pb-2(0V) are formed in this order from the P- support substrate 115A-3 side, and on the left side of the N+ well 350Nb(+1V) a P- well 350Pb-1(0V) is formed in contact with the P- support substrate 115A-3, and on the right side of the N+ well 350Nb(+1V) a P- well 350Pb-3(0V) is formed in contact with the P- support substrate 115A-3. Then, a leakage current flows from the N+ well 350Nb(+3V) to the N+ well 350Na(+1V) via the P- support substrate 115A-3. It is conductive.

[0164] The semiconductor substrate 115A-2a of the second substrate on the left side and the semiconductor substrate 115A-2b of the second substrate on the right side that constitute the solid-state imaging device 115A are thinner semiconductor substrates than the semiconductor substrate 113A-2a of the second substrate on the left side and the semiconductor substrate 113A-2b of the second substrate on the right side that constitute the solid-state imaging device 113A, and the semiconductor substrate 114A-2a of the second substrate on the left side and the semiconductor substrate 114A-2b of the second substrate on the right side that constitute the solid-state imaging device 114A.

[0165] In FIG. 18B, the third substrate (support substrate) 115B-3 constituting the solid-state imaging device 115B has a P+ well 35P-B (floating) in contact with the N+ well 350Nb (3V) and the N+ well 350Na (1V), thereby preventing leakage current.

[0166] In the semiconductor substrate 116A-2a of the second substrate on the left side constituting the solid-state imaging device 116A shown in FIG. 19A, an N+ well 360Na(+1V) (the N+ well 360Na and the P-support substrate 116A-3 are in contact) and a P+ well 360Pa-2(0V) are formed, in that order from the P-support substrate 116A-3 side, and to the left of the N+ well 360Na(+1V) a P-well 360Pa-1(0V) is formed in contact with the P-support substrate 116A-3, and to the right of the N+ well 360Na(+1V) a P-well 360Pa-3(0V) is formed in contact with the P-support substrate 116A-3.

[0167] In the semiconductor substrate 116A-2b, the second substrate on the right side constituting the solid-state imaging device 116A, an N+ well 360Nb(+1V) (the N+ well 360Nb and the P- support substrate 116A-3 are in contact) and a P+ well 360Pb-2(0V) are formed, in that order from the P- support substrate 116A-3 side, and to the left of the N+ well 360Nb(+1V) a P- well 360Pb-1(-1V) is formed in contact with the P- support substrate 116A-3, and to the right of the N+ well 360Nb(+1V) a P- well 360Pb-3(0V) is formed in contact with the P- support substrate 116A-3. Then, a leakage current flows from the N+ well 360Nb (+3V) through the P- support substrate 116A-3 to the N+ well 360Na (+1V), and in the opposite direction, a leakage current flows from the P- well 360Pa-1 (0V) through the P- support substrate 116A-3 to the P- well 360Pb-1 (-1V), providing electrical continuity.

[0168] The semiconductor substrate 116A-2a of the second substrate on the left side and the semiconductor substrate 116A-2b of the second substrate on the right side that constitute the solid-state imaging device 116A are thinner semiconductor substrates than the semiconductor substrate 113A-2a of the second substrate on the left side and the semiconductor substrate 113A-2b of the second substrate on the right side that constitute the solid-state imaging device 113A, and the semiconductor substrate 114A-2a of the second substrate on the left side and the semiconductor substrate 114A-2b of the second substrate on the right side that constitute the solid-state imaging device 114A.

[0169] In Figure 19B, the third substrate (support substrate) 116B-3 constituting the solid-state imaging device 116B has two N+ wells 36Na-B and 36Nb-B in contact with the N+ well 360Nb (3V) and N+ well 360Na (1V), as well as the P- well 360Pa-3 (0V) and P- well 360Pb-3 (-1V), thereby preventing leakage current.

[0170] In Figure 19C, the third substrate (support substrate) 116C-3 constituting the solid-state imaging device 116C has two N+ wells 36Na-B and 36Nb-B in contact with the N+ well 360Nb (3V) and N+ well 360Na (1V), as well as the P- well 360Pa-3 (0V) and P- well 360Pb-3 (-1V), and a P+ well 36P-C (floating) in contact with the two N+ wells 36Na-B and 36Nb-B, thereby preventing leakage current.

[0171] In the semiconductor substrate 117A-2a of the second substrate on the left side constituting the solid-state imaging device 117A shown in Figure 20A, an N-well 370Na-1(-3V) (N-well 370Na-1 and N-support substrate 117A-3 are in contact), a P+ well 370Pa(-1V), and an N+ well 370Na-2(+3V) are formed, in that order from the N-support substrate 117A-3 side, and in the semiconductor substrate 117A-2b of the second substrate on the right side constituting the solid-state imaging device 117A, an N-well 370Nb-1(-1V) (N-well 370Nb-1 and N-support substrate 117A-3 are in contact), a P+ well 370Pb(0V), and an N+ well 370Nb-2(+1V) are formed, in that order from the N-support substrate 117A-3 side. A leakage current flows from N-well 370Na-1(-3V) through N-support substrate 117A-3 to N-well 370Nb-1(-1V), providing conduction.

[0172] In Figure 20B, the third substrate (support substrate) 117B-3 constituting the solid-state imaging device 117B has two P+ wells 37P-B (floating) in contact with the N-well 370Na-1 (3V) and the N-well 370Nb-1 (1V), thereby preventing leakage current.

[0173] In FIG. 20C, a third substrate (support substrate) 117C-3 constituting a solid-state imaging device 117C is of P-type, thereby preventing leakage current.

[0174] In the semiconductor substrate 118A-2a of the second substrate on the left side constituting the solid-state imaging device 118A shown in FIG. 21A, an N-well 380Na-1(-3V) (the N-well 380Na-1 and the N-support substrate 118A-3 are in contact), a P+ well 380Pa(-1V), and an N+ well 380Na-2(+3V) are formed, in that order from the N-support substrate 118A-3 side, and in the semiconductor substrate 118A-2b of the second substrate on the right side constituting the solid-state imaging device 118A, an N-well 380Nb-1(-1V) (the N-well 380Nb-1 and the N-support substrate 118A-3 are in contact), a P+ well 380Pb(0V), and an N+ well 380Nb-2(+1V) are formed, in that order from the N-support substrate 118A-3 side. A leakage current flows from N-well 380Na-1(-3V) through N-support substrate 118A-3 to N-well 380Nb-1(-1V), providing conduction.

[0175] In FIG. 21B, a third substrate (support substrate) 118B-3 constituting a solid-state imaging device 118B has a P+ well 38P-B (floating) in contact with an N-well 380Nb-1(1V), thereby preventing leakage current.

[0176] 21C, the third substrate (support substrate) 118C-3 constituting the solid-state imaging device 118C has a P+ well 38P-C (floating) in contact with a part of the N-well 380Na-1(3V) and a part of the N-well 380Nb-1(1V), thereby preventing leakage current. Note that 38P-C (floating) of the third substrate (support substrate) 118C-3 constituting the solid-state imaging device 118C may be in contact with the entire N-well 380Na-1(3V) and the entire N-well 380Nb-1(1V) to prevent leakage current.

[0177] In semiconductor substrate 119A-2a, the second substrate on the left side constituting solid-state imaging device 119A shown in FIG. 22A, a P+ well 390Pa(-1V) (P+ well 390Pa and N-support substrate 119A-3 are in contact) and an N+ well 390Na-2(+3V) are formed, in that order from the N-support substrate 119A-3 side, and to the left of P+ well 390Pa(-1V) an N-well 390Na-1(3V) is formed in contact with N-support substrate 119A-3, and to the right of P+ well 390Pa(-1V) an N-well 390Na-3(3V) is formed in contact with N-support substrate 119A-3.

[0178] In semiconductor substrate 119A-2b, the second substrate on the right side constituting solid-state imaging device 119A, P+ well 390Pb(0V) (P+ well 390Pb and N-support substrate 119A-3 are in contact) and N+ well 390Nb-2(+3V) are formed in this order from the N-support substrate 119A-3 side, and to the left of P+ well 390Pa(0V) N-well 390Nb-1(3V) is formed in contact with N-support substrate 119A-3, and to the right of P+ well 390Pa(0V) N-well 390Nb-3(3V) is formed in contact with N-support substrate 119A-3. A leakage current flows from P+ well 390Pb(0V) to P+ well 390Pa(-1V) via N-support substrate 119A-3, providing electrical continuity.

[0179] The semiconductor substrate 119A-2a of the second substrate on the left side and the semiconductor substrate 119A-2b of the second substrate on the right side that constitute the solid-state imaging device 119A are thinner semiconductor substrates than the semiconductor substrate 117A-2a of the second substrate on the left side and the semiconductor substrate 117A-2b of the second substrate on the right side that constitute the solid-state imaging device 117A, and the semiconductor substrate 118A-2a of the second substrate on the left side and the semiconductor substrate 118A-2b of the second substrate on the right side that constitute the solid-state imaging device 118A.

[0180] In FIG. 22B, the third substrate (support substrate) 119B-3 constituting the solid-state imaging device 119B has an N+ well 39N-B (floating) in contact with a P+ well 390Pb (0V) and a P+ well 390Pa (-1V), thereby preventing leakage current.

[0181] In the semiconductor substrate 120A-2a of the second substrate on the left side constituting the solid-state imaging device 120A shown in FIG. 23A, a P+ well 400Pa-1(-1V) (the P+ well 400Pa-1 and the N-support substrate 120A-3 are in contact) and a P+ well 400Pa-2(0V) are formed, in that order from the N-support substrate 120A-3 side, and to the left of the P+ well 400Pa-1(-1V) an N-well 400Na-1(3V) is formed in contact with the N-support substrate 120A-3, and to the right of the P+ well 400Pa-1(-1V) an N-well 400Na-2(3V) is formed in contact with the N-support substrate 120A-3.

[0182] In the semiconductor substrate 120A-2b of the second substrate on the right side constituting the solid-state imaging device 120A, a P+ well 400Pb-1(0V) (the P+ well 400Pb-1 and the N-support substrate 120A-3 are in contact) and a P+ well 400Pb-2(0V) are formed in that order from the N-support substrate 120A-3 side, and to the left of the P+ well 400Pa-1(0V) an N-well 400Nb-1(1V) is formed in contact with the N-support substrate 120A-3, and to the right of the P+ well 400Pb-1(0V) an N-well 400Nb-2(1V) is formed in contact with the N-support substrate 120A-3. Then, a leakage current flows from the P+ well 400Pb-1 (0V) through the N-support substrate 120A-3 to the P+ well 400Pa-1 (-1V), and in the opposite direction, a leakage current flows from the N-well 400Na-2 (3V) through the N-support substrate 120A-3 to the N-well 400Nb-1 (1V), providing electrical continuity.

[0183] The semiconductor substrate 120A-2a of the second substrate on the left side and the semiconductor substrate 120A-2b of the second substrate on the right side that constitute the solid-state imaging device 120A are thinner semiconductor substrates than the semiconductor substrate 117A-2a of the second substrate on the left side and the semiconductor substrate 117A-2b of the second substrate on the right side that constitute the solid-state imaging device 117A, and the semiconductor substrate 118A-2a of the second substrate on the left side and the semiconductor substrate 118A-2b of the second substrate on the right side that constitute the solid-state imaging device 118A.

[0184] In Figure 23B, the third substrate (support substrate) 120B-3 constituting the solid-state imaging device 120B has two P+ wells 40Pa-B and 40Pb-B in contact with the P+ well 400Pb-1 (0V) and P+ well 400Pa-1 (-1V), as well as the N-well 400Na-2 (3V) and N-well 400Nb-1 (1V), thereby preventing leakage current.

[0185] In Figure 23C, the third substrate (support substrate) 120C-3 constituting the solid-state imaging device 120C has two P+ wells 40Pa-B and 40Pb-B in contact with the P+ well 400Pb-1 (0V) and P+ well 400Pa-1 (-1V), as well as the N-well 400Na-2 (3V) and N-well 400Nb-1 (1V), and an N+ well 40N-C (floating) in contact with the two P+ wells 40Pa-B and 40Pb-B, thereby preventing leakage current.

[0186] Finally, an example of a manufacturing method for the solid-state imaging device according to the first embodiment of the present technology will be described with reference to FIGS.

[0187] 27A-B, electrodes 1210a constituting CuCu junctions are formed on a semiconductor substrate 9K of a second substrate (a circuit board such as a logic circuit board), KGB measurement is performed, and then needles are embedded and planarized, wiring 1340 is formed, completing the CuCu junction surface. Then, as shown in FIG. 27C, the substrate is divided into individual pieces.

[0188] 27D-E, electrodes 1200a constituting a CuCu bond are formed on the semiconductor substrate 12K of the first substrate (sensor substrate), KGB measurement is performed, post-probe embedding and planarization are performed, wiring 1340 is formed, and the CuCu bonded surface is completed. Then, as shown in Fig. 27F, the semiconductor substrate 12K of the first substrate (sensor substrate) and two semiconductor substrates 9K of each of the two second substrates (circuit boards such as logic circuit boards) are Cu-Cu bonded (directly bonded) using CoW.

[0189] 28A-B, the semiconductor substrate 12K is thinned, steps are filled, and the substrate is planarized, and in FIG. 28C, a third substrate (support substrate) 124-3 having a well formed therein is bonded. In FIGS. 28D-F, the semiconductor substrate 12K is thinned, on-chip lenses 1301 and color filters 13-2 are formed, and the substrate is singulated to manufacture the solid-state imaging device 124. In the solid-state imaging device 124, an insulating layer 50 is arranged between the third substrate (support substrate) 124-3 and the two second substrates (circuit substrates such as logic circuit boards) 124-2a and 124-2b as shown in FIG. 28F, but instead of the insulating layer 50, a film (which may be a thin film) such as a nitride film may be arranged. Furthermore, as shown in FIG. 28F, an insulating layer 50 may not be arranged between the third substrate (support substrate) 124-3 and the two second substrates (circuit boards such as logic circuit boards) 124-2a and 124-2b, and the third substrate (support substrate) 124-3 may be in contact with the two second substrates (circuit boards such as logic circuit boards) 124-2a and 124-2b.

[0190] The above description of the solid-state imaging device of the first embodiment (example 1 of solid-state imaging device) of the present technology can be applied to the solid-state imaging devices of the second to sixth embodiments of the present technology described later, and to the manufacturing method of the solid-state imaging device of the seventh embodiment of the present technology described later, unless there is any particular technical contradiction.

[0191] 3. Second Embodiment (Second Example of Solid-State Imaging Device) A solid-state imaging device according to a second embodiment (second example of a solid-state imaging device) of the present technology will be described with reference to Fig. 24. Fig. 24 is a cross-sectional view showing a configuration example of the solid-state imaging device according to the second embodiment of the present technology.

[0192] 24 includes a first substrate 121-1, second substrates 121-2a and 121-2b stacked on the first substrate 121-1 by direct bonding on the opposite side (lower side in FIG. 24) from the light incident side (upper side in FIG. 24) of the first substrate 121-1 and having a size different from that of the first substrate 121-1, a third substrate 121-3 provided on the opposite side (lower side in FIG. 24) from the light incident side (upper side in FIG. 24) of the second substrates 121-2a and 121-2b, and a cavity 50-1 (the cavity 50-1 may be an air layer or an air gap) formed between the first substrate 121-1 and the third substrate 121-3. In the solid-state imaging device 121, the third substrate 121-3 contacts the second substrates 121-2a and 121-2b and also contacts the cavity 50-1.

[0193] The first substrate 121-1 is a sensor substrate on which photodiodes and multiple transistors that constitute pixels are formed. The second substrate 121-2a is, for example, any one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The second substrate 121-2b is, for example, any one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The third substrate 121-3 is a support substrate.

[0194] From the viewpoint of preventing leakage current, the configurations of wells 41PNa and 41PNb constituting the third substrate 121-3, and 410NPa constituting the second substrate 121-2a and 410NPb constituting the second substrate 121-2b can be directly applied to the contents described in the solid-state imaging device section of the first embodiment (example 1 of solid-state imaging device) of the present technology.

[0195] The above description of the solid-state imaging device of the second embodiment (example 2 of solid-state imaging device) of the present technology can be applied to the solid-state imaging device of the first embodiment of the present technology described above, as well as the solid-state imaging devices of the third to sixth embodiments of the present technology described below and the method for manufacturing the solid-state imaging device of the seventh embodiment of the present technology described below, unless there is any particular technical contradiction.

[0196] 4. Third Embodiment (Example 3 of Solid-State Imaging Device) A solid-state imaging device according to a third embodiment (third example of a solid-state imaging device) of the present technology will be described with reference to Fig. 25. Fig. 25 is a cross-sectional view showing a configuration example of the solid-state imaging device according to the third embodiment of the present technology.

[0197] 25 includes a first substrate 122-1, second substrates 122-2a and 122-2b that are stacked on the first substrate 122-1 by direct bonding on the opposite side (lower side in FIG. 25) from the light incident side (upper side in FIG. 25) of the first substrate 122-1 and have a size different from that of the first substrate 122-1, a third substrate 122-3 that is provided on the opposite side (lower side in FIG. 25) from the light incident side (upper side in FIG. 25) of the second substrates 122-2a and 122-2b, and an insulating layer 50 formed between the first substrate 122-1 and the third substrate 122-3. In the solid-state imaging device 122, the third substrate 122-3 is in contact with the second substrates 122-2a and 122-2b and also in contact with the insulating layer 50.

[0198] The first substrate 122-1 is a sensor substrate on which photodiodes and multiple transistors that constitute pixels are formed. The second substrate 122-2a is, for example, any one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The second substrate 122-2b is, for example, any one of an analog circuit board on which an analog circuit is formed, a logic circuit board on which a logic circuit is formed, and a memory circuit board on which a memory circuit is formed. The third substrate 122-3 is a support substrate.

[0199] In a solid-state imaging device according to a third embodiment (third example of a solid-state imaging device) of the present technology, the second substrates 122-2a and 122-2b are oriented in the opposite direction, and the wiring layers 10-1 and 10-2 are formed on the support substrate 122-3c side. The well of the support substrate 122-3c and the second substrates 122-2a and 122-2b are bonded (for example, by Cu-Cu bonding) with wiring metals (electrodes) 1200a-2 and 1220a-1 instead of the semiconductor substrate 9-1.

[0200] From the viewpoint of preventing leakage current, the configuration of wells 42PNa and 42PNb constituting the third substrate 122-3c can be directly applied to the contents described in the section on the solid-state imaging device of the first embodiment (example 1 of solid-state imaging device) of the present technology.

[0201] The above description of the solid-state imaging device of the third embodiment (example 3 of solid-state imaging device) of the present technology can be applied to the solid-state imaging devices of the first and second embodiments of the present technology described above, as well as the solid-state imaging devices of the fourth to sixth embodiments of the present technology described below, and the method for manufacturing the solid-state imaging device of the seventh embodiment of the present technology described below, unless there is any particular technical contradiction.

[0202] 5. Fourth Embodiment (Fourth Example of Solid-State Imaging Device) A solid-state imaging device according to a fourth embodiment (fourth example of a solid-state imaging device) of the present technology will be described with reference to Fig. 26. Fig. 26 is a cross-sectional view showing an example of the configuration of the solid-state imaging device according to the fourth embodiment of the present technology.

[0203] 26 includes a first substrate 123-1, second substrates 123-2a and 123-2b that are stacked on the first substrate 123-1 by direct bonding on the opposite side (lower side in FIG. 25) from the light incident side (upper side in FIG. 26) of the first substrate 123-1 and have a size different from that of the first substrate 123-1, a third substrate 123-3 that is provided on the opposite side (lower side in FIG. 26) from the light incident side (upper side in FIG. 26) of the second substrates 123-2a and 123-2b, and an insulating layer 50 that is formed between the first substrate 123-1 and the third substrate 123-3. In the solid-state imaging device 123, the third substrate 123-3 is in contact with the second substrates 123-2a and 123-2b and also in contact with the insulating layer 50. A fourth substrate 123-4 is formed on the first substrate 123-1.

[0204] The fourth substrate 123-4 is a sensor substrate on which photodiodes and multiple transistors that constitute pixels are formed. The first substrate 123-1 is, for example, any one of an analog circuit substrate on which an analog circuit is formed, a logic circuit substrate on which a logic circuit is formed, and a memory circuit substrate on which a memory circuit is formed. The second substrate 123-2a is, for example, any one of an analog circuit substrate on which an analog circuit is formed, a logic circuit substrate on which a logic circuit is formed, and a memory circuit substrate on which a memory circuit is formed, and the second substrate 123-2b is, for example, any one of an analog circuit substrate on which an analog circuit is formed, a logic circuit substrate on which a logic circuit is formed, and a memory circuit substrate on which a memory circuit is formed. The third substrate 122-3 is a support substrate.

[0205] From the viewpoint of preventing leakage current, the configurations of wells 43PNa and 43PNb constituting the third substrate 123-3, and 430NPa constituting the second substrate 123-2a and 430NPb constituting the second substrate 123-2b can be directly applied to the contents described in the solid-state imaging device section of the first embodiment (example 1 of solid-state imaging device) of the present technology.

[0206] The above description of the solid-state imaging device of the fourth embodiment (example 4 of solid-state imaging device) of the present technology can be applied to the solid-state imaging devices of the first to third embodiments of the present technology described above, as well as the solid-state imaging devices of the fifth and sixth embodiments of the present technology described below, and the method for manufacturing the solid-state imaging device of the seventh embodiment of the present technology described below, unless there is any particular technical contradiction.

[0207] 6. Fifth Embodiment (Fifth Example of Solid-State Imaging Device) A solid-state imaging device according to a fifth embodiment (fifth example of a solid-state imaging device) of the present technology will be described with reference to Fig. 31. Fig. 31 is a cross-sectional view showing a configuration example of the solid-state imaging device according to the fifth embodiment of the present technology.

[0208] 31 includes a first substrate 127-1, a second substrate 127-2 that is stacked on the first substrate 127-1 by direct bonding on the opposite side (lower side in FIG. 31) of the first substrate 127-1 from the light incident side (upper side in FIG. 31) of the first substrate 127-1 and has a size different from that of the first substrate 127-1, a third substrate 127-3 that is provided on the opposite side (lower side in FIG. 31) of the second substrate 127-2 from the light incident side (upper side in FIG. 31) of the second substrate 127-2, and two insulating layers 50 formed between the first substrate 127-1 and the third substrate 127-3 (it can also be said that an insulating layer 50 is formed on each of the left and right side sides of the second substrate 127-2). In the solid-state imaging device 127, the third substrate 127-3 is in contact with the second substrate 127-2 and also in contact with the two insulating layers 50.

[0209] The first substrate 127-1 is a sensor substrate on which photodiodes and multiple transistors that constitute pixels are formed. The second substrate 127-2 is, for example, one of an analog circuit substrate on which an analog circuit is formed, a logic circuit substrate on which a logic circuit is formed, and a memory circuit substrate on which a memory circuit is formed. The third substrate 127-3 is a support substrate.

[0210] The above description of the solid-state imaging device of the fifth embodiment (example 5 of solid-state imaging device) of the present technology can be applied to the solid-state imaging devices of the first to fourth embodiments of the present technology described above, as well as the solid-state imaging device of the sixth embodiment of the present technology described below and the method for manufacturing the solid-state imaging device of the seventh embodiment of the present technology described below, unless there is any particular technical contradiction.

[0211] 7. Sixth Embodiment (Sixth Example of Solid-State Imaging Device) A solid-state imaging device according to a sixth embodiment (sixth example of a solid-state imaging device) of the present technology will be described with reference to Fig. 32 to Fig. 38. Each of Fig. 32 to Fig. 38 is a cross-sectional view showing a configuration example of the solid-state imaging device according to the sixth embodiment of the present technology.

[0212] The solid-state imaging device 128 shown in Figure 32 comprises a first substrate 128-1, a second substrate 128-2 stacked on the first substrate 128-1 by direct bonding on the opposite side (lower side of Figure 32) of the first substrate 128-1 from the light incident side (upper side of Figure 32) of the first substrate 128-1 and having a size different from the size of the first substrate 128-1, a third substrate 128-3 provided on the opposite side (lower side of Figure 32) of the second substrate 128-2 from the light incident side (upper side of Figure 32), two insulating layers 50 formed between the first substrate 128-1 and the third substrate 128-3 (it can also be said that an insulating layer 50 is formed on each of the left and right side sides of the second substrate 128-2), and two films 70 and 80 formed between the first substrate 128-1 and the third substrate 128-3 and made of a material different from the material constituting the insulating layer 50. In the solid-state imaging device 128, an insulating layer 50, a film 70, and a film 80 are formed in this order from the light incident side (the upper side in FIG. 32). The film 70 contacts the second substrate 128-2 and the insulating layer 50, and the film 80 contacts the third substrate 128-3, with the films 70 and 80 being stacked.

[0213] The first substrate 128-1 is a sensor substrate on which photodiodes and multiple transistors that constitute pixels are formed. The second substrate 128-2 is, for example, one of an analog circuit substrate on which an analog circuit is formed, a logic circuit substrate on which a logic circuit is formed, and a memory circuit substrate on which a memory circuit is formed. The third substrate 128-3 is a support substrate.

[0214] Film 70 may include at least one of a heat dissipation member and a member having a film stress greater than that of Si (silicon). Film 80 may also include at least one of a heat dissipation member and a member having a film stress greater than that of Si (silicon). Film 80 may also include a member having a linear expansion coefficient greater than that of Si (silicon), particularly for the purpose of alleviating stress when supporting substrate 128-3 is bonded at high temperature and cooled to room temperature. The heat dissipation member may include at least one selected from the group consisting of SiC, AlN, SiN, Cu, Al, and C, and the member having a film stress greater than that of Si may include at least one selected from the group consisting of SiO2, SiN, Cu, Al, and C.

[0215] The insulating layer 50 may include an inorganic oxide film.

[0216] The solid-state imaging device 129 shown in Figure 33 comprises a first substrate 129-1, a second substrate 129-2 stacked on the first substrate 129-1 by direct bonding on the opposite side (lower side of Figure 33) of the first substrate 129-1 from the light incident side (upper side of Figure 33) of the first substrate 129-1 and having a size different from the size of the first substrate 129-1, a third substrate 129-3 provided on the opposite side (lower side of Figure 33) of the second substrate 129-2 from the light incident side (upper side of Figure 33), two insulating layers 50-U formed between the first substrate 129-1 and the third substrate 129-3 (it can also be said that the insulating layer 50-U is formed on each of the left and right side sides of the second substrate 129-2), and two films 70 and 80 formed between the first substrate 129-1 and the third substrate 129-3 and made of a material different from the material constituting the insulating layer 50-U. In the solid-state imaging device 129, an insulating layer 50-U, a film 70, and a film 80 are formed in this order from the light incident side (the upper side in FIG. 33). The film 70 contacts the second substrate 129-2 and the insulating layer 50-U, and the film 80 contacts the third substrate 129-3, with the films 70 and 80 being stacked.

[0217] The first substrate 129-1 is a sensor substrate on which photodiodes and multiple transistors that constitute pixels are formed. The second substrate 129-2 is, for example, one of an analog circuit substrate on which an analog circuit is formed, a logic circuit substrate on which a logic circuit is formed, and a memory circuit substrate on which a memory circuit is formed. The third substrate 129-3 is a support substrate.

[0218] Film 70 may include at least one of a heat dissipation member and a member having a film stress greater than that of Si (silicon). Film 80 may also include at least one of a heat dissipation member and a member having a film stress greater than that of Si (silicon). Film 80 may also include a member having a linear expansion coefficient greater than that of Si (silicon), particularly for the purpose of alleviating stress when supporting substrate 129-3 is bonded at high temperature and cooled to room temperature. The heat dissipation member may include at least one selected from the group consisting of SiC, AlN, SiN, Cu, Al, and C, and the member having a film stress greater than that of Si may include at least one selected from the group consisting of SiO2, SiN, Cu, Al, and C.

[0219] The insulating layer 50-U may include an organic film, which is softer and has better thermal conductivity than inorganic oxide films, and therefore can further improve stress relaxation and thermal conductivity.

[0220] The solid-state imaging device 130 shown in FIG. 34A comprises a first substrate 130-1, a second substrate 130-2 stacked on the first substrate 130-1 by direct bonding on the opposite side (lower side of FIG. 34A) of the light incident side (upper side of FIG. 34A) of the first substrate 130-1 and having a size different from that of the first substrate 130-1, a third substrate 130-3 provided on the opposite side (lower side of FIG. 34A) of the second substrate 130-2 on the light incident side (upper side of FIG. 34A) of the second substrate 130-2, two insulating layers 50-1 formed between the first substrate 130-1 and the third substrate 130-3 (it can also be said that the insulating layer 50-1 is formed on each of the left and right side sides of the second substrate 130-2), and two films 70 and 80 formed between the first substrate 130-1 and the third substrate 130-3 and made of a material different from the material constituting the insulating layer 50-1. In the solid-state imaging device 130, an insulating layer 50-1, a film 70, and a film 80 are formed in this order from the light incident side (the upper side in FIG. 34A). The film 70 is in contact with the second substrate 130-2 and the insulating layer 50-1, and the film 80 is in contact with the third substrate 130-3, and the films 70 and 80 are stacked.

[0221] In the solid-state imaging device 130, the surface of the second substrate 130-2 that contacts the film 70 and the surface of the insulating layer 50-1 that contacts the film 70 (upper convex portion 70a that constitutes the film 70) are not flush with each other, and the surface of the insulating layer 50-1 that contacts the film 70 (upper convex portion 70a that constitutes the film 70) is located closer to the first substrate 130-1 (upper side in Figure 34A) than the surface of the second substrate 130-2 that contacts the film 70.

[0222] As shown in Figure 34B (Figure 34B-1), the surfaces of the semiconductor substrates 9-1 and 9-2 that contact the film 70 (the surfaces opposite the light incident side (wiring layer 11-1 and 11-2 side) of the semiconductor substrates 9-1 and 9-2) are flush with the surface of the insulating layer 50 that contacts the film 70 (the surface opposite the light incident side (wiring layer 11 side) of the insulating layer 50).

[0223] 34B (FIG. 34B-2), the surfaces of the semiconductor substrates 9-1 and 9-2 in contact with the film 70 (the surfaces opposite the light incident sides (wiring layer 11-1 and 11-2 sides) of the semiconductor substrates 9-1 and 9-2) and the surface of the insulating layer 50-1 in contact with the film 70 (the surface opposite the light incident side (wiring layer 11 side) of the insulating layer 50-1) are not flush with each other, and the surface of the insulating layer 50-1 in contact with the film 70 (the surface opposite the light incident side (wiring layer 11 side) of the insulating layer 50-1) is located on the semiconductor substrate 12 (wiring layer 11) side (the upper side of FIG. 34B-2). The above-described structure results from the fact that the insulating layer 50-1 may be scraped off when the back side of the second substrate 130-2 (the opposite side to the light incident side, the lower side of FIG. 34B-2) is cleaned after the insulating layer 50-1 is embedded.

[0224] The first substrate 130-1 is a sensor substrate on which photodiodes and multiple transistors that constitute pixels are formed. The second substrate 127-2 is, for example, one of an analog circuit substrate on which an analog circuit is formed, a logic circuit substrate on which a logic circuit is formed, and a memory circuit substrate on which a memory circuit is formed. The third substrate 130-3 is a support substrate.

[0225] The film 70 may include at least one of a heat dissipation member and a member having a film stress greater than that of Si (silicon). Similarly, the film 80 may include at least one of a heat dissipation member and a member having a film stress greater than that of Si (silicon). However, in particular, for the purpose of alleviating stress when the support substrate 130-3 is bonded at high temperature and cooled to room temperature, the film 80 may include a member having a linear expansion coefficient greater than that of Si (silicon). The heat dissipation member may include at least one selected from the group consisting of SiC, AlN, SiN, Cu, Al, and C, and the member having a film stress greater than that of Si may include at least one selected from the group consisting of SiO2, SiN, Cu, Al, and C.

[0226] The insulating layer 50-1 may include an inorganic oxide film.

[0227] The solid-state imaging device 131 shown in Figure 35 comprises a first substrate 131-1, a second substrate 131-2 stacked on the first substrate 131-1 by direct bonding on the opposite side (lower side of Figure 35) of the first substrate 131-1 from the light incident side (upper side of Figure 35) of the first substrate 131-1 and having a size different from the size of the first substrate 131-1, a third substrate 131-3 provided on the opposite side (lower side of Figure 35) of the second substrate 131-2 from the light incident side (upper side of Figure 35), two insulating layers 50 formed between the first substrate 131-1 and the third substrate 131-3 (it can also be said that the insulating layer 50 is formed on each of the left and right side sides of the second substrate 131-2), and two films 70 and 80 formed between the first substrate 131-1 and the third substrate 131-3 and made of a material different from the material constituting the insulating layer 50. In the solid-state imaging device 131, an insulating layer 50, a film 70, and a film 80 are formed in this order from the light incident side (the upper side in FIG. 35). The film 70 is in contact with the second substrate 131-2 and the insulating layer 50, and the film 80 is in contact with the third substrate 131-3, and the films 70 and 80 are stacked.

[0228] The first substrate 131-1 is a sensor substrate on which photodiodes and multiple transistors that constitute pixels are formed. The second substrate 131-2 is, for example, one of an analog circuit substrate on which an analog circuit is formed, a logic circuit substrate on which a logic circuit is formed, and a memory circuit substrate on which a memory circuit is formed. The third substrate 131-3 is a support substrate.

[0229] 35, membrane 70 is made up of four membranes (four layers), and membrane 80 is made up of four membranes (four layers). Note that membrane 70 may be made up of multiple membranes (multiple layers) other than four membranes (four layers), and membrane 80 may be made up of multiple membranes (multiple layers) other than four membranes (four layers).

[0230] Each of the four films (each of the four layers) of film 70 may include at least one of a heat dissipation member and a member having a film stress greater than that of Si (silicon). Similarly, each of the four films (each of the four layers) of film 80 may include at least one of a heat dissipation member and a member having a film stress greater than that of Si (silicon). Furthermore, each of the four films (each of the four layers) of film 80 may include a member having a linear expansion coefficient greater than that of Si (silicon) for the purpose of alleviating stress when bonding support substrate 131-3 at high temperature and cooling to room temperature. The heat dissipation member may include at least one material selected from the group consisting of SiC, AlN, SiN, Cu, Al, and C, and the member having a film stress greater than that of Si may include at least one material selected from the group consisting of SiO2, SiN, Cu, Al, and C.

[0231] The insulating layer 50 may include an inorganic oxide film.

[0232] The solid-state imaging device 132 shown in FIG. 36 includes a first substrate 132-1, two second substrates 132-2a and 132-2b that are stacked on the first substrate 132-1 by direct bonding on the opposite side (lower side in FIG. 36) of the light incident side (upper side in FIG. 36) of the first substrate 132-1 and that have a size different from the size of the first substrate 132-1 and are arranged in the same layer, and a third substrate 132- 36 ), three insulating layers 50 formed between the first substrate 132-1 and the third substrate 132-3 (it can also be said that the insulating layers 50 are formed on the left side surface of the second substrate 132-2a, the right side surface of the second substrate 132-2a (the left side surface of the second substrate 132-2b), and the right side surface of the second substrate 132-2b), and two films 70 and 80 formed between the first substrate 132-1 and the third substrate 132-3 and made of a material different from the material constituting the insulating layers 50. In the solid-state imaging device 132, the insulating layer 50, the film 70, and the film 80 are formed in this order from the light incident side (upper side of FIG. 36 ). The film 70 is in contact with the second substrate 132-2 and the insulating layer 50, and the film 80 is in contact with the third substrate 132-3, and the films 70 and 80 are stacked. Although the second substrate 132-2 is described as including two second substrates in FIG. 36, the second substrate 132-2 may be configured from three or more second substrates.

[0233] The first substrate 132-1 is a sensor substrate on which photodiodes and multiple transistors that constitute pixels are formed. Each of the second substrates 132-2a and 132-2b is, for example, one of an analog circuit substrate on which an analog circuit is formed, a logic circuit substrate on which a logic circuit is formed, and a memory circuit substrate on which a memory circuit is formed. The third substrate 132-3 is a support substrate.

[0234] The film 70 may include at least one of a heat dissipation member and a member having a film stress greater than that of Si (silicon). Similarly, the film 80 may include at least one of a heat dissipation member and a member having a film stress greater than that of Si (silicon). However, in particular, for the purpose of alleviating stress when the support substrate 132-3 is bonded at high temperature and cooled to room temperature, the film 80 may include a member having a linear expansion coefficient greater than that of Si (silicon). The heat dissipation member may include at least one selected from the group consisting of SiC, AlN, SiN, Cu, Al, and C, and the member having a film stress greater than that of Si may include at least one selected from the group consisting of SiO2, SiN, Cu, Al, and C.

[0235] The insulating layer 50 may include an inorganic oxide film.

[0236] The solid-state imaging device 133 shown in FIG. 37 includes a first substrate 133-1, n second substrates (second substrates 133-2, 133-4a to 4c, 133-5a to 5c) that are stacked on the first substrate 133-1 by direct bonding on the opposite side (lower side of FIG. 37) to the light incident side (upper side of FIG. 37) of the first substrate 133-1, and that have sizes different from the size of the first substrate 133-1 and are formed by stacking and are formed in the same layer, and n second substrates (second substrates 133-2, 133-4a to 133-4c, 133-5a to 133-5c) that are stacked on the opposite side (lower side of FIG. 37) to the light incident side (upper side of FIG. 37) of the first substrate 133-1. The solid-state imaging device 133 includes a third substrate 133-3 provided on the opposite side (lower side in FIG. 32) to the first substrate 133-1 side (upper side in FIG. 37), two insulating layers 50 formed between the first substrate 133-1 and the third substrate 133-3 (it can also be said that insulating layers 50 are formed on each of the left and right side surfaces of the second substrate 133-2), and a plurality of films 70 and 80 formed between the first substrate 133-1 and the third substrate 133-3 and made of a material different from that of the insulating layer 50. In the solid-state imaging device 133, the insulating layers 50 and the films 70 are alternately formed in order from the light incident side (upper side in FIG. 37), and finally the films 70 and 80 are formed. The film 70 contacts the second substrate 133-2 and the insulating layer 50, and the film 80 contacts the third substrate 133-3, and the films 70 and 80 are stacked.

[0237] The first substrate 133-1 is a sensor substrate on which photodiodes and multiple transistors that constitute pixels are formed. The second substrate 133-2 and the like are, for example, any one of an analog circuit substrate on which an analog circuit is formed, a logic circuit substrate on which a logic circuit is formed, and a memory circuit substrate on which a memory circuit is formed. The third substrate 133-3 is a support substrate.

[0238] Film 70 may include at least one of a heat dissipation member and a member having a film stress greater than that of Si (silicon). Film 80 may also include at least one of a heat dissipation member and a member having a film stress greater than that of Si (silicon). Film 80 may also include a member having a linear expansion coefficient greater than that of Si (silicon), particularly for the purpose of alleviating stress when supporting substrate 133-3 is bonded at high temperature and cooled to room temperature. The heat dissipation member may include at least one selected from the group consisting of SiC, AlN, SiN, Cu, Al, and C, and the member having a film stress greater than that of Si may include at least one selected from the group consisting of SiO2, SiN, Cu, Al, and C.

[0239] The insulating layer 50 may include an inorganic oxide film.

[0240] The solid-state imaging device 134 shown in FIG. 38 includes a first substrate 134-1, two second substrates 134-2a and 134-2b that are stacked on the first substrate 134-1 by direct bonding on the opposite side (lower side in FIG. 38) of the light incident side (upper side in FIG. 38) of the first substrate 134-1 and that have a size different from the size of the first substrate 134-1 and are arranged in the same layer, and a third substrate 134- 38 ), three insulating layers 50 formed between the first substrate 134-1 and the third substrate 134-3 (it can also be said that the insulating layers 50 are formed on the left side surface of the second substrate 134-2a, the right side surface of the second substrate 134-2a (the left side surface of the second substrate 134-2b), and the right side surface of the second substrate 134-2b), and two films 70 and 80 formed between the first substrate 134-1 and the third substrate 134-3 and made of a material different from the material constituting the insulating layer 50. In the solid-state imaging device 134, the insulating layer 50, the film 70, and the film 80 are formed in this order from the light incident side (upper side of FIG. 38 ). The film 70 is in contact with the second substrate 134-2 and the insulating layer 50, and the film 80 is in contact with the third substrate 134-3, and the films 70 and 80 are stacked. Although second substrate 134-2 is described as including two second substrates in FIG. 38, second substrate 134-2 may be configured from three or more second substrates.

[0241] The first substrate 134-1 is a sensor substrate on which photodiodes and multiple transistors that constitute pixels are formed. Each of the second substrates 134-2a and 134-2b is, for example, one of an analog circuit substrate on which an analog circuit is formed, a logic circuit substrate on which a logic circuit is formed, and a memory circuit substrate on which a memory circuit is formed. The third substrate 134-3 is a support substrate.

[0242] The film 70 may include at least one of a heat dissipation member and a member having a film stress greater than that of Si (silicon). Similarly, the film 80 may include at least one of a heat dissipation member and a member having a film stress greater than that of Si (silicon). However, in particular, for the purpose of alleviating stress when the support substrate 134-3 is bonded at high temperature and cooled to room temperature, the film 80 may include a member having a linear expansion coefficient greater than that of Si (silicon). The heat dissipation member may include at least one selected from the group consisting of SiC, AlN, SiN, Cu, Al, and C, and the member having a film stress greater than that of Si may include at least one selected from the group consisting of SiO2, SiN, Cu, Al, and C.

[0243] The solid-state imaging device 134 further includes a metal diffusion prevention film 90, which is formed to cover the surface of the insulating layer 50 that is not in contact with the film 70, and the metal diffusion prevention film 90 is disposed between the second substrate 134-2 and the insulating layer 50, and between the first substrate 134-1 and the insulating layer 50. By disposing the metal diffusion prevention film 90, metal diffusion within the wiring layers 11 and 10 can be prevented.

[0244] The above description of the solid-state imaging device of the sixth embodiment (example 6 of solid-state imaging device) of the present technology can be applied to the solid-state imaging devices of the first to fifth embodiments of the present technology described above, and the method for manufacturing the solid-state imaging device of the seventh embodiment of the present technology described below, unless there is any particular technical contradiction.

[0245] 8. Seventh Embodiment (First Example of Manufacturing Method of Solid-State Imaging Device) A method for manufacturing a solid-state imaging device according to a seventh embodiment (first example of a method for manufacturing a solid-state imaging device) of the present technology will be described with reference to Fig. 39. Fig. 39 is a diagram for explaining the method for manufacturing a solid-state imaging device according to the seventh embodiment of the present technology.

[0246] As shown in FIG. 39A, bonding (e.g., direct CuCu bonding) is performed, as shown in FIG. 39B, an insulating layer 50 is embedded and deposited, as shown in FIG. 39B, the semiconductor substrates 9-1 and 9-2 are thinned and planarized, as shown in FIG. 39C, a support substrate 135-2 is bonded, as shown in FIG. 39D, and finally, customization is performed, as shown in FIG. 39F, to manufacture the solid-state imaging device 135.

[0247] In the manufacturing method shown in Figure 39, the process flow calls for bonding the substrate (chip), then thinning and embedding it, but here the substrate (chip) is embedded with a embedding film before being thinned, and the Si and embedding film are simultaneously ground and flattened. This makes it easy to manufacture a structure in which the back surface (lower side of Figure 39) of the substrate (chip) is not embedded, and the insulating layer 50 (embedded film) functions as a protective film, preventing the substrate (chip) from peeling off when the substrate (chip, semiconductor substrate) is thinned and flattened, and is also expected to have the effect of preventing grinding silicon debris from remaining as contamination.

[0248] The above description of the manufacturing method of the solid-state imaging device of the seventh embodiment (example 1 of the manufacturing method of the solid-state imaging device) of the present technology can be applied to the solid-state imaging devices of the first to sixth embodiments of the present technology described above, unless there is any particular technical contradiction.

[0249] 9. Eighth Embodiment (Example of Electronic Device) An electronic device of an eighth embodiment of the present technology is an electronic device that is equipped with a solid-state imaging device of the first aspect of the present technology as a first aspect, and the solid-state imaging device of the first aspect of the present technology is a solid-state imaging device that includes a first substrate, a second substrate that is stacked on the first substrate by direct bonding on the opposite side of the first substrate from the light incident side and has a size different from the size of the first substrate, a third substrate that is provided on the opposite side of the second substrate from the light incident side, and an insulating layer formed between the first substrate and the third substrate, and the third substrate is in contact with the second substrate, and the third substrate is in contact with the insulating layer.

[0250] Furthermore, an electronic device of an eighth embodiment of the present technology is an electronic device equipped with a solid-state imaging device of the second aspect of the present technology as a second aspect, and the solid-state imaging device of the second aspect of the present technology is a solid-state imaging device comprising: a first substrate; a second substrate stacked on the first substrate by direct bonding on the opposite side of the first substrate from the light incident side and having a size different from that of the first substrate; a third substrate provided on the opposite side of the second substrate from the light incident side; an insulating layer formed between the first substrate and the third substrate; and at least one film formed between the first substrate and the third substrate and made of a material different from the material constituting the insulating layer, and the insulating layer and the at least one film are formed in order from the light incident side, with the at least one film in contact with the second substrate, the at least one film in contact with the insulating layer, and the at least one film in contact with the third substrate.

[0251] Furthermore, an electronic device of an eighth embodiment of the present technology is an electronic device equipped with a solid-state imaging device of the third aspect of the present technology as a third aspect, and the solid-state imaging device of the third aspect of the present technology is a solid-state imaging device comprising: a first substrate; a second substrate stacked on the first substrate by direct bonding on the opposite side of the first substrate from the light incident side, the second substrate having a size different from the size of the first substrate; a third substrate provided on the opposite side of the second substrate from the light incident side; and a cavity formed between the first substrate and the third substrate, wherein the third substrate is in contact with the second substrate and the third substrate is in contact with the cavity.

[0252] Furthermore, an electronic device of an eighth embodiment of the present technology is an electronic device equipped with a solid-state imaging device of the fourth aspect of the present technology as a fourth aspect, and the solid-state imaging device of the fourth aspect of the present technology is a solid-state imaging device comprising: a first substrate; a second substrate stacked on the first substrate by direct bonding on the opposite side of the first substrate from the light incident side, the second substrate having a size different from that of the first substrate; a third substrate provided on the opposite side of the second substrate from the light incident side; a cavity formed between the first substrate and the third substrate; and at least one film formed between the first substrate and the third substrate, in which, in order from the light incident side, the cavity and the at least one film are formed, and at least one film is in contact with the second substrate, at least one film is in contact with the cavity, and at least one film is in contact with the third substrate.

[0253] The electronic device according to the eighth embodiment of the present technology is, for example, an electronic device equipped with a solid-state imaging device according to any one of the first to eighth embodiments of the present technology.

[0254] 10. Examples of use of solid-state imaging devices that use this technology FIG. 42 is a diagram showing an example of using the solid-state imaging devices according to the first to sixth embodiments of the present technology as an image sensor.

[0255] The solid-state imaging devices according to the first to sixth embodiments described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, X-rays, etc., as described below. That is, as shown in Fig. 42, the solid-state imaging device according to any one of the first to sixth embodiments can be used in devices (for example, the electronic device according to the eighth embodiment described above) used in the fields of appreciation for capturing images for appreciation, transportation, home appliances, medicine and healthcare, security, beauty, sports, agriculture, etc.

[0256] Specifically, in the field of appreciation, the solid-state imaging device of any one of the first to sixth embodiments can be used in devices for capturing images for appreciation, such as digital cameras, smartphones, and mobile phones with camera functions.

[0257] In the field of transportation, for example, the solid-state imaging device of any one of the first to sixth embodiments can be used in devices used in transportation, such as on-board sensors that capture images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping, or for recognizing the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles, etc.

[0258] In the field of home appliances, for example, the solid-state imaging device according to any one of the first to sixth embodiments can be used in devices provided in home appliances such as television sets, refrigerators, and air conditioners to capture images of user gestures and operate the appliances in accordance with the gestures.

[0259] In the field of medicine and healthcare, the solid-state imaging device according to any one of the first to sixth embodiments can be used in devices used for medicine and healthcare, such as endoscopes and devices that take blood vessel images by receiving infrared light.

[0260] In the field of security, the solid-state imaging device according to any one of the first to sixth embodiments can be used in devices used for security purposes, such as surveillance cameras for crime prevention and cameras for person authentication.

[0261] In the field of beauty, the solid-state imaging device according to any one of the first to sixth embodiments can be used in devices used for beauty, such as a skin measuring device for photographing the skin or a microscope for photographing the scalp.

[0262] In the field of sports, the solid-state imaging device according to any one of the first to sixth embodiments can be used in devices used for sports, such as action cameras and wearable cameras for sports applications.

[0263] In the agricultural field, for example, the solid-state imaging device according to any one of the first to sixth embodiments can be used in devices used in agriculture, such as cameras for monitoring the conditions of fields and crops.

[0264] Next, specific examples of use of the solid-state imaging devices according to the first to sixth embodiments of the present technology will be described. For example, the solid-state imaging device according to any one of the first to sixth embodiments described above can be applied as a solid-state imaging device 101CM to any type of electronic device equipped with an imaging function, such as a camera system such as a digital still camera or a video camera, or a mobile phone with an imaging function. FIG. 43 shows a schematic configuration of an electronic device 102 (camera) CM as an example. The electronic device 102CM is, for example, a video camera capable of capturing still images or videos, and includes a solid-state imaging device 101CM, an optical system (optical lens) 310CM, a shutter device 311CM, a drive unit 313CM that drives the solid-state imaging device 101CM and the shutter device 311CM, and a signal processing unit 312CM.

[0265] The optical system 310CM guides image light (incident light) from the subject to the pixel unit of the solid-state imaging device 101CM. This optical system 310CM may be composed of multiple optical lenses. The shutter device 311CM controls the light irradiation period and light blocking period of the solid-state imaging device 101CM. The drive unit 313CM controls the transfer operation of the solid-state imaging device 101CM and the shutter operation of the shutter device 311CM. The signal processing unit 312CM performs various signal processing on the signal output from the solid-state imaging device 101CM. The video signal Dout after signal processing is stored in a storage medium such as a memory or output to a monitor, etc.

[0266] <11. Application example to endoscopic surgery system> The present technology can be applied to various products. For example, the technology according to the present disclosure (the present technology) may be applied to an endoscopic surgery system.

[0267] FIG. 44 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0268] Figure 44 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical instruments 11110 such as an insufflation tube 11111 and an energy treatment instrument 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0269] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0270] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens towards an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0271] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0272] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102, and performs various image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0273] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0274] The light source device 11203 is configured from a light source such as an LED (Light Emitting Diode), and supplies irradiation light to the endoscope 11100 when photographing an operation site or the like.

[0275] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiating light, magnification, focal length, etc.) of the endoscope 11100.

[0276] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0277] The light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical site can be configured from a white light source configured from, for example, an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, making it possible to adjust the white balance of the captured image in the light source device 11203. In this case, it is also possible to capture images corresponding to each RGB in a time-division manner by irradiating the object of observation with laser light from each RGB laser light source in a time-division manner and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0278] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free of so-called blocked-up shadows and blown-out highlights.

[0279] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may be performed using fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation can involve irradiating excitation light onto body tissues and observing the fluorescence from the tissues (autofluorescence observation), or locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0280] FIG. 45 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0281] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other by a transmission cable 11400 so that they can communicate with each other.

[0282] The lens unit 11401 is an optical system provided at the connection point with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0283] The imaging unit 11402 is configured with an imaging element. The imaging element constituting the imaging unit 11402 may be one (a so-called single-chip type) or multiple (a so-called multi-chip type). When the imaging unit 11402 is configured with a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured with a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. 3D display enables the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is configured with a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0284] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0285] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0286] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0287] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0288] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0289] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0290] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0291] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0292] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data sent from the camera head 11102 .

[0293] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0294] Furthermore, the control unit 11413 causes the display device 11202 to display a captured image showing the surgical site, etc., based on the image signal that has been image processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0295] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for communication of electrical signals, an optical fiber for optical communication, or a composite cable of these.

[0296] In the illustrated example, communication is performed by wire using the transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0297] The foregoing has described an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. Of the configurations described above, the technology according to the present disclosure can be applied to the endoscope 11100, the camera head 11102 (the imaging unit 11402), and the like. Specifically, the solid-state imaging device 111 according to the present disclosure can be applied to the imaging unit 10402. By applying the technology according to the present disclosure to the endoscope 11100, the camera head 11102 (the imaging unit 11402), and the like, it is possible to improve yield and reduce manufacturing costs.

[0298] Here, an endoscopic surgery system has been described as an example, but the technology according to the present disclosure may also be applied to other systems, such as a microsurgery system.

[0299] <12. Mobile Application Examples> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0300] FIG. 46 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0301] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 46, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-of-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0302] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, etc.

[0303] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0304] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc., based on the received images.

[0305] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0306] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0307] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drivetrain control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating collisions between vehicles, following based on the distance between vehicles, maintaining vehicle speed, warning of vehicle collisions, or warning of vehicle lane departure.

[0308] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0309] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0310] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to passengers in the vehicle or to the outside of the vehicle. In the example of Fig. 46, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0311] FIG. 47 is a diagram showing an example of the installation position of the imaging unit 12031.

[0312] In FIG. 47, a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0313] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0314] 47 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

[0315] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0316] For example, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on driver operation.

[0317] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drivetrain control unit 12010.

[0318] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. The pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104, which are infrared cameras, and then performing pattern matching on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0319] An example of a vehicle control system to which the technology according to the present disclosure (the present technology) can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031 among the configurations described above. Specifically, the solid-state imaging device 111 according to the present disclosure can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to improve yield and reduce manufacturing costs.

[0320] It should be noted that the present technology is not limited to the above-described embodiments and application examples, and various modifications are possible without departing from the spirit of the present technology.

[0321] Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0322] The present technology can also be configured as follows. [1] a first substrate; a second substrate that is laminated on the first substrate by direct bonding on the opposite side of the first substrate from the light incident side, and has a size different from that of the first substrate; a third substrate provided on the opposite side of the second substrate with respect to the light incident side; an insulating layer formed between the first substrate and the third substrate; The solid-state imaging device, wherein the third substrate has a well formed on a light incident side of the third substrate. [2] the third substrate is in contact with the second substrate, The solid-state imaging device according to [1], wherein the third substrate is in contact with the insulating layer. [3] The solid-state imaging device according to [1] or [2], wherein the well of the third substrate is formed so as to separate different potential regions of the second substrate. [4] A solid-state imaging device described in any one of [1] to [3], wherein the well of the third substrate is formed up to a region corresponding to the edge surface of the second substrate facing the insulating layer, and the edge surface of the well and the edge surface of the second substrate are approximately flush with each other. [5] A solid-state imaging device described in any one of [1] to [3], wherein the well of the third substrate is formed up to a region corresponding to the outside of the edge surface of the second substrate facing the insulating layer, the edge surface of the well and the edge surface of the second substrate are not flush with each other, and the edge surface of the well is located in a region corresponding to the insulating layer. [6] The solid-state imaging device according to any one of [1] to [5], wherein the second substrate has a well formed on the opposite side of the second substrate to the light incident side. [7] the third substrate is composed of a well formed on the light incident side of the third substrate and a substrate, The solid-state imaging device according to any one of [1] to [6], wherein at least one of at least a portion of the well and at least a portion of the substrate is electrically connected to the second substrate. [8] The solid-state imaging device according to any one of [1] to [7], wherein at least a partial area of ​​a surface of the third substrate that contacts the second substrate has a resistance of 1 Ωcm or more. [9] The solid-state imaging device according to any one of [1] to [8], wherein the surface of the second substrate that contacts the third substrate and the surface of the insulating layer that contacts the third substrate are substantially flush with each other.

[10] The solid-state imaging device according to any one of [1] to [9], wherein the insulating layer includes at least one of an inorganic oxide film and an organic film.

[11] a first substrate; a second substrate that is laminated on the first substrate by direct bonding on the opposite side of the first substrate from the light incident side, and has a size different from that of the first substrate; a third substrate provided on the opposite side of the second substrate with respect to the light incident side; an insulating layer formed between the first substrate and the third substrate; the third substrate is in contact with the second substrate; The third substrate is in contact with the insulating layer.

[12] The solid-state imaging device according to

[11] , wherein the third substrate has a well formed on the light incident side of the third substrate.

[13] The solid-state imaging device according to

[12] , wherein the well of the third substrate is formed so as to separate different potential regions of the second substrate.

[14] A solid-state imaging device according to

[12] or

[13] , wherein the well of the third substrate is formed up to a region corresponding to the end face of the second substrate facing the insulating layer, and the end face of the well and the end face of the second substrate are approximately flush with each other.

[15] A solid-state imaging device according to

[12] or

[13] , wherein the well of the third substrate is formed up to a region corresponding to the outside of the edge surface of the second substrate facing the insulating layer, the edge surface of the well and the edge surface of the second substrate are not flush with each other, and the edge surface of the well is located in a region corresponding to the insulating layer.

[16] The solid-state imaging device according to any one of

[12] to

[15] , wherein the second substrate has a well formed on the opposite side of the second substrate from the light incident side.

[17] the third substrate is composed of a well formed on the light incident side of the third substrate and a substrate, A solid-state imaging device according to any one of

[11] to

[16] , wherein at least one of at least a portion of the well and at least a portion of the substrate is electrically connected to the second substrate.

[18] The solid-state imaging device according to any one of

[11] to

[17] , wherein at least a partial region of a surface of the third substrate that contacts the second substrate has a resistance of 1 Ωcm or more.

[19] A solid-state imaging device according to any one of

[11] to

[18] , wherein the surface of the second substrate that contacts the third substrate and the surface of the insulating layer that contacts the third substrate are substantially flush with each other.

[20] The solid-state imaging device according to any one of

[11] to

[19] , wherein the insulating layer includes at least one of an inorganic oxide film and an organic film. [twenty one] a first substrate; a second substrate that is laminated on the first substrate by direct bonding on the opposite side of the first substrate from the light incident side, and has a size different from that of the first substrate; a third substrate provided on the opposite side of the second substrate with respect to the light incident side; an insulating layer formed between the first substrate and the third substrate; at least one film formed between the first substrate and the third substrate and made of a material different from a material constituting the insulating layer; the insulating layer and the at least one film are formed in this order from the light incident side, the at least one film contacting the second substrate; the at least one film contacts the insulating layer; The at least one film is in contact with the third substrate. [twenty two] The solid-state imaging device according to

[21] , wherein a surface of the second substrate in contact with the at least one film and a surface of the insulating layer in contact with the at least one film are substantially flush with each other. [twenty three] a surface of the second substrate in contact with the at least one film and a surface of the insulating layer in contact with the at least one film are not flush with each other; A solid-state imaging device according to

[21] , wherein the surface of the insulating layer that contacts the at least one film is located closer to the first substrate than the surface of the second substrate that contacts the at least one film. [twenty four] The solid-state imaging device according to any one of

[21] to

[23] , wherein the insulating layer includes at least one of an inorganic oxide film and an organic film. [twenty five] Further provided with a metal diffusion prevention film, the metal diffusion preventing film is formed so as to cover a surface of the insulating layer that is not in contact with the at least one film, The solid-state imaging device according to any one of

[21] to

[24] , wherein the metal diffusion prevention film is disposed between the second substrate and the insulating layer, and between the first substrate and the insulating layer.

[26] A solid-state imaging device according to any one of

[21] to

[25] , wherein the at least one film includes at least one selected from the group consisting of a heat dissipation member, a member having a film stress greater than that of Si, and a member having a linear expansion coefficient greater than that of Si.

[27] The solid-state imaging device according to

[26] , wherein the heat dissipation member contains at least one selected from the group consisting of SiC, AlN, SiN, Cu, Al, and C.

[28] The solid-state imaging device according to

[26] or

[27] , wherein the member having a film stress greater than the film stress of Si includes at least one selected from the group consisting of SiO2, SiN, Cu, Al and C.

[29] An electronic device equipped with the solid-state imaging device according to any one of [1] to

[28] .

[30] a first substrate; a second substrate that is laminated on the first substrate by direct bonding on the opposite side of the first substrate from the light incident side, and has a size different from that of the first substrate; a third substrate provided on the opposite side of the second substrate with respect to the light incident side; a cavity formed between the first substrate and the third substrate; the third substrate is in contact with the second substrate; The third substrate is in contact with the cavity.

[31] The solid-state imaging device according to

[30] , wherein the third substrate has a well formed on the light incident side of the third substrate.

[32] The solid-state imaging device according to

[31] , wherein the well of the third substrate is formed so as to separate different potential regions of the second substrate.

[33] A solid-state imaging device according to

[31] or

[32] , wherein the well of the third substrate is formed up to a region corresponding to the end face of the second substrate facing the cavity, and the end face of the well and the end face of the second substrate are approximately flush with each other.

[34] A solid-state imaging device according to

[31] or

[32] , wherein the well of the third substrate is formed up to an area corresponding to the outside of the edge surface of the second substrate facing the cavity, the edge surface of the well and the edge surface of the second substrate are not flush with each other, and the edge surface of the well is located in an area corresponding to the cavity.

[35] The solid-state imaging device according to any one of

[31] to

[34] , wherein the second substrate has a well formed on the opposite side of the second substrate from the light incident side.

[36] the third substrate is composed of a well formed on the light incident side of the third substrate and a substrate, A solid-state imaging device according to any one of

[30] to

[35] , wherein at least one of at least a portion of the well and at least a portion of the substrate is electrically connected to the second substrate.

[37] The solid-state imaging device according to any one of

[30] to

[36] , wherein at least a partial region of a surface of the third substrate that contacts the second substrate has a resistance of 1 Ωcm or more.

[38] A solid-state imaging device according to any one of

[30] to

[37] , wherein the surface of the second substrate that contacts the third substrate and the surface of the cavity that contacts the third substrate are substantially flush with each other.

[39] a first substrate; a second substrate that is laminated on the first substrate by direct bonding on the opposite side of the first substrate from the light incident side, and has a size different from that of the first substrate; a third substrate provided on the opposite side of the second substrate with respect to the light incident side; a cavity formed between the first substrate and the third substrate; at least one film formed between the first substrate and the third substrate; the cavity and the at least one film are formed in this order from the light incident side, the at least one film contacting the second substrate; the at least one membrane contacts the cavity; The at least one film is in contact with the third substrate.

[40] The solid-state imaging device according to

[39] , wherein a surface of the second substrate in contact with the at least one film and a surface of the cavity in contact with the at least one film are substantially flush with each other.

[41] a surface of the second substrate in contact with the at least one film and a surface of the cavity in contact with the at least one film are not flush with each other; A solid-state imaging device according to

[39] , wherein the surface of the cavity that contacts the at least one film is located closer to the first substrate than the surface of the second substrate that contacts the at least one film.

[42] Further provided with a metal diffusion prevention film, the metal diffusion prevention film is formed so as to cover a surface of the cavity that is not in contact with the at least one film, The solid-state imaging device according to any one of

[39] to

[41] , wherein the metal diffusion prevention film is disposed between the second substrate and the cavity, and between the first substrate and the cavity.

[43] A solid-state imaging device according to any one of

[39] to

[42] , wherein the at least one film includes at least one selected from the group consisting of a heat dissipation member, a member having a film stress greater than that of Si, and a member having a linear expansion coefficient greater than that of Si.

[44] The solid-state imaging device according to

[43] , wherein the heat dissipation member contains at least one selected from the group consisting of SiC, AlN, SiN, Cu, Al, and C.

[45] The solid-state imaging device according to

[43] or

[44] , wherein the member having a film stress greater than the film stress of Si includes at least one selected from the group consisting of SiO2, SiN, Cu, Al and C.

[46] An electronic device equipped with the solid-state imaging device according to any one of

[30] to

[45] .

[47] a first substrate; a second substrate that is laminated on the first substrate by direct bonding on the opposite side of the first substrate from the light incident side, and has a size different from that of the first substrate; a third substrate provided on the opposite side of the second substrate with respect to the light incident side; an insulating layer formed between the first substrate and the third substrate; the third substrate is in contact with the second substrate; the third substrate is in contact with the insulating layer, the first substrate formed by a semiconductor process; bonding the second substrate formed by the semiconductor process to the second substrate that has been determined to be a non-defective product by an electrical inspection; After the bonding, an insulating layer is formed on the first substrate and the second substrate from the second substrate side; After the film formation, thinning the second substrate and the insulating layer until the second substrate is exposed.

[48]

[47] A method for manufacturing a solid-state imaging device according to

[47] , wherein the surface of the second substrate obtained by the thinning process and the surface of the insulating layer obtained by the thinning process are approximately flush with each other.

[49] the surface of the second substrate obtained by the thinning process and the surface of the insulating layer obtained by the thinning process are not flush with each other, The method for manufacturing a solid-state imaging device according to

[47] , wherein a surface of the insulating layer is located closer to the first substrate than a surface of the second substrate. [Explanation of symbols]

[0323] 50, 50-U···insulation layer, 101-1, 102-1, 103-1, 104-1, 105-1, 106-1, 107-1, 108-1, 109-1, 110-1, 111-1, 112-1, 121-1, 122-1, 123-1, 124-1, 126-1, 127-1, 128-1, 129-1, 130-1, 131-1, 132-1, 133-1, 134-1, 135-1, 1001-1, 1002-1, 1003-1, 1004-1, 1005-1, 1250-1, 1360-1, 1370-1...first substrate, 101-2, 102-2, 103-2, 104-2, 105-2, 106-2, 107-2, 108-2, 109-2, 110-2, 111-2, 112-2, 121-2, 122-2, 123-2, 124-2, 126-2, 127-2, 128-2, 129-2, 130-2, 131-2, 132-2, 133-2, 134-2, 135-2, 1001-2, 1002-2, 1003-2, 1004-2, 1005-2, 1250-2, 1360-2, 1370-2... Second board, 101-3, 102-3, 103-3, 104-3, 105-3, 106-3, 107-3, 108-3, 109-3, 110-3, 111-3, 112-3, 121-3, 122-3, 123-3, 124-3, 126-3, 127-3, 128-3, 129-3, 130-3, 131-3, 132-3, 133-3, 134-3, 135-3, 1001-3, 1002-3, 1003-3, 1004-3, 1005-3, 1250-3, 1360-3, 1370-3...Third board, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113A, 113B, 113C, 11 4A, 114B, 114C, 115A, 115B, 116A, 116B, 116C, 117A, 117B, 117C, 118A, 118B, 118 C, 119A, 119B, 120A, 120B, 120C, 121, 122, 123, 124, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 1001, 1002, 1003, 1004, 1005, 1250, 1360, 1370···Solid-state imaging device.

Claims

1. a first substrate; a second substrate that is laminated on the first substrate by direct bonding on the side opposite to the light incident side of the first substrate and has a size different from that of the first substrate; a third substrate provided on the opposite side of the second substrate with respect to the light incident side; an insulating layer formed between the first substrate and the third substrate; the third substrate has a well formed on a light incident side of the third substrate; The well of the third substrate is formed so as to separate different potential regions of the second substrate.

2. the third substrate is in contact with the second substrate; The solid-state imaging device according to claim 1 , wherein the third substrate is in contact with the insulating layer.

3. 3. The solid-state imaging device of claim 1, wherein the well of the third substrate is formed up to a region corresponding to the end face of the second substrate facing the insulating layer, and the end face of the well and the end face of the second substrate are approximately flush with each other.

4. A solid-state imaging device as described in any one of claims 1 to 3, wherein the well of the third substrate is formed up to an area corresponding to the outside of the edge surface of the second substrate facing the insulating layer, the edge surface of the well and the edge surface of the second substrate are not flush with each other, and the edge surface of the well is located in an area corresponding to the insulating layer.

5. 5. The solid-state imaging device according to claim 1, wherein the second substrate has a well formed on a side opposite to a light incident side of the second substrate.

6. the third substrate is composed of a well formed on a light incident side of the third substrate and a substrate, 6. The solid-state imaging device according to claim 1, wherein at least one of at least a portion of the well and at least a portion of the substrate is electrically connected to the second substrate.

7. 7. The solid-state imaging device according to claim 1, wherein at least a partial area of ​​the surface of said third substrate that contacts said second substrate has a resistance of 1 Ωcm or more.

8. 8. The solid-state imaging device according to claim 1, wherein a surface of the second substrate in contact with the third substrate and a surface of the insulating layer in contact with the third substrate are substantially flush with each other.

9. 9. The solid-state imaging device according to claim 1, wherein the insulating layer includes at least one of an inorganic oxide film and an organic film.

10. 10. An electronic device equipped with the solid-state imaging device according to claim 1.

Images