Semiconductor Devices

Abstract

To provide a semiconductor device capable of suppressing element breakdown.SOLUTION: A semiconductor device comprises a first electrode, a second electrode, and a silicon carbide layer. The silicon carbide layer has: an n-type first layer electrically connected with the first electrode; an n-type second layer provided on the first layer, having an impurity concentration lower than that of the first layer; a super-junction structure part provided on the second layer; a p-type third layer provided on the super-junction structure part; and an n-type fourth layer provided on the third layer and electrically connected with the second electrode. The super-junction structure part has: a plurality of n-type pillars having an impurity concentration higher than that of the second layer; a plurality of p-type pillars having an impurity concentration higher than that of the second layer; and a boundary region located between the n-type pillars and the p-type pillars in a second direction, extending in a first direction continuously from the second layer and having an impurity concentration lower than those of the n-type pillars and the p-type pillars.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] A known power device is a vertical device with a periodic arrangement of p-type and n-type pillars, known as a superjunction structure. The superjunction structure maintains a high breakdown voltage by depleting the drift region through the p-type and n-type pillars by making the amount of impurities contained in them approximately equal, while achieving low on-resistance by passing current through the n-type pillars. Development of power devices using silicon carbide (SiC) is also underway. SiC devices require a development approach that is different from that of silicon devices. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-192541 [Patent Document 2] Japanese Patent Application Laid-Open No. 2009-4805 Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiment provides a semiconductor device that can suppress element breakdown. [Means for solving the problem]

[0005] According to an embodiment, a semiconductor device includes a first electrode, a second electrode, and a silicon carbide layer provided between the first electrode and the second electrode in a first direction, the silicon carbide layer having an n-type first layer electrically connected to the first electrode, an n-type second layer provided on the first layer and having a lower impurity concentration than the first layer, a super junction structure provided on the second layer, a p-type third layer provided on the super junction structure, and an n-type fourth layer provided on the third layer and electrically connected to the second electrode, the super junction structure having a plurality of n-type pillars having a higher impurity concentration than the second layer, a plurality of p-type pillars having a higher impurity concentration than the second layer, and a boundary region located between the n-type pillars and the p-type pillars in a second direction perpendicular to the first direction, extending continuously from the second layer in the first direction, and having a lower impurity concentration than the n-type pillars and the p-type pillars. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] 3 is a schematic diagram showing an impurity concentration profile of a super junction structure according to an embodiment; FIG. [Figure 3] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 4] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a third embodiment. [Figure 5] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 6] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment. [Figure 7] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings, in which the same components are denoted by the same reference numerals.

[0008] [First embodiment] 1, the semiconductor device 1 of the first embodiment includes a first electrode 51, a second electrode 52, and a silicon carbide (SiC) layer 10. For example, the first electrode 51 functions as a drain electrode, and the second electrode 52 functions as a source electrode.

[0009] The direction from the first electrode 51 toward the second electrode 52 is defined as a first direction d1. The silicon carbide layer 10 is provided between the first electrode 51 and the second electrode 52 in the first direction d1. In the first direction d1, the direction of the arrow is defined as relatively upward, and the direction opposite to the arrow is defined as relatively downward.

[0010] Silicon carbide layer 10 has first n-type layer 11, second n-type layer 12, super junction structure 30, third p-type layer 13, and fourth n-type layer .

[0011] The first layer 11 is a SiC substrate. The n-type impurity concentration of the first layer 11 is, for example, 1×10 20 / cm 3 A first electrode 51 is provided on the lower surface of the first layer 11, and the first layer 11 is electrically connected to the first electrode 51.

[0012] The second layer 12 is provided on the first layer 11. The second layer 12 is epitaxially grown on the first layer (SiC substrate) 11. Alternatively, the second layer 12 may be provided on the first layer 11 via an n-type fifth layer 15. The fifth layer 15 functions as a buffer layer for epitaxial growth.

[0013] The n-type impurity concentration of the second layer 12 is lower than the n-type impurity concentration of the first layer 11. The n-type impurity concentration of the second layer 12 is, for example, 1×10 17 / cm 3 The n-type impurity concentration of the fifth layer 15 is lower than the n-type impurity concentration of the first layer 11 and higher than the n-type impurity concentration of the second layer 12. The n-type impurity concentration of the fifth layer 15 is, for example, 1×10 18 / cm 3 is.

[0014] A super junction structure 30 is provided on the second layer 12. The super junction structure 30 has a plurality of n-type pillars 31n and a plurality of p-type pillars 31p. The n-type pillars 31n and the p-type pillars 31p are alternately arranged in a second direction d2 perpendicular to the first direction d1. The bottom ends of the n-type pillars 31n and the p-type pillars 31p are in contact with the second layer 12. The planar shapes of the n-type pillars 31n and the p-type pillars 31p are formed, for example, in stripes extending in a direction perpendicular to the first direction d1 and the second direction d2 (a direction penetrating the paper).

[0015] The n-type impurity concentration of the n-type pillar 31n is higher than the n-type impurity concentration of the second layer 12. The n-type impurity concentration of the n-type pillar 31n is, for example, 5×10 17 / cm 3 The p-type impurity concentration of the p-type pillar 31p is higher than the n-type impurity concentration of the second layer 12. The p-type impurity concentration of the p-type pillar 31p is, for example, 5×10 17 / cm 3 is.

[0016] The n-type impurity concentration of the n-type pillar 31n is approximately the same as the p-type impurity concentration of the p-type pillar 31p. Furthermore, the width of the n-type pillar 31n in the second direction d2 is approximately the same as the width of the p-type pillar 31p in the second direction d2. Therefore, the amount of n-type impurity in the n-type pillar 31n is approximately the same as the amount of p-type impurity in the p-type pillar 31p.

[0017] The super junction structure 30 further has a plurality of boundary regions 32. The boundary regions 32 are located between the n-type pillar 31n and the p-type pillar 31p that are adjacent to each other in the second direction d2, and extend continuously from the second layer 12 in the first direction d1. The planar shape of the boundary regions 32, like the n-type pillar 31n and the p-type pillar 31p, is formed, for example, in a stripe shape that extends in a direction perpendicular to the first direction d1 and the second direction d2 (the direction penetrating the paper).

[0018] The boundary region 32 is, for example, an n-type region having a concentration similar to that of the second layer 12. The n-type impurity concentration of the boundary region 32 is lower than the n-type impurity concentration of the n-type pillar 31n and the p-type impurity concentration of the p-type pillar 31p. The n-type impurity concentration of the boundary region 32 is, for example, 1×10 17 / cm 3 is.

[0019] As shown in FIG. 2, between the n-type pillar 31n and the p-type pillar 31p, there is a boundary region 32 where the n-type impurity concentration is lower than the n-type impurity concentration of the n-type pillar 31n and the p-type impurity concentration of the p-type pillar 31p and where the impurity concentration is approximately constant in the width direction (second direction d2).

[0020] A plurality of third layers 13 are provided on the super junction structure 30. The third layers 13 function as, for example, p-type base layers. The upper ends of the p-type pillars 31p and the upper ends of the boundary regions 32 contact the third layers 13.

[0021] An n-type seventh layer 17 is provided on the n-type pillar 31n. The seventh layer 17 is in contact with the n-type pillar 31n and is located between adjacent third layers 13 in the second direction d2.

[0022] A fourth layer 14 is provided on the third layer 13. The fourth layer 14 functions as, for example, an n-type source layer. The n-type impurity concentration of the fourth layer 14 is higher than the n-type impurity concentration of the n-type pillar 31n. The fourth layer 14 contacts the second electrode 52 and is electrically connected to the second electrode 52.

[0023] A p-type sixth layer 16 is provided on the third layer 13. The p-type impurity concentration of the sixth layer 16 is higher than the p-type impurity concentration of the third layer 13 and the p-type impurity concentration of the p-type pillar 31p. The sixth layer 16 is in contact with the second electrode 52. The potential of the second electrode 52 is applied to the third layer 13 and the p-type pillar 31p via the sixth layer 16.

[0024] The semiconductor device 1 further includes a gate electrode 53 provided on the silicon carbide layer 10. An insulating film 41 is provided between the gate electrode 53 and the silicon carbide layer 10 and between the gate electrode 53 and the second electrode 52. The gate electrode 53 may be made of, for example, polycrystalline silicon. The insulating film 41 is, for example, a silicon oxide film. A region (channel region) 13a between the fourth layer 14 and the seventh layer 17 in the third layer 13 faces the gate electrode 53 via the insulating film 41.

[0025] When the semiconductor device 1 is in an on-state, a potential equal to or higher than the threshold is applied to the gate electrode 53, and an inversion layer (n-type channel) is formed in the channel region 13a. Then, an electron current flows between the second electrode 52 and the first electrode 51 through the fourth layer 14, the channel region 13a, the seventh layer 17, the n-type pillar 31n, the second layer 12, the fifth layer 15, and the first layer 11.

[0026] When the potential of gate electrode 53 becomes lower than the threshold, the n-type channel in channel region 13a is cut off, turning off semiconductor device 1. In this off state, a depletion layer spreads laterally (in second direction d2) from boundary region 32 between n-type pillar 31n and p-type pillar 31p in super junction structure 30, and the breakdown voltage of semiconductor device 1 is maintained.

[0027] Furthermore, since the second layer 12, which has a lower n-type impurity concentration than the first layer 11, is provided between the first layer 11 and the super junction structure 30, in the off state, a depletion layer tends to spread from the boundary between the bottom end of the p-type pillar 31p and the second layer 12. This also increases the breakdown voltage of the semiconductor device 1.

[0028] In SiC crystals, defects 100 that cross the boundary between n-type pillars and p-type pillars are more likely to occur than in Si crystals. The boundary between n-type pillars and p-type pillars is a portion where the impurity concentration profile can become steep, and if defects 100 cross this boundary, a strong electric field is likely to be applied to the boundary defect as the depletion layer expands, which can cause breakdown.

[0029] According to this embodiment, by providing a boundary region 32 between the n-type pillar 31n and the p-type pillar 31p, in which the impurity concentration is lower than the n-type impurity concentration of the n-type pillar 31n and the p-type impurity concentration of the p-type pillar 31p and is approximately constant in the width direction (second direction d2), even if there is a defect 100 that crosses the super junction structure 30, the electric field applied to the defect in the boundary region 32 can be alleviated, and the reliability of the semiconductor device 1 against high voltages can be improved.

[0030] The super junction structure 30 can be formed by repeating ion implantation multiple times in the first direction d1. After epitaxially growing the second layer 12 on the first layer (SiC substrate) 11, p-type impurities are implanted into regions on the surface of the second layer 12 where the p-type pillars 31p are to be formed. Examples of p-type impurities that can be used include Al, B, and Ga. Then, n-type impurities are implanted into regions on the surface of the second layer 12 where the n-type pillars 31n are to be formed. Examples of n-type impurities that can be used include N and P. Note that p-type impurities may be implanted after the n-type impurities are implanted.

[0031] After the first impurity implantation, a layer (e.g., an n-type layer with an n-type impurity concentration similar to that of the second layer 12) is epitaxially grown on the impurity-implanted region, a portion of which will become the boundary region 32. A second impurity implantation is performed on this epitaxially grown layer, similar to the first implantation. Thereafter, the process of epitaxially growing a layer on the impurity-implanted region, a portion of which will become the boundary region 32, and the process of implanting impurities into the epitaxially grown layer are repeated a predetermined number of times. Thereafter, a heat treatment is performed at a temperature of, for example, about 1900°C to diffuse the implanted impurities, thereby forming n-type pillars 31n and p-type pillars 31p.

[0032] Impurities in SiC are less susceptible to thermal diffusion than impurities in Si, and a boundary region 32, which is part of the epitaxially grown layer, is maintained between the n-type pillar 31n and the p-type pillar 31p. The boundary region 32 extends continuously from the second layer 12 in the first direction.

[0033] 1 , the left side surface of a p-pillar 31p contacts the right side surface of the adjacent n-pillar 31n on the left, the distance between the right side surface of the p-pillar 31p and the adjacent n-pillar 31n on the right will be increased by the amount that the p-pillar 31p is shifted to the left.

[0034] That is, neither side surface of the p-pillar 31p in the second direction d2 comes into contact with the n-pillar 31n, and at least one of the two side surfaces of the p-pillar 31p in the second direction d2 does not have a portion in contact with the n-pillar 31n. Similarly, neither side surface of the n-pillar 31n in the second direction d2 comes into contact with the p-pillar 31p, and at least one of the two side surfaces of the n-pillar 31n in the second direction d2 does not have a portion in contact with the p-pillar 31p. Even if there are portions where the n-pillar 31n and the p-pillar 31p come into contact, the number of such portions is small and not concentrated in a specific location.

[0035] Other embodiments will be described below. In these other embodiments, the configuration of super junction structure 30 is the same as in the first embodiment, and the same effects can be obtained.

[0036] [Second embodiment] As shown in FIG. 3, the semiconductor device 2 of the second embodiment has a gate electrode 53 with a trench gate structure.

[0037] An eighth p-type layer 18 is provided on the p-pillar 31p. An seventh n-type layer 17 is provided on the n-pillar 31n and the eighth layer 18. The upper end of the p-pillar 31p is in contact with the eighth layer 18. The upper end of the n-pillar 31n is in contact with the seventh layer 17. A third layer 13 is provided on the seventh layer 17.

[0038] The gate electrode 53 is provided in a trench that penetrates the fourth layer 14, the third layer 13, and the seventh layer 17 and reaches the eighth layer 18, via an insulating film 41. An insulating film 42 is provided between the gate electrode 53 and the second electrode 52.

[0039] During on-operation, an inversion layer (n-type channel) is formed in the channel region 13a in the third layer 13, which faces the gate electrode 53 via the insulating film 41. An electron current flows between the fourth layer 14 and the n-type pillar 31n via the channel region 13a and the seventh layer 17.

[0040] [Third embodiment] As shown in FIG. 4, in the semiconductor device 3 of the third embodiment, the upper ends of the n-type pillars 31n, the p-type pillars 31p, and the boundary region 32 are in contact with the third layer 13 provided in the super junction structure 30.

[0041] The gate electrode 53 is provided above the p-type pillar 31p, via an insulating film 41, in a trench that penetrates the fourth layer 14 and reaches partway through the third layer 13. During on-operation, an inversion layer (n-type channel) is formed in the channel region 13a in the third layer 13 that faces the gate electrode 53 via the insulating film 41, and an electron current flows between the fourth layer 14 and the n-type pillar 31p via the channel region 13a.

[0042] [Fourth embodiment] As shown in FIG. 5, in the semiconductor device 4 of the fourth embodiment, the upper ends of the n-type pillars 31n, the p-type pillars 31p, and the boundary region 32 are in contact with the third layer 13 provided in the super junction structure 30.

[0043] The gate electrode 53 is provided in a trench that penetrates the fourth layer 14 and the third layer 13 to reach the n-type pillar 31n, via an insulating film 41. During on-operation, an inversion layer (n-type channel) is formed in the channel region 13a in the third layer 13 that faces the gate electrode 53 via the insulating film 41, and an electron current flows between the fourth layer 14 and the n-type pillar 31n via the channel region 13a.

[0044] [Fifth embodiment] As shown in FIG. 6 , in the semiconductor device 5 of the fifth embodiment, a p-type ninth layer 19 is provided on an n-type pillar 31n. Furthermore, an n-type eleventh layer 22 is provided on the n-type pillar 31n so as to cover the ninth layer 19. The upper end of the n-type pillar 31n is in contact with the ninth layer 19 and the eleventh layer 22. A p-type tenth layer 21 is provided on a p-type pillar 31p. The upper end of the p-type pillar 31p is in contact with the tenth layer 21. A third layer 13 is provided on the tenth layer 21 and the eleventh layer 22.

[0045] The gate electrode 53 is provided in a trench that penetrates the fourth layer 14, the third layer 13, and the eleventh layer 22 to reach the ninth layer 19, via an insulating film 41. During on-operation, an inversion layer (n-type channel) is formed in the channel region 13a in the third layer 13 that faces the gate electrode 53 via the insulating film 41, and an electron current flows between the fourth layer 14 and the n-type pillar 31n via the channel region 13a and the eleventh layer 22.

[0046] [Sixth embodiment] As shown in FIG. 7, in the semiconductor device 6 of the sixth embodiment, an n-type seventh layer 17, a p-type eighth layer 18, and a p-type tenth layer 21 are provided between the super junction structure 30 and the third layer 13.

[0047] For example, p-type pillars 31p having a tenth layer 21 provided thereon and p-type pillars 31p having an eighth layer 18 provided thereon are arranged alternately in the second direction d2. The tenth layer 21 contacts the upper ends of the p-type pillars 31p and the lower surface of the third layer 13. The seventh layer 17 is provided on the n-type pillars 31n and further covers the eighth layer 18.

[0048] The gate electrode 53 is provided in a trench that penetrates the fourth layer 14, the third layer 13, and the seventh layer 17 on the eighth layer 18, and reaches the eighth layer 18, via an insulating film 41. During on-operation, an inversion layer (n-type channel) is formed in the channel region 13a in the third layer 13 that faces the gate electrode 53 via the insulating film 41, and an electron current flows between the fourth layer 14 and the n-type pillar 31n via the channel region 13a and the seventh layer 17.

[0049] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0050] 1 to 6... semiconductor device, 10... silicon carbide layer, 11... first layer, 12... second layer, 13... third layer, 14... fourth layer, 15... fifth layer, 30... super junction structure, 31n... n-type pillar, 31p... p-type pillar, 32... boundary region, 51... first electrode, 52... second electrode, 53... gate electrode

Claims

1. A first electrode; A second electrode; a silicon carbide layer provided between the first electrode and the second electrode in a first direction; Equipped with The silicon carbide layer is an n-type first layer electrically connected to the first electrode; an n-type second layer provided on the first layer and having a lower impurity concentration than the first layer; a super junction structure provided on the second layer; a p-type third layer provided on the super junction structure; an n-type fourth layer provided on the third layer and electrically connected to the second electrode; and the super junction structure includes a plurality of n-type pillars having an impurity concentration higher than that of the second layer, a plurality of p-type pillars having an impurity concentration higher than that of the second layer, and a boundary region located between the n-type pillars and the p-type pillars in a second direction perpendicular to the first direction, extending continuously from the second layer in the first direction, and having an impurity concentration lower than that of the n-type pillars and the p-type pillars; The n-type pillars and the p-type pillars are arranged alternately in the second direction.

2. 2. The semiconductor device according to claim 1, wherein the boundary region is n-type.

3. 3. The semiconductor device according to claim 1, wherein an upper end of the boundary region is in contact with the third layer.

4. 4. The semiconductor device according to claim 1, wherein at least one of both side surfaces of the n-type pillar in the second direction does not have a portion in contact with the p-type pillar.

5. 5. The semiconductor device according to claim 1, wherein at least one of both side surfaces of the p-type pillar in the second direction does not have a portion in contact with the n-type pillar.

6. 6. The semiconductor device according to claim 1, wherein the silicon carbide layer further comprises an n-type fifth layer provided between the first layer and the second layer and having an impurity concentration lower than that of the first layer and higher than that of the second layer.

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