Semiconductor Devices

Abstract

To provide a semiconductor device that increases a short-circuit resistance amount.SOLUTION: A MOSFET 100 comprises: gate electrodes 16a, 16b in a trench extending in a first direction on a side of a first surface of a silicon carbide layer 10; a first silicon carbide region 26a of a first conductivity type, a second silicon carbide region of a second conductivity type, and third and fourth silicon carbide regions of the first conductivity type, which are arranged in order in the first direction in the silicon carbide layer; a fifth silicon carbide region 30a of the first conductivity type, sixth and eighth silicon carbide regions of the second conductivity type, and a seventh silicon carbide region of the first conductivity type, which are provided between the first to fourth silicon carbide regions F1 and the first surface, are arranged in order in the first direction, and have a higher impurity concentration than the first to fourth silicon carbide regions; a ninth silicon carbide region 34 of the first conductivity type provided between the fifth to eighth silicon carbide regions and the first surface; a tenth silicon carbide region 36a of the second conductivity type between the ninth silicon carbide region and the first surface; and an eleventh silicon carbide region of the first conductivity type between the ninth silicon carbide region and the first surface.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Silicon carbide (SiC) is expected to be a promising material for semiconductor devices. Compared to silicon, silicon carbide has excellent physical properties, such as a band gap approximately three times larger, a breakdown field strength approximately ten times larger, and a thermal conductivity approximately three times larger. Utilizing these properties, for example, can realize a metal oxide semiconductor field effect transistor (MOSFET) that can withstand high voltages, have low loss, and operate at high temperatures.

[0003] In vertical MOSFETs, a trench gate structure in which a gate electrode is provided inside a trench is used to achieve low on-resistance. By using the trench gate structure, the channel area per unit area increases, reducing on-resistance.

[0004] When a short circuit occurs in a load driven by a MOSFET, a large current flows through the MOSFET, causing it to be destroyed. The time it takes for a MOSFET to be destroyed is called its short-circuit withstand capability. From the perspective of improving the reliability of MOSFETs, it is desirable to improve the short-circuit withstand capability. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-194065 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a semiconductor device capable of improving short-circuit resistance. [Means for solving the problem]

[0007] A semiconductor device according to an embodiment includes a silicon carbide layer having a first surface parallel to a first direction and a second direction orthogonal to the first direction, and a second surface opposite to the first surface; a first trench provided in the silicon carbide layer on a side of the first surface and extending in the first direction; a second trench provided in the silicon carbide layer on a side of the first surface and extending in the second direction relative to the first trench; a first gate electrode provided in the first trench; a second gate electrode provided in the second trench; a first gate insulating layer provided between the second gate electrode and the silicon carbide layer; a second gate insulating layer provided between the second gate electrode and the silicon carbide layer; a first silicon carbide region of a first conductivity type provided in the silicon carbide layer and extending in the second direction; a second silicon carbide region of a second conductivity type provided in the silicon carbide layer and extending in the second direction and positioned in the first direction relative to the first silicon carbide region; and a third silicon carbide region of the first conductivity type provided in the silicon carbide layer and extending in the second direction and positioned in the first direction relative to the second silicon carbide region. a fourth silicon carbide region of a second conductivity type provided in the silicon carbide layer, extending in the second direction, and positioned in the first direction relative to the third silicon carbide region; and a fifth silicon carbide region of a first conductivity type provided in the silicon carbide layer, extending in the second direction, and positioned between the first silicon carbide region and the first surface, and positioned in a third direction perpendicular to the first surface relative to the first silicon carbide region, and positioned between the first trench, the second trench, and the second surface, and having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the first silicon carbide region. a sixth silicon carbide region of a second conductivity type that is provided in the silicon carbide layer, extends in the second direction, is located between the second silicon carbide region and the first surface, is located in the third direction relative to the second silicon carbide region, is located between the first trench and the second trench and the second surface, and has a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the second silicon carbide region; and a sixth silicon carbide region of a second conductivity type that is provided in the silicon carbide layer, extends in the second direction, is located between the third silicon carbide region and the first surface, and is located in the third direction relative to the third silicon carbide region;a seventh silicon carbide region of a first conductivity type, which is located between the first trench and the second trench and the second surface, and has a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the third silicon carbide region; an eighth silicon carbide region of a second conductivity type, which is provided in the silicon carbide layer, extends in the second direction, is located between the fourth silicon carbide region and the first surface, is located in the third direction relative to the fourth silicon carbide region, is located between the first trench and the second trench and the second surface, and has a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the fourth silicon carbide region; and an eighth silicon carbide region of a second conductivity type, which is provided in the silicon carbide layer, and has an interlayer insulating film between the fifth silicon carbide region and the first surface, between the sixth silicon carbide region and the first surface, between the seventh silicon carbide region and the first surface, and between the eighth silicon carbide region and the first surface. a ninth silicon carbide region of a first conductivity type located between the first surface and the first trench and between the first trench and the second trench; a tenth silicon carbide region of a second conductivity type provided in the silicon carbide layer and located between the ninth silicon carbide region and the first surface and between the first trench and the second trench; an eleventh silicon carbide region of the first conductivity type provided in the silicon carbide layer and located between the ninth silicon carbide region and the first surface and between the first trench and the second trench, the eleventh silicon carbide region having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the ninth silicon carbide region; a first electrode provided on the first surface side of the silicon carbide layer and in contact with the tenth silicon carbide region and the eleventh silicon carbide region; and a second electrode provided on the second surface side of the silicon carbide layer. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment. [Figure 3] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 4] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 5]1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 6] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 7] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 8] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 9] 5A to 5C are explanatory diagrams illustrating the operation and effect of the semiconductor device according to the first embodiment. [Figure 10] 5A to 5C are explanatory diagrams illustrating the operation and effect of the semiconductor device according to the first embodiment. [Figure 11] 5A to 5C are explanatory diagrams illustrating the operation and effect of the semiconductor device according to the first embodiment. [Figure 12] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 13] FIG. 10 is a schematic plan view of a semiconductor device according to a third embodiment. [Figure 14] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 15] FIG. 10 is a schematic plan view of a semiconductor device according to a fourth embodiment. [Figure 16] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 17] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 18] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 19] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 20] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 21] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 22] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment. [Figure 23] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components will be designated by the same reference numerals, and the description of components that have already been described will be omitted as appropriate.

[0010] In the following description, n + , n, n - and p + , p, p - When the notation is used, these notations represent the relative level of impurity concentration in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + type, n - The type is simply n-type, p + type, p - The type is sometimes simply referred to as p-type.

[0011] The impurity concentration can be measured by, for example, Secondary Ion Mass Spectrometry (SIMS). The relative level of the impurity concentration can also be determined from the level of the carrier concentration determined by, for example, Scanning Capacitance Microscopy (SCM). The distance, such as the depth, of the impurity region can be determined by, for example, SIMS. The distance, such as the width and depth of the impurity region, can be determined from, for example, an SCM image.

[0012] The shape of the trench, the thickness of the insulating layer, etc. can be measured on an image taken with a Transmission Electron Microscope (TEM), for example.

[0013] In this specification, the "p-type impurity concentration" of a p-type silicon carbide region means the net p-type impurity concentration obtained by subtracting the n-type impurity concentration of that region from the p-type impurity concentration of that region. Also, the "n-type impurity concentration" of an n-type silicon carbide region means the net n-type impurity concentration obtained by subtracting the p-type impurity concentration of that region from the n-type impurity concentration of that region.

[0014] In addition, in this specification, the impurity concentration of a specific region is represented by the impurity concentration at the center of the region unless otherwise defined.

[0015] (First embodiment) The semiconductor device of the first embodiment includes a silicon carbide layer having a first surface parallel to a first direction and a second direction orthogonal to the first direction, and a second surface opposite to the first surface; a first trench provided in the silicon carbide layer on the side of the first surface and extending in the first direction; a second trench provided in the silicon carbide layer on the side of the first surface and extending in a second direction relative to the first trench, also extending in the first direction; a first gate electrode provided in the first trench; a second gate electrode provided in the second trench; and a first gate electrode provided between the first gate electrode and the silicon carbide layer. a gate insulating layer, a second gate insulating layer provided between the second gate electrode and the silicon carbide layer; a first silicon carbide region of a first conductivity type provided in the silicon carbide layer and extending in a second direction; a second silicon carbide region of a second conductivity type provided in the silicon carbide layer and extending in the second direction and positioned in a first direction relative to the first silicon carbide region; a third silicon carbide region of the first conductivity type provided in the silicon carbide layer and extending in the second direction and positioned in the first direction relative to the second silicon carbide region; a fourth silicon carbide region of a first conductivity type; a fifth silicon carbide region of a first conductivity type provided in the silicon carbide layer, extending in the second direction, located between the first silicon carbide region and the first surface, located in a third direction perpendicular to the first surface with respect to the first silicon carbide region, located between the first trench and the second trench, and the second surface, and having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the first silicon carbide region; and a fifth silicon carbide region of a first conductivity type provided in the silicon carbide layer, extending in the second direction, located between the second silicon carbide region and the first surface, and located in the third direction with respect to the second silicon carbide region, a sixth silicon carbide region of the second conductivity type located between the second trench and the second surface and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the second silicon carbide region; a seventh silicon carbide region of the first conductivity type located in the silicon carbide layer and extending in the second direction, located between the third silicon carbide region and the first surface and located in the third direction relative to the third silicon carbide region, located between the first trench, the second trench and the second surface and having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the third silicon carbide region; and a seventh silicon carbide region of the first conductivity type located in the silicon carbide layer and extending in the second direction,an eighth silicon carbide region of a second conductivity type located between the fourth silicon carbide region and the first surface, located in a third direction relative to the fourth silicon carbide region, located between the first trench and the second trench and the second surface, and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the fourth silicon carbide region; a ninth silicon carbide region of the first conductivity type provided in the silicon carbide layer and located between the fifth silicon carbide region and the first surface, between the sixth silicon carbide region and the first surface, between the seventh silicon carbide region and the first surface, between the eighth silicon carbide region and the first surface, and between the first trench and the second trench; the silicon carbide layer includes: a tenth silicon carbide region of the second conductivity type located between the ninth silicon carbide region and the first surface and between the first trench and the second trench; an eleventh silicon carbide region of the first conductivity type provided in the silicon carbide layer, located between the ninth silicon carbide region and the first surface, located between the first trench and the second trench, and having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the ninth silicon carbide region; a first electrode provided on the first surface side of the silicon carbide layer and in contact with the tenth silicon carbide region and the eleventh silicon carbide region; and a second electrode provided on the second surface side of the silicon carbide layer.

[0016] The following description will be given taking as an example a case where the first conductivity type is p-type and the second conductivity type is n-type.

[0017] 1 is a schematic cross-sectional view of a semiconductor device according to the first embodiment, taken along the line AA' in FIG.

[0018] 2 is a schematic plan view of the semiconductor device of the first embodiment, taken along the first plane (F1 in FIG. 1) of FIG.

[0019] 3 is a schematic cross-sectional view of the semiconductor device of the first embodiment, taken along the line BB' in FIG.

[0020] 4 is a schematic cross-sectional view of the semiconductor device of the first embodiment, taken along line CC' in FIG.

[0021] 5 is a schematic cross-sectional view of the semiconductor device of the first embodiment, taken along the line DD' in FIG.

[0022] 6 is a schematic cross-sectional view of the semiconductor device of the first embodiment, taken along the line EE' of FIG.

[0023] 7 is a schematic cross-sectional view of the semiconductor device of the first embodiment, taken along line Fx in FIG.

[0024] 8 is a schematic cross-sectional view of the semiconductor device of the first embodiment, taken along line Fy in FIG.

[0025] The semiconductor device of the first embodiment is a trench-gate vertical MOSFET 100 using silicon carbide. The MOSFET 100 is an n-channel MOSFET that uses electrons as carriers.

[0026] The MOSFET 100 has a superjunction structure (hereinafter also referred to as "SJ structure"). The SJ structure is a structure in which p-type semiconductor regions and n-type semiconductor regions are arranged alternately. A high breakdown voltage is achieved by depleting the p-type and n-type semiconductor regions. At the same time, a low on-resistance can be achieved by passing a current through a highly doped region.

[0027] The MOSFET 100 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a first gate electrode 16a, a second gate electrode 16b, a first gate insulating layer 18a, a second gate insulating layer 18b, an interlayer insulating layer 20, a first trench 22a, and a second trench 22b.

[0028] In the silicon carbide layer 10, n + a drain region 24, an n-type buffer region 25, and a p - First p-pillar region 26a (first silicon carbide region) of type p - a second p-pillar region 26b (third silicon carbide region) of the n type; - First n-pillar region 28a (second silicon carbide region) of the n type- a second n-pillar region 28b (fourth silicon carbide region) of the n type; - a third n-pillar region 28c of the n-type, a first p-type control region 30a (fifth silicon carbide region), a second p-type control region 30b (seventh silicon carbide region), a first n-type control region 32a (sixth silicon carbide region), a second n-type control region 32b (eighth silicon carbide region), a third n-type control region 32c of the n-type, a p-type body region 34 (ninth silicon carbide region), an n-type source region 35 (fourteenth silicon carbide region), and + a first n-type contact region 36a (tenth silicon carbide region), + a second n-contact region 36b (twelfth silicon carbide region) of type p + a first p-type contact region 38a (eleventh silicon carbide region), + a second p-type contact region 38b (a thirteenth silicon carbide region), + A third p-contact region 38c of the same type is provided.

[0029] Hereinafter, the first gate electrode 16a and the second gate electrode 16b may be collectively referred to as the gate electrode 16. Furthermore, the first gate insulating layer 18a and the second gate insulating layer 18b may be collectively referred to as the gate insulating layer 18. Furthermore, the first trench 22a and the second trench 22b may be collectively referred to as the trench 22.

[0030] Hereinafter, the first p-pillar region 26a and the second p-pillar region 26b may be collectively referred to as p-pillar regions 26. The first n-pillar region 28a, the second n-pillar region 28b, and the third n-pillar region 28c may be collectively referred to as n-pillar regions 28. The first p-control region 30a and the second p-control region 30b may be collectively referred to as p-control regions 30. The first n-control region 32a, the second n-control region 32b, and the third n-control region 32c may be collectively referred to as n-control regions 32. The first n-contact region 36a and the second n-contact region 36b may be collectively referred to as n-contact regions 36. Furthermore, the first p contact region 38a, the second p contact region 38b, and the third p contact region 38c may be collectively referred to as the p contact region 38.

[0031] The silicon carbide layer 10 is made of single-crystal SiC, for example, 4H—SiC.

[0032] Silicon carbide layer 10 has a first surface ("F1" in FIG. 1) and a second surface ("F2" in FIG. 1) opposite to the first surface. Hereinafter, first surface F1 will also be referred to as the front surface, and second surface F2 will also be referred to as the back surface. Note that, hereinafter, "depth" refers to the depth based on first surface F1.

[0033] 1, 2, 3, 4, 5, 6, 7, and 8, the first direction and the second direction are parallel to the first face F1 and the second face F2. The third direction is perpendicular to the first face F1 and the second face F2. The second direction is perpendicular to the first direction.

[0034] The first plane F1 is, for example, a plane inclined at an angle of 0 to 8 degrees with respect to the (0001) plane. That is, the normal is a plane inclined at an angle of 0 to 8 degrees with respect to the c-axis in the

[0001] direction. In other words, the off-angle with respect to the (0001) plane is 0 to 8 degrees. The second plane F2 is, for example, a plane inclined at an angle of 0 to 8 degrees with respect to the (000-1) plane.

[0035] The (0001) plane is called the silicon plane. The (000-1) plane is called the carbon plane. The tilt direction of the first plane F1 and the second plane F2 is, for example, the [11-20] direction. The [11-20] direction is the a-axis direction. In FIG. 1, for example, the second direction shown in the figure is the a-axis direction.

[0036] The first trench 22a and the second trench 22b are provided on the first face F1 side of the silicon carbide layer 10. The first trench 22a and the second trench 22b extend in a first direction as shown in FIG. 2. A plurality of trenches including the first trench 22a and the second trench 22b are repeatedly arranged in a second direction. The repeat pitch of the trenches in the second direction is, for example, not less than 1.0 μm and not more than 5.0 μm. The depth of the first trench 22a and the second trench 22b is, for example, not less than 1 μm and not more than 2 μm.

[0037] First trench 22a and second trench 22b are recesses provided in first face F1 of silicon carbide layer 10.

[0038] The first gate electrode 16a is provided in the first trench 22a. The first gate electrode 16a is provided between the source electrode 12 and the drain electrode 14. The first gate electrode 16a extends in a first direction.

[0039] The second gate electrode 16b is provided in the second trench 22b. The second gate electrode 16b is provided between the source electrode 12 and the drain electrode 14. The second gate electrode 16b extends in the first direction.

[0040] The gate electrode 16 is a conductive layer, and is, for example, polycrystalline silicon containing p-type impurities or n-type impurities.

[0041] The first gate insulating layer 18a is provided between the first gate electrode 16a and the silicon carbide layer 10. The first gate insulating layer 18a is provided at least between the first gate electrode 16a and each of the source region 35, the body region 34, the p-control region 30, and the n-control region 32.

[0042] The second gate insulating layer 18b is provided between the second gate electrode 16b and the silicon carbide layer 10. The second gate insulating layer 18b is provided at least between the second gate electrode 16b and each of the source region 35, the body region 34, the p-control region 30, and the n-control region 32.

[0043] The gate insulating layer 18 includes, for example, silicon oxide, silicon nitride, or aluminum oxide. The gate insulating layer 18 is, for example, a stacked film of films including any of the above materials. The gate insulating layer 18 includes, for example, silicon oxide including nitrogen.

[0044] The interlayer insulating layer 20 is provided on the first gate electrode 16 a and the second gate electrode 16 b. The interlayer insulating layer 20 is provided between the first gate electrode 16 a and the second gate electrode 16 b and the source electrode 12. The interlayer insulating layer 20 includes, for example, silicon oxide.

[0045] n + The n-type drain region 24 is provided on the back surface side of the silicon carbide layer 10. The drain region 24 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 24 is, for example, 5×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0046] The n-type buffer region 25 is provided on the drain region 24. The buffer region 25 is provided between the drain region 24 and the surface of the silicon carbide layer 10.

[0047] The buffer region 25 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the buffer region 25 is lower than the n-type impurity concentration of the drain region 24. The n-type impurity concentration of the buffer region 25 is, for example, 5×10 17 cm -3 5x10 or more 19 cm -3 The following is the result.

[0048] p - The first p-pillar region 26a is provided between the buffer region 25 and the surface of the silicon carbide layer 10. As shown in Fig. 7, the first p-pillar region 26a extends in the second direction.

[0049] n - The first n-pillar region 28a is provided between the buffer region 25 and the surface of the silicon carbide layer 10. As shown in FIG. 7, the first n-pillar region 28a extends in a second direction. The first n-pillar region 28a is located in a first direction relative to the first p-pillar region 26a. The first n-pillar region 28a contacts the first p-pillar region 26a.

[0050] p - The second p-pillar region 26b is provided between the buffer region 25 and the surface of the silicon carbide layer 10. As shown in FIG. 7, the second p-pillar region 26b extends in a second direction. The second p-pillar region 26b is located in a first direction relative to the first n-pillar region 28a. The second p-pillar region 26b contacts the first n-pillar region 28a.

[0051] n - The second n-pillar region 28b is provided between the buffer region 25 and the surface of the silicon carbide layer 10. As shown in FIG. 7, the second n-pillar region 28b extends in a second direction. The second n-pillar region 28b is located in a first direction relative to the second p-pillar region 26b. The second n-pillar region 28b contacts the second p-pillar region 26b.

[0052] n -The third n-pillar region 28c is provided between the buffer region 25 and the surface of the silicon carbide layer 10. As shown in FIG. 7, the third n-pillar region 28c extends in the second direction. The third n-pillar region 28c is located in the first direction relative to the first p-pillar region 26a. The third n-pillar region 28c contacts the first p-pillar region 26a. The first p-pillar region 26a is located between the third n-pillar region 28c and the first n-pillar region 28a.

[0053] The p-pillar region 26 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the p-pillar region 26 is, for example, 5×10 15 cm -3 5x10 or more 17 cm -3 The following is the result.

[0054] The n-pillar region 28 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the n-pillar region 28 is lower than the n-type impurity concentration of the buffer region 25. The n-type impurity concentration of the n-pillar region 28 is, for example, 5×10 15 cm -3 5x10 or more 17 cm -3 The following is the result.

[0055] A plurality of p-pillar regions 26 and a plurality of n-pillar regions 28 are alternately arranged in a first direction. The plurality of p-pillar regions 26 and the plurality of n-pillar regions 28 form an SJ structure. The SJ structure has the function of improving the breakdown voltage of the MOSFET 100.

[0056] The repeat pitch (P1 in FIG. 7) of the p-pillar regions 26 and the n-pillar regions 28 in the first direction is, for example, not less than 1.0 μm and not more than 5.0 μm.

[0057] The p-type first p control region 30a is located between the first p pillar region 26a and the surface of the silicon carbide layer 10. The first p control region 30a is located in a third direction relative to the first p pillar region 26a.

[0058] 8, first p control region 30a extends in the second direction. First p control region 30a is located between trench 22 and the back surface of silicon carbide layer 10. First p control region 30a contacts, for example, the bottom surface of first trench 22a and the bottom surface of second trench 22b.

[0059] The n-type first n control region 32a is located between the first n pillar region 28a and the surface of the silicon carbide layer 10. The first n control region 32a is located in a third direction relative to the first n pillar region 28a.

[0060] 8, the first n control region 32a extends in the second direction. The first n control region 32a is located in the first direction relative to the first p control region 30a. The first n control region 32a is in contact with the first p control region 30a.

[0061] The first n control region 32a is located between the trench 22 and the rear surface of the silicon carbide layer 10. The first n control region 32a contacts the bottom surface of the first trench 22a and the bottom surface of the second trench 22b.

[0062] The p-type second p control region 30b is located between the second p pillar region 26b and the surface of the silicon carbide layer 10. The second p control region 30b is located in a third direction relative to the second p pillar region 26b.

[0063] 8, second p control region 30b extends in a second direction. Second p control region 30b is located in a first direction relative to first n control region 32a. Second p control region 30b is adjacent to first n control region 32a.

[0064] The second p control region 30b is located between the trench 22 and the rear surface of the silicon carbide layer 10. The second p control region 30b contacts, for example, the bottom surface of the first trench 22a and the bottom surface of the second trench 22b.

[0065] The n-type second n control region 32b is located between the second n pillar region 28b and the surface of the silicon carbide layer 10. The second n control region 32b is located in a third direction relative to the second n pillar region 28b.

[0066] 8, the second n control region 32b extends in the second direction. The second n control region 32b is located in the first direction relative to the second p control region 30b. The second n control region 32b is in contact with the second p control region 30b.

[0067] The second n control region 32b is located between the trench 22 and the rear surface of the silicon carbide layer 10. The second n control region 32b contacts the bottom surface of the first trench 22a and the bottom surface of the second trench 22b.

[0068] The n-type third n control region 32c is located between the third n pillar region 28c and the surface of the silicon carbide layer 10. The third n control region 32c is located in a third direction relative to the third n pillar region 28c.

[0069] 8, the third n control region 32c extends in the second direction. The third n control region 32c is located in the first direction relative to the first p control region 30a. The third n control region 32c is in contact with the first p control region 30a.

[0070] The third n control region 32c is located between the trench 22 and the rear surface of the silicon carbide layer 10. The third n control region 32c contacts the bottom surface of the first trench 22a and the bottom surface of the second trench 22b.

[0071] The p-type control region 30 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the p-type control region 30 is higher than the p-type impurity concentration of the p-pillar region 26. The p-type impurity concentration of the p-type control region 30 is, for example, 5×10 16 cm -3 5x10 or more 18 cm -3 The following is the result.

[0072] The n-type control region 32 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the n-type control region 32 is higher than the n-type impurity concentration of the n-pillar region 28. The n-type impurity concentration of the n-type control region 32 is, for example, 5×10 16 cm -3 More than 1×10 18 cm -3 The following is the result.

[0073] The plurality of p control regions 30 and the plurality of n control regions 32 are alternately arranged in a first direction. The plurality of p control regions 30 and the plurality of n control regions 32 have the function of improving the short circuit resistance of the MOSFET 100.

[0074] The plurality of p control regions 30 face the bottom surface of the trench 22. The p control regions 30 have the function of improving the reliability of the gate insulating layer 18.

[0075] The repeat pitch in the first direction of the p control region 30 and the n control region 32 (P2 in FIG. 8) is equal to the repeat pitch in the first direction of the p pillar region 26 and the n pillar region 28 (P1 in FIG. 7). The repeat pitch in the first direction of the p control region 30 and the n control region 32 is, for example, not less than 1.0 μm and not more than 5.0 μm.

[0076] The p-type body region 34 is located between the p-control region 30 and the surface of the silicon carbide layer 10. The p-type body region 34 is located between the n-control region 32 and the surface of the silicon carbide layer 10. The body region 34 is located between the first trench 22a and the second trench 22b. The body region 34 extends in a first direction.

[0077] The body region 34 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the body region 34 is, for example, 5×10 16 cm -3 5x10 or more 18 cm -3 The following is the result.

[0078] The depth of the body region 34 is shallower than the depth of the trench 22. The depth of the body region 34 is, for example, not less than 0.5 μm and not more than 1.0 μm.

[0079] The body region 34 functions as a channel region of the MOSFET 100. For example, when the MOSFET 100 is in an on-state, a channel through which electrons flow is formed in a region of the body region 34 that is in contact with the gate insulating layer 18. The region of the body region 34 that is in contact with the gate insulating layer 18 serves as a channel formation region.

[0080] The n-type source region 35 is provided between the body region 34 and the surface of the silicon carbide layer 10. The source region 35 extends in a first direction as shown in FIG.

[0081] The source region 35 is provided along the first trench 22a. The source region 35 is provided along the second trench 22b.

[0082] The source region 35 is provided along the first gate insulating layer 18a. The source region 35 is provided along the second gate insulating layer 18b. The source region 35 contacts the gate insulating layer 18.

[0083] The source region 35 is located between the trench 22 and the n-contact region 36. The source region 35 is located between the trench 22 and the p-contact region 38. The n-contact region 36 is sandwiched between two source regions 35. In addition, the p-contact region 38 is sandwiched between two source regions 35.

[0084] The source region 35 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the source region 35 is lower than the n-type impurity concentration of the n-contact region 36. The n-type impurity concentration of the source region 35 is, for example, 1×10 19 cm -3 5x10 or more 19 cm -3 The following is the result.

[0085] n + The first n-type contact region 36a is located between the body region 34 and the surface of the silicon carbide layer 10. The first n-type contact region 36a is located between the first trench 22a and the second trench 22b.

[0086] 4, the first n-contact region 36a is located in a third direction relative to the first p-control region 30a. The first n-contact region 36a is located directly above the first p-control region 30a.

[0087] p + The first p contact region 38a is located between the body region 34 and the surface of the silicon carbide layer 10. The first p contact region 38a is located between the first trench 22a and the second trench 22b. As shown in FIG. 2 , the first p contact region 38a is located in a first direction relative to the first n contact region 36a.

[0088] 4, the first p contact region 38a is located in the third direction relative to the first n control region 32a. The first p contact region 38a is located directly above the first n control region 32a.

[0089] n +The second n-type contact region 36b is located between the body region 34 and the surface of the silicon carbide layer 10. The second n-type contact region 36b is located between the first trench 22a and the second trench 22b. As shown in FIG. 2 , the second n-type contact region 36b is located in a first direction relative to the first p-type contact region 38a.

[0090] 4, the second n-contact region 36b is located in a third direction relative to the second p-control region 30b. The second n-contact region 36b is located directly above the second p-control region 30b.

[0091] p + The second p-type contact region 38b is located between the body region 34 and the surface of the silicon carbide layer 10. The second p-type contact region 38b is located between the first trench 22a and the second trench 22b. As shown in FIG. 2 , the second p-type contact region 38b is located in the first direction relative to the second n-type contact region 36b.

[0092] 4, the second p-contact region 38b is located in a third direction relative to the second n-control region 32b. The second p-contact region 38b is located directly above the second n-control region 32b.

[0093] p + The third p-type contact region 38c is located between the body region 34 and the surface of the silicon carbide layer 10. As shown in FIG. 2, the third p-type contact region 38c is located in a first direction relative to the first n-type contact region 36a.

[0094] 4, the third p-contact region 38c is located in a third direction relative to the third n-control region 32c. The third p-contact region 38c is located directly above the third n-control region 32c.

[0095] The n-contact region 36 contains, for example, phosphorus (P) as an n-type impurity. The n-type impurity concentration of the n-contact region 36 is higher than the n-type impurity concentration of the source region 35. The n-type impurity concentration of the n-contact region 36 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0096] The p-type contact region 38 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the p-type contact region 38 is higher than the p-type impurity concentration of the body region 34. The p-type impurity concentration of the p-type contact region 38 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0097] The plurality of n-contact regions 36 and p-contact regions 38 are arranged alternately in a first direction. The plurality of n-contact regions 36 and p-contact regions 38 have the function of reducing the contact resistance of the MOSFET 100 and reducing the on-resistance of the MOSFET 100.

[0098] The repeat pitch of the n contact region 36 and the p contact region 38 in the first direction is, for example, equal to the repeat pitch of the p control region 30 and the n control region 32 in the first direction.

[0099] The n-contact region 36 is located in the third direction of the p-control region 30. The n-contact region 36 is provided directly above the p-control region 30.

[0100] The p-contact region 38 is located in the third direction from the n-control region 32. The p-contact region 38 is provided directly above the n-control region 32.

[0101] The area of ​​the n contact region 36 provided in the third direction of the p control region 30 on the first face F1 is, for example, larger than the area of ​​the p contact region 38 provided in the third direction of the p control region 30 on the first face F1.

[0102] The area of ​​the p contact region 38 provided in the third direction of the n control region 32 on the first face F1 is, for example, larger than the area of ​​the n contact region 36 provided in the third direction of the n control region 32 on the first face F1.

[0103] The source electrode 12 is provided on the surface side of the silicon carbide layer 10. The source electrode 12 is provided on the surface of the silicon carbide layer 10. The source electrode 12 is in contact with the n-contact region 36 and the p-contact region 38, for example.

[0104] The source electrode 12 includes a metal. The metal forming the source electrode 12 is, for example, a laminated structure of titanium (Ti) and aluminum (Al). The source electrode 12 may include, for example, a metal silicide in the portions in contact with the n-contact region 36 and the p-contact region 38 to reduce contact resistance. The metal silicide is, for example, nickel silicide.

[0105] The connection between the source electrode 12 and the n-contact region 36 and the p-contact region 38 is, for example, an ohmic connection.

[0106] The drain electrode 14 is provided on the back surface side of the silicon carbide layer 10. The drain electrode 14 is provided on the back surface of the silicon carbide layer 10. The drain electrode 14 is in contact with the drain region 24.

[0107] The drain electrode 14 is, for example, a metal or a metal-semiconductor compound, and includes, for example, a material selected from the group consisting of nickel silicide (NiSi), titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0108] Next, the operation and effects of the semiconductor device of the first embodiment will be described.

[0109] The MOSFET 100 has a trench gate structure in which a gate electrode 16 is provided in a trench 22. By adopting the trench gate structure, the channel area per unit area increases, and the on-resistance of the MOSFET 100 is reduced.

[0110] The MOSFET 100 also has an SJ structure. When the MOSFET 100 is in an off state, a depletion layer expands in a first direction in the SJ structure. This improves the breakdown voltage of the MOSFET 100.

[0111] When a short circuit occurs in a load driven by a MOSFET, a large current flows through the MOSFET, causing it to be destroyed. The time it takes for a MOSFET to be destroyed is called its short-circuit withstand capability. From the perspective of improving the reliability of MOSFETs, it is desirable to improve the short-circuit withstand capability.

[0112] The MOSFET 100 includes an n-control region 32 having a higher n-type impurity concentration than the n-pillar region 28, located above the n-pillar region 28, which serves as a current path when the MOSFET 100 is in on-state. That is, the MOSFET 100 includes an n-control region 32 having a higher n-type impurity concentration and lower electrical resistance than the n-pillar region 28.

[0113] When a short circuit occurs in the load and a large current flows through the MOSFET 100, heat generation increases near the interface between the n-control region 32 and the n-pillar region 28. This is because electrical resistance increases near the interface between the n-control region 32 and the n-pillar region 28.

[0114] If the n control region 32 were not present, when a short circuit occurs in the load and a large current flows through the MOSFET 100, heat would be generated in the vicinity of the interface between the body region 34 and the n pillar region 28. By providing the n control region 32 in the MOSFET 100, the location of heat generation in the event of a short circuit in the load can be shifted to a deeper position in the silicon carbide layer 10. This, for example, suppresses melting of the source electrode 12 due to heat generation, improving the short circuit resistance of the MOSFET 100.

[0115] Furthermore, as will be described later, the MOSFET 100 has an improved short-circuit resistance due to the p-contact region 38 being located directly above the n-control region 32.

[0116] 9, 10, and 11 are diagrams illustrating the operation and effects of the semiconductor device of the first embodiment. Fig. 9 is an AA' cross section of the MOSFET 100, Fig. 10 is a first face F1 of the MOSFET 100, and Fig. 11 is a DD' cross section of the MOSFET 100. In Fig. 9, 10, and 11, black arrows indicate current paths when a short circuit occurs in the load and a large current flows through the MOSFET 100.

[0117] 9, current flows from the n-pillar region 28, through the n-control region 32, and into the channel region where the body region 34 contacts the gate insulating layer 18, and reaches the source region 35. Because the contact resistance between the low-concentration source region 35 and the source electrode 12 is high, the current does not easily escape from above the source region 35 to the source electrode 12.

[0118] In the portion of the source region 35 adjacent to the p-contact region 38 in the second direction, the current flows through the source region 35 in the first direction, bypassing the p-contact region 38, as shown in Figures 10 and 11. Then, the current flows from the source region 35 to the n-contact region 36, as shown in Figure 10. The current then flows from above the n-contact region 36 to the source electrode 12.

[0119] When a short circuit occurs in the load and a large current flows through the MOSFET 100, the current path is narrowed by the source region 35. This suppresses the saturation current of the MOSFET 100. This improves the short circuit resistance of the MOSFET 100.

[0120] If, unlike the MOSFET 100, the n-contact region 36 were located directly above the n-control region 32, the current that reaches the source region 35 would flow to the n-contact region 36 adjacent to the source region 35 without bypassing the p-contact region 38. Therefore, the current path is not narrowed by the source region 35, and the saturation current of the MOSFET 100 is not suppressed.

[0121] 5, the MOSFET 100 also includes p-control regions 30 on both sides of the n-control region 32 in the first direction. By providing the p-control regions 30, the width of the depletion layer extending from the n-control region 32 to the channel formation region of the body region 34 is reduced when the MOSFET 100 is in an off state. This reduces the short-channel effect of the MOSFET 100 and reduces the off-leakage current. This allows, for example, the depth of the body region 34 of the MOSFET 100 to be shallower.

[0122] From the viewpoint of improving the short-circuit resistance of the MOSFET 100, it is preferable that the area of ​​the p contact region 38 provided in the third direction of the n control region 32 on the first face F1 be larger than the area of ​​the n contact region 36 provided in the third direction of the n control region 32 on the first face F1.

[0123] From the viewpoint of reducing the on-resistance of the MOSFET 100, it is preferable that the area of ​​the n contact region 36 provided in the third direction of the p control region 30 on the first face F1 be larger than, for example, the area of ​​the p contact region 38 provided in the third direction of the p control region 30 on the first face F1.

[0124] From the viewpoint of improving the short-circuit resistance of the MOSFET 100, the width of the p-contact region 38 in the first direction is preferably larger than the width of the n-contact region 36 in the first direction.

[0125] From the viewpoint of reducing the on-resistance of the MOSFET 100, the width of the n-contact region 36 in the first direction is preferably larger than the width of the p-contact region 38 in the first direction.

[0126] As described above, according to the first embodiment, a MOSFET capable of improving short-circuit resistance can be realized.

[0127] (Second embodiment) The semiconductor device of the second embodiment differs from the first embodiment in that the distance in the first direction between the fifth silicon carbide region and the seventh silicon carbide region is smaller than the distance in the first direction between the first silicon carbide region and the third silicon carbide region. Hereinafter, some description of content that overlaps with the first embodiment may be omitted.

[0128] Fig. 12 is a schematic cross-sectional view of a semiconductor device according to the second embodiment, which corresponds to Fig. 5 of the first embodiment.

[0129] The semiconductor device of the second embodiment is a trench-gate vertical MOSFET 200 using silicon carbide. The MOSFET 200 is an n-channel MOSFET that uses electrons as carriers.

[0130] The distance in the first direction between the first p control region 30a and the second p control region 30b (d1 in FIG. 12) is smaller than the distance in the first direction between the first p pillar region 26a and the second p pillar region 26b (d2 in FIG. 12). In other words, the width in the first direction of the first n control region 32a is smaller than the width in the first direction of the first n pillar region 28a. The width in the first direction of the n control region 32 is smaller than the width in the first direction of the n pillar region 28.

[0131] In the MOSFET 200, the width of the n-control region 32 in the first direction is smaller than the width of the n-pillar region 28 in the first direction. Therefore, when a short circuit occurs in the load and a large current flows through the MOSFET 200, the current path is narrowed by the n-control region 32. This suppresses the saturation current of the MOSFET 200. This further improves the short-circuit resistance compared to the MOSFET 100.

[0132] As described above, according to the second embodiment, a MOSFET capable of improving short-circuit resistance can be realized.

[0133] (Third embodiment) The semiconductor device of the third embodiment differs from the first embodiment in that the tenth silicon carbide region extends in a first direction, the eleventh silicon carbide region extends in the first direction, and the eleventh silicon carbide region is located in a second direction relative to the tenth silicon carbide region. Hereinafter, some description of content that overlaps with the first embodiment may be omitted.

[0134] Fig. 13 is a schematic plan view of a semiconductor device according to the third embodiment, which corresponds to Fig. 2 of the first embodiment.

[0135] The semiconductor device of the third embodiment is a trench-gate vertical MOSFET 300 using silicon carbide. The MOSFET 300 is an n-channel MOSFET that uses electrons as carriers.

[0136] n + The first n-type contact region 36a (tenth silicon carbide region) extends in the first direction. + The first p-type contact region 38a (eleventh silicon carbide region) extends in a first direction and is located in a second direction relative to the first n-type contact region 36a.

[0137] Similar to the MOSFET 100 of the first embodiment, the MOSFET 300 includes an n-control region 32 having a higher n-type impurity concentration than the n-pillar region 28, located above the n-pillar region 28, which serves as a current path when the MOSFET 300 is in on-state. That is, the MOSFET 300 includes an n-control region 32 having a high n-type impurity concentration and lower electrical resistance than the n-pillar region 28.

[0138] Therefore, when a short circuit occurs in the load, the heat generation location can be shifted to a deeper position in silicon carbide layer 10. This, for example, suppresses melting of source electrode 12 due to heat generation, and improves the short circuit resistance of MOSFET 300.

[0139] As described above, according to the third embodiment, a MOSFET capable of improving short-circuit resistance can be realized.

[0140] (Fourth embodiment) A semiconductor device according to a fourth embodiment includes a silicon carbide layer having a first surface parallel to a first direction and a second direction orthogonal to the first direction, and a second surface opposite to the first surface; a first trench provided in the silicon carbide layer on the side of the first surface and extending in the first direction; a second trench provided in the silicon carbide layer on the side of the first surface and extending in a second direction relative to the first trench and extending in the first direction; a first gate electrode provided in the first trench; a second gate electrode provided in the second trench; and a first gate electrode provided between the first gate electrode and the silicon carbide layer. a gate insulating layer, a second gate insulating layer provided between the second gate electrode and the silicon carbide layer; a first silicon carbide region of a first conductivity type provided in the silicon carbide layer and extending in a first direction; a second silicon carbide region of a second conductivity type provided in the silicon carbide layer and extending in the first direction and positioned in a second direction relative to the first silicon carbide region; a third silicon carbide region of the first conductivity type provided in the silicon carbide layer and extending in the first direction and positioned in the second direction relative to the second silicon carbide region; and a third silicon carbide region of the first conductivity type provided in the silicon carbide layer and extending in the first direction and positioned in the second direction relative to the third silicon carbide region. a fourth silicon carbide region of the second conductivity type provided in the silicon carbide layer, extending in the second direction, and located between the first silicon carbide region and the first surface, between the second silicon carbide region and the first surface, between the third silicon carbide region and the first surface, between the fourth silicon carbide region and the first surface, and between the first trench, the second trench, and the second surface, and having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the first silicon carbide region; a fifth silicon carbide region of the first conductivity type provided in the silicon carbide layer, extending in the second direction, and located between the first silicon carbide region and the first surface a sixth silicon carbide region of the second conductivity type, the sixth silicon carbide region being located between the first trench and the first surface, the third silicon carbide region and the first surface, the fourth silicon carbide region and the first surface, and the first trench and the second surface, and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the second silicon carbide region; a sixth silicon carbide region of the second conductivity type, provided in the silicon carbide layer, extending in the second direction, and located between the first silicon carbide region and the first surface, the second silicon carbide region and the first surface, and the third silicon carbide region and the first surface;a seventh silicon carbide region of the first conductivity type located between the fourth silicon carbide region and the first surface, and located between the first trench and the second trench and the second surface, and having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the first silicon carbide region; and a third silicon carbide region provided in the silicon carbide layer, extending in the second direction, and located between the first silicon carbide region and the first surface, and between the second silicon carbide region and the first surface. an eighth silicon carbide region of the second conductivity type, which is located between the silicon carbide region and the first surface, between the fourth silicon carbide region and the first surface, and between the first trench, the second trench and the second surface, and which has a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the second silicon carbide region; and four silicon carbide regions provided in the silicon carbide layer, which are located between the fifth silicon carbide region and the first surface, between the sixth silicon carbide region and the first surface, and between the seventh silicon carbide region and the fifth silicon carbide region. a ninth silicon carbide region of the first conductivity type located between the first silicon carbide region and the first surface, between the eighth silicon carbide region and the first surface, and between the first trench and the second trench; a tenth silicon carbide region of the second conductivity type provided in the silicon carbide layer and located between the ninth silicon carbide region and the first surface and between the first trench and the second trench; The semiconductor device of the fourth embodiment comprises: an eleventh silicon carbide region of a first conductivity type located between the first trench and the first surface, the eleventh silicon carbide region being located between the first trench and the second trench and having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the ninth silicon carbide region; a first electrode provided on the first surface side of the silicon carbide layer and in contact with the tenth and eleventh silicon carbide regions; and a second electrode provided on the second surface side of the silicon carbide layer. The semiconductor device of the fourth embodiment differs from the first embodiment in that the first silicon carbide region, the second silicon carbide region, the third silicon carbide region, and the fourth silicon carbide region extend in a first direction. Hereinafter, some description of content that overlaps with the first embodiment may be omitted.

[0141] The following description will be given taking as an example a case where the first conductivity type is p-type and the second conductivity type is n-type.

[0142] 14 is a schematic cross-sectional view of the semiconductor device of the fourth embodiment, taken along the line AA' in FIG.

[0143] Fig. 15 is a schematic plan view of the semiconductor device of the fourth embodiment, taken along the first plane (F1 in Fig. 14) of Fig. 14.

[0144] 16 is a schematic cross-sectional view of the semiconductor device of the fourth embodiment, taken along the line BB' in FIG.

[0145] 17 is a schematic cross-sectional view of the semiconductor device of the fourth embodiment, taken along line CC' in FIG.

[0146] 18 is a schematic cross-sectional view of the semiconductor device of the fourth embodiment, taken along the line DD' in FIG.

[0147] 19 is a schematic cross-sectional view of the semiconductor device of the fourth embodiment, taken along the line EE' of FIG.

[0148] 20 is a schematic cross-sectional view of the semiconductor device of the fourth embodiment, taken along line Fx in FIG.

[0149] 21 is a schematic cross-sectional view of the semiconductor device of the fourth embodiment, taken along line Fy in FIG.

[0150] The semiconductor device of the fourth embodiment is a trench-gate vertical MOSFET 400 using silicon carbide. The MOSFET 400 is an n-channel MOSFET that uses electrons as carriers.

[0151] The MOSFET 400 has a superjunction structure (hereinafter also referred to as an "SJ structure").

[0152] The MOSFET 400 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a first gate electrode 16a, a second gate electrode 16b, a first gate insulating layer 18a, a second gate insulating layer 18b, an interlayer insulating layer 20, a first trench 22a, and a second trench 22b.

[0153] In the silicon carbide layer 10, n + a drain region 24, an n-type buffer region 25, and a p - First p-pillar region 26a (first silicon carbide region) of type p - a second p-pillar region 26b (third silicon carbide region) of the n type; - First n-pillar region 28a (second silicon carbide region) of the n type - a second n-pillar region 28b (fourth silicon carbide region) of the n type; - a third n-pillar region 28c of the n-type, a first p-type control region 30a (fifth silicon carbide region), a second p-type control region 30b (seventh silicon carbide region), a first n-type control region 32a (sixth silicon carbide region), a second n-type control region 32b (eighth silicon carbide region), a third n-type control region 32c of the n-type, a p-type body region 34 (ninth silicon carbide region), an n-type source region 35 (fourteenth silicon carbide region), and + a first n-type contact region 36a (tenth silicon carbide region), + a second n-contact region 36b (twelfth silicon carbide region) of type p + a first p-type contact region 38a (eleventh silicon carbide region), + a second p-type contact region 38b (a thirteenth silicon carbide region), + A third p-contact region 38c of the same type is provided.

[0154] Hereinafter, the first gate electrode 16a and the second gate electrode 16b may be collectively referred to as the gate electrode 16. Furthermore, the first gate insulating layer 18a and the second gate insulating layer 18b may be collectively referred to as the gate insulating layer 18. Furthermore, the first trench 22a and the second trench 22b may be collectively referred to as the trench 22.

[0155] Hereinafter, the first p-pillar region 26a and the second p-pillar region 26b may be collectively referred to as p-pillar regions 26. The first n-pillar region 28a, the second n-pillar region 28b, and the third n-pillar region 28c may be collectively referred to as n-pillar regions 28. The first p-control region 30a and the second p-control region 30b may be collectively referred to as p-control regions 30. The first n-control region 32a, the second n-control region 32b, and the n-type third n-control region 32c may be collectively referred to as n-control regions 32. The first n-contact region 36a and the second n-contact region 36b may be collectively referred to as n-contact regions 36. Furthermore, the first p contact region 38a, the second p contact region 38b, and the third p contact region 38c may be collectively referred to as the p contact region 38.

[0156] p - The first p-pillar region 26a is provided between the buffer region 25 and the surface of the silicon carbide layer 10. As shown in Fig. 20, the first p-pillar region 26a extends in a first direction.

[0157] The first trench 22a is located, for example, in the third direction relative to the first p-pillar region 26a. The first trench 22a is located, for example, directly above the first p-pillar region 26a.

[0158] n - The first n-pillar region 28a is provided between the buffer region 25 and the surface of the silicon carbide layer 10. As shown in FIG. 20 , the first n-pillar region 28a extends in a first direction. The first n-pillar region 28a is located in a second direction relative to the first p-pillar region 26a. The first n-pillar region 28a contacts the first p-pillar region 26a.

[0159] The body region 34 is located, for example, in the third direction relative to the first n-pillar region 28a. The body region 34 is located, for example, directly above the first n-pillar region 28a.

[0160] p - The second p-pillar region 26b is provided between the buffer region 25 and the surface of the silicon carbide layer 10. As shown in FIG. 20 , the second p-pillar region 26b extends in a first direction. The second p-pillar region 26b is located in a second direction relative to the first n-pillar region 28a. The second p-pillar region 26b contacts the first n-pillar region 28a.

[0161] The second trench 22b is located in the third direction relative to the second p-pillar region 26b. The second trench 22b is located directly above the second p-pillar region 26b.

[0162] n - The second n-pillar region 28b is provided between the buffer region 25 and the surface of the silicon carbide layer 10. As shown in FIG. 20 , the second n-pillar region 28b extends in a first direction. The second n-pillar region 28b is located in a second direction relative to the second p-pillar region 26b. The second n-pillar region 28b contacts the second p-pillar region 26b.

[0163] The body region 34 is located, for example, in the third direction relative to the second n-pillar region 28b. The body region 34 is located, for example, directly above the second n-pillar region 28b.

[0164] n - The third n-pillar region 28c is provided between the buffer region 25 and the surface of the silicon carbide layer 10. As shown in FIG. 20 , the third n-pillar region 28c extends in a first direction. The third n-pillar region 28c is located in a second direction relative to the first p-pillar region 26a. The third n-pillar region 28c contacts the first p-pillar region 26a. The first p-pillar region 26a is located between the third n-pillar region 28c and the first n-pillar region 28a.

[0165] The p-pillar region 26 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the p-pillar region 26 is, for example, 5×10 15 cm -3 5x10 or more17 cm -3 The following is the result.

[0166] The n-pillar region 28 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the n-pillar region 28 is lower than the n-type impurity concentration of the buffer region 25. The n-type impurity concentration of the n-pillar region 28 is, for example, 5×10 15 cm -3 5x10 or more 17 cm -3 The following is the result.

[0167] The plurality of p-pillar regions 26 and the plurality of n-pillar regions 28 are alternately arranged in the second direction. The plurality of p-pillar regions 26 and the plurality of n-pillar regions 28 form an SJ structure. The SJ structure has the function of improving the breakdown voltage of the MOSFET 400.

[0168] The repeat pitch (P1 in FIG. 20) of the p-pillar regions 26 and the n-pillar regions 28 in the second direction is, for example, not less than 1.5 μm and not more than 6 μm.

[0169] The p-type first p control region 30a is located between the first p pillar region 26a and the surface of the silicon carbide layer 10, between the first n pillar region 28a and the surface of the silicon carbide layer 10, between the second p pillar region 26b and the surface of the silicon carbide layer 10, and between the second n pillar region 28b and the surface of the silicon carbide layer 10.

[0170] 21, the first p control region 30a extends in the second direction. The first p control region 30a is located between the trench 22 and the back surface of the silicon carbide layer 10. The first p control region 30a contacts, for example, the bottom surface of the first trench 22a and the bottom surface of the second trench 22b.

[0171] The n-type first n control region 32a is located between the first p pillar region 26a and the surface of the silicon carbide layer 10, between the first n pillar region 28a and the surface of the silicon carbide layer 10, between the second p pillar region 26b and the surface of the silicon carbide layer 10, and between the second n pillar region 28b and the surface of the silicon carbide layer 10.

[0172] 21, the first n control region 32a extends in the second direction. The first n control region 32a is located in the first direction relative to the first p control region 30a. The first n control region 32a is in contact with the first p control region 30a.

[0173] The first n control region 32a is located between the trench 22 and the rear surface of the silicon carbide layer 10. The first n control region 32a contacts the bottom surface of the first trench 22a and the bottom surface of the second trench 22b.

[0174] The p-type second p control region 30b is located between the first p pillar region 26a and the surface of the silicon carbide layer 10, between the first n pillar region 28a and the surface of the silicon carbide layer 10, between the second p pillar region 26b and the surface of the silicon carbide layer 10, and between the second n pillar region 28b and the surface of the silicon carbide layer 10.

[0175] 21, second p control region 30b extends in a second direction. Second p control region 30b is located in a first direction relative to first n control region 32a. Second p control region 30b is adjacent to first n control region 32a.

[0176] The second p control region 30b is located between the trench 22 and the rear surface of the silicon carbide layer 10. The second p control region 30b contacts, for example, the bottom surface of the first trench 22a and the bottom surface of the second trench 22b.

[0177] The n-type second n control region 32b is located between the first p pillar region 26a and the surface of the silicon carbide layer 10, between the first n pillar region 28a and the surface of the silicon carbide layer 10, between the second p pillar region 26b and the surface of the silicon carbide layer 10, and between the second n pillar region 28b and the surface of the silicon carbide layer 10.

[0178] 21, second n control region 32b extends in the second direction. Second n control region 32b is located in the first direction relative to second p control region 30b. Second n control region 32b is in contact with second p control region 30b.

[0179] The second n control region 32b is located between the trench 22 and the rear surface of the silicon carbide layer 10. The second n control region 32b contacts the bottom surface of the first trench 22a and the bottom surface of the second trench 22b.

[0180] The n-type third n control region 32c is located between the first p pillar region 26a and the surface of the silicon carbide layer 10, between the first n pillar region 28a and the surface of the silicon carbide layer 10, between the second p pillar region 26b and the surface of the silicon carbide layer 10, and between the second n pillar region 28b and the surface of the silicon carbide layer 10.

[0181] 21, the third n control region 32c extends in the second direction. The third n control region 32c is located in the first direction relative to the first p control region 30a. The third n control region 32c is in contact with the first p control region 30a.

[0182] The third n control region 32c is located between the trench 22 and the rear surface of the silicon carbide layer 10. The third n control region 32c contacts the bottom surface of the first trench 22a and the bottom surface of the second trench 22b.

[0183] The p-type control region 30 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the p-type control region 30 is higher than the p-type impurity concentration of the p-pillar region 26. The p-type impurity concentration of the p-type control region 30 is, for example, 5×10 16 cm -3 5x10 or more 18 cm -3 The following is the result.

[0184] The n-type control region 32 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the n-type control region 32 is higher than the n-type impurity concentration of the n-pillar region 28. The n-type impurity concentration of the n-type control region 32 is, for example, 5×10 16 cm -3 More than 1×10 18 cm -3 The following is the result.

[0185] The plurality of p control regions 30 and the plurality of n control regions 32 are alternately arranged in a first direction. The plurality of p control regions 30 and the plurality of n control regions 32 have the function of improving the short circuit resistance of the MOSFET 400.

[0186] The plurality of p control regions 30, for example, face the bottom surface of the trench 22. The p control regions 30 have the function of improving the reliability of the gate insulating layer 18.

[0187] The repeat pitch in the first direction of the p control region 30 and the n control region 32 (P2 in FIG. 21) is, for example, equal to the repeat pitch in the second direction of the p pillar region 26 and the n pillar region 28 (P1 in FIG. 20). The repeat pitch in the first direction of the p control region 30 and the n control region 32 is, for example, not less than 1.0 μm and not more than 5.0 μm.

[0188] Next, the operation and effects of the semiconductor device of the fourth embodiment will be described.

[0189] By applying the trench gate structure, the channel area per unit area increases, and the on-resistance of the MOSFET 400 is reduced.

[0190] Furthermore, the MOSFET 400 has an SJ structure, which improves the breakdown voltage of the MOSFET 400.

[0191] When a short circuit occurs in a load driven by a MOSFET, a large current flows through the MOSFET, causing it to be destroyed. The time it takes for a MOSFET to be destroyed is called its short-circuit withstand capability. From the perspective of improving the reliability of MOSFETs, it is desirable to improve the short-circuit withstand capability.

[0192] The MOSFET 400 includes an n-type control region 32 having a higher n-type impurity concentration than the n-pillar region 28, located above the n-pillar region 28 that serves as a current path when the MOSFET 400 is in an on-state. By providing the n-type control region 32, the MOSFET 400 can shift the heat generation location in the event of a short circuit in the load to a deeper position in the silicon carbide layer 10. This prevents the source electrode 12 from melting due to heat generation, improving the short-circuit resistance of the MOSFET 400.

[0193] Furthermore, in the MOSFET 400, the p-contact region 38 is located directly above the n-control region 32, thereby improving the short-circuit resistance.

[0194] 17, the MOSFET 400 has p control regions 30 on both sides of the n control region 32 in the first direction. By providing the p control regions 30, the width of the depletion layer extending from the n control region 32 to the channel formation region of the body region 34 is reduced when the MOSFET 400 is in an off state. This reduces the short channel effect of the MOSFET 400 and reduces the off-leakage current. This allows, for example, the depth of the body region 34 of the MOSFET 400 to be shallower.

[0195] From the viewpoint of improving the short-circuit resistance of the MOSFET 400, it is preferable that the area of ​​the p contact region 38 provided in the third direction of the n control region 32 on the first face F1 be larger than the area of ​​the n contact region 36 provided in the third direction of the n control region 32 on the first face F1.

[0196] From the viewpoint of reducing the on-resistance of the MOSFET 400, it is preferable that the area of ​​the n contact region 36 provided in the third direction of the p control region 30 on the first face F1 be larger than, for example, the area of ​​the p contact region 38 provided in the third direction of the p control region 30 on the first face F1.

[0197] From the viewpoint of improving the short-circuit resistance of the MOSFET 400, the width of the p-contact region 38 in the first direction is preferably larger than the width of the n-contact region 36 in the first direction.

[0198] From the viewpoint of reducing the on-resistance of the MOSFET 400, the width of the n-contact region 36 in the first direction is preferably larger than the width of the p-contact region 38 in the first direction.

[0199] As described above, according to the fourth embodiment, a MOSFET capable of improving short-circuit resistance can be realized.

[0200] (Fifth embodiment) The semiconductor device of the fifth embodiment differs from the fourth embodiment in that the distance in the second direction between the first silicon carbide region and the fourth silicon carbide region is greater than the distance in the first direction between the fifth silicon carbide region and the eighth silicon carbide region. Hereinafter, some description of content that overlaps with the fourth embodiment may be omitted.

[0201] Fig. 22 is a schematic cross-sectional view of a semiconductor device according to the fifth embodiment, which corresponds to Fig. 20 of the fourth embodiment.

[0202] Fig. 23 is a schematic cross-sectional view of a semiconductor device according to the fifth embodiment, which corresponds to Fig. 21 of the fourth embodiment.

[0203] The semiconductor device of the fifth embodiment is a trench-gate vertical MOSFET 500 using silicon carbide.

[0204] The distance in the second direction between the first p-pillar region 26a and the second n-pillar region 28b (P1 in FIG. 22) is greater than the distance in the first direction between the first p-control region 30a and the second n-control region 32b (P2 in FIG. 23). For example, the distance in the second direction between the first p-pillar region 26a and the second n-pillar region 28b (P1 in FIG. 22) is 1.5 times or more the distance in the first direction between the first p-control region 30a and the second n-control region 32b (P2 in FIG. 23).

[0205] The repeat pitch (P1 in FIG. 22) of the p-pillar regions 26 and n-pillar regions 28 in the second direction is larger than the repeat pitch (P2 in FIG. 23) of the p-control regions 30 and n-control regions 32 in the first direction.

[0206] In the MOSFET 500, the repetition pitch of the SJ structure is increased, which makes it easier to form the SJ structure than, for example, the MOSFET 400 of the fourth embodiment.

[0207] As described above, according to the fifth embodiment, a MOSFET capable of improving short-circuit resistance can be realized.

[0208] While the first to fifth embodiments have been described above using 4H-SiC as the crystal structure of silicon carbide, the present invention can also be applied to silicon carbide with other crystal structures such as 6H-SiC, 3C-SiC, etc. Furthermore, a plane other than the (0001) plane can also be applied to the surface of silicon carbide layer 10.

[0209] In the first to fifth embodiments, the first conductivity type is p-type and the second conductivity type is n-type, but it is also possible for the first conductivity type to be n-type and the second conductivity type to be p-type.

[0210] In the first to fifth embodiments, aluminum (Al) is used as an example of a p-type impurity, but boron (B) can also be used. Furthermore, nitrogen (N) and phosphorus (P) are used as examples of n-type impurities, but arsenic (As), antimony (Sb), etc. can also be used.

[0211] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and modifications thereof are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0212] 10 Silicon carbide layer 12 source electrode (first electrode) 14 Drain electrode (second electrode) 16a First gate electrode 16b Second gate electrode 18a First gate insulating layer 18b Second gate insulating layer 22a First Trench 22b Second Trench 26a First p-pillar region (first silicon carbide region) 26b Second p-pillar region (third silicon carbide region) 28a First n-pillar region (second silicon carbide region) 28b Second n-pillar region (fourth silicon carbide region) 30a: First p control region (fifth silicon carbide region) 30b Second p control region (seventh silicon carbide region) 32a First n control region (sixth silicon carbide region) 32b Second n control region (eighth silicon carbide region) 34 Body region (9th silicon carbide region) 35 source region (14th silicon carbide region) 36a: first n-contact region (tenth silicon carbide region) 36b second n-contact region (twelfth silicon carbide region) 38a: first p-contact region (eleventh silicon carbide region) 38b: second p-contact region (thirteenth silicon carbide region) 100 MOSFET (semiconductor device) 200 MOSFET (semiconductor device) 300 MOSFET (semiconductor device) 400 MOSFET (semiconductor device) 500 MOSFET (semiconductor device) F1 First Side F2 Second side

Claims

1. a silicon carbide layer having a first surface parallel to a first direction and a second direction orthogonal to the first direction, and a second surface opposite to the first surface; a first trench provided in the silicon carbide layer on a side of the first surface and extending in the first direction; a second trench provided in the silicon carbide layer on a side of the first surface, in the second direction relative to the first trench, and extending in the first direction; a first gate electrode disposed in the first trench; a second gate electrode disposed in the second trench; a first gate insulating layer provided between the first gate electrode and the silicon carbide layer; a second gate insulating layer provided between the second gate electrode and the silicon carbide layer; a first silicon carbide region of a first conductivity type provided in the silicon carbide layer and extending in the second direction; a second silicon carbide region of a second conductivity type provided in the silicon carbide layer, extending in the second direction and positioned in the first direction relative to the first silicon carbide region; a third silicon carbide region of the first conductivity type provided in the silicon carbide layer, extending in the second direction and positioned in the first direction relative to the second silicon carbide region; a fourth silicon carbide region of the second conductivity type provided in the silicon carbide layer, extending in the second direction and positioned in the first direction relative to the third silicon carbide region; a fifth silicon carbide region of a first conductivity type provided in the silicon carbide layer, extending in the second direction, located between the first silicon carbide region and the first surface, located in a third direction perpendicular to the first surface with respect to the first silicon carbide region, located between the first trench and the second trench and the second surface, and having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the first silicon carbide region; a sixth silicon carbide region of a second conductivity type provided in the silicon carbide layer, extending in the second direction, located between the second silicon carbide region and the first surface, located in the third direction relative to the second silicon carbide region, located between the first trench and the second trench and the second surface, and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the second silicon carbide region; a seventh silicon carbide region of a first conductivity type provided in the silicon carbide layer, extending in the second direction, located between the third silicon carbide region and the first surface, located in the third direction relative to the third silicon carbide region, located between the first trench and the second trench and the second surface, and having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the third silicon carbide region; an eighth silicon carbide region of a second conductivity type provided in the silicon carbide layer, extending in the second direction, located between the fourth silicon carbide region and the first surface, located in the third direction relative to the fourth silicon carbide region, located between the first trench and the second trench and the second surface, and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the fourth silicon carbide region; a ninth silicon carbide region of the first conductivity type provided in the silicon carbide layer and positioned between the fifth silicon carbide region and the first surface, between the sixth silicon carbide region and the first surface, between the seventh silicon carbide region and the first surface, between the eighth silicon carbide region and the first surface, and between the first trench and the second trench; a tenth silicon carbide region of the second conductivity type provided in the silicon carbide layer and located between the ninth silicon carbide region and the first surface and between the first trench and the second trench; an eleventh silicon carbide region of a first conductivity type provided in the silicon carbide layer, the eleventh silicon carbide region being located between the ninth silicon carbide region and the first surface, and between the first trench and the second trench, the eleventh silicon carbide region having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the ninth silicon carbide region; a first electrode provided on the first surface side of the silicon carbide layer and in contact with the tenth silicon carbide region and the eleventh silicon carbide region; a second electrode provided on the second surface side of the silicon carbide layer; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein a distance in the first direction between the fifth silicon carbide region and the seventh silicon carbide region is smaller than a distance in the first direction between the first silicon carbide region and the third silicon carbide region.

3. the eleventh silicon carbide region is located in the first direction relative to the tenth silicon carbide region; the tenth silicon carbide region is located in the third direction relative to the fifth silicon carbide region; 3 . The semiconductor device according to claim 1 , wherein the eleventh silicon carbide region is located in the third direction relative to the sixth silicon carbide region.

4. a twelfth silicon carbide region of the second conductivity type provided in the silicon carbide layer, the twelfth silicon carbide region being located between the ninth silicon carbide region and the first surface, between the first trench and the second trench, and located in the third direction relative to the seventh silicon carbide region; a thirteenth silicon carbide region of the first conductivity type provided in the silicon carbide layer, the thirteenth silicon carbide region being located between the ninth silicon carbide region and the first surface, the thirteenth silicon carbide region being located between the first trench and the second trench, and the eighth silicon carbide region being located in the third direction; The semiconductor device according to claim 3 further comprising:

5. a fourteenth silicon carbide region of a second conductivity type provided in the silicon carbide layer, located between the ninth silicon carbide region and the first surface, extending in the first direction, located between the first trench and the tenth silicon carbide region, located between the first trench and the eleventh silicon carbide region, located between the first trench and the twelfth silicon carbide region, and located between the first trench and the thirteenth silicon carbide region, and having a second conductivity type impurity concentration lower than a second conductivity type impurity concentration of the tenth silicon carbide region; The semiconductor device according to claim 4, further comprising:

6. a silicon carbide layer having a first surface parallel to a first direction and a second direction orthogonal to the first direction, and a second surface opposite to the first surface; a first trench provided in the silicon carbide layer on a side of the first surface and extending in the first direction; a second trench provided in the silicon carbide layer on a side of the first surface, in the second direction relative to the first trench, and extending in the first direction; a first gate electrode disposed in the first trench; a second gate electrode disposed in the second trench; a first gate insulating layer provided between the first gate electrode and the silicon carbide layer; a second gate insulating layer provided between the second gate electrode and the silicon carbide layer; a first silicon carbide region of a first conductivity type provided in the silicon carbide layer and extending in the first direction; a second silicon carbide region of a second conductivity type provided in the silicon carbide layer, extending in the first direction and positioned in the second direction relative to the first silicon carbide region; a third silicon carbide region of the first conductivity type provided in the silicon carbide layer, extending in the first direction and positioned in the second direction relative to the second silicon carbide region; a fourth silicon carbide region of the second conductivity type provided in the silicon carbide layer, extending in the first direction and positioned in the second direction relative to the third silicon carbide region; a fifth silicon carbide region of a first conductivity type provided in the silicon carbide layer, extending in the second direction, located between the first silicon carbide region and the first surface, located between the second silicon carbide region and the first surface, located between the third silicon carbide region and the first surface, located between the fourth silicon carbide region and the first surface, and located between the first trench, the second trench, and the second surface, and having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the first silicon carbide region; a sixth silicon carbide region of a second conductivity type provided in the silicon carbide layer, extending in the second direction, located between the first silicon carbide region and the first surface, located between the second silicon carbide region and the first surface, located between the third silicon carbide region and the first surface, located between the fourth silicon carbide region and the first surface, and located between the first trench, the second trench, and the second surface, and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the second silicon carbide region; a seventh silicon carbide region of a first conductivity type provided in the silicon carbide layer, extending in the second direction, located between the first silicon carbide region and the first surface, located between the second silicon carbide region and the first surface, located between the third silicon carbide region and the first surface, located between the fourth silicon carbide region and the first surface, and located between the first trench, the second trench, and the second surface, and having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the first silicon carbide region; an eighth silicon carbide region of a second conductivity type provided in the silicon carbide layer, extending in the second direction, located between the first silicon carbide region and the first surface, located between the second silicon carbide region and the first surface, located between the third silicon carbide region and the first surface, located between the fourth silicon carbide region and the first surface, and located between the first trench, the second trench, and the second surface, and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the second silicon carbide region; a ninth silicon carbide region of the first conductivity type provided in the silicon carbide layer and positioned between the fifth silicon carbide region and the first surface, between the sixth silicon carbide region and the first surface, between the seventh silicon carbide region and the first surface, between the eighth silicon carbide region and the first surface, and between the first trench and the second trench; a tenth silicon carbide region of the second conductivity type provided in the silicon carbide layer and located between the ninth silicon carbide region and the first surface and between the first trench and the second trench; an eleventh silicon carbide region of a first conductivity type provided in the silicon carbide layer, the eleventh silicon carbide region being located between the ninth silicon carbide region and the first surface, and between the first trench and the second trench, the eleventh silicon carbide region having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the ninth silicon carbide region; a first electrode provided on the first surface side of the silicon carbide layer and in contact with the tenth silicon carbide region and the eleventh silicon carbide region; a second electrode provided on the second surface side of the silicon carbide layer; A semiconductor device comprising:

7. the eleventh silicon carbide region is located in the first direction relative to the tenth silicon carbide region; the tenth silicon carbide region is located in a third direction perpendicular to the first surface with respect to the fifth silicon carbide region; The semiconductor device according to claim 6 , wherein the eleventh silicon carbide region is located in the third direction relative to the sixth silicon carbide region.

8. the first trench is located in a third direction perpendicular to the first surface with respect to the first silicon carbide region; The semiconductor device according to claim 6 , wherein the ninth silicon carbide region is located in the third direction relative to the second silicon carbide region.

9. 8. The semiconductor device according to claim 6, wherein a distance in the second direction between the first silicon carbide region and the fourth silicon carbide region is greater than a distance in the first direction between the fifth silicon carbide region and the eighth silicon carbide region.

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