insulated gate bipolar transistor

Abstract

Provided is an insulated gate bipolar transistor comprising: a base region provided between an emitter region and a drift region; an accumulation region provided between the base region and the drift region and having a higher doping concentration than the drift region; a gate trench portion provided on an upper surface of a semiconductor substrate under the accumulation region; and a lower end region provided in contact with a lower end of the gate trench portion. The accumulation region in a depth direction has a first concentration peak at which the doping concentration shows a maximum value, and the distance between the first concentration peak and the lower end region in the depth direction is less than the distance between the first concentration peak and the base region in the depth direction.

Description

[Technical Field]

[0001] The present invention relates to an insulated gate bipolar transistor. [Background technology]

[0002] BACKGROUND ART Conventionally, insulated gate bipolar transistors (IGBTs), a structure in which an N+ type accumulation region is provided between a P type base layer and an N type drift layer is known (see, for example, Patent Documents 1 and 2). [Prior art document] [Patent Documents] [Patent Document 1] WO2019 / 142706 [Patent Document 2] JP 2017-28250 A Problem to be Solved

[0003] If the electron injection enhancement (IE) effect is increased by increasing the concentration of the accumulation region, the clamping capability may be reduced.

[0004] To solve the above problems, a first aspect of the present invention provides an insulated gate bipolar transistor. The insulated gate bipolar transistor may include a semiconductor substrate having an upper surface and a lower surface and including a first conductivity type drift region. The insulated gate bipolar transistor may include an emitter region of the first conductivity type provided between the upper surface of the semiconductor substrate and the drift region, the emitter region having a doping concentration higher than that of the drift region. The insulated gate bipolar transistor may include a base region of a second conductivity type provided between the emitter region and the drift region. The insulated gate bipolar transistor may include an accumulation region of the first conductivity type provided between the base region and the drift region, the accumulation region having a doping concentration higher than that of the drift region. The insulated gate bipolar transistor may include a gate trench portion provided from the upper surface of the semiconductor substrate to below the accumulation region. The insulated gate bipolar transistor may include a lower end region of the second conductivity type provided in contact with the lower end of the gate trench portion. The accumulation region may have a first concentration peak at which the doping concentration in the depth direction is maximum. The distance in the depth direction between the first concentration peak and the lower end region may be smaller than the distance in the depth direction between the first concentration peak and the base region.

[0005] The accumulation region may be in contact with the base region.

[0006] Between the accumulation region and the base region, a region having the same doping concentration as the drift region may be provided.

[0007] The doping concentration of the first concentration peak is 2×10 18 / cm 3 It may be the following:

[0008] The integral concentration obtained by integrating the doping concentration of the first concentration peak in the depth direction is 1×10 15 / cm 2 That's it, 1.5 x 10 17 / cm 2 It may be the following:

[0009] The full width at half maximum of the first concentration peak in the depth direction may be 2 μm or more.

[0010] The base region may have a base concentration peak where the doping concentration exhibits a maximum value in the depth direction, and the distance in the depth direction between the first concentration peak and the base concentration peak may be 2 μm or more.

[0011] The insulated gate bipolar transistor may include a dummy trench portion provided from the upper surface of the semiconductor substrate to below the accumulation region, and the lower end region may be in contact with a lower end of the dummy trench portion.

[0012] The accumulation region may have a second concentration peak located at a position different from the first concentration peak in the depth direction and having a doping concentration equal to or lower than the first concentration peak.

[0013] The doping concentration of the second concentration peak may be less than the doping concentration of the first concentration peak, and the second concentration peak may be disposed between the first concentration peak and the base region.

[0014] The maximum doping concentration of the accumulation region may be greater than the maximum doping concentration of the bottom region.

[0015] The boundary between the lower end region and the accumulation region may be located closer to the upper surface of the semiconductor substrate than the lower end of the gate trench portion.

[0016] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a cross-sectional view showing an example of a semiconductor device 100 according to an embodiment of the present invention. [Figure 2] 2 is an enlarged view showing an example of a trench portion and a mesa portion 60 on the upper surface 21 of the semiconductor substrate 10. FIG. [Figure 3] 2 is a diagram showing an example of a doping concentration distribution in the depth direction along the line AA in FIG. 1. FIG. [Figure 4] FIG. 10 is a diagram showing a doping concentration distribution according to a comparative example. [Figure 5] 1. FIG. 4 is a diagram showing another example of the doping concentration distribution in the depth direction along the line AA in FIG. [Figure 6] 1. FIG. 4 is a diagram showing another example of the doping concentration distribution in the depth direction along the line AA in FIG. [Figure 7] 10 is a diagram illustrating another configuration example of the semiconductor device 100. FIG. [Figure 8] 2A to 2C are diagrams illustrating some steps in a manufacturing method of the semiconductor device 100. DETAILED DESCRIPTION OF THE INVENTION

[0018] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0019] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0020] In this specification, technical matters may be explained using the Cartesian coordinate axes of the X-axis, Y-axis, and Z-axis. The Cartesian coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is written without specifying positive or negative, it means the direction parallel to the +Z-axis and -Z-axis.

[0021] In this specification, orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0022] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate may be referred to as the top surface side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate may be referred to as the bottom surface side.

[0023] In this specification, when we say "same" or "equal," it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0024] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting N-type conductivity or a semiconductor exhibiting P-type conductivity.

[0025] In this specification, when P+ type or N+ type is used, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is used, it means that the doping concentration is lower than that of P type or N type. Furthermore, when P++ type or N++ type is used in this specification, it means that the doping concentration is higher than that of P+ type or N+ type. The unit system used in this specification is the SI unit system unless otherwise specified. The unit of length may be expressed in cm, but various calculations may be performed after converting to meters (m).

[0026] In this specification, the doping concentration refers to the concentration of donors or acceptors in a thermal equilibrium state. In this specification, the net doping concentration refers to the net concentration obtained by adding together the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account the polarity of the charge. As an example, the donor concentration is N D , acceptor concentration N A Then, the net doping concentration at any point is N D -N A In this specification, the net doping concentration may be simply referred to as the doping concentration.

[0027] In addition, when the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be taken as the concentration of the donor, acceptor, or net doping in that region. In cases where the concentration of the donor, acceptor, or net doping is almost uniform, the average value of the concentration of the donor, acceptor, or net doping in that region may be taken as the concentration of the donor, acceptor, or net doping. In this specification, the concentration per unit volume is expressed in atoms / cm. 3 , or / cm 3 This unit is used for the donor or acceptor concentration in a semiconductor substrate. The atoms notation may be omitted.

[0028] 1 is a cross-sectional view showing an example of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes a portion that functions as an IGBT. The cross-section of FIG. 1 shows the portion that functions as an IGBT.

[0029] The semiconductor device 100 includes a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate, but is not limited to this. The semiconductor substrate 10 may also be a compound semiconductor substrate such as silicon carbide or gallium nitride.

[0030] The semiconductor substrate 10 has an upper surface 21 and a lower surface 23. The upper surface 21 and the lower surface 23 are two main surfaces arranged opposite to each other on the semiconductor substrate 10. The semiconductor device 100 of this example is a vertical device in which a main current flows between the upper surface 21 and the lower surface 23 when the IGBT is controlled to be in the on state.

[0031] The interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with a contact hole 54 that exposes the upper surface 21 of the semiconductor substrate 10.

[0032] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 passes through a contact hole 54 in the interlayer insulating film 38 and contacts the upper surface 21 of the semiconductor substrate 10. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metal material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (the Z-axis direction) is referred to as the depth direction.

[0033] The semiconductor substrate 10 has an N-type drift region 18. The drift region 18 may be a region in the semiconductor substrate 10 that remains without being locally implanted with dopants. In other words, the semiconductor device 100 may be manufactured by locally implanting dopants into the N-type semiconductor substrate 10.

[0034] The semiconductor substrate 10 is provided with an N+ type emitter region 12, a P type base region 14, an N+ type accumulation region 16, and a P type lower end region 90 in this order from the upper surface 21 side of the semiconductor substrate 10.

[0035] The emitter region 12 is provided so as to be exposed on the upper surface 21 of the semiconductor substrate 10. The emitter region 12 is electrically connected to the emitter electrode 52 via a contact hole .

[0036] The base region 14 is provided between the emitter region 12 and the accumulation region 16. The base region 14 may have a portion exposed on the upper surface 21 of the semiconductor substrate 10. The base region 14 is electrically connected to the emitter electrode 52 via a contact hole 54.

[0037] The accumulation region 16 is provided between the base region 14 and the bottom region 90. The accumulation region 16 has a higher doping concentration than the drift region 18. By providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire bottom surface of the base region 14.

[0038] The lower end region 90 is provided between the accumulation region 16 and the drift region 18. The lower end region 90 is a floating region electrically isolated from the emitter electrode 52. The lower end region 90 is provided in contact with the lower ends of at least a portion of the gate trench portion 40 and the dummy trench portion 30 described below. In this specification, the gate trench portion 40 and the dummy trench portion 30 may be simply referred to as trench portions. The term trench portion refers to at least one of the gate trench portion 40 and the dummy trench portion 30. By providing the lower end region 90, the drift region 18 can be depleted quickly when the IGBT is turned off, thereby reducing turn-off loss (see Patent Document 2).

[0039] An N+ type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer that extends from the lower end of the base region 14 to the drift region 18 from reaching the P+ type collector region 22.

[0040] A P+ type collector region 22 is provided below the buffer region 20. The doping concentration of the collector region 22 is higher than the doping concentration of the base region 14. The collector region 22 is exposed at a lower surface 23 of the semiconductor substrate 10 and is electrically connected to a collector electrode 24.

[0041] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the upper surface 21 of the semiconductor substrate 10. In the drawings, the gate trench portions 40 may be marked with the letter "G" and the dummy trench portions 30 may be marked with the letter "E." The trench portions are arranged at predetermined intervals on the upper surface 21 of the semiconductor substrate 10 along a predetermined arrangement direction (the X-axis direction in FIG. 1). Furthermore, the trench portions extend on the upper surface 21 of the semiconductor substrate 10 so that their longitudinal axes are in a predetermined extension direction (the Y-axis direction in FIG. 1).

[0042] 1, two dummy trenches 30 are arranged between two gate trenches 40 as in G / E / E / G / ··, but one dummy trench 30 may be arranged between two gate trenches 40 as in G / E / G / E / ··. The arrangement of the gate trenches 40 and the dummy trenches 30 may have other patterns.

[0043] Each trench portion is provided from the upper surface 21 of the semiconductor substrate 10 to below the accumulation region 16. In this specification, the region inside the semiconductor substrate 10 sandwiched between two trench portions may be referred to as a mesa portion 60. Each mesa portion 60 is provided with an emitter region 12, a base region 14, and an accumulation region 16. A part of the lower end region 90 may be provided in the mesa portion 60.

[0044] The gate trench portion 40 has a gate trench provided in the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate trench is a groove provided in the upper surface 21 of the semiconductor substrate 10 and extending in a predetermined extension direction (the Y-axis direction in FIG. 1).

[0045] The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench, more inward than the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0046] The gate conductive portion 44 may be provided longer in the depth direction than the base region 14. The gate trench portion 40 in this cross section is covered with an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to a gate pad arranged above the upper surface 21 of the semiconductor substrate 10, and a gate voltage is applied to the gate conductive portion 44. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench portion 40.

[0047] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the cross section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy conductive portion 34 may be at a floating potential. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is provided further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 is formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length in the depth direction as the gate conductive portion 44. By providing the dummy trench portion 30, the IE effect can be further improved.

[0048] The above-mentioned lower end region 90 is in contact with the lower end of at least one gate trench portion 40. The lower end region 90 may be in contact with the lower ends of multiple gate trench portions 40. In FIG. 1 , the depth position of the lower end of the gate trench portion 40 is designated as Zt. The lower end region 90 may also be in contact with the lower end of at least one dummy trench portion 30. The lower end region 90 may be in contact with the lower ends of multiple dummy trench portions 30. The lower end region 90 may be provided continuously across multiple trench portions provided along the arrangement direction. The lower end region 90 may be arranged so as to cover the lower parts of multiple mesa portions 60. The lower end region 90 may be provided for all mesa portions 60.

[0049] 2 is an enlarged view showing an example of trench portions and mesa portions 60 on the upper surface 21 of the semiconductor substrate 10. As described above, each trench portion is provided extending in the Y-axis direction. The region sandwiched between each trench portion is the mesa portion 60.

[0050] The mesa portion 60 may include an emitter region 12 and a contact region 15 exposed on the upper surface 21 of the semiconductor substrate 10. The contact region 15 is a P+ type region having a higher doping concentration than the base region 14. The contact region 15 is exposed on the upper surface 21 of the semiconductor substrate 10 and is in contact with the base region 14 on its lower surface. In this example, the emitter regions 12 and the contact regions 15 are alternately arranged along the extension direction (Y-axis direction) of the trench portion. The cross section in FIG. 1 is an XZ plane passing through the emitter region 12 shown in FIG. 2.

[0051] 3 is a diagram showing an example of the doping concentration distribution in the depth direction along the line AA in FIG. 1. The horizontal axis in FIG. 3 represents the distance from the upper surface 21 of the semiconductor substrate 10, and the vertical axis represents the doping concentration ( / cm 3) is shown. The doping concentration distribution may be a distribution measured by a spreading resistance (SR) method. Line AA is a line that passes through parts of the emitter region 12, the base region 14, the accumulation region 16, the bottom region 90, and the drift region 18 and is parallel to the Z axis. In this example, the emitter region 12, the base region 14, the accumulation region 16, and the bottom region 90 are regions formed by locally implanting dopants into the N-type semiconductor substrate 10. In this specification, the maximum value of the doping concentration of each region may be taken as the doping concentration of each region.

[0052] The drift region 18 is an N-type region having a substantially constant doping concentration in the depth direction. "Substantially constant" may mean, for example, that the maximum value of the doping concentration is not more than twice the minimum value, or may mean that the maximum value is not more than 1.5 times the minimum value. In FIG. 3, the doping concentration of the drift region 18 is designated as D18. The doping concentration D18 may be the average value or the maximum value of the doping concentration of the drift region 18. The doping concentration D18 of the drift region 18 is 1×10 13 / cm 3 That's it, 1 x 10 15 / cm 3 The doping concentration D18 may be 1×10 14 / cm 3 The drift region 18 may be provided over one-third or more of the thickness of the semiconductor substrate 10 in the Z-axis direction, or may be provided over one-half or more of the thickness of the semiconductor substrate 10 in the Z-axis direction.

[0053] The emitter region 12 is an N+ type region having a higher doping concentration than the drift region 18. The emitter region 12 may have a concentration peak near the upper surface 21 of the semiconductor substrate 10. The maximum doping concentration of the emitter region 12 is 1×10 18 / cm 3 May be greater than or equal to 1 x 10 19 / cm 3 It may be more than that.

[0054] The base region 14 is a P-type region with a doping concentration higher than that of the drift region 18 and lower than that of the emitter region 12. A PN junction is formed at the boundary between the base region 14 and the emitter region 12, where the doping concentration decreases abruptly. The base region 14 may have a base concentration peak 102 near the boundary with the emitter region 12. In FIG. 3, the maximum value of the doping concentration in the base region 14 (i.e., the doping concentration at the apex of the base concentration peak 102) is designated as D14. The doping concentration D14 is 1×10 16 / cm 3 May be greater than or equal to 1 x 10 17 / cm 3 The doping concentration D14 may be 1×10 19 / cm 3 may be less than or equal to 1 x 10 18 / cm 3 It may be the following:

[0055] The bottom region 90 is a P-type region having a doping concentration higher than that of the drift region 18 and lower than that of the emitter region 12. The bottom region 90 may have a doping concentration lower than that of the base region 14. PN junctions are formed at the boundary between the bottom region 90 and the drift region and at the boundary between the bottom region 90 and the accumulation region 16, where the doping concentration decreases sharply. The bottom region 90 may have a concentration peak 101. The maximum value of the doping concentration in the bottom region 90 (i.e., the doping concentration at the apex of the concentration peak 101) is defined as D90. The doping concentration D90 is 1×10 15 / cm 3 May be greater than or equal to 1 x 10 16 / cm 3 The doping concentration D90 may be 1×10 18 / cm 3 may be less than or equal to 1 x 10 17 / cm 3 It may be the following:

[0056] The accumulation region 16 is an N+ type region having a doping concentration higher than the drift region 18 and a doping concentration lower than the emitter region 12. The accumulation region 16 may have a doping concentration higher or lower than the base region 14. The accumulation region 16 may also have a doping concentration higher or lower than the bottom region 90. PN junctions are formed at the boundary between the accumulation region 16 and the bottom region 90 and at the boundary between the accumulation region 16 and the base region 14, where the doping concentration decreases sharply. The portion sandwiched between the two PN junctions and having a doping concentration higher than the drift region 18 may be the accumulation region 16.

[0057] The accumulation region 16 has a first concentration peak 91 in the doping concentration distribution in the depth direction. A doping concentration D16 at the apex of the first concentration peak 91 is the maximum value of the doping concentration in the accumulation region 16. The first concentration peak 91 has an upper base where the doping concentration decreases from the apex toward the upper surface 21, and a lower base where the doping concentration decreases from the apex toward the lower surface 23. The accumulation region 16 of this example does not have any concentration peaks in the depth direction other than the first concentration peak 91. In other words, the accumulation region 16 has a single concentration peak in the depth direction.

[0058] The IE effect can be improved by increasing the doping concentration D16 of the accumulation region 16. On the other hand, if the doping concentration D16 is increased, the accumulation region 16 inhibits the extension of the depletion layer from the base region 14 when the semiconductor device 100 is turned off. As a result, the electric field is concentrated near the first concentration peak 91 of the accumulation region 16.

[0059] In this example, the distance Z1 in the depth direction between the first concentration peak 91 and the lower end region 90 is smaller than the distance Z2 in the depth direction between the first concentration peak 91 and the base region 14. The position of the apex of the first concentration peak 91 may be taken as the position of the first concentration peak 91 in the depth direction. The position of the PN junction between the first concentration peak 91 and the lower end region 90 may be taken as the position of the upper end of the lower end region 90. The position of the PN junction between the first concentration peak 91 and the base region 14 may be taken as the position of the lower end of the base region 14.

[0060] According to this example, since the first concentration peak 91 is located away from the base region 14, the doping concentration gradient near the PN junction becomes gentler, and the depletion layer near the base region 14 is more likely to extend. This allows the position where the electric field concentrates to be separated from the base region 14, improving the withstand voltage of the semiconductor device 100. Although the first concentration peak 91 approaches the bottom end region 90, a forward bias is applied between the bottom end region 90 and the accumulation region 16 when the semiconductor device 100 is turned off, so the withstand voltage at the time of turn-off does not deteriorate.

[0061] Distance Z1 may be 0.9 times or less, 0.7 times or less, or 0.5 times or less of distance Z2. However, if first concentration peak 91 is too close to lower end region 90, the IE effect may be suppressed. Therefore, distance Z1 may be 0.5 μm or more, 0.7 μm or more, or 1 μm or more.

[0062] Furthermore, distance Z2 may be 1 μm or more, 1.5 μm or more, or 2 μm or more. Furthermore, the distance in the Z-axis direction between the apex of base concentration peak 102 and the apex of first concentration peak 91 may be 2 μm or more, 2.5 μm or more, or 3 μm or more.

[0063] The doping concentration D16 of the first concentration peak 91 is 1×10 15 / cm 3 May be greater than or equal to 1 x 10 16 / cm 3 It is acceptable to use a doping concentration D16 of 1×10 or more. However, if the doping concentration D16 of the first concentration peak 91 becomes too high, the electric field concentration at the first concentration peak 91 will increase. If the electric field at the first concentration peak 91 reverses the electric field at the bottom end of the trench portion, the withstand voltage of the semiconductor device 100 will decrease. The doping concentration D16 is 1×10 18 / cm 3 may be less than or equal to 1 x 10 17 / cm 3 It may be the following:

[0064] The full width at half maximum W1 in the depth direction of the first concentration peak 91 may be 2 μm or more. The full width at half maximum is the width of a region that includes the apex of the first concentration peak 91 and has a doping concentration of 0.5×D16 or more. Increasing the full width at half maximum W1 makes it easier to increase the integrated concentration in the accumulation region 16 without increasing the doping concentration D16. This makes it easier to suppress local electric field concentration. The full width at half maximum W1 may be 2.5 μm or more, or may be 3 μm or more. The full width at half maximum W1 may also be half or more of the distance from the base region 14 to the lower end region 90 (Z1+Z2 in FIG. 3).

[0065] The integral concentration obtained by integrating the doping concentration of the first concentration peak 91 in the depth direction is 1×10 15 / cm 2 That's it, 1.5 x 10 17 / cm 2 The integral concentration may be 5×10 15 / cm 2 The integral concentration may be 1×10 17 / cm 2 The integrated concentration may be a value obtained by integrating the doping concentration within the range of the full width at half maximum W1 of the first concentration peak 91. If the integrated concentration is low, the IE effect will be low, and if the integrated concentration is high, the withstand voltage will be easily reduced.

[0066] When the clamp withstand capability at turn-off of a semiconductor device 100 in which the doping concentration D16 of the first concentration peak 91 is greater than the doping concentration D90 of the lower end region 90 is compared with that of a semiconductor device 100 in which the doping concentration D16 of the first concentration peak 91 is less than the doping concentration D90 of the lower end region 90, the former has a better withstand capability. The doping concentration D16 of the first concentration peak 91 is preferably greater than the doping concentration D90 of the lower end region 90. The doping concentration D16 may be 1.5 times or more, 2 times or more, or 5 times or more the doping concentration D90.

[0067] The accumulation region 16 may also be in contact with the base region 14. In other words, the drift region 18 does not remain between the accumulation region 16 and the base region 14, and no region with the same doping concentration D18 as the drift region 18 is provided. Similarly, the accumulation region 16 may be in contact with the bottom region 90. In other words, the drift region 18 does not remain between the accumulation region 16 and the bottom region 90, and no region with the same doping concentration D18 as the drift region 18 is provided. However, the spike-shaped doping concentration distribution in the PN junction portion between each region may include a point with the doping concentration D18.

[0068] 3, the depth position of the boundary between the lower end region 90 and the accumulation region 16 is designated as Zj. If the accumulation region 16 is formed below the lower end of the gate trench portion 40, the static breakdown voltage of the semiconductor device 100 will decrease. The depth position Zj may be located closer to the upper surface 21 of the semiconductor substrate 10 than the depth position Zt of the lower end of the gate trench portion 40. The distance in the Z-axis direction between the depth position Zj and the depth position Zt may be 0.1 μm or more, 0.2 μm or more, or 0.3 μm or more.

[0069] 4 is a diagram showing the doping concentration distribution according to the comparative example. In this example, the distance Z2 is shorter than the distance Z1. That is, the first concentration peak 91 is located near the base region 14. In addition, a region 110 having the same doping concentration as the drift region 18 is provided between the accumulation region 16 and the bottom region 90.

[0070] In the semiconductor device of this example, the first concentration peak 91 is located near the base region 14. Therefore, the clamping withstand voltage at turn-off of the semiconductor device is smaller than the clamping withstand voltage at turn-off of the semiconductor device 100 of the example shown in FIG.

[0071] Fig. 5 is a diagram showing another example of the doping concentration distribution in the depth direction along line AA in Fig. 1. The doping concentration distribution of this example differs from the example of Fig. 3 in that it includes a region 110. Other than the region 110, it is the same as the example of Fig. 3.

[0072] Region 110 is disposed between accumulation region 16 and base region 14. Region 110 has the same doping concentration as drift region 18. Note that a doping concentration with an error of ±10% or less with respect to doping concentration D18 may be set to the same doping concentration as drift region 18. Region 110 may be a region in which drift region 18 remains without base region 14 and accumulation region 16 being formed. The length of region 110 in the Z-axis direction is defined as Z3. Length Z3 may be 0.3 μm or more, or may be 0.5 μm or more.

[0073] Providing the region 110 makes it easier to increase the distance between the first concentration peak 91 and the base region 14. This improves the clamping resistance of the semiconductor device 100 when it is turned off.

[0074] Fig. 6 is a diagram showing another example of the doping concentration distribution in the depth direction along line AA in Fig. 1. The doping concentration distribution of this example differs from the example of Fig. 3 in that it has a second concentration peak 92. Other than the second concentration peak 92, it is the same as the example of Fig. 3. In this example as well, the region 110 shown in Fig. 5 may be provided.

[0075] The second concentration peak 92 is located at a different position in the depth direction from the first concentration peak 91. The position of each concentration peak may be determined by using the position of its apex. The apex of the second concentration peak 92 may be located within the range of the full width at half maximum W1 of the first concentration peak 91. In other words, the doping concentration in the region between the first concentration peak 91 and the second concentration peak 92 is greater than 0.5 times the doping concentration of the first concentration peak 91. The apex of the second concentration peak 92 may be located outside the range of the full width at half maximum W1 of the first concentration peak 91.

[0076] The doping concentration D16-2 of the second concentration peak 92 is equal to or less than the doping concentration D16-1 of the first concentration peak 91. In the example of Fig. 6, the doping concentration D16-2 is less than the doping concentration D16-1. The doping concentration D16-2 may be equal to or greater than 0.1 times the doping concentration D16-1, or may be equal to or greater than 0.5 times the doping concentration D16-1.

[0077] By providing the second concentration peak 92, it becomes easier to reduce each concentration peak while maintaining the integrated concentration in the accumulation region 16. Therefore, it is possible to alleviate the electric field concentration on one concentration peak.

[0078] The second concentration peak 92 may be located between the first concentration peak 91 and the base region 14. In other words, a larger concentration peak may be located farther away from the base region 14. This allows the position where an electric field is likely to concentrate to be moved away from the base region 14. The accumulation region 16 may have three or more concentration peaks in the depth direction. In this case, the doping concentration may be increased as the concentration peak is farther away from the base region 14.

[0079] 7 is a diagram showing another configuration example of the semiconductor device 100. The semiconductor device 100 of this example includes a transistor section 70 and a diode section 80. The semiconductor device 100 of this example is a reverse conducting IGBT (RC-IGBT) in which an IGBT and a free wheeling diode are connected in antiparallel.

[0080] The transistor sections 70 and the diode sections 80 may be arranged alternately along the X-axis direction. The transistor sections 70 have the same structure as the semiconductor device 100 described with reference to FIG.

[0081] In the diode section 80, a P-type base region 14, an N+-type accumulation region 16, and a P-type bottom region 90 are provided in this order from the top surface 21 of the semiconductor substrate 10. In the diode section 80, the base region 14 may be exposed at the top surface 21 of the semiconductor substrate 10. In another example, a P+-type contact region 15 may be provided between the base region 14 and the top surface 21. The accumulation region 16 and the bottom region 90 in the diode section 80 are similar to the accumulation region 16 and the bottom region 90 in the transistor section 70. In other words, the diode section 80 may have the doping concentration distribution described with reference to FIG. 3, FIG. 5, or FIG. 6, except that the emitter region 12 is not provided.

[0082] The diode section 80 has an N+ type cathode region 82 instead of the collector region 22 of the transistor section 70. The doping concentration of the cathode region 82 is higher than the doping concentration of the drift region 18. The cathode region 82 is exposed at the lower surface 23 of the semiconductor substrate 10 and is electrically connected to the collector electrode 24.

[0083] In the diode section 80, one or more dummy trench sections 30 are provided on the upper surface 21 of the semiconductor substrate 10. The diode section 80 does not need to be provided with a gate trench section 40. In the diode section 80, the lower end region 90 is in contact with the lower end of at least one dummy trench section 30. The lower end region 90 may be in contact with the lower ends of multiple dummy trench sections 30.

[0084] 7 illustrates the structure of an RC-IGBT, but the semiconductor device 100 may also be a reverse-blocking IGBT (RB-IGBT). An RB-IGBT is a semiconductor device 100 in which a P-type region is formed in a region that contacts the side surface of the semiconductor substrate 10 so that the PN junction is not exposed on the side surface of the semiconductor substrate 10. The structure other than the P-type region is the same as that of the semiconductor device 100 described in FIGS. 1 to 6.

[0085] Fig. 8 is a diagram showing some steps in the manufacturing method of the semiconductor device 100. Fig. 8 shows the steps of forming the base region 14 and the accumulation region 16. Structures other than the base region 14 and the accumulation region 16 may be formed before or after the steps shown in Fig. 8.

[0086] First, in a first implantation step S802, dopant ions for forming the base region 14 are implanted into the upper surface 21 of the semiconductor substrate 10. The dopant ions are, for example, boron ions, but are not limited to this.

[0087] Next, in a second implantation step S804, dopant ions for forming the accumulation region 16 are implanted from the upper surface 21 of the semiconductor substrate 10. The dopant ions are, for example, but not limited to, phosphorus or nitrogen. In the second implantation step S804, the dopant ions are implanted at a position where the apex of the first concentration peak 91 described with reference to FIG. 3 etc. should be formed.

[0088] Next, in annealing step S806, the semiconductor substrate 10 is annealed. The semiconductor substrate 10 does not need to be annealed between the first implantation step S802 and the second implantation step S804. That is, in annealing step S806, the dopants for forming the base region 14 and the dopants for forming the accumulation region 16 are diffused and activated. By such processing, the base region 14 and the accumulation region 16 can be formed. Note that the semiconductor substrate 10 may be annealed between the first implantation step S802 and the second implantation step S804.

[0089] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0090] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0091] 10 semiconductor substrate, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 18 drift region, 20 buffer region, 21 upper surface, 22 collector region, 23 lower surface, 24 collector electrode, 30 dummy trench portion, 32 dummy insulating film, 34 dummy conductive portion, 38 interlayer insulating film, 40 gate trench 1. A semiconductor device comprising: a first concentration peak; a second concentration peak; a base concentration peak; and a region including a first mesa portion, a second concentration peak, and a second concentration peak.

Claims

1. a semiconductor substrate having an upper surface and a lower surface and provided with a drift region of a first conductivity type; an emitter region of a first conductivity type provided between the upper surface of the semiconductor substrate and the drift region, the emitter region having a doping concentration higher than that of the drift region; a base region of a second conductivity type provided between the emitter region and the drift region; an accumulation region of a first conductivity type provided between the base region and the drift region and having a doping concentration higher than that of the drift region; a gate trench portion provided from the upper surface of the semiconductor substrate to below the accumulation region; a second conductivity type lower end region provided in contact with a lower end of the gate trench portion; Equipped with the accumulation region has a first concentration peak at which the doping concentration exhibits a maximum value in a depth direction; a distance in the depth direction between the first concentration peak and the bottom end region is smaller than a distance in the depth direction between the first concentration peak and the base region; The accumulation region is in contact with the base region. Insulated gate bipolar transistor.

2. a semiconductor substrate having an upper surface and a lower surface and provided with a drift region of a first conductivity type; an emitter region of a first conductivity type provided between the upper surface of the semiconductor substrate and the drift region, the emitter region having a doping concentration higher than that of the drift region; a base region of a second conductivity type provided between the emitter region and the drift region; an accumulation region of a first conductivity type provided between the base region and the drift region and having a doping concentration higher than that of the drift region; a gate trench portion provided from the upper surface of the semiconductor substrate to below the accumulation region; a second conductivity type lower end region provided in contact with a lower end of the gate trench portion; Equipped with the accumulation region has a first concentration peak at which the doping concentration exhibits a maximum value in a depth direction; a distance in the depth direction between the first concentration peak and the bottom end region is smaller than a distance in the depth direction between the first concentration peak and the base region; The integral concentration obtained by integrating the doping concentration of the first concentration peak in the depth direction is 1×10 １５ / cm ２ That's it, 1.5 x 10 １７ / cm ２ is Insulated gate bipolar transistor.

3. a semiconductor substrate having an upper surface and a lower surface and provided with a drift region of a first conductivity type; an emitter region of a first conductivity type provided between the upper surface of the semiconductor substrate and the drift region, the emitter region having a doping concentration higher than that of the drift region; a base region of a second conductivity type provided between the emitter region and the drift region; an accumulation region of a first conductivity type provided between the base region and the drift region and having a doping concentration higher than that of the drift region; a gate trench portion provided from the upper surface of the semiconductor substrate to below the accumulation region; a second conductivity type lower end region provided in contact with a lower end of the gate trench portion; Equipped with the accumulation region has a first concentration peak at which the doping concentration exhibits a maximum value in a depth direction; a distance in the depth direction between the first concentration peak and the bottom end region is smaller than a distance in the depth direction between the first concentration peak and the base region; the accumulation region is in contact with the bottom region; The maximum value of the doping concentration of the accumulation region is greater than the maximum value of the doping concentration of the bottom region. Insulated gate bipolar transistor.

4. a semiconductor substrate having an upper surface and a lower surface and provided with a drift region of a first conductivity type; an emitter region of a first conductivity type provided between the upper surface of the semiconductor substrate and the drift region, the emitter region having a doping concentration higher than that of the drift region; a base region of a second conductivity type provided between the emitter region and the drift region; an accumulation region of a first conductivity type provided between the base region and the drift region and having a doping concentration higher than that of the drift region; a gate trench portion provided from the upper surface of the semiconductor substrate to below the accumulation region; a second conductivity type lower end region provided in contact with a lower end of the gate trench portion; Equipped with the accumulation region has a first concentration peak at which the doping concentration exhibits a maximum value in a depth direction; a distance in the depth direction between the first concentration peak and the bottom end region is smaller than a distance in the depth direction between the first concentration peak and the base region; a full width at half maximum of the first concentration peak in the depth direction is equal to or greater than half the distance in the depth direction from the base region to the bottom region; Insulated gate bipolar transistor.

5. a semiconductor substrate having an upper surface and a lower surface and provided with a drift region of a first conductivity type; an emitter region of a first conductivity type provided between the upper surface of the semiconductor substrate and the drift region, the emitter region having a doping concentration higher than that of the drift region; a base region of a second conductivity type provided between the emitter region and the drift region; an accumulation region of a first conductivity type provided between the base region and the drift region and having a doping concentration higher than that of the drift region; a gate trench portion provided from the upper surface of the semiconductor substrate to below the accumulation region; a second conductivity type lower end region provided in contact with a lower end of the gate trench portion; Equipped with the accumulation region has a first concentration peak at which the doping concentration exhibits a maximum value in a depth direction; a distance in the depth direction between the first concentration peak and the bottom end region is smaller than a distance in the depth direction between the first concentration peak and the base region; The gate trench portion is a gate conductive portion to which a gate voltage is applied; a gate insulating film insulating the gate conductive portion from the semiconductor substrate; and the lower end region is provided in the depth direction from a lower end of the gate conductive portion to the upper surface side of the semiconductor substrate, The maximum value of the doping concentration of the accumulation region is greater than the maximum value of the doping concentration of the bottom region. Insulated gate bipolar transistor.

6. A semiconductor substrate having an upper surface and a lower surface and having a first conductivity type drift region provided therein; an emitter region of a first conductivity type provided between the upper surface of the semiconductor substrate and the drift region, the emitter region having a doping concentration higher than that of the drift region; a base region of a second conductivity type provided between the emitter region and the drift region; an accumulation region of a first conductivity type provided between the base region and the drift region and having a doping concentration higher than that of the drift region; a gate trench portion provided from the upper surface of the semiconductor substrate to below the accumulation region; a second conductivity type lower end region provided in contact with a lower end of the gate trench portion; Equipped with the accumulation region has a first concentration peak at which the doping concentration exhibits a maximum value in a depth direction; a distance in the depth direction between the first concentration peak and the bottom end region is smaller than a distance in the depth direction between the first concentration peak and the base region; the accumulation region is in contact with the bottom region; The full width at half maximum of the first concentration peak in the depth direction is 2 μm or more. Insulated gate bipolar transistor.

7. A semiconductor substrate having an upper surface and a lower surface and having a first conductivity type drift region provided therein; an emitter region of a first conductivity type provided between the upper surface of the semiconductor substrate and the drift region, the emitter region having a doping concentration higher than that of the drift region; a base region of a second conductivity type provided between the emitter region and the drift region; an accumulation region of a first conductivity type provided between the base region and the drift region and having a doping concentration higher than that of the drift region; a gate trench portion provided from the upper surface of the semiconductor substrate to below the accumulation region; a second conductivity type lower end region provided in contact with a lower end of the gate trench portion; Equipped with the accumulation region has a first concentration peak at which the doping concentration exhibits a maximum value in a depth direction; a distance in the depth direction between the first concentration peak and the bottom end region is smaller than a distance in the depth direction between the first concentration peak and the base region; The gate trench portion is a gate conductive portion to which a gate voltage is applied; a gate insulating film insulating the gate conductive portion from the semiconductor substrate; and the lower end region is provided in the depth direction from a lower end of the gate conductive portion to the upper surface side of the semiconductor substrate, The full width at half maximum of the first concentration peak in the depth direction is 2 μm or more. Insulated gate bipolar transistor.

8. A region having the same doping concentration as the drift region is provided between the accumulation region and the base region.

5. The insulated gate bipolar transistor according to claim 4.

9. The doping concentration of the first concentration peak is 2×10 １８ / cm ３ is 5. The insulated gate bipolar transistor according to claim 4.

10. The full width at half maximum of the first concentration peak in the depth direction is 2 μm or more.

5. The insulated gate bipolar transistor according to claim 4.

11. the base region has a base concentration peak at which the doping concentration exhibits a maximum value in a depth direction; The distance between the first concentration peak and the base concentration peak in the depth direction is 2 μm or more.

5. The insulated gate bipolar transistor according to claim 4.

12. a dummy trench portion provided from the upper surface of the semiconductor substrate to below the accumulation region, The lower end region is in contact with the lower end of the dummy trench portion.

5. The insulated gate bipolar transistor according to claim 4.

13. The accumulation region further has a second concentration peak that is disposed at a position different from the first concentration peak in the depth direction and has a doping concentration equal to or lower than the first concentration peak.

13. The insulated gate bipolar transistor of claim 1, 2, 4, or 6 to 12.

14. the doping concentration of the second concentration peak is less than the doping concentration of the first concentration peak; The second concentration peak is disposed between the first concentration peak and the base region.

14. The insulated gate bipolar transistor of claim 13.

15. The boundary between the lower end region and the accumulation region is located closer to the upper surface of the semiconductor substrate than the lower end of the gate trench portion.

13. The insulated gate bipolar transistor of claim 1, 2, 4, or 6 to 12.

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