Quantum device, quantum computer, and method for manufacturing quantum device

Abstract

A quantum device (1) has: a substrate (10); a two-dimensional topological insulator layer (23) provided on the substrate; a first protective layer (21) for covering the two-dimensional topological insulator layer; an opening (25) which is provided to the first protective layer and through which a side surface of the two-dimensional topological insulator layer is exposed; and, a superconductor layer (30) which is provided in the opening and contacts the side surface of the two-dimensional topological insulator layer.

Description

[Technical Field]

[0001] The present disclosure relates to quantum devices, quantum computers, and methods for manufacturing quantum devices. [Background technology]

[0002] Research is being conducted into quantum computers using Majorana quasiparticles. A technique using two-dimensional topological insulators has been proposed as a technique for generating Majorana quasiparticles. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2020 / 0356887 Summary of the Invention [Problem to be solved by the invention]

[0004] Conventional techniques using two-dimensional topological insulators have difficulty in achieving stable properties.

[0005] An object of the present disclosure is to provide a quantum device, a quantum computer, and a method for manufacturing a quantum device that can easily stabilize characteristics. [Means for solving the problem]

[0006] According to one aspect of the present disclosure, there is provided a quantum device including: a substrate; a two-dimensional topological insulator layer provided on the substrate; a first protective layer covering the two-dimensional topological insulator layer; an opening provided in the first protective layer and exposing a side surface of the two-dimensional topological insulator layer; and a superconductor layer provided in the opening and in contact with the side surface of the two-dimensional topological insulator layer. [Effects of the Invention]

[0007] According to the present disclosure, characteristics can be easily stabilized. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a top view showing the quantum device according to the first embodiment. [Figure 2] FIG. 2 is a cross-sectional view showing the quantum device according to the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view (part 1) illustrating the method for manufacturing the quantum device according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view (part 2) illustrating the method for manufacturing the quantum device according to the first embodiment. [Figure 5] FIG. 5 is a cross-sectional view (part 3) illustrating the method for manufacturing the quantum device according to the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view (part 4) illustrating the method for manufacturing the quantum device according to the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view (part 5) illustrating the method for manufacturing the quantum device according to the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 6) illustrating the method for manufacturing the quantum device according to the first embodiment. [Figure 9] FIG. 9 is a cross-sectional view (part 7) illustrating the method for manufacturing the quantum device according to the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view (part 8) illustrating the method for manufacturing the quantum device according to the first embodiment. [Figure 11] FIG. 11 is a top view (part 1) illustrating the method for manufacturing the quantum device according to the first embodiment. [Figure 12] FIG. 12 is a top view (part 2) illustrating the method for manufacturing the quantum device according to the first embodiment. [Figure 13] FIG. 13 is a top view (part 3) illustrating the method for manufacturing the quantum device according to the first embodiment. [Figure 14] FIG. 14 is a top view (part 4) illustrating the method for manufacturing the quantum device according to the first embodiment. [Figure 15] FIG. 15 is a top view (part 5) illustrating the method for manufacturing the quantum device according to the first embodiment. [Figure 16] FIG. 16 is a top view (part 6) illustrating the method for manufacturing the quantum device according to the first embodiment. [Figure 17] FIG. 17 is a top view showing the quantum device according to the second embodiment. [Figure 18] FIG. 18 is a top view (part 1) illustrating the method for manufacturing a quantum device according to the second embodiment. [Figure 19] FIG. 19 is a top view (part 2) illustrating the method for manufacturing a quantum device according to the second embodiment. [Figure 20] FIG. 20 is a top view (part 3) illustrating the method for manufacturing a quantum device according to the second embodiment. [Figure 21] FIG. 21 is a top view (part 4) illustrating the method for manufacturing a quantum device according to the second embodiment. [Figure 22] FIG. 22 is a top view (part 5) illustrating the method for manufacturing a quantum device according to the second embodiment. [Figure 23] FIG. 23 is a top view (part 6) illustrating the method for manufacturing a quantum device according to the second embodiment. [Figure 24] FIG. 24 is a cross-sectional view showing the quantum device according to the third embodiment. [Figure 25] FIG. 25 is a cross-sectional view (part 1) illustrating the method for manufacturing the quantum device according to the third embodiment. [Figure 26] FIG. 26 is a cross-sectional view (part 2) illustrating the method for manufacturing the quantum device according to the third embodiment. [Figure 27] FIG. 27 is a cross-sectional view (part 3) illustrating the method for manufacturing the quantum device according to the third embodiment. [Figure 28] FIG. 28 is a diagram illustrating a quantum computer according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description may be omitted.

[0010] (First embodiment) First, a first embodiment will be described. The first embodiment relates to a quantum device including a two-dimensional topological insulator. FIG. 1 is a top view showing the quantum device according to the first embodiment. FIG. 2 is a cross-sectional view showing the quantum device according to the first embodiment. FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIG. 1.

[0011] 1 and 2, the quantum device 1 according to the first embodiment includes a substrate 10, a stack 120, a superconductor layer 30, magnetic layers 141 and 142, a gate insulating layer 91, and a gate electrode 92. Note that the gate insulating layer 91 and the gate electrode 92 are omitted from FIG.

[0012] The substrate 10 includes a Si substrate 11 and a Si oxide film 12 formed on the Si substrate 11. The substrate 10 may be an insulating substrate.

[0013] The stack 120 includes a first protective layer 21, a second protective layer 22, and a two-dimensional topological insulator layer 23. The two-dimensional topological insulator layer 23 is, for example, a single layer of 1T'-2 tungsten telluride (WTe2). The two-dimensional topological insulator layer 23 may also be a single layer of 1T'-2 tungsten selenide (WSe2) or 1T'-2 molybdenum telluride (MoTe2). The thickness of the two-dimensional topological insulator layer 23 is, for example, approximately 1 nm. The two-dimensional topological insulator layer 23 has an edge 23E. The first protective layer 21 and the second protective layer 22 include, for example, hexagonal boron nitride (h-BN). The first protective layer 21 and the second protective layer 22 may be h-BN layers. The h-BN layer is an example of a layered material layer. The thickness of the first protective layer 21 and the second protective layer 22 is, for example, approximately 10 nm to 20 nm. The first protective layer 21 covers one surface (first surface) of the two-dimensional topological insulator layer 23, and the second protective layer 22 covers the other surface (second surface) of the two-dimensional topological insulator layer 23. The first protective layer 21 and the second protective layer 22 are in contact with each other around the entire periphery of the two-dimensional topological insulator layer 23, outside the edge 23E of the two-dimensional topological insulator layer 23. The stacked body 120 is provided on the substrate 10, with the two-dimensional topological insulator layer 23 closer to the substrate 10 than the first protective layer 21. The second protective layer 22 is in contact with the substrate 10.

[0014] An opening 25 is formed in the laminate 120. The opening 25 penetrates the first protective layer 21. The side surface of the two-dimensional topological insulator layer 23 is exposed in the opening 25. In plan view, a recess 24 that constitutes the opening 25 is formed in the two-dimensional topological insulator layer 23. The opening 25 may reach the second protective layer 22, or the bottom surface of the opening 25 may be closer to the substrate 10 than the top surface of the second protective layer 22.

[0015] Openings 26 and 27 are formed in the stack 120. The openings 26 and 27 penetrate the first protective layer 21. The openings 26 and 27 may reach the second protective layer 22, and the bottom surfaces of the openings 26 and 27 may be closer to the substrate 10 than the top surface of the second protective layer 22. The opening 26 is formed along the edge 23E of the two-dimensional topological insulator layer 23, away from the opening 25 on one side. The opening 27 is formed along the edge 23E of the two-dimensional topological insulator layer 23, away from the opening 25 on the other side. The opening 25 is located between the openings 26 and 27. The openings 26 and 27 are away from the edge 23E.

[0016] The superconductor layer 30 is provided within the opening 25. The superconductor layer 30 contacts the side surface of the two-dimensional topological insulator layer 23, and the side surface of the two-dimensional topological insulator layer 23 exposed in the opening 25 is covered with the superconductor layer 30. The superconductor layer 30 may protrude above the upper surface of the first protective layer 21. The superconductor layer 30 is, for example, a tungsten (W) layer. The thickness of the superconductor layer 30 is, for example, about 10 nm to 30 nm.

[0017] The magnetic layer 141 is provided in the opening 26. The magnetic layer 142 is provided in the opening 27. The magnetic layers 141 and 142 generate a magnetic field that extends to the two-dimensional topological insulator layer 23. The magnetic layers 141 and 142 are away from the edge 23E of the two-dimensional topological insulator layer 23 and are not in contact with the two-dimensional topological insulator layer 23. The magnetic layers 141 and 142 are, for example, cobalt (Co) layers.

[0018] A gate insulating layer 91 is provided on the substrate 10 so as to cover the stack 120 and the superconductor layer 30. A gate electrode 92 is provided on the gate insulating layer 91. The gate insulating layer 91 is, for example, a thin film layer of silicon nitride (Si3N4), silicon dioxide (SiO2), or hexagonal boron nitride. The gate electrode 92 is, for example, a gold (Au) electrode.

[0019] In the quantum device 1, an edge channel is formed at the edge 23E by the edge states of the two-dimensional topological insulator layer 23. Then, a Majorana quasiparticle γ1 appears in a portion closer to the magnetic layer 141 than the superconductor layer 30, and a Majorana quasiparticle γ2 appears in a portion closer to the magnetic layer 142 than the superconductor layer 30. The Majorana quasiparticle γ1 is confined in the vicinity of the superconductor layer 30 due to the influence of the magnetic field generated by the magnetic layer 141, and the Majorana quasiparticle γ2 is confined in the vicinity of the superconductor layer 30 due to the influence of the magnetic field generated by the magnetic layer 142.

[0020] The distance between the superconductor layer 30 and the magnetic layers 141, 142 is, for example, about 50 nm to 500 nm.

[0021] Next, a method for manufacturing the quantum device 1 according to the first embodiment will be described. Figures 3 to 10 are cross-sectional views showing the method for manufacturing the quantum device 1 according to the first embodiment. Figures 11 to 16 are top views showing the method for manufacturing the quantum device 1 according to the first embodiment.

[0022] First, as shown in FIG. 3, a laminate 120 is formed. To form the laminate 120, a two-dimensional topological insulator layer 23 is prepared in a non-oxidizing atmosphere, such as an argon (Ar) atmosphere. The two-dimensional topological insulator layer 23 can be obtained, for example, by peeling a single layer of 1T'-WTe2 from bulk WTe2. After the two-dimensional topological insulator layer 23 is prepared, a first protective layer 21 is attached to one surface of the two-dimensional topological insulator layer 23 in a non-oxidizing atmosphere, and a second protective layer 22 is attached to the other surface.

[0023] Next, as shown in FIGS. 4 and 11, a stack 120 is provided on the substrate 10 with the two-dimensional topological insulator layer 23 closer to the substrate 10 than the first protective layer 21. In this embodiment, the stack 120 is provided on the substrate 10 with the second protective layer 22 in contact with the substrate 10. The stack 120 can be provided on the substrate 10 by, for example, a stamping method. The stack 120 may also be provided on the substrate 10 in the atmosphere. This is because the entire two-dimensional topological insulator layer 23 is covered by the first protective layer 21 and the second protective layer 22, preventing oxidation of the two-dimensional topological insulator layer 23. FIG. 4 corresponds to a cross-sectional view taken along line IV-IV in FIG. 11. .

[0024] Thereafter, as shown in FIGS. 5 and 12, a sacrificial layer 81 covering the stacked body 120 is formed on the substrate 10. The sacrificial layer 81 can be formed by, for example, a vapor deposition method. The sacrificial layer 81 is, for example, an aluminum (Al) layer. The sacrificial layer 81 may also be an Au layer. The thickness of the sacrificial layer 81 is preferably 20 nm or more, and more preferably 30 nm or more. FIG. 5 corresponds to a cross-sectional view taken along line VV in FIG. 12.

[0025] Next, as shown in FIGS. 6 and 13, a protective layer 82 is formed on the sacrificial layer 81. As described below, the openings 25, 26, and 27 are formed using a focused ion beam (FIB). The protective layer 82 is provided above a portion where damage caused by FIB irradiation during the formation of the openings 25, 26, and 27 is to be suppressed. For example, the protective layer 82 is formed around the region where the openings 25, 26, and 27 are to be formed, above a portion of the two-dimensional topological insulator layer 23 that will remain after the openings 25, 26, and 27 are formed. The protective layer 82 is, for example, a platinum (Pt) layer. The thickness of the protective layer 82 is, for example, approximately 20 nm to 50 nm. The protective layer 82 can be formed using, for example, an FIB. If the output of the FIB during the formation of the protective layer 82 is approximately 5 V, the sacrificial layer 81 can suppress damage to the stack 120. FIG. 6 corresponds to a cross-sectional view taken along line VI-VI in FIG. 13.

[0026] Next, as shown in FIGS. 7 and 14 , openings 25, 26, and 27 are formed in the stack 120. The openings 25, 26, and 27 can be formed, for example, using FIB in a vacuum. The opening 25 penetrates the first protective layer 21 and is formed so as to expose the side surface of the two-dimensional topological insulator layer 23. That is, the opening 25 is formed so as to remove a portion of the two-dimensional topological insulator layer 23. As a result, a portion of the edge 23E of the two-dimensional topological insulator layer 23 moves, and a recess 24 that constitutes the opening 25 is formed in the two-dimensional topological insulator layer 23. In addition, the second protective layer 22 is exposed at the bottom of the openings 25, 26, and 27. For example, when the sacrificial layer 81 is 20 nm thick, the first protective layer 21 is 10 nm thick, and the two-dimensional topological insulator layer 23 is 1 nm thick, the depth of the openings 25, 26, and 27 is approximately 35 nm. The formation of the protective layer 82 suppresses damage to the two-dimensional topological insulator layer 23 during the formation of the openings 25, 26, and 27. As shown in FIG. 7, cutting residues 83 may be generated around the openings 25, 26, and 27. The cutting residues 83 are omitted in FIGS. 14 and 15. FIG. 7 corresponds to a cross-sectional view taken along line VII-VII in FIG. 14.

[0027] Thereafter, as shown in FIGS. 8 and 15 , a superconductor layer 30 is formed in the opening 25. The superconductor layer 30 can be formed, for example, using an FIB in a vacuum. The formation of the openings 25, 26, and 27 and the formation of the superconductor layer 30 may be performed consecutively in the same apparatus without exposure to air. The superconductor layer 30 is formed to a thickness sufficient to cover at least the entire side surface of the two-dimensional topological insulator layer 23 exposed in the opening 25. Furthermore, a magnetic layer 141 is formed in the opening 26, and a magnetic layer 142 is formed in the opening 27. The magnetic layers 141 and 142 can be formed, for example, using an FIB in a vacuum. When the superconductor layer 30 is formed, the material of the superconductor layer 30 may be attached to the periphery of the opening 25. When the magnetic layer 141 is formed, the material of the magnetic layer 141 may be attached to the periphery of the opening 26. When the magnetic layer 142 is formed, the material of the magnetic layer 142 may be attached to the periphery of the opening 27. FIG. 8 corresponds to a cross-sectional view taken along line VIII-VIII in FIG.

[0028] Next, as shown in FIG. 9 and FIG. 16, the sacrificial layer 81 is removed. When the sacrificial layer 81 is removed, the protective layer 82 and the cutting residue 83 are also removed. When the sacrificial layer 81 is an Al layer, the sacrificial layer 81 can be removed using hydrochloric acid. When the sacrificial layer 81 is an Au layer, the sacrificial layer 81 can be removed using a solution containing iodine. FIG. 9 is taken along the line IX-IX in FIG. This corresponds to a cross-sectional view.

[0029] 10, a gate insulating layer 91 and a gate electrode 92 are formed. The gate insulating layer 91 is formed by, for example, atomic layer deposition (ALD). The gate electrode 92 can be formed by, for example, deposition using a mask and lift-off by removing the mask. The gate electrode 92 may also be formed by film formation and subsequent etching.

[0030] In this manner, the quantum device 1 according to the first embodiment can be manufactured.

[0031] In the first embodiment, the superconductor layer 30 is provided in the opening 25 and contacts the edge 23E of the two-dimensional topological insulator layer 23. Therefore, it is easy to achieve a stable relationship among the two-dimensional topological insulator layer 23, the superconductor layer 30, and the magnetic layers 141 and 142 for manifesting the Majorana quasiparticles γ1 and γ2.

[0032] Furthermore, because the openings 25, 26, and 27 are formed using FIB, the openings 25, 26, and 27 can be formed with high precision. When manufacturing the quantum device 1, if the preparation of the stack 120 and the processes from the formation of the openings 25 to the formation of the superconductor layer 30 are performed in a non-oxidizing atmosphere, oxidation of the two-dimensional topological insulator layer 23 can be easily suppressed, thereby suppressing variations in characteristics due to oxidation. Even if cutting residues are generated during the formation of the openings 25, 26, and 27, the sacrificial layer 81 has been formed beforehand, so the cutting residues can be easily removed by removing the sacrificial layer 81. Because the protective layer 82 has been formed before the formation of the openings 25, 26, and 27, damage to the stack 120 during the formation of the openings 25, 26, and 27 can be suppressed.

[0033] Even if damage occurs near the side surface of the two-dimensional topological insulator layer 23 during the formation of the opening 25, resulting in a portion where the topological properties are deteriorated, the topological properties are restored within a few atoms. Therefore, the superconducting proximity effect from the superconductor layer 30 is brought about in the portion where the topological properties are restored.

[0034] Furthermore, when 1T'-WTe2 is peeled off from bulk WTe2, the shape of the two-dimensional topological insulator layer 23 may change each time the two-dimensional topological insulator layer 23 is peeled off. According to this embodiment, even if the shape of the two-dimensional topological insulator layer 23 changes each time the two-dimensional topological insulator layer 23 is peeled off, the superconductor layer 30 and the magnetic layers 141 and 142 can be appropriately arranged according to the shape of the two-dimensional topological insulator layer 23.

[0035] (Second embodiment) Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in the arrangement of the magnetic layers. Fig. 17 is a top view showing a quantum device according to the second embodiment. Note that the gate insulating layer 91 and the gate electrode 92 are omitted in Fig. 17.

[0036] In the quantum device 2 according to the second embodiment, as shown in FIG. 17, the openings 26 and 27 are not formed in the stack 120, and magnetic layers 241 and 242 are provided instead of the magnetic layers 141 and 142.

[0037] The magnetic layer 241 is provided on the first protective layer 21, along the edge 23E of the two-dimensional topological insulator layer 23, and spaced apart on one side from the superconductor layer 30. The magnetic layer 242 is provided on the first protective layer 21, along the edge 23E of the two-dimensional topological insulator layer 23, and spaced apart on the other side from the superconductor layer 30. The superconductor layer 30 is located between the magnetic layer 241 and the magnetic layer 242. The magnetic layers 241 and 242 overlap the edge 23E of the two-dimensional topological insulator layer 23 in a planar view. The magnetic layers 241 and 242 generate a magnetic field that extends to the two-dimensional topological insulator layer 23. The magnetic layers 241 and 242 are not in contact with the two-dimensional topological insulator layer 23. The magnetic layers 241 and 242 are, for example, Co layers.

[0038] The other configurations are the same as those in the first embodiment.

[0039] In quantum device 2, Majorana quasiparticle γ1 appears in a portion closer to magnetic layer 141 than superconductor layer 30, and Majorana quasiparticle γ2 appears in a portion closer to magnetic layer 142 than superconductor layer 30. Majorana quasiparticle γ1 is confined in the vicinity of superconductor layer 30 due to the influence of the magnetic field generated by magnetic layer 141, and Majorana quasiparticle γ2 is confined in the vicinity of superconductor layer 30 due to the influence of the magnetic field generated by magnetic layer 142.

[0040] Next, a method for manufacturing the quantum device 2 according to the second embodiment will be described. Figures 18 to 23 are top views illustrating the method for manufacturing the quantum device 2 according to the second embodiment.

[0041] First, similarly to the first embodiment, processing up to the step of providing the laminate 120 on the substrate 10 is performed (see FIGS. 4 and 11). Next, as shown in FIG. 18, magnetic layers 241 and 242 are formed on the first protective layer 21. The magnetic layers 241 and 242 can be formed, for example, by vapor deposition using a mask and lift-off by removing the mask. The magnetic layers 241 and 242 may also be formed by film formation and subsequent etching.

[0042] 19, a sacrificial layer 81 that covers the stacked body 120 and the magnetic layers 241 and 242 is formed on the substrate 10. The sacrificial layer 81 is, for example, an Al layer or an Au layer.

[0043] 20, a protective layer 82 is formed on the sacrificial layer 81. When forming the protective layer 82, a scanning ion microscope (SIM) or the like is used to observe the magnetic The positions of the layers 241 and 242 may be specified, and the magnetic layers 241 and 242 may be used as alignment marks. The protective layer 82 is provided above a portion where damage caused by FIB irradiation during the formation of the opening 25 is to be suppressed. For example, the protective layer 82 is formed around the region where the opening 25 is to be formed, above a portion of the two-dimensional topological insulator layer 23 that is to remain after the formation of the opening 25. The protective layer 82 is, for example, a Pt layer.

[0044] 21, an opening 25 is formed in the stack 120. As a result, a part of the edge 23E of the two-dimensional topological insulator layer 23 moves, and a recess 24 that forms the opening 25 is formed in the two-dimensional topological insulator layer 23. In addition, the second protective layer 22 is exposed at the bottom of the opening 25. Cutting residue 83 may be generated around the opening 25 (see FIG. 7).

[0045] 22, a superconductor layer 30 is formed in the opening 25. The superconductor layer 30 is formed to a thickness sufficient to cover at least the entire side surface of the two-dimensional topological insulator layer 23 exposed in the opening 25. When the superconductor layer 30 is formed, the material of the superconductor layer 30 may be attached to the periphery of the opening 25.

[0046] 23, the sacrificial layer 81 is removed. When the sacrificial layer 81 is removed, the protective layer 82 and cutting residue 83 are also removed.

[0047] Next, similarly to the first embodiment, a gate insulating layer 91 and a gate electrode 92 are formed (see FIG. 10).

[0048] In this way, the quantum device 2 according to the second embodiment can be manufactured.

[0049] In the second embodiment as well, the superconductor layer 30 is provided in the opening 25 and contacts the edge 23E of the two-dimensional topological insulator layer 23. This makes it easy to achieve a stable relationship among the two-dimensional topological insulator layer 23, the superconductor layer 30, and the magnetic layers 241 and 242 for manifesting the Majorana quasiparticles γ1 and γ2.

[0050] (Third embodiment) Next, a third embodiment will be described. The third embodiment differs from the first embodiment mainly in the configuration of the stack. Fig. 24 is a cross-sectional view showing a quantum device according to the third embodiment.

[0051] 24, the quantum device 3 according to the third embodiment has a stack 320 instead of the stack 120. The stack 320 has a first protective layer 21 and a two-dimensional topological insulator layer 23, but does not have a second protective layer 22. The stack 320 is provided on a substrate 10, with the two-dimensional topological insulator layer 23 closer to the substrate 10 than the first protective layer 21. The two-dimensional topological insulator layer 23 is in contact with the substrate 10. In addition, the first protective layer 21 is also in contact with the substrate 10 around the entire periphery of the two-dimensional topological insulator layer 23, outside the edge 23E of the two-dimensional topological insulator layer 23.

[0052] The opening 25 may reach the substrate 10, or the bottom surface of the opening 25 may be located closer to the bottom surface of the substrate 10 than the top surface of the substrate 10. The bottom surface of the opening 25 may be located in the Si oxide film 12, in the Si substrate 11, or at the interface between the Si substrate 11 and the Si oxide film 12. The bottom surface of the opening 25 may be located on the top surface of the substrate 10.

[0053] The other configurations are the same as those in the first embodiment.

[0054] In the quantum device 3, the Majorana quasiparticle γ1 appears in the portion closer to the magnetic layer 141 than the superconductor layer 30, and the Majorana quasiparticle γ2 appears in the portion closer to the magnetic layer 142 than the superconductor layer 30 (see FIG. 1).

[0055] Next, a method for manufacturing the quantum device 3 according to the third embodiment will be described. Figures 25 to 27 are cross-sectional views showing the method for manufacturing the quantum device 3 according to the third embodiment.

[0056] 25, in a non-oxidizing atmosphere, for example, an Ar atmosphere, a two-dimensional topological insulator layer 23 is attached to a substrate 10, and a first protective layer 21 is attached on the two-dimensional topological insulator layer 23. In this way, a stacked body 320 is formed.

[0057] Next, as shown in FIG. 26, in the same manner as in the first embodiment, a sacrificial layer 81 is formed, a protective layer 82 is formed, openings 25, 26 and 27 are formed, a superconductor layer 30 is formed, magnetic layers 141 and 142 are formed, and the sacrificial layer 81 is removed.

[0058] Thereafter, as shown in FIG. 27, a gate insulating layer 91 and a gate electrode 92 are formed in the same manner as in the first embodiment.

[0059] In this manner, the quantum device 3 according to the third embodiment can be manufactured.

[0060] Also in the second embodiment, the superconductor layer 30 is provided in the opening 25 and contacts the edge 23E of the two-dimensional topological insulator layer 23. Therefore, it is easy to achieve a stable relationship among the two-dimensional topological insulator layer 23, the superconductor layer 30, and the magnetic layers 141 and 142 for manifesting the Majorana quasiparticles γ1 and γ2.

[0061] Furthermore, even if the second protective layer 22 is not provided, the first surface of the two-dimensional topological insulator layer 23 is covered by the first protective layer 21, and the second surface is covered by the substrate 10, so oxidation of the two-dimensional topological insulator layer 23 can be easily suppressed, thereby suppressing fluctuations in characteristics due to oxidation.

[0062] (Fourth embodiment) Next, a fourth embodiment will be described. The fourth embodiment relates to a quantum computer. 4 FIG. 1 is a diagram illustrating a quantum computer according to an embodiment.

[0063] The quantum computer 4 according to the fourth embodiment includes a general-purpose computer 401, a control unit 402, and a quantum device 403. The control unit 402 controls the quantum device 403 based on a control signal from the general-purpose computer 401. The quantum device 403 may be a quantum device according to any of the first to third embodiments. The control unit 402 and the quantum device 403 are housed in a cryostat 404.

[0064] The quantum computer 4 makes it possible to perform stable quantum operations.

[0065] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. [Explanation of symbols]

[0066] 1, 2, 3, 403: Quantum Devices 4: Quantum computers 10: Circuit board 21: 1st protective layer 22:Second protective layer 23: Two-dimensional topological insulator layer 23E: Edge 24: Recess 25, 26, 27: Openings 30: Superconductor layer 81: Sacrificial Layer 82:Protective layer 120, 320: Laminate 141, 142, 241, 242: Magnetic layer

Claims

1. A substrate; a two-dimensional topological insulator layer disposed on the substrate; a first protective layer covering the two-dimensional topological insulator layer; an opening provided in the first protective layer, through which a side surface of the two-dimensional topological insulator layer is exposed; a superconductor layer provided in the opening and in contact with the side surface of the two-dimensional topological insulator layer; A quantum device comprising:

2. 2. The quantum device according to claim 1, wherein, in a plan view, a recess that forms the opening is formed in the two-dimensional topological insulator layer.

3. The two-dimensional topological insulator layer is a single layer of 1T'-WTe ２ 3. The quantum device according to claim 1, wherein the quantum device comprises:

4. 4. The quantum device according to claim 1, wherein the first protective layer comprises a first layered material layer.

5. 5. The quantum device according to claim 1, further comprising a second protective layer provided between the substrate and the two-dimensional topological insulator layer.

6. The quantum device of claim 5 , wherein the second protective layer comprises a second layered material layer.

7. A quantum device as described in any one of claims 1 to 6, characterized in that it has a magnetic layer in contact with the first protective layer, spaced apart from the superconductor layer, and generating a magnetic field that extends to the two-dimensional topological insulator layer.

8. A quantum computer comprising the quantum device according to any one of claims 1 to 7.

9. forming a two-dimensional topological insulator layer on a substrate in a non-oxidizing atmosphere; forming a first protective layer on the two-dimensional topological insulator layer; forming an opening in the first protective layer in a non-oxidizing atmosphere, the opening exposing a side surface of the two-dimensional topological insulator layer; forming a superconductor layer in the opening in a non-oxidizing atmosphere; 1. A method for manufacturing a quantum device, comprising:

10. The method for manufacturing a quantum device according to claim 9 , wherein the opening is formed using a focused ion beam.

11. a step of forming a sacrificial layer covering the first protective layer between the step of forming the first protective layer and the step of forming the opening; the opening is formed through the sacrificial layer; 11. The method for manufacturing a quantum device according to claim 9, further comprising the step of removing the sacrificial layer after the step of forming the superconductor layer.

12. a step of forming a sacrificial layer covering the first protective layer between the step of providing the first protective layer and the step of forming the opening; the opening is formed through the sacrificial layer using a focused ion beam; forming a protective layer on the sacrificial layer between the step of forming the sacrificial layer and the step of forming the opening, the protective layer protecting the two-dimensional topological insulator layer from the focused ion beam; 10. The method for manufacturing a quantum device according to claim 9, further comprising the step of removing the sacrificial layer and the protective layer after the step of forming the superconductor layer.

13. 13. The method for manufacturing a quantum device according to claim 9, further comprising the step of forming a second protective layer on the substrate before forming the two-dimensional topological insulator layer.

Images