semiconductor memory device

Abstract

According to the present invention, nanosheets (21-24) are formed side by side in the order of the nanosheets (21-24) in an X-direction. Nanosheets (25-28) are formed side by side in the order of the nanosheets (25-28) in the X-direction. In the nanosheets (21, 23, 25, 27), first side surfaces are respectively exposed from gate lines (30, 33, 35, 36) in the X-direction. In the nanosheets (22, 24, 26, 28), second side surfaces are respectively exposed from gate lines (33, 34, 36, 39) in the X-direction.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor memory device equipped with a nanosheet FET (Field Effect Transistor), and in particular to a layout structure of a two-port SRAM (Static Random Access Memory) cell (hereinafter simply referred to as a cell, as appropriate) using a nanosheet FET. [Background technology]

[0002] SRAMs are widely used in semiconductor integrated circuits, and include two-port SRAMs that have one write port and one read port (see, for example, Patent Document 1).

[0003] Furthermore, transistors, which are the basic components of LSIs, have achieved increased integration density, reduced operating voltages, and improved operating speeds through the reduction of gate length (scaling). However, in recent years, excessive scaling has caused problems with off-state current and the resulting significant increase in power consumption. To solve this problem, there has been active research into three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional one. One type of three-dimensional transistor that has attracted attention is the nanosheet FET (nanowire FET).

[0004] Among nanosheet FETs, a fork sheet transistor with a fork-shaped gate electrode has been proposed. Non-Patent Document 1 discloses the layout of an SRAM memory cell using a fork sheet transistor, which realizes a reduction in the area of ​​a semiconductor memory device. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent No. 9,646,973 (Figure 1) [Non-patent literature]

[0006] [Non-Patent Document 1] P. Weckx et al., “Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3nm”, 2017 IEEE International Electron Devices Meeting (IEDM), December 2017, IEDM17-505~508 [Non-patent document 2] P. Weckx et al., “Novel forksheet device architecture as ultimate logic scaling device towards 2nm”, 2019 IEEE International Electron Devices Meeting (IEDM), December 2019, IEDM19-871~874 Summary of the Invention [Problem to be solved by the invention]

[0007] In this specification, a nanosheet FET having a fork-shaped gate electrode is referred to as a fork-sheet transistor, following the prior art.

[0008] However, no concrete study has been done on the layout of a two-port SRAM cell using fork-sheet transistors.

[0009] The present disclosure aims to provide a layout structure for a two-port SRAM cell using fork-sheet transistors. [Means for solving the problem]

[0010] In a first aspect of the present disclosure, there is provided a semiconductor memory device including a two-port SRAM cell, the two-port SRAM cell comprising: a first transistor having one node connected to a first power supply that supplies a first voltage, the other node connected to a first node, and a gate connected to a second node; a second transistor having one node connected to the first power supply, the other node connected to the second node, and a gate connected to the first node; a third transistor having one node connected to a first bit line, the other node connected to the first node, and a gate connected to a first word line; and a third transistor having one node connected to a second bit line that forms a first complementary bit line pair with the first bit line, the other node connected to the second node, and a gate connected to the first word line. a fourth transistor connected to the third bit line, a fifth transistor having one node connected to the third bit line, the other node connected to the first node, and a gate connected to the second word line, a sixth transistor having one node connected to the fourth bit line forming a second complementary bit line pair with the third bit line, the other node connected to the second node, and a gate connected to the second word line, a seventh transistor having one node connected to the first node and the other node connected to a second power supply that supplies a second voltage different from the first voltage, and a gate connected to the second node, and an eighth transistor having one node connected to the second node, the other node connected to the second power supply, and a gate connected to the first node, respectively. The first to eighth transistors each include first to eighth nanosheets extending in a first direction and first to eighth gate wirings that surround the first to eighth nanosheets in a second direction perpendicular to the first direction and a third direction perpendicular to the first and second directions, respectively. The second, fifth, sixth, and eighth nanosheets are formed side by side in the second direction in the order of the fifth, second, eighth, and sixth nanosheets. The first, third, fourth, and seventh nanosheets are formed side by side in the second direction in the order of the third, seventh, first, and fourth nanosheets. The second, fourth, sixth, and seventh nanosheets have first side surfaces, which are one side in the second direction, exposed from the second, fourth, sixth, and seventh gate wirings, respectively.The first, third, fifth and eighth nanosheets have second-side surfaces, which are the other sides in the second direction, exposed from the first, third, fifth and eighth gate wirings, respectively.

[0011] According to the present disclosure, the first to eighth transistors are each configured as a fork sheet transistor, thereby realizing a two-port SRAM cell using fork sheet transistors.

[0012] Furthermore, when the first side is the side of the seventh nanosheet facing the third nanosheet and the side of the sixth nanosheet facing the eighth nanosheet, the surfaces of the third and seventh nanosheets facing each other are exposed from the third and seventh gate wirings, respectively, and the surfaces of the sixth and eighth nanosheets facing each other are exposed from the sixth and eighth gate wirings, respectively. This allows the area of ​​the semiconductor memory device to be reduced.

[0013] Furthermore, when the first side is the side of the seventh nanosheet facing the first nanosheet and the side of the second nanosheet facing the eighth nanosheet, the surfaces of the first and seventh nanosheets facing each other are exposed from the first and seventh gate wirings, respectively, and the surfaces of the second and eighth nanosheets facing each other are exposed from the second and eighth gate wirings, respectively. This allows the area of ​​the semiconductor memory device to be reduced.

[0014] Therefore, a two-port SRAM cell using fork-sheet transistors can be realized, and the area of ​​the semiconductor memory device can be reduced.

[0015] A second aspect of the present disclosure is a semiconductor memory device including a two-port SRAM cell, wherein the two-port SRAM cell includes a first transistor having one node connected to a first power supply that supplies a first voltage, the other node connected to a first node, and a gate connected to a second node; a second transistor having one node connected to the first power supply, the other node connected to the second node, and a gate connected to the first node; a third transistor having one node connected to a first bit line, the other node connected to the first node, and a gate connected to a first word line; and a third transistor having one node connected to a second bit line that forms a first complementary bit line pair with the first bit line, the other node connected to the second node, and a gate connected to the first word line. a fourth transistor connected to the third bit line, a fifth transistor having one node connected to the third bit line, the other node connected to the first node, and a gate connected to the second word line, a sixth transistor having one node connected to the fourth bit line forming a second complementary bit line pair with the third bit line, the other node connected to the second node, and a gate connected to the second word line, a seventh transistor having one node connected to the first node and the other node connected to a second power supply that supplies a second voltage different from the first voltage, and a gate connected to the second node, and an eighth transistor having one node connected to the second node, the other node connected to the second power supply, and a gate connected to the first node, respectively. The first to sixth transistors each include first to sixth nanosheets extending in a first direction and first to sixth gate wirings that surround the first to sixth nanosheets in a second direction perpendicular to the first direction and a third direction perpendicular to the first and second directions, respectively. The seventh transistor includes seventh and eighth nanosheets extending in the first direction and seventh and eighth gate wirings surrounding the seventh and eighth nanosheets in the second and third directions, respectively. The eighth transistor includes ninth and tenth nanosheets extending in the first direction and ninth and tenth gate wirings surrounding the ninth and tenth nanosheets in the second and third directions, respectively.The second, fifth, sixth, ninth, and tenth nanosheets are formed side by side in the second direction in the order of the fifth, second, ninth, tenth, and sixth nanosheets. The first, third, fourth, seventh, and eighth nanosheets are formed side by side in the second direction in the order of the third, seventh, eighth, first, and fourth nanosheets. The first, sixth, seventh, and ninth nanosheets have first-side surfaces, which are one side in the second direction, exposed from the first, sixth, seventh, and ninth gate wirings, respectively. The second, third, eighth, and tenth nanosheets have second-side surfaces, which are the other side in the second direction, exposed from the second, third, eighth, and tenth gate wirings, respectively. The fourth nanosheet has either the first or second side surface exposed from the fourth gate wiring. The fifth nanosheet has a surface on either the first side or the second side exposed from the fifth gate wiring.

[0016] According to the present disclosure, the first to eighth transistors are each configured as a fork sheet transistor, thereby realizing a two-port SRAM cell using fork sheet transistors.

[0017] Furthermore, when the first side is the side of the ninth nanosheet facing the second nanosheet, the side of the sixth nanosheet facing the tenth nanosheet, the side of the seventh nanosheet facing the third nanosheet, and the side of the first nanosheet facing the eighth nanosheet, the surfaces of the second and ninth nanosheets facing each other are exposed from the second and ninth gate wirings, respectively, the surfaces of the sixth and tenth nanosheets facing each other are exposed from the sixth and tenth gate wirings, respectively, the surfaces of the third and seventh nanosheets facing each other are exposed from the third and seventh gate wirings, respectively, and the surfaces of the first and eighth nanosheets facing each other are exposed from the first and eighth gate wirings, respectively. This allows the area of ​​the semiconductor memory device to be reduced.

[0018] Furthermore, when the first side is the side of the eighth nanosheet facing the seventh nanosheet and the side of the tenth nanosheet facing the ninth nanosheet, the surfaces of the seventh and eighth nanosheets facing each other are exposed from the seventh and eighth gate wirings, respectively, and the surfaces of the ninth and tenth nanosheets facing each other are exposed from the ninth and tenth gate wirings, respectively. This allows the area of ​​the semiconductor memory device to be reduced.

[0019] Therefore, a two-port SRAM cell using fork-sheet transistors can be realized, and the area of ​​the semiconductor memory device can be reduced.

[0020] A third aspect of the present disclosure is a semiconductor memory device including a two-port SRAM cell, the two-port SRAM cell comprising: a first transistor having one node connected to a first power supply that supplies a first voltage, the other node connected to a first node, and a gate connected to a second node; a second transistor having one node connected to the first power supply, the other node connected to the second node, and a gate connected to the first node; a third transistor having one node connected to a first bit line, the other node connected to the first node, and a gate connected to a first word line; and a third transistor having one node connected to a second bit line that forms a first complementary bit line pair with the first bit line, the other node connected to the second node, and a gate connected to the first word line. a fourth transistor connected to the third bit line, a fifth transistor having one node connected to the third bit line, the other node connected to the first node, and a gate connected to the second word line, a sixth transistor having one node connected to the fourth bit line forming a second complementary bit line pair with the third bit line, the other node connected to the second node, and a gate connected to the second word line, a seventh transistor having one node connected to the first node and the other node connected to a second power supply that supplies a second voltage different from the first voltage, and a gate connected to the second node, and an eighth transistor having one node connected to the second node, the other node connected to the second power supply, and a gate connected to the first node, respectively. The first to sixth transistors each include first to sixth nanosheets extending in a first direction and first to sixth gate wirings that surround the first to sixth nanosheets in a second direction perpendicular to the first direction and a third direction perpendicular to the first and second directions, respectively. The seventh transistor includes seventh and eighth nanosheets extending in the first direction and seventh and eighth gate wirings surrounding the seventh and eighth nanosheets in the second and third directions, respectively. The eighth transistor includes ninth and tenth nanosheets extending in the first direction and ninth and tenth gate wirings surrounding the ninth and tenth nanosheets in the second and third directions, respectively.The second, fifth, sixth, ninth, and tenth nanosheets are formed side by side in the second direction in the order of the sixth, fifth, second, ninth, and tenth nanosheets. The first, third, fourth, seventh, and eighth nanosheets are formed side by side in the second direction in the order of the seventh, eighth, first, fourth, and third nanosheets. The second, sixth, eighth, and tenth nanosheets have first-side surfaces, which are one side in the second direction, exposed from the second, sixth, eighth, and tenth gate wirings, respectively. The first, third, seventh, and ninth nanosheets have second-side surfaces, which are the other side in the second direction, exposed from the first, third, seventh, and ninth gate wirings, respectively. The fourth nanosheet has either the first or second side surface exposed from the fourth gate wiring. The fifth nanosheet has a surface on either the first side or the second side exposed from the fifth gate wiring.

[0021] According to the present disclosure, the first to eighth transistors are each configured as a fork sheet transistor, thereby realizing a two-port SRAM cell using fork sheet transistors.

[0022] Furthermore, when the first side is the side of the tenth nanosheet facing the ninth nanosheet and the side of the eighth nanosheet facing the seventh nanosheet, the surfaces of the ninth and tenth nanosheets facing each other are exposed from the ninth and tenth gate wirings, respectively, and the surfaces of the seventh and eighth nanosheets facing each other are exposed from the seventh and eighth gate wirings, respectively. This allows the area of ​​the semiconductor memory device to be reduced.

[0023] Furthermore, when the first side is the side of the second nanosheet facing the ninth nanosheet and the side of the eighth nanosheet facing the first nanosheet, the surfaces of the second and ninth nanosheets facing each other are exposed from the second and ninth gate wirings, respectively, and the surfaces of the first and eighth nanosheets facing each other are exposed from the first and eighth gate wirings, respectively. This allows the area of ​​the semiconductor memory device to be reduced.

[0024] Therefore, a two-port SRAM cell using fork-sheet transistors can be realized, and the area of ​​the semiconductor memory device can be reduced.

[0025] A fourth aspect of the present disclosure is a semiconductor memory device including a two-port SRAM cell, wherein the two-port SRAM cell includes a first transistor having one node connected to a first power supply that supplies a first voltage, the other node connected to a first node, and a gate connected to a second node; a second transistor having one node connected to the first power supply, the other node connected to the second node, and a gate connected to the first node; a third transistor having one node connected to a first bit line, the other node connected to the first node, and a gate connected to a first word line; and a third transistor having one node connected to a second bit line that forms a first complementary bit line pair with the first bit line, the other node connected to the second node, and a gate connected to the first word line. a fourth transistor connected to the third bit line, a fifth transistor having one node connected to the third bit line, the other node connected to the first node, and a gate connected to the second word line, a sixth transistor having one node connected to the fourth bit line forming a second complementary bit line pair with the third bit line, the other node connected to the second node, and a gate connected to the second word line, a seventh transistor having one node connected to the first node and the other node connected to a second power supply that supplies a second voltage different from the first voltage, and a gate connected to the second node, and an eighth transistor having one node connected to the second node, the other node connected to the second power supply, and a gate connected to the first node, respectively. The first to sixth transistors each include first to sixth nanosheets extending in a first direction and first to sixth gate wirings that surround the first to sixth nanosheets in a second direction perpendicular to the first direction and a third direction perpendicular to the first and second directions, respectively. The seventh transistor includes seventh and eighth nanosheets extending in the first direction and seventh and eighth gate wirings surrounding the seventh and eighth nanosheets in the second and third directions, respectively. The eighth transistor includes ninth and tenth nanosheets extending in the first direction and ninth and tenth gate wirings surrounding the ninth and tenth nanosheets in the second and third directions, respectively.The second, third, fifth, ninth, and tenth nanosheets are formed side by side in the second direction in the order of the fifth, third, second, ninth, and tenth nanosheets. The first, fourth, sixth, seventh, and eighth nanosheets are formed side by side in the second direction in the order of the seventh, eighth, first, sixth, and fourth nanosheets. The first, fifth, sixth, seventh, and ninth nanosheets have first-side surfaces, which are one side in the second direction, exposed from the first, fifth, sixth, seventh, and ninth gate wirings, respectively. The second, third, fourth, eighth, and tenth nanosheets have second-side surfaces, which are the other side in the second direction, exposed from the second, third, fourth, eighth, and tenth gate wirings, respectively.

[0026] According to the present disclosure, the first to eighth transistors are each configured as a fork sheet transistor, thereby realizing a two-port SRAM cell using fork sheet transistors.

[0027] Furthermore, when the first side is the side of the ninth nanosheet facing the second nanosheet and the side of the first nanosheet facing the eighth nanosheet, the surfaces of the second and ninth nanosheets facing each other are exposed from the second and ninth gate wirings, respectively, and the surfaces of the first and eighth nanosheets facing each other are exposed from the first and eighth gate wirings, respectively. This allows the area of ​​the semiconductor memory device to be reduced.

[0028] Furthermore, when the first side is the side of the fifth nanosheet facing the third nanosheet, the side of the ninth nanosheet facing the tenth nanosheet, the side of the seventh nanosheet facing the eighth nanosheet, and the side of the sixth nanosheet facing the fourth nanosheet, the surfaces of the third and fifth nanosheets facing each other are exposed from the third and fifth gate wirings, respectively, the surfaces of the ninth and tenth nanosheets facing each other are exposed from the ninth and tenth gate wirings, respectively, the surfaces of the seventh and eighth nanosheets facing each other are exposed from the seventh and eighth gate wirings, respectively, and the surfaces of the fourth and sixth nanosheets facing each other are exposed from the fourth and sixth gate wirings, respectively. This allows the area of ​​the semiconductor memory device to be reduced.

[0029] Therefore, a two-port SRAM cell using fork-sheet transistors can be realized, and the area of ​​the semiconductor memory device can be reduced. [Effects of the Invention]

[0030] According to the present disclosure, a two-port SRAM cell using fork-sheet transistors can be realized, and the area of ​​a semiconductor memory device can be reduced. [Brief explanation of the drawings]

[0031] [Figure 1] FIG. 2 is a plan view showing an example of a layout structure of a 2-port SRAM cell according to the first embodiment. [Figure 2] FIG. 2 is a cross-sectional view showing an example of a layout structure of a 2-port SRAM cell according to the first embodiment. [Figure 3] FIG. 2 is a cross-sectional view showing an example of a layout structure of a 2-port SRAM cell according to the first embodiment. [Figure 4] FIG. 2 is a circuit diagram showing the configuration of a 2-port SRAM cell according to the first embodiment. [Figure 5] FIG. 10 is a plan view showing another example of the layout structure of the 2-port SRAM cell according to the first embodiment. [Figure 6]FIG. 10 is a plan view showing another example of the layout structure of the 2-port SRAM cell according to the first embodiment. [Figure 7] FIG. 10 is a plan view showing another example of the layout structure of the 2-port SRAM cell according to the first embodiment. [Figure 8] FIG. 4 is a cross-sectional view showing another example of the layout structure of the 2-port SRAM cell according to the first embodiment. [Figure 9] FIG. 10 is a plan view showing another example of the layout structure of the 2-port SRAM cell according to the first embodiment. [Figure 10] FIG. 10 is a plan view showing another example of the layout structure of the 2-port SRAM cell according to the first embodiment. [Figure 11] FIG. 10 is a plan view showing another example of the layout structure of the 2-port SRAM cell according to the first embodiment. [Figure 12] FIG. 10 is a plan view showing an example of a layout structure of a 2-port SRAM cell according to the second embodiment. [Figure 13] FIG. 10 is a plan view showing another example of the layout structure of the 2-port SRAM cell according to the second embodiment. [Figure 14] FIG. 10 is a plan view showing another example of the layout structure of the 2-port SRAM cell according to the second embodiment. [Figure 15] FIG. 10 is a plan view showing another example of the layout structure of the 2-port SRAM cell according to the second embodiment. [Figure 16] FIG. 11 is a plan view showing an example of a layout structure of a 2-port SRAM cell according to the third embodiment. [Figure 17] FIG. 11 is a plan view showing another example of the layout structure of the 2-port SRAM cell according to the third embodiment. [Figure 18] A diagram showing the basic structure of a fork seat FET. DETAILED DESCRIPTION OF THE INVENTION

[0032] Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor integrated memory device includes a plurality of SRAM cells (hereinafter, simply referred to as cells as appropriate), and at least some of the plurality of SRAM cells include fork sheet transistors, which are nanosheet FETs (nanowire FETs) and have fork-shaped gate electrodes. A nanosheet FET is a FET that uses a thin sheet (nanosheet) through which current flows. The nanosheet is formed of, for example, silicon. In a semiconductor integrated circuit device, some of the nanosheet FETs are fork sheet FETs with fork-shaped gate electrodes.

[0033] In the present disclosure, the semiconductor layer portions formed on both ends of the nanosheet and constituting the terminals that serve as the source or drain of the nanosheet FET are referred to as "pads." In the following description, in plan views such as Figure 1, the vertical direction of the drawing is the Y direction (corresponding to the first direction), the horizontal direction of the drawing is the X direction (corresponding to the second direction), and the direction perpendicular to the substrate surface is the Z direction (corresponding to the third direction).

[0034] (Fork seat structure) 18 shows the basic structure of a fork-sheet FET, where (a) is a plan view and (b) is a cross-sectional view taken along line Y-Y' in (a). In the basic structure of FIG. 18, two transistors TR1 and TR2 are arranged side by side with a gap S therebetween in the Y direction. A gate wiring 531 serving as the gate of transistor TR1 and a gate wiring 532 serving as the gate of transistor TR2 both extend in the Y direction and are arranged at the same position in the X direction.

[0035] A channel portion 521 that serves as the channel region of transistor TR1 and a channel portion 526 that serves as the channel region of transistor TR2 are made of nanosheets. In FIG. 18, the channel portions 521 and 526 are each made of a nanosheet having a three-sheet structure that overlaps in a planar view. Pads 522a and 522b that serve as the source region or drain region of transistor TR1 are formed on both sides of the channel portion 521 in the X direction. Pads 527a and 527b that serve as the source region or drain region of transistor TR2 are formed on both sides of the channel portion 526 in the X direction. The pads 522a and 522b are formed by epitaxial growth from the nanosheet that constitutes the channel portion 521. The pads 527a and 527b are formed by epitaxial growth from the nanosheet that constitutes the channel portion 526.

[0036] The gate wiring 531 surrounds the outer periphery of the channel portion 521 made of the nanosheet in the Y and Z directions via a gate insulating film (not shown). However, the surface of the nanosheet making up the channel portion 521 facing the transistor TR2 in the Y direction is not covered by the gate wiring 531 and is exposed from the gate wiring 531. That is, in the cross-sectional view of FIG. 18(b), the gate wiring 531 does not cover the right side of the nanosheet making up the channel portion 521 in the drawing, but covers the upper, left, and lower sides in the drawing. The gate wiring 531 overlaps the nanosheet making up the channel portion 521 on the opposite side of the transistor TR2 in the Y direction by a length OL.

[0037] The gate wiring 532 surrounds the outer periphery of the channel portion 526 made of the nanosheet in the Y and Z directions via a gate insulating film (not shown). However, the surface of the nanosheet making up the channel portion 526 facing the transistor TR1 in the Y direction is not covered by the gate wiring 532 and is exposed from the gate wiring 532. That is, in the cross-sectional view of FIG. 18(b), the gate wiring 532 does not cover the left side of the nanosheet making up the channel portion 526 in the drawing, but covers the upper, right, and lower sides in the drawing. The gate wiring 532 overlaps the nanosheet making up the channel portion 526 on the opposite side of the transistor TR1 in the Y direction by a length OL.

[0038] If the width (size in the Y direction) of each nanosheet is W and its height (size in the Z direction) is H, the effective gate width Weff is Weff=2×W+H Since the channel portions 521 and 526 of the transistors TR1 and TR2 are made up of three nanosheets, the effective gate widths of the transistors TR1 and TR2 are 3×(2×W+H) This becomes:

[0039] 18, the gate wiring 531 does not overlap the nanosheet that forms the channel portion 521 on the side of the transistor TR2 in the Y direction. Also, the gate wiring 532 does not overlap the nanosheet that forms the channel portion 526 on the side of the transistor TR1 in the Y direction. This allows the transistors TR1 and TR2 to be closer to each other, thereby realizing a smaller area.

[0040] The number of nanosheets constituting the channel portion of a transistor is not limited to three. That is, the nanosheet may be composed of a single sheet structure, or may be composed of multiple sheets that overlap in a planar view. In addition, although the cross-sectional shape of the nanosheet is illustrated as a rectangle in FIG. 18(b), this is not limited thereto, and the cross-sectional shape of the nanosheet may be, for example, a square, a circle, an ellipse, or the like.

[0041] Furthermore, a semiconductor integrated circuit device may contain a mixture of fork-sheet FETs and nanosheet FETs in which the gate wiring surrounds the entire periphery of the nanosheet.

[0042] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. Furthermore, in this specification, expressions such as "same wiring width" that mean the same width, etc., are assumed to include the range of manufacturing variations.

[0043] In this specification, the semiconductor layer portions formed on both ends of the nanosheet and constituting the terminals that serve as the source or drain of the transistor are referred to as "pads."

[0044] In the plan views and cross-sectional views of the following embodiments, the illustration of each insulating film may be omitted. In the plan views and cross-sectional views of the following embodiments, the nanosheet and the pads on both sides thereof may be depicted as simplified linear shapes. In this specification, expressions such as "same size" that mean the same size, etc., are intended to include the range of manufacturing variations.

[0045] In this specification, the source and drain of a transistor are referred to as the "node" of the transistor, where appropriate. That is, one node of a transistor refers to the source or drain of the transistor, and both nodes of a transistor refer to the source and drain of the transistor.

[0046] In addition, in the following embodiments and their modifications, the same components and the like are denoted by the same reference numerals and descriptions thereof may be omitted.

[0047] (First embodiment) 1 to 3 show examples of the layout structure of a two-port SRAM cell according to the first embodiment, with FIGS. 1(a) and 1(b) being plan views, and FIGS. 2(a) to 2(c) and 3(a) and 3(b) being cross-sectional views in the horizontal direction in a plan view. Specifically, FIG. 1(a) shows the upper part of the cell, which is the M1 and M2 wiring layers, and FIG. 1(b) shows the lower part of the cell, which is a layer below the M1 and M2 wiring layers and includes a nanosheet FET. FIG. 2(a) shows the cross section along line X1-X1', FIG. 2(b) shows the cross section along line X2-X2', FIG. 2(c) shows the cross section along line X3-X3', FIG. 3(a) shows the cross section along line X4-X4', and FIG. 3(b) shows the cross section along line X5-X5'.

[0048] 4 is a circuit diagram showing the configuration of a 2-port SRAM cell according to the first embodiment. As shown in FIG. 4, the 2-port SRAM cell according to this embodiment has a 2-port SRAM cell circuit made up of load transistors PU1 and PU2, drive transistors PD1 and PD2, and access transistors PG1 to PG4. The load transistors PU1 and PU2 are P-type FETs, and the drive transistors PD1 and PD2 and access transistors PG1 to PG4 are N-type FETs.

[0049] The load transistor PU1 is provided between a power supply VDD and a first node NA, and the drive transistor PD1 is provided between the first node NA and a power supply VSS. The load transistor PU1 and the drive transistor PD1 have their gates connected to a second node NB, forming an inverter INV1. The load transistor PU2 is provided between the power supply VDD and the second node NB, and the drive transistor PD2 is provided between the second node NB and the power supply VSS. The load transistor PU2 and the drive transistor PD2 have their gates connected to the first node NA, forming an inverter INV2. In other words, the output of one inverter is connected to the input of the other inverter, forming a latch.

[0050] The access transistor PG1 is provided between the first bit line BLA and the first node NA, and its gate is connected to the first word line WLA. The access transistor PG2 is provided between the second bit line BLAX and the second node NB, and its gate is connected to the first word line WLA. The access transistor PG3 is provided between the third bit line BLB and the first node NA, and its gate is connected to the second word line WLB. The access transistor PG4 is provided between the fourth bit line BLBX and the second node NB, and its gate is connected to the second word line WLB. The first and second bit lines BLA and BLAX form a first complementary bit line pair, and the third and fourth bit lines BLB and BLBX form a second complementary bit line pair.

[0051] In a two-port SRAM cell circuit, when the first and second bit lines BLA, BLAX constituting a first complementary bit line pair are driven to a high level and a low level, respectively, and the first word line WLA is driven to a high level, a high level is written to the first node NA and a low level is written to the second node NB. On the other hand, when the first and second bit lines BLA, BLAX are driven to a low level and a high level, respectively, and the first word line WLA is driven to a high level, a low level is written to the first node NA and a high level is written to the second node NB. Then, when the first word line WLA is driven to a low level while data is written to the first and second nodes NA, NB, the latch state is established and the data written to the first and second nodes NA, NB is held.

[0052] Furthermore, when the first and second bit lines BLA and BLAX are precharged to a high level and the first word line WLA is driven to a high level, the states of the first and second bit lines BLA and BLAX are determined according to the data written to the first and second nodes NA and NB, allowing data to be read from the SRAM cell. Specifically, when the first node NA is at a high level and the second node NB is at a low level, the first bit line BLA remains at a high level and the second bit line BLAX is discharged to a low level. On the other hand, when the first node NA is at a low level and the second node NB is at a high level, the first bit line BLA is discharged to a low level and the second bit line BLAX remains at a high level.

[0053] Furthermore, when the third and fourth bit lines BLB, BLBX constituting the second complementary bit line pair are driven to high and low levels, respectively, and the second word line WLB is driven to high level, a high level is written to the first node NA and a low level is written to the second node NB. On the other hand, when the third and fourth bit lines BLB, BLBX are driven to low and high levels, respectively, and the second word line WLB is driven to high level, a low level is written to the first node NA and a high level is written to the second node NB. Then, when the second word line WLB is driven to low level while data is written to the first and second nodes NA, NB, the latch state is established and the data written to the first and second nodes NA, NB is held.

[0054] Furthermore, when the third and fourth bit lines BLB, BLBX are precharged to a high level and the second word line WLB is driven to a high level, the states of the third and fourth bit lines BLB, BLBX are determined according to the data written to the first and second nodes NA, NB, allowing data to be read from the SRAM cell. Specifically, when the first node NA is at a high level and the second node NB is at a low level, the third bit line BLB remains at a high level and the fourth bit line BLBX is discharged to a low level. On the other hand, when the first node NA is at a low level and the second node NB is at a high level, the third bit line BLB is discharged to a low level and the fourth bit line BLBX remains at a high level.

[0055] As described above, the two-port SRAM cell has the functions of writing data to, retaining data, and reading data from the SRAM cell by controlling the first and second bit lines BLA, BLAX and the first word line WLA. Also, the two-port SRAM cell has the functions of writing data to, retaining data, and reading data from the SRAM cell by controlling the third and fourth bit lines BLB, BLBX and the second word line WLB.

[0056] In the following description, the solid lines running vertically and horizontally in plan views such as FIG. 1 and the solid lines running vertically in cross-sectional views such as FIG. 2 indicate grids used for component placement during design. The grids are arranged at equal intervals in the X direction and at equal intervals in the Y direction. The grid spacing may be the same or different in the X and Y directions. The grid spacing may also be different for each layer. Furthermore, each component does not necessarily have to be arranged on a grid. However, from the perspective of suppressing manufacturing variations, it is preferable to arrange the components on a grid.

[0057] In addition, the dotted line surrounding the cell in the plan view of Figure 1 indicates the cell frame (the outer edge of the 2-port SRAM cell) of the 2-port SRAM cell. The 2-port SRAM cell is arranged so that the cell frame is in contact with the cell frame of the adjacent cell in the X or Y direction.

[0058] 1, two 2-port SRAM cells are arranged on both sides of the 2-port SRAM cell in the X direction, and two 2-port SRAM cells are arranged on both sides of the 2-port SRAM cell in the Y direction, respectively.

[0059] As shown in FIG. 1(b), nanosheets 21 to 28 are formed, extending in the X and Y directions. Nanosheets 21 to 24 are aligned in the order of nanosheets 21 to 24 in the X direction. Nanosheets 25 to 28 are aligned in the order of nanosheets 25 to 28 in the X direction. Nanosheets 21 and 25 are aligned in the Y direction. Nanosheets 24 and 28 are aligned in the Y direction.

[0060] The width in the X direction of nanosheets 21, 24, 25, and 28 is twice the width in the X direction of nanosheets 22 and 27. The width in the X direction of nanosheets 23 and 26 is four times the width in the X direction of nanosheets 22 and 27.

[0061] Nanosheets 21 and 25 are formed close to the cell boundary on the left side of the drawing, and nanosheets 24 and 28 are formed close to the cell boundary on the right side of the drawing.

[0062] The nanosheets 21 to 28 form the channel portions of the access transistor PG3, the load transistor PU2, the drive transistor PD2, the access transistors PG4 and PG1, the drive transistor PD1, the load transistor PU1, and the access transistor PG2, respectively.

[0063] The gate wirings (Gate) 30 to 39 extend in the X and Z directions. The gate wirings 30 to 34 are lined up in the X direction. The gate wirings 35 to 39 are lined up in the X direction.

[0064] Furthermore, gate wiring 30 overlaps with nanosheet 21 in a planar view. Gate wiring 33 overlaps with nanosheets 22 and 23 in a planar view. Gate wiring 34 overlaps with nanosheet 24 in a planar view. Gate wiring 35 overlaps with nanosheet 25 in a planar view. Gate wiring 36 overlaps with nanosheets 26 and 27 in a planar view. Gate wiring 39 overlaps with nanosheet 28 in a planar view.

[0065] Gate wiring 30 serves as the gate of access transistor PG3. Gate wiring 33 serves as the gates of load transistor PU2 and drive transistor PD2. Gate wiring 34 serves as the gate of access transistor PG4. Gate wiring 35 serves as the gate of access transistor PG1. Gate wiring 36 serves as the gates of drive transistor PD1 and load transistor PU1. Gate wiring 39 serves as the gate of access transistor PG2.

[0066] The gate wirings 32 and 33 are connected via a bridge portion 10 extending in the X direction. The gate wirings 36 and 37 are connected via a bridge portion 11 extending in the X direction.

[0067] Pads 401 to 410 doped with N-type semiconductor are formed at the top of nanosheet 21 in the drawing, between nanosheets 21 and 25, the bottom of nanosheet 25 in the drawing, the top of nanosheet 26 in the drawing, the bottom of nanosheet 26 in the drawing, the top of nanosheet 23 in the drawing, the bottom of nanosheet 23 in the drawing, the top of nanosheet 24 in the drawing, between nanosheets 24 and 28, and the bottom of nanosheet 28 in the drawing. Pads 401 and 402 form the node of access transistor PG3. Pads 402 and 403 form the node of access transistor PG1. Pads 404 and 405 form the node of drive transistor PD1. Pads 406 and 407 form the node of drive transistor PD2. Pads 408 and 409 form the node of access transistor PG4. Pads 409 and 410 form the node of access transistor PG2.

[0068] That is, the nanosheet 21, gate wiring 30, and pads 401 and 402 form the access transistor PG3. The nanosheet 23, gate wiring 33, and pads 406 and 407 form the drive transistor PD2. The nanosheet 24, gate wiring 34, and pads 408 and 409 form the access transistor PG4. The nanosheet 25, gate wiring 35, and pads 402 and 403 form the access transistor PG1. The nanosheet 26, gate wiring 36, and pads 404 and 405 form the drive transistor PD1. The nanosheet 28, gate wiring 39, and pads 409 and 410 form the access transistor PG2.

[0069] Pads 411 to 414 doped with a P-type semiconductor are formed at the upper end of nanosheet 22 in the drawing, the lower end of nanosheet 22 in the drawing, the upper end of nanosheet 27 in the drawing, and the lower end of nanosheet 27 in the drawing. Pads 411 and 412 form the node of load transistor PU2. Pads 413 and 414 form the node of load transistor PU1.

[0070] That is, the load transistor PU2 is formed by the nanosheet 22, the gate wiring 33, and the pads 411 and 412. The nanosheet 27, the gate wiring 36, and the pads 413 and 414 form the load transistor PU1.

[0071] Therefore, the access transistor PG3, the load transistor PU2, the drive transistor PD2, and the access transistor PG4 are arranged side by side in the X direction. The access transistor PG1, the drive transistor PD1, the load transistor PU1, and the access transistor PG2 are arranged side by side in the X direction. The access transistors PG3 and PG1 are arranged side by side in the Y direction. The access transistors PG4 and PG2 are arranged side by side in the Y direction.

[0072] Local interconnects (LI) 50 to 59 extending in the X direction are formed in the local interconnect layer above each transistor. Local interconnect 50 is connected to pad 401. Local interconnect 51 is connected to pad 411. Local interconnect 52 is connected to pad 406. Local interconnect 53 is connected to pad 408. Local interconnect 54 is connected to pads 402, 404, and 413. Local interconnect 55 is connected to pads 412, 407, and 409. Local interconnect 56 is connected to pad 403. Local interconnect 57 is connected to pad 405. Local interconnect 58 is connected to pad 414. Local interconnect 59 is connected to pad 410.

[0073] Furthermore, the local wiring 54 is connected to the gate wiring 32 via a shared contact 61. The local wiring 55 is connected to the gate wiring 37 via a shared contact 62. The gate wirings 32 and 33, the bridge portion 10, the local wiring 54, and the shared contact 61 correspond to a first node NA. The gate wirings 36 and 37, the bridge portion 11, the local wiring 55, and the shared contact 62 correspond to a second node NB.

[0074] As shown in FIG. 1(a), the M1 wiring layer is formed with wirings 71a-71g extending in the Y direction from the top to the bottom of the cell in the drawing. Also, wirings 71h-71k are formed. The wiring 71a supplies a power supply voltage VDD. The wirings 71b and 71c supply a power supply voltage VSS. The wirings 71d-71g correspond to the first bit line BLA, the third bit line BLB, the second bit line BLAX, and the fourth bit line BLBX, respectively.

[0075] Wiring 71a is connected to local wiring 51 via contact (via) 81a and to local wiring 58 via contact 81b. Wiring 71b is connected to local wiring 57 via contact 81c. Wiring 71c is connected to local wiring 52 via contact 81d. Wiring 71d is connected to local wiring 56 via contact 81e. Wiring 71e is connected to local wiring 50 via contact 81f. Wiring 71f is connected to local wiring 59 via contact 81g. Wiring 71g is connected to local wiring 53 via contact 81h.

[0076] The wiring 71h is connected to the gate wiring 30 via a contact (gate-contact) 82a. The wiring 71i is connected to the gate wiring 34 via a contact 82b. The wiring 71j is connected to the gate wiring 35 via a contact 82c. The wiring 71k is connected to the gate wiring 39 via a contact 82d.

[0077] In the M2 wiring layer, which is the layer above the M1 wiring layer, wirings 91 and 92 are formed, which extend in the X direction from the left to the right ends of the cell in the drawing. The wiring 91 corresponds to the second word line WLB, and the wiring 92 corresponds to the first word line WLA.

[0078] The wiring 91 is connected to the wiring 71h via a contact 101 and to the wiring 71i via a contact 102. The wiring 92 is connected to the wiring 71j via a contact 103 and to the wiring 71k via a contact 104.

[0079] As shown in Figures 2(b) and 3(a), each of the nanosheets 21 to 28 is made up of three sheet-shaped semiconductors (nanosheets). The nanosheets constituting each of the nanosheets 21 to 28 are arranged so as to overlap in a plan view and are spaced apart in the Z direction. That is, each of the nanosheet FETs configured in the two-port SRAM according to this embodiment includes three nanosheets.

[0080] The outer peripheries of the nanosheets 21 to 28 in the X and Z directions are surrounded by the gate wiring. Here, part of the outer periphery of each of the nanosheets 21 to 28 in the X and Z directions is not covered by the gate wiring and is exposed from the gate wiring.

[0081] Specifically, the surfaces of nanosheets 21, 23, 25, and 27 on the right side of the drawing are not covered by gate wirings 30, 33, 35, and 36, respectively, and are exposed from gate wirings 30, 33, 35, and 36, respectively. The surfaces of nanosheets 22, 24, 26, and 28 on the left side of the drawing are not covered by gate wirings 33, 34, 36, and 39, respectively, and are exposed from gate wirings 33, 34, 36, and 39, respectively.

[0082] That is, the surfaces of the nanosheets 23 and 24 that face each other in the X direction are exposed from the gate wirings 33 and 34, respectively. The surfaces of the nanosheets 25 and 26 that face each other in the X direction are exposed from the gate wirings 35 and 36, respectively.

[0083] In addition, in plan view, nanosheet 22 is formed above and to the right of nanosheet 27. That is, the surfaces of nanosheets 22 and 27 that face each other in the X direction are exposed from gate wirings 33 and 36, respectively.

[0084] With the above configuration, the load transistor PU1 has its pad 414 connected to the wiring 71a that supplies the power supply voltage VDD, its pad 413 connected to the local wiring 54 (first node NA), and its gate wiring 36 connected to the shared contact 62 (second node NB). The load transistor PU2 has its pad 411 connected to the wiring 71a that supplies the power supply voltage VDD, its pad 412 connected to the local wiring 55 (second node NB), and its gate wiring 33 connected to the shared contact 61 (first node NA). The drive transistor PD1 has its pad 404 connected to the local wiring 54 (first node NA), its pad 405 connected to the wiring 71b that supplies the power supply voltage VSS, and its gate wiring 36 connected to the shared contact 62 (second node NB). The drive transistor PD2 has its pad 407 connected to the local wiring 55 (second node NB), its pad 406 connected to the wiring 71c that supplies the power supply voltage VSS, and its gate wiring 33 connected to the shared contact 61 (first node NA). The access transistor PG1 has a pad 403 connected to the wiring 71d (first bit line BLA), a pad 402 connected to the local wiring 54 (first node NA), and a gate wiring 35 connected to the wiring 92 (first word line WLA). The access transistor PG2 has a pad 410 connected to the wiring 71f (second bit line BLAX), a pad 409 connected to the local wiring 55 (second node NB), and a gate wiring 39 connected to the wiring 92 (first word line WLA). The access transistor PG3 has a pad 401 connected to the wiring 71e (third bit line BLB), a pad 402 connected to the local wiring 54 (first node NA), and a gate wiring 30 connected to the wiring 91 (second word line WLB). In the access transistor PG4, the pad 408 is connected to the wiring 71g (fourth bit line BLBX), the pad 409 is connected to the local wiring 55 (second node NB), and the gate wiring 34 is connected to the wiring 91 (second word line WLB).

[0085] The load transistors PU1 and PU2, the drive transistors PD1 and PD2, and the access transistors PG1 to PG4 each include nanosheets 27, 22, 26, 23, 25, 28, 21, and 24 extending in the Y direction, and gate wirings 36, 33, 36, 33, 35, 39, 30, and 34 extending in the X direction. The nanosheets 21 to 24 are formed side by side in the X direction in the order of nanosheets 21 to 24. The nanosheets 25 to 28 are formed side by side in the X direction in the order of nanosheets 25 to 28. The gate wirings 30, 34, 35, and 39 surround the outer peripheries of the nanosheets 21, 24, 25, and 28 in the X and Z directions, respectively. The gate wiring 33 surrounds the outer peripheries of the nanosheets 22 and 23 in the X and Z directions. The gate wiring 36 surrounds the outer peripheries of the nanosheets 26 and 27 in the X and Z directions. The right-hand surfaces of the nanosheets 21, 23, 25, and 27 are exposed from the gate wirings 30, 33, 35, and 36, respectively. The left-hand surfaces of the nanosheets 22, 24, 26, and 28 are exposed from the gate wirings 33, 34, 36, and 39, respectively.

[0086] That is, the load transistors PU1 and PU2, the drive transistors PD1 and PD2, and the access transistors PG1 to PG4 are each configured with a fork sheet transistor, thereby realizing a two-port SRAM cell using fork sheet transistors.

[0087] Furthermore, the surfaces of the nanosheets 23 and 24 that face each other in the X direction are exposed from the gate wirings 33 and 34, respectively. The surfaces of the nanosheets 25 and 26 that face each other in the X direction are exposed from the gate wirings 35 and 36, respectively. This makes it possible to reduce the distance d1 in the X direction between the drive transistor PD2 and the access transistor PG4, and the distance d1 in the X direction between the access transistor PG1 and the drive transistor PD1. This allows the area of ​​the semiconductor memory device to be reduced.

[0088] Therefore, a two-port SRAM cell using fork-sheet transistors can be realized, and the area of ​​the semiconductor memory device can be reduced.

[0089] Furthermore, nanosheet 22 is formed above and to the right of nanosheet 27 in plan view. That is, the surfaces of nanosheets 22 and 27 that face each other in the X direction are exposed from gate wirings 33 and 36, respectively. This allows for a reduction in the distance d1 in the X direction between load transistors PU1 and PU2. This allows for a reduction in the area of ​​the semiconductor memory device.

[0090] Although 2-port SRAM cells inverted in the X direction are arranged on both the left and right sides of the 2-port SRAM cell in Fig. 1, this is not limitative. 2-port SRAM cells inverted in the X direction may also be arranged on both the left and right sides of the 2-port SRAM cell in Fig. 1.

[0091] 1, the X-direction width of nanosheets 21, 24, 25, and 28 is twice the X-direction width of nanosheets 22 and 27, and the X-direction width of nanosheets 23 and 26 is four times the X-direction width of nanosheets 22 and 27, but this is not limited to this. The X-direction width of each of nanosheets 21 to 28 (i.e., the gate width of each transistor) may be determined taking into consideration the operational stability of the two-port SRAM cell circuit, etc.

[0092] Furthermore, the shared contacts 61 and 62 may be manufactured in the same process step as the contacts 82a to 82d that connect the gate wiring and the M1 wiring, or may be manufactured in a different process step.

[0093] 1, the wiring 71b is arranged to the right of the wiring 71e in the drawing, and the wiring 71c is arranged to the left of the wiring 71f in the drawing, but this is not limited to this. The positions of the wirings 71b and 71e may be interchanged, or the positions of the wirings 71c and 71f may be interchanged. In this case, the wiring 71b is arranged between the wirings 71d and 71e, and the wiring 71c is arranged between the wirings 71f and 71g. This makes it possible to suppress crosstalk between the wirings 71d and 71e and between the wirings 71f and 71g, i.e., crosstalk between the first bit line BLA and the third bit line BLB and between the second bit line BLAX and the fourth bit line BLBX.

[0094] Furthermore, the wirings 71d and 71e may be spaced apart in the X direction, and the wirings 71f and 71g may be spaced apart in the X direction, thereby suppressing crosstalk between the first bit line BLA and the third bit line BLB and between the second bit line BLAX and the fourth bit line BLBX.

[0095] (Variation 1) FIG. 5 is a plan view showing another example of the layout structure of the two-port SRAM cell according to the first embodiment. Specifically, FIG. 5(a) shows the upper part of the cell, and FIG. 5(b) shows the lower part of the cell. In FIG. 5, compared to FIG. 1, the drive transistors PD1 and PD2 are each composed of two nanosheet FETs. Specifically, the drive transistor PD1 is composed of transistors PD11 and PD12. The drive transistor PD2 is composed of transistors PD21 and PD22.

[0096] 5(b), nanosheets 23a, 23b, 26a, and 26b are formed to extend in the X and Y directions. The nanosheets 26a, 26b, 23a, and 23b form the channels of transistors PD11, PD12, PD21, and PD22, respectively.

[0097] The nanosheets 21, 22, 23a, 23b, and 24 are formed side by side in the X direction in the order of nanosheets 21, 22, 23a, 23b, and 24. The nanosheets 25, 26a, 26b, 27, and 28 are formed side by side in the X direction in the order of nanosheets 25, 26a, 26b, 27, and 28.

[0098] The width of the nanosheets 23a, 23b, 26a, and 26b in the X direction is twice the width of the nanosheets 22 and 27 in the X direction.

[0099] The gate wiring 32 overlaps with the nanosheet 22 in a planar view. The gate wiring 33 overlaps with the nanosheets 23a and 23b in a planar view. The gate wiring 36 overlaps with the nanosheets 26a and 26b in a planar view. The gate wiring 37 overlaps with the nanosheet 27 in a planar view. In FIG. 5, the gate wiring 32 serves as the gate of the load transistor PU2. The gate wiring 33 serves as the gates of the transistors PD21 and PD22. The gate wiring 36 serves as the gates of the transistors PD11 and PD12. The gate wiring 37 serves as the gate of the load transistor PU1.

[0100] Pads 404a, 405a, 404b, 405b, 406a, 407a, 406b, and 407b doped with N-type semiconductor are formed at the upper end of nanosheet 26a in the drawing, the lower end of nanosheet 26a in the drawing, the upper end of nanosheet 26b in the drawing, the lower end of nanosheet 26b in the drawing, the upper end of nanosheet 23a in the drawing, the lower end of nanosheet 23a in the drawing, the upper end of nanosheet 23b in the drawing, and the lower end of nanosheet 23b in the drawing. Pads 404a and 405a form the node of transistor PD11. Pads 404b and 405b form the node of transistor PD12. Pads 406a and 407a form the node of transistor PD21. Pads 406b and 407b form the node of transistor PD22.

[0101] 5, transistor PD11 is formed by nanosheet 26a, gate wiring 36, and pads 404a and 405a. Transistor PD12 is formed by nanosheet 26b, gate wiring 36, and pads 404b and 405b. Transistor PD21 is formed by nanosheet 23a, gate wiring 33, and pads 406a and 407a. Transistor PD22 is formed by nanosheet 23b, gate wiring 33, and pads 406b and 407b.

[0102] In addition, local wiring 52 is connected to pads 406a and 406b. Local wiring 54 is connected to pads 402, 404a, 404b, and 413. Local wiring 55 is connected to pads 412, 407a, 407b, and 409. Local wiring 57 is connected to pads 405a and 405b.

[0103] In FIG. 5, nanosheets 21, 22, 23a, 23b, 24, 25, 26a, 26b, 27, and 28 each have a portion of their periphery in the X and Z directions that is not covered by the gate wiring and is exposed from the gate wiring.

[0104] Specifically, the surfaces of nanosheets 21, 22, 23b, 25, and 26b on the right side of the drawing are not covered by gate wirings 30, 32, 33, 35, and 36, respectively, and are exposed from gate wirings 30, 32, 33, 35, and 36, respectively. The surfaces of nanosheets 23a, 24, 26a, 27, and 28 on the left side of the drawing are not covered by gate wirings 33, 34, 36, 37, and 39, respectively, and are exposed from gate wirings 33, 34, 36, 37, and 39, respectively.

[0105] That is, the surfaces of the nanosheets 22 and 23a that face each other in the X direction are exposed from the gate wirings 32 and 33, respectively. The surfaces of the nanosheets 23b and 24 that face each other in the X direction are exposed from the gate wirings 33 and 34, respectively. The surfaces of the nanosheets 25 and 26a that face each other in the X direction are exposed from the gate wirings 35 and 36, respectively. The surfaces of the nanosheets 26b and 27 that face each other in the X direction are exposed from the gate wirings 36 and 37, respectively.

[0106] According to the layout structure of FIG. 5, the surfaces of nanosheets 22 and 23a facing each other in the X direction are exposed from gate wirings 32 and 33, respectively. The surfaces of nanosheets 23b and 24 facing each other in the X direction are exposed from gate wirings 33 and 34, respectively. The surfaces of nanosheets 25 and 26a facing each other in the X direction are exposed from gate wirings 35 and 36, respectively. The surfaces of nanosheets 26b and 27 facing each other in the X direction are exposed from gate wirings 36 and 37, respectively. This reduces the distance d1 in the X direction between load transistor PU2 and transistor PD21, the distance d1 in the X direction between transistor PD22 and access transistor PG4, the distance d1 in the X direction between access transistor PG1 and transistor PD11, and the distance d1 in the X direction between transistor PD12 and load transistor PU1. This allows for a reduction in the area of ​​the semiconductor memory device.

[0107] Furthermore, the width in the X direction of nanosheets 23a, 23b, 26a, and 26b is twice the width in the X direction of nanosheets 23 and 26. This allows the width in the X direction of the nanosheets that form drive transistors PD1 and PD2 to be reduced, thereby improving the ease of manufacturing the semiconductor memory device.

[0108] In addition, the same effects as those shown in FIG. 1 can be obtained.

[0109] Although 2-port SRAM cells inverted in the X direction are arranged on both the left and right sides of the 2-port SRAM cell in Fig. 5, this is not limitative. 2-port SRAM cells inverted in the X direction may also be arranged on both the left and right sides of the 2-port SRAM cell in Fig. 5.

[0110] (Variation 2) 6 is a plan view showing another example of the layout structure of the 2-port SRAM cell according to the first embodiment. Specifically, FIG. 6(a) shows the upper part of the cell, and FIG. 6(b) shows the lower part of the cell. In FIG. 6, the arrangement of the access transistors PG2 and PG3 and the wirings 71e and 71f is different from that in FIG. 5. Specifically, the access transistor PG2 is arranged on the left side of the drawing compared to FIG. 5, and the access transistor PG3 is arranged on the right side of the drawing compared to FIG. 5. Furthermore, the wirings 71e and 71f are arranged spaced apart from the wirings 71d and 71g in the X direction, respectively.

[0111] As shown in Figure 6(b), nanosheet 21 is formed above pad 404a in the drawing and is connected to pad 404a. Nanosheet 28 is formed below pad 407b in the drawing and is connected to pad 407b. Pad 401 is formed above nanosheet 21 in the drawing. Pad 410 is formed below nanosheet 28 in the drawing.

[0112] 6, the nanosheets 21 and 26a are formed side by side in the Y direction, and the nanosheets 23b and 28 are formed side by side in the Y direction.

[0113] Gate wirings 31a and 31b extending in the X and Z directions are formed between the gate wirings 30 and 32. Gate wirings 38a and 38b extending in the X and Z directions are formed between the gate wirings 37 and 39.

[0114] The gate wiring 31a overlaps the nanosheet 21 in a planar view. The gate wiring 38b overlaps the nanosheet 28 in a planar view. In Fig. 6, the gate wiring 31a serves as the gate of the access transistor PG3. The gate wiring 38b serves as the gate of the access transistor PG2.

[0115] 6, the nanosheet 21, the gate wiring 31a, and the pads 401 and 404a form an access transistor PG3, while the nanosheet 28, the gate wiring 38b, and the pads 407b and 410 form an access transistor PG2.

[0116] 6(a), a wiring 71d which is a first bit line BLA and a wiring 71e which is a third bit line BLB are arranged spaced apart in the X direction. A wiring 71f which is a second bit line BLAX and a wiring 71g which is a fourth bit line BLBX are arranged spaced apart in the X direction. Furthermore, the wirings 71a to 71c are arranged closely to each other.

[0117] Furthermore, the wiring 71h is disposed between the wirings 71d and 71e. The wiring 71k is disposed between the wirings 71f and 71g. The wiring 71h is connected to the gate wiring 31a via a contact 82a. The wiring 71k is connected to the gate wiring 38b via a contact 82d.

[0118] 6, the surface of nanosheet 21 on the left side of the drawing is not covered by gate wiring 31a and is exposed from gate wiring 31a, and the surface of nanosheet 28 on the right side of the drawing is not covered by gate wiring 38b and is exposed from gate wiring 38b.

[0119] 6, the spacing between the first bit line BLA and the third bit line BLB and between the second bit line BLAX and the fourth bit line BLBX is widened, reducing the coupling capacitance between the bit lines, thereby suppressing noise due to the coupling capacitance between the bit lines and enabling faster write and read operations to the 2-port SRAM cell.

[0120] In addition, the same effects as those in FIG. 5 can be obtained.

[0121] (Variation 3) FIG. 7 is a plan view showing another example of the layout structure of the 2-port SRAM cell according to the first embodiment. Specifically, FIG. 7(a) shows the upper part of the cell, and FIG. 7(b) shows the lower part of the cell. In FIG. 7, the arrangement of the access transistors PG2 and PG3 and the wirings 71b, 71c, 71e, and 71f is different from that in FIG. 6. Specifically, the access transistor PG2 is arranged on the left side of the drawing compared to FIG. 6, and the access transistor PG3 is arranged on the right side of the drawing compared to FIG. 6. Furthermore, the wiring 71b is arranged between the wirings 71d and 71e, and the wiring 71c is arranged between the wirings 71f and 71g.

[0122] As shown in Figure 7(b), nanosheet 21 is formed above pad 404b in the drawing and is connected to pad 404b. Nanosheet 28 is formed below pad 407a in the drawing and is connected to pad 407a. Pad 401 is formed above nanosheet 21 in the drawing. Pad 410 is formed below nanosheet 28 in the drawing.

[0123] 7, the nanosheets 21 and 26b are formed side by side in the Y direction. The nanosheets 23a and 28 are formed side by side in the Y direction.

[0124] The gate wiring 31b overlaps with the nanosheet 21 in a planar view. The gate wiring 38a overlaps with the nanosheet 28 in a planar view. In Fig. 7, the gate wiring 31b serves as the gate of the access transistor PG3. The gate wiring 38a serves as the gate of the access transistor PG2.

[0125] 7, the nanosheet 21, the gate wiring 31b, and the pads 401 and 404b form an access transistor PG3, while the nanosheet 28, the gate wiring 38a, and the pads 407a and 410 form an access transistor PG2.

[0126] 7(a), a line 71b for supplying a power supply voltage VSS is disposed between a line 71d which is the first bit line BLA and a line 71e which is the third bit line BLB, and a line 71c for supplying a power supply voltage VSS is disposed between a line 71f which is the second bit line BLAX and a line 71g which is the fourth bit line BLBX.

[0127] Furthermore, the wiring 71h is disposed between the wirings 71a and 71e. The wiring 71k is disposed between the wirings 71a and 71f. The wiring 71h is connected to the gate wiring 31b via a contact 82a. The wiring 71k is connected to the gate wiring 38a via a contact 82d.

[0128] 7, the surface of nanosheet 21 on the right side of the drawing is not covered by gate wiring 31b and is exposed from gate wiring 31b, and the surface of nanosheet 28 on the left side of the drawing is not covered by gate wiring 38a and is exposed from gate wiring 38a.

[0129] 7, the power supply wiring VSS is arranged between the first bit line BLA and the third bit line BLB and between the second bit line BLAX and the fourth bit line BLBX, thereby reducing the coupling capacitance between the bit lines, thereby suppressing noise due to the coupling capacitance between the bit lines and enabling faster write and read operations to the 2-port SRAM cell.

[0130] In addition, the same effects as those in FIG. 6 can be obtained.

[0131] (Variation 4) 8A and 8B are plan views showing another example of the layout structure of the two-port SRAM cell according to the first embodiment. Specifically, FIG. 8A shows the upper part of the cell, and FIG. 8B shows the lower part of the cell. In FIG. 8, the surface of each nanosheet opposite to that shown in FIG. 1 in the X direction is exposed from the gate wiring.

[0132] As shown in FIG. 8(b), the gate wirings 32, 33, 36, and 37 overlap with the nanosheets 22, 23, 26, and 27, respectively, in a planar view. In FIG. 8, the gate wiring 32 serves as the gate of the load transistor PU2. The gate wiring 33 serves as the gate of the drive transistor PD2. The gate wiring 36 serves as the gate of the drive transistor PD1. The gate wiring 37 serves as the gate of the load transistor PU1.

[0133] Furthermore, the gate wirings 30 and 35 are connected to the gate wirings 30 and 35 arranged on the left side of the two-port SRAM cell in the drawing via bridge portions 12 and 14 extending in the X direction, respectively. The gate wirings 34 and 39 are connected to the gate wirings 34 and 39 arranged on the right side of the two-port SRAM cell in the drawing via bridge portions 13 and 15 extending in the X direction, respectively.

[0134] The wiring 71h is connected to the gate wiring 30 via the contact 82a and the bridge portion 12. The wiring 71i is connected to the gate wiring 34 via the contact 82b and the bridge portion 13. The wiring 71j is connected to the gate wiring 35 via the contact 82c and the bridge portion 14. The wiring 71k is connected to the gate wiring 39 via the contact 82d and the bridge portion 15.

[0135] 8, the surfaces of nanosheets 21, 23, 25, and 27 on the left side of the drawing are not covered by gate wirings 30, 33, 35, and 37, respectively, and are exposed from gate wirings 30, 33, 35, and 37, respectively. The surfaces of nanosheets 22, 24, 26, and 28 on the right side of the drawing are not covered by gate wirings 32, 34, 36, and 39, respectively, and are exposed from gate wirings 32, 34, 36, and 39, respectively.

[0136] That is, the surfaces of the nanosheets 22 and 23 that face each other in the X direction are exposed from the gate wirings 32 and 33, respectively. The surfaces of the nanosheets 26 and 27 that face each other in the X direction are exposed from the gate wirings 36 and 37, respectively.

[0137] Furthermore, nanosheets 21 and 25 are arranged close to the cell boundary on the left side of the drawing. Nanosheets 24 and 28 are arranged close to the cell boundary on the right side of the drawing. In the two-port SRAM cell of FIG. 8, two-port SRAM cells inverted in the X direction are arranged on both the left and right sides of the drawing. That is, in the two-port SRAM cells arranged side by side in the X direction, the surfaces of nanosheets 21 facing each other in the X direction are exposed from gate wiring 30. The surfaces of nanosheets 24 facing each other in the X direction are exposed from gate wiring 34. The surfaces of nanosheets 25 facing each other in the X direction are exposed from gate wiring 35. The surfaces of nanosheets 28 facing each other in the X direction are exposed from gate wiring 39.

[0138] 8, the surfaces of the nanosheets 22 and 23 facing each other in the X direction are exposed from the gate wirings 32 and 33, respectively. The surfaces of the nanosheets 26 and 27 facing each other in the X direction are exposed from the gate wirings 36 and 37, respectively. This reduces the distance d1 in the X direction between the load transistor PU2 and the drive transistor PD2, and the distance d1 in the X direction between the drive transistor PD1 and the load transistor PU1. This allows the area of ​​the semiconductor memory device to be reduced.

[0139] Furthermore, in the two-port SRAM cells arranged side by side in the X direction, the surfaces of the nanosheets 21 facing each other in the X direction are exposed from the gate wiring 30. The surfaces of the nanosheets 24 facing each other in the X direction are exposed from the gate wiring 34. The surfaces of the nanosheets 25 facing each other in the X direction are exposed from the gate wiring 35. The surfaces of the nanosheets 28 facing each other in the X direction are exposed from the gate wiring 39. This makes it possible to reduce the distance d1 in the X direction between the access transistors PG3, the distance d1 in the X direction between the access transistors PG4, the distance d1 in the X direction between the access transistors PG1, and the distance d1 in the X direction between the access transistors PG2. This allows the area of ​​the semiconductor memory device to be reduced.

[0140] In addition, the same effects as those shown in FIG. 1 can be obtained.

[0141] Although 2-port SRAM cells inverted in the X direction are arranged on both the left and right sides of the 2-port SRAM cell in Fig. 8, this is not limitative. 2-port SRAM cells inverted in the X direction may also be arranged on both the left and right sides of the 2-port SRAM cell in Fig. 8.

[0142] (Variation 5) FIG. 9 is a plan view showing another example of the layout structure of the two-port SRAM cell according to the first embodiment. Specifically, FIG. 9(a) shows the upper part of the cell, and FIG. 9(b) shows the lower part of the cell. In FIG. 9, compared with FIG. 8, the drive transistors PD1 and PD2 are each composed of two nanosheet FETs. Specifically, the drive transistor PD1 is composed of transistors PD11 and PD12. The drive transistor PD2 is composed of transistors PD21 and PD22.

[0143] As shown in Fig. 9(b), nanosheets 23a, 23b, 26a, and 26b are formed. In Fig. 9, the nanosheets 26a, 26b, 23a, and 23b form the channels of transistors PD11, PD12, PD21, and PD22, respectively.

[0144] The nanosheets 21, 22, 23a, 23b, and 24 are formed side by side in the X direction in the order of nanosheets 21, 22, 23a, 23b, and 24. The nanosheets 25, 26a, 26b, 27, and 28 are formed side by side in the X direction in the order of nanosheets 25, 26a, 26b, 27, and 28.

[0145] The width of the nanosheets 23a, 23b, 26a, and 26b in the X direction is twice the width of the nanosheets 23 and 26 in the X direction.

[0146] Gate wirings 31a and 31b extending in the X and Z directions are formed between gate wirings 30 and 32. Gate wirings 33a and 33b extending in the X and Z directions are formed between gate wirings 32 and 34. Gate wirings 36a and 36b extending in the X and Z directions are formed between gate wirings 35 and 37. Gate wirings 38a and 38b extending in the X and Z directions are formed between gate wirings 37 and 39.

[0147] The gate wiring 33a overlaps with the nanosheets 22 and 23a in a planar view. The gate wiring 33b overlaps with the nanosheet 23b in a planar view. The gate wiring 36a overlaps with the nanosheet 26a in a planar view. The gate wiring 36b overlaps with the nanosheets 26b and 27 in a planar view. In FIG. 9, the gate wiring 33a serves as the gate of the load transistor PU2 and the transistor PD21. The gate wiring 33b serves as the gate of the transistor PD22. The gate wiring 36a serves as the gate of the transistor PD11. The gate wiring 36b serves as the gate of the transistor PD12 and the load transistor PU1.

[0148] The gate wirings 31a and 31b are connected to each other via a bridge portion 16 extending in the X direction. The gate wirings 32 and 33a are connected to each other via a bridge portion 10. The gate wirings 33a and 33b are connected to each other via a bridge portion 17 extending in the X direction. The gate wirings 36a and 36b are connected to each other via a bridge portion 18. The gate wirings 36b and 37 are connected to each other via a bridge portion 11. The gate wirings 38a and 38b are connected to each other via a bridge portion 19.

[0149] 9, pads 404a and 405a form a node for transistor PD11. Pads 404b and 405b form a node for transistor PD12. Pads 406a and 407a form a node for transistor PD21. Pads 406b and 407b form a node for transistor PD22.

[0150] In FIG. 9, the surfaces of nanosheets 23a, 26a, and 27 on the right side of the drawing are not covered by gate wirings 33a, 36a, and 36b, respectively, and are exposed from the gate wirings 33a, 36a, and 36b, respectively. The surfaces of nanosheets 22, 23b, and 26b on the left side of the drawing are not covered by gate wirings 33a, 33b, and 36b, respectively, and are exposed from the gate wirings 33a, 33b, and 36b, respectively. That is, the surfaces of nanosheets 23a and 23b that face each other in the X direction are exposed from the gate wirings 33a and 33b, respectively. The surfaces of nanosheets 26a and 26b that face each other in the X direction are exposed from the gate wirings 36a and 36b, respectively.

[0151] In addition, in plan view, nanosheet 22 is formed above and to the right of nanosheet 27. That is, the surfaces of nanosheets 22 and 27 that face each other in the X direction are exposed from gate wirings 33a and 36b, respectively.

[0152] 9, the surfaces of nanosheets 23a and 23b facing each other in the X direction are exposed from gate wirings 33a and 33b, respectively. The surfaces of nanosheets 26a and 26b facing each other in the X direction are exposed from gate wirings 36a and 36b, respectively. This reduces the distance d1 in the X direction between transistors PD21 and PD22 and the distance d1 in the X direction between transistors PD11 and PD12. This allows the area of ​​the semiconductor memory device to be reduced.

[0153] Furthermore, the nanosheets 22 and 27 have their opposing surfaces exposed from the gate wirings 33a and 36b in the X direction, respectively. This reduces the distance d1 between the load transistors PU1 and PU2 in the X direction, thereby enabling the semiconductor memory device to have a smaller area.

[0154] Furthermore, the width in the X direction of nanosheets 23a, 23b, 26a, and 26b is twice the width in the X direction of nanosheets 23 and 26. This allows the width in the X direction of the nanosheets that make up drive transistors PD1 and PD2 to be reduced, thereby improving the ease of manufacturing the semiconductor memory device.

[0155] In addition, the same effects as those in FIG. 8 can be obtained.

[0156] 9, two-port SRAM cells inverted in the X direction are arranged on both the left and right sides of the two-port SRAM cell in the drawing, but this is not limited to this. Two-port SRAM cells inverted in the X direction may also be arranged on both the left and right sides of the two-port SRAM cell in the drawing.

[0157] (Variation 6) FIG. 10 is a plan view showing another example of the layout structure of the 2-port SRAM cell according to the first embodiment. Specifically, FIG. 10(a) shows the upper part of the cell, and FIG. 10(b) shows the lower part of the cell. In FIG. 10, the arrangement of the access transistors PG2 and PG3 and the wirings 71e and 71f is different from that in FIG. 9. Specifically, the access transistor PG2 is arranged on the left side of the drawing compared to FIG. 9, and the access transistor PG3 is arranged on the right side of the drawing compared to FIG. 9. Furthermore, the wirings 71e and 71f are arranged spaced apart from the wirings 71d and 71g in the X direction. Note that the bridge portions 16 and 19 are omitted.

[0158] 10(b), nanosheet 21 is formed above pad 404a in the drawing and is connected to pad 404a. Nanosheet 28 is formed below pad 407b in the drawing and is connected to pad 407b. Pad 401 is formed above nanosheet 21 in the drawing. Pad 410 is formed below nanosheet 28 in the drawing.

[0159] 10, the nanosheets 21 and 26a are formed side by side in the Y direction. The nanosheets 23b and 28 are formed side by side in the Y direction.

[0160] The gate wiring 31a overlaps the nanosheet 21 in a planar view. The gate wiring 38b overlaps the nanosheet 28 in a planar view. In Fig. 10, the gate wiring 31a serves as the gate of the access transistor PG3. The gate wiring 38b serves as the gate of the access transistor PG2.

[0161] 10, the nanosheet 21, the gate wiring 31a, and the pads 401 and 404a form an access transistor PG3, while the nanosheet 28, the gate wiring 38b, and the pads 407b and 410 form an access transistor PG2.

[0162] 10(a), a wiring 71d which is a first bit line BLA and a wiring 71e which is a third bit line BLB are arranged spaced apart in the X direction. A wiring 71f which is a second bit line BLAX and a wiring 71g which is a fourth bit line BLBX are arranged spaced apart in the X direction. Furthermore, the wirings 71a to 71c are arranged closely to each other.

[0163] Furthermore, the wiring 71h is disposed between the wirings 71d and 71e. The wiring 71k is disposed between the wirings 71f and 71g. The wiring 71h is connected to the gate wiring 31a via a contact 82a. The wiring 71k is connected to the gate wiring 38b via a contact 82d.

[0164] 10, the surface of nanosheet 21 on the right side of the drawing is not covered by gate wiring 31a and is exposed from gate wiring 31a, and the surface of nanosheet 28 on the left side of the drawing is not covered by gate wiring 38b and is exposed from gate wiring 38b.

[0165] 10, the spacing between the first bit line BLA and the third bit line BLB and between the second bit line BLAX and the fourth bit line BLBX is widened, reducing the coupling capacitance between the bit lines, thereby suppressing noise due to the coupling capacitance between the bit lines and enabling faster write and read operations to the 2-port SRAM cell.

[0166] In addition, the same effects as those in FIG. 9 can be obtained.

[0167] (Variation 7) FIG. 11 is a plan view showing another example of the layout structure of the 2-port SRAM cell according to the first embodiment. Specifically, FIG. 11(a) shows the upper part of the cell, and FIG. 11(b) shows the lower part of the cell. In FIG. 11, the arrangement of the access transistors PG2 and PG3 and the wirings 71b, 71c, 71e, and 71f is different from that in FIG. 10. Specifically, the access transistor PG2 is arranged on the left side of the drawing compared to FIG. 10, and the access transistor PG3 is arranged on the right side of the drawing compared to FIG. 10. Furthermore, the wiring 71b is arranged between the wirings 71d and 71e, and the wiring 71c is arranged between the wirings 71f and 71g.

[0168] 11(b), nanosheet 21 is formed above pad 404b in the drawing and is connected to pad 404b. Nanosheet 28 is formed below pad 407a in the drawing and is connected to pad 407a. Pad 401 is formed above nanosheet 21 in the drawing. Pad 410 is formed below nanosheet 28 in the drawing.

[0169] 11, the nanosheets 21 and 26b are formed side by side in the Y direction. The nanosheets 23a and 28 are formed side by side in the Y direction.

[0170] The gate wiring 31b overlaps with the nanosheet 21 in a planar view. The gate wiring 38a overlaps with the nanosheet 28 in a planar view. In FIG. 11, the gate wiring 31b serves as the gate of the access transistor PG3. The gate wiring 38a serves as the gate of the access transistor PG2. Note that the gate wirings 30 and 39 are omitted.

[0171] 11, the nanosheet 21, the gate wiring 31b, and the pads 401 and 404b form an access transistor PG3, while the nanosheet 28, the gate wiring 38a, and the pads 407a and 410 form an access transistor PG2.

[0172] 11(a), a line 71b for supplying a power supply voltage VSS is arranged between a line 71d which is the first bit line BLA and a line 71e which is the third bit line BLB. A line 71c for supplying a power supply voltage VSS is arranged between a line 71f which is the second bit line BLAX and a line 71g which is the fourth bit line BLBX.

[0173] Furthermore, the wiring 71h is disposed between the wirings 71a and 71e. The wiring 71k is disposed between the wirings 71a and 71f. The wiring 71h is connected to the gate wiring 31b via a contact 82a. The wiring 71k is connected to the gate wiring 38a via a contact 82d.

[0174] 11, the surface of nanosheet 21 on the left side of the drawing is not covered by gate wiring 31b and is exposed from gate wiring 31b, and the surface of nanosheet 28 on the right side of the drawing is not covered by gate wiring 38a and is exposed from gate wiring 38a.

[0175] 11, the power supply wiring VSS is arranged between the first bit line BLA and the third bit line BLB and between the second bit line BLAX and the fourth bit line BLBX, thereby reducing the coupling capacitance between the bit lines, thereby suppressing noise due to the coupling capacitance between the bit lines and enabling faster write and read operations to the 2-port SRAM cell.

[0176] In addition, the same effects as those in FIG. 10 can be obtained.

[0177] (Second embodiment) 12 is a plan view showing an example of the layout structure of a 2-port SRAM cell according to the second embodiment. Specifically, FIG. 12(a) shows the upper part of the cell, and FIG. 12(b) shows the lower part of the cell. In FIG. 12, the 2-port SRAM cell circuit of FIG. 4 is configured by load transistors PU1 and PU2, drive transistor PD1 (transistors PD11 and PD12), drive transistor PD2 (transistors PD21 and PD22), and access transistors PG1 to PG4. In the 2-port SRAM cell of FIG. 12, 2-port SRAM cells inverted in the X direction are arranged on both the left and right sides of the drawing.

[0178] 12(b), the nanosheets 21, 22, 23a, 23b, and 24 are arranged in the X direction in the order of nanosheets 24, 21, 22, 23a, and 23b. The nanosheets 25, 26a, 26b, 27, and 28 are arranged in the X direction in the order of nanosheets 26a, 26b, 27, 28, and 25.

[0179] The nanosheets 21 and 26a are formed side by side in the Y direction. The nanosheets 23b and 28 are formed side by side in the Y direction.

[0180] Gate wiring 30 overlaps with nanosheets 24 and 21 in a planar view. Gate wiring 33 overlaps with nanosheets 22 and 23a in a planar view. Gate wiring 34 overlaps with nanosheet 23b in a planar view. Gate wiring 35 overlaps with nanosheet 26a in a planar view. Gate wiring 36 overlaps with nanosheets 26b and 27 in a planar view. Gate wiring 39 overlaps with nanosheets 28 and 25 in a planar view.

[0181] The gate wiring 30 is connected to the gate wiring 30 of a 2-port SRAM cell arranged on the left side of the 2-port SRAM cell in the drawing via a bridge portion 12. The gate wirings 32 and 33 are connected to each other via a bridge portion 10. The gate wirings 33 and 34 are connected to each other via a bridge portion 110 extending in the X direction. The gate wirings 35 and 36 are connected to each other via a bridge portion 111 extending in the X direction. The gate wirings 36 and 37 are connected to each other via a bridge portion 11. The gate wiring 39 is connected to the gate wiring 39 of a 2-port SRAM cell arranged on the right side of the 2-port SRAM cell in the drawing via a bridge portion 15.

[0182] In FIG. 12, access transistor PG4 is formed by nanosheet 24, gate wiring 30, and pads 408 and 409. Access transistor PG3 is formed by nanosheet 21, gate wiring 30, and pads 401 and 404a. Load transistor PU2 is formed by nanosheet 22, gate wiring 33, and pads 411 and 412. Transistor PD21 is formed by nanosheet 23a, gate wiring 33, and pads 406a and 407a. Transistor PD22 is formed by nanosheet 23b, gate wiring 34, and pads 406b and 407b. Transistor PD11 is formed by nanosheet 26a, gate wiring 35, and pads 404a and 405a. Transistor PD12 is formed by nanosheet 26b, gate wiring 36, and pads 404b and 405b. Load transistor PU1 is formed by nanosheet 27, gate wiring 36, and pads 413 and 414. The nanosheet 28, the gate wiring 39, and the pads 407b and 410 form an access transistor PG2. The nanosheet 25, the gate wiring 39, and the pads 402 and 403 form an access transistor PG1.

[0183] Therefore, the access transistors PG4 and PG3, the load transistor PU2, and the transistors PD21 and PD22 are arranged side by side in the X direction. The transistors PD11 and PD12, the load transistor PU1, and the access transistors PG2 and PG1 are arranged side by side in the X direction. The access transistor PG3 and the transistor PD11 are arranged side by side in the Y direction. The transistor PD22 and the access transistor PG2 are arranged side by side in the Y direction.

[0184] Local wirings 150 and 151 extending in the X direction are formed in the local wiring layer. The local wiring 150 is connected to a pad 402 and to a gate wiring 34 via a shared contact 63. The local wiring 151 is connected to a pad 409 and to a gate wiring 35 via a shared contact 64. In FIG. 12 , the gate wirings 32, 33, and 34, the bridge portions 10 and 110, the local wirings 54 and 150, and the shared contacts 61 and 63 correspond to a first node NA. The gate wirings 35, 36, and 37, the bridge portions 11 and 111, the local wirings 55 and 151, and the shared contacts 62 and 64 correspond to a second node NB.

[0185] As shown in FIG. 12(a), on the left side of the drawing, a wiring 71g which is the fourth bit line BLBX and a wiring 71e which is the third bit line BLB are arranged spaced apart in the X direction. On the right side of the drawing, a wiring 71f which is the second bit line BLAX and a wiring 71d which is the first bit line BLA are arranged spaced apart in the X direction. That is, the third and fourth bit lines BLB and BLBX which are complementary to each other are arranged on the left side of the drawing. The first and second bit lines BLA and BLAX which are complementary to each other are arranged on the right side of the drawing.

[0186] Here, the surfaces of nanosheets 21, 23a, 26a, 27, and 25 on the right side of the drawing are not covered by gate wirings 30, 33, 35, 36, and 39, respectively, and are exposed from gate wirings 30, 33, 35, 36, and 39, respectively. The surfaces of nanosheets 24, 22, 23b, 26b, and 28 on the left side of the drawing are not covered by gate wirings 30, 33, 34, 36, and 39, respectively, and are exposed from gate wirings 30, 33, 34, 36, and 39, respectively.

[0187] That is, the surfaces of the nanosheets 23a and 23b that face each other in the X direction are exposed from the gate wirings 33 and 34, respectively. The surfaces of the nanosheets 26a and 26b that face each other in the X direction are exposed from the gate wirings 35 and 36, respectively.

[0188] In addition, in plan view, nanosheet 22 is formed above and to the right of nanosheet 27. That is, the surfaces of nanosheets 22 and 27 that face each other in the X direction are exposed from gate wirings 33 and 36, respectively.

[0189] Furthermore, nanosheet 24 is arranged adjacent to the cell boundary on the left side of the drawing in plan view. Nanosheet 25 is arranged adjacent to the cell boundary on the right side of the drawing in plan view. In the two-port SRAM cell of FIG. 12, two-port SRAM cells inverted in the X direction are arranged on both the left and right sides of the drawing. That is, in the two-port SRAM cells arranged side by side in the X direction, the surfaces of nanosheets 24 facing each other in the X direction are exposed from gate wiring 30. The surfaces of nanosheets 25 facing each other in the X direction are exposed from gate wiring 39.

[0190] With the above configuration, the surfaces of nanosheets 23a and 23b facing each other in the X direction are exposed from gate wirings 33 and 34, respectively. The surfaces of nanosheets 26a and 26b facing each other in the X direction are exposed from gate wirings 35 and 36, respectively. This makes it possible to reduce the distance d1 in the X direction between transistors PD21 and PD22 and the distance d1 in the X direction between transistors PD11 and PD12. This allows the area of ​​the semiconductor memory device to be reduced.

[0191] Furthermore, the surfaces of the nanosheets 22 and 27 that face each other in the X direction are exposed from the gate wirings 33 and 36, respectively. This reduces the distance d1 in the X direction between the load transistors PU1 and PU2. This allows the area of ​​the semiconductor memory device to be reduced.

[0192] Furthermore, in the two-port SRAM cells arranged side by side in the X direction, the surfaces of the nanosheets 24 facing each other in the X direction are exposed from the gate wiring 30. The surfaces of the nanosheets 25 facing each other in the X direction are exposed from the gate wiring 39. This makes it possible to reduce the distance d1 in the X direction between the access transistors PG4 and the distance d1 in the X direction between the access transistors PG1. This allows the area of ​​the semiconductor memory device to be reduced.

[0193] Furthermore, the distance between the first bit line BLA and the second bit line BLAX and the distance between the third bit line BLB and the fourth bit line BLBX are increased, reducing the coupling capacitance between the bit lines, thereby suppressing noise due to the coupling capacitance between the bit lines and enabling faster write and read operations to the 2-port SRAM cell.

[0194] Shield wiring (wiring connected to power supply voltages VDD and VSS) extending in the Y direction may be disposed between the wiring 71g and the wiring 71e, and between the wiring 71f and the wiring 71d.

[0195] (Variation 1) FIG. 13 is a plan view showing another example of the layout structure of a 2-port SRAM cell according to the second embodiment. Specifically, FIG. 13(a) shows the upper part of the cell, and FIG. 13(b) shows the lower part of the cell. In FIG. 13, the arrangement of access transistors PG2 and PG3 and wires 71b, 71c, 71e, and 71f is different from that in FIG. 12. Specifically, access transistor PG2 is arranged on the left side of the drawing compared to FIG. 12, and access transistor PG3 is arranged on the right side of the drawing compared to FIG. 12. Furthermore, wire 71b is arranged between wires 71g and 71e, and wire 71c is arranged between wires 71f and 71d.

[0196] 13(b), nanosheet 21 is formed above pad 404b in the drawing and is connected to pad 404b. Nanosheet 28 is formed below pad 407a in the drawing and is connected to pad 407a. Pad 401 is formed above nanosheet 21 in the drawing. Pad 410 is formed below nanosheet 28 in the drawing.

[0197] 13, the nanosheets 21 and 26b are formed side by side in the Y direction. The nanosheets 23a and 28 are formed side by side in the Y direction.

[0198] The gate wiring 31 overlaps the nanosheet 21 in plan view. The gate wiring 38 overlaps the nanosheet 28 in plan view. In Fig. 13, the gate wiring 31 serves as the gate of the access transistor PG3. The gate wiring 38 serves as the gate of the access transistor PG2.

[0199] The gate wirings 30 and 31 are connected to each other via a bridge portion 112. The gate wirings 38 and 39 are connected to each other via a bridge portion 113.

[0200] 13, the nanosheet 21, the gate wiring 31, and the pads 401 and 404b form an access transistor PG3, while the nanosheet 28, the gate wiring 38, and the pads 407a and 410 form an access transistor PG2.

[0201] 13(a), a line 71b for supplying a power supply voltage VSS is formed between a line 71g which is the fourth bit line BLBX and a line 71e which is the third bit line BLB. A line 71c for supplying a power supply voltage VSS is formed between a line 71f which is the second bit line BLAX and a line 71d which is the first bit line BLA.

[0202] 13, the surface of nanosheet 21 on the left side of the drawing is not covered by gate wiring 31 and is exposed from gate wiring 31. The surface of nanosheet 28 on the right side of the drawing is not covered by gate wiring 38 and is exposed from gate wiring 38.

[0203] 13, the power supply wiring VSS is arranged between the first bit line BLA and the second bit line BLAX and between the third bit line BLB and the fourth bit line BLBX, thereby reducing the coupling capacitance between the bit lines, thereby suppressing noise due to the coupling capacitance between the bit lines and increasing the speed of write and read operations to the 2-port SRAM cell.

[0204] In addition, the same effects as those in FIG. 12 can be obtained.

[0205] (Variation 2) 14 is a plan view showing another example of the layout structure of a two-port SRAM cell according to the second embodiment. Specifically, FIG. 14(a) shows the upper part of the cell, and FIG. 14(b) shows the lower part of the cell. In FIG. 14, compared to FIG. 12, the surface of each nanosheet opposite to that in FIG. 12 in the X direction is exposed from the gate wiring.

[0206] 14(b), gate wirings 30a and 30b extending in the X and Z directions are formed on the left side of gate wiring 31 in the drawing. Gate wirings 39a and 39b extending in the X and Z directions are formed on the right side of gate wiring 38 in the drawing.

[0207] Gate wiring 30a overlaps with nanosheet 24 in a planar view. Gate wiring 30b overlaps with nanosheet 21 in a planar view. Gate wiring 32 overlaps with nanosheet 22 in a planar view. Gate wiring 33 overlaps with nanosheets 23a and 23b in a planar view. Gate wiring 36 overlaps with nanosheets 26a and 26b in a planar view. Gate wiring 37 overlaps with nanosheet 27 in a planar view. Gate wiring 39a overlaps with nanosheet 28 in a planar view. Gate wiring 39b overlaps with nanosheet 25 in a planar view.

[0208] In FIG. 14, gate wiring 30a serves as the gate of access transistor PG4. Gate wiring 30b serves as the gate of access transistor PG3. Gate wiring 32 serves as the gate of load transistor PU2. Gate wiring 33 serves as the gates of transistors PD21 and PD22. Gate wiring 36 serves as the gates of transistors PD11 and PD12. Gate wiring 37 serves as the gate of load transistor PU1. Gate wiring 39a serves as the gate of access transistor PG2. Gate wiring 39b serves as the gate of access transistor PG1.

[0209] Gate wirings 30a and 30b are connected to each other via a bridge portion 114. Gate wirings 39a and 39b are connected to each other via a bridge portion 115. Gate wiring 30a is connected to wiring 71h via a contact 82a. Gate wiring 39b is connected to wiring 71k via a contact 82d.

[0210] 14, the right-hand surfaces of nanosheets 24, 22, 23b, 26b, and 28 are not covered by gate wirings 30a, 32, 33, 36, and 39a, respectively, and are exposed from gate wirings 30a, 32, 33, 36, and 39a, respectively. The left-hand surfaces of nanosheets 21, 23a, 26a, 27, and 25 are not covered by gate wirings 30b, 33, 36, 37, and 39b, respectively, and are exposed from gate wirings 30b, 33, 36, 37, and 39b, respectively.

[0211] That is, the surfaces of the nanosheets 24 and 21 that face each other in the X direction are exposed from the gate wirings 30a and 30b, respectively. The surfaces of the nanosheets 22 and 23a that face each other in the X direction are exposed from the gate wirings 32 and 33, respectively. The surfaces of the nanosheets 26b and 27 that face each other in the X direction are exposed from the gate wirings 36 and 37, respectively. The surfaces of the nanosheets 28 and 25 that face each other in the X direction are exposed from the gate wirings 39a and 39b, respectively.

[0212] According to the layout structure of FIG. 14, the surfaces of nanosheets 24 and 21 facing each other in the X direction are exposed from gate wirings 30a and 30b, respectively. The surfaces of nanosheets 22 and 23a facing each other in the X direction are exposed from gate wirings 32 and 33, respectively. The surfaces of nanosheets 26b and 27 facing each other in the X direction are exposed from gate wirings 36 and 37, respectively. The surfaces of nanosheets 28 and 25 facing each other in the X direction are exposed from gate wirings 39a and 39b, respectively. This reduces the distance d1 in the X direction between access transistors PG4 and PG3, the distance d1 in the X direction between load transistor PU2 and transistor PD21, the distance d1 in the X direction between transistor PD12 and load transistor PU1, and the distance d1 in the X direction between access transistors PG2 and PG1. This allows for a reduction in the area of ​​the semiconductor memory device.

[0213] Furthermore, the distance between the first bit line BLA and the second bit line BLAX and the distance between the third bit line BLB and the fourth bit line BLBX are increased, reducing the coupling capacitance between the bit lines, thereby suppressing noise due to the coupling capacitance between the bit lines and enabling faster write and read operations to the 2-port SRAM cell.

[0214] In addition, the same effects as those in FIG. 12 can be obtained.

[0215] Shield wiring (wiring connected to power supply voltages VDD and VSS) extending in the Y direction may be disposed between the wiring 71g and the wiring 71e, and between the wiring 71f and the wiring 71d.

[0216] (Variation 3) FIG. 15 is a plan view showing another example of the layout structure of a 2-port SRAM cell according to the second embodiment. Specifically, FIG. 15(a) shows the upper part of the cell, and FIG. 15(b) shows the lower part of the cell. In FIG. 15, the arrangement of access transistors PG2 and PG3 and wires 71b, 71c, 71e, and 71f is different from that in FIG. 14. Specifically, access transistor PG2 is arranged on the left side of the drawing compared to FIG. 14, and access transistor PG3 is arranged on the right side of the drawing compared to FIG. 14. Furthermore, wire 71b is arranged between wires 71g and 71e, and wire 71c is arranged between wires 71f and 71d.

[0217] As shown in Figure 15(b), nanosheet 21 is formed above pad 404b in the drawing and is connected to pad 404b. Nanosheet 28 is formed below pad 407a in the drawing and is connected to pad 407a. Pad 401 is formed above nanosheet 21 in the drawing. Pad 410 is formed below nanosheet 28 in the drawing.

[0218] 15, the nanosheets 21 and 26b are formed side by side in the Y direction. The nanosheets 23a and 28 are formed side by side in the Y direction.

[0219] Gate wiring 30b is formed so that its right end in the drawing is at the same position in the X direction as the right end of gate wiring 36. Gate wiring 39a is formed so that its left end in the drawing is at the same position in the X direction as the left end of gate wiring 33. Note that gate wirings 31 and 38 are omitted.

[0220] 15, the nanosheet 21, the gate wiring 30b, and the pads 401 and 404b form an access transistor PG3, while the nanosheet 28, the gate wiring 39a, and the pads 407a and 410 form an access transistor PG2.

[0221] 15(a), a line 71b for supplying a power supply voltage VSS is formed between a line 71g which is the fourth bit line BLBX and a line 71e which is the third bit line BLB. A line 71c for supplying a power supply voltage VSS is formed between a line 71f which is the second bit line BLAX and a line 71d which is the first bit line BLA.

[0222] 15, the surface of nanosheet 21 on the right side of the drawing is not covered by gate wiring 30b and is exposed from gate wiring 30b, and the surface of nanosheet 28 on the left side of the drawing is not covered by gate wiring 39a and is exposed from gate wiring 39a.

[0223] 15, the power supply wiring VSS is arranged between the first bit line BLA and the second bit line BLAX and between the third bit line BLB and the fourth bit line BLBX, thereby reducing the coupling capacitance between the bit lines, thereby suppressing noise due to the coupling capacitance between the bit lines and increasing the speed of write and read operations to the 2-port SRAM cell.

[0224] In addition, the same effects as those in FIG. 14 can be obtained.

[0225] (Third embodiment) 16 is a plan view showing an example of the layout structure of a 2-port SRAM cell according to the third embodiment. Specifically, FIG. 16(a) shows the upper part of the cell, and FIG. 16(b) shows the lower part of the cell. In FIG. 16, the 2-port SRAM cell circuit of FIG. 4 is configured with load transistors PU1 and PU2, drive transistor PD1 (transistors PD11 and PD12), drive transistor PD2 (transistors PD21 and PD22), and access transistors PG1 to PG4. In the 2-port SRAM cell of FIG. 16, 2-port SRAM cells inverted in the X direction are arranged on both the left and right sides of the drawing.

[0226] As shown in FIG. 16(b), the nanosheets 21, 22, 23a, 23b, and 25 are formed side by side in the X direction in the order of nanosheets 21, 25, 22, 23a, and 23b. The nanosheets 26a, 26b, 27, 24, and 28 are formed side by side in the X direction in the order of nanosheets 26a, 26b, 27, 24, and 28. The nanosheets 21 and 26a are formed side by side in the Y direction. The nanosheets 25 and 26b are formed side by side in the Y direction. The nanosheets 23a and 24 are formed side by side in the Y direction. The nanosheets 23b and 28 are formed side by side in the Y direction.

[0227] Gate wiring 30 overlaps with nanosheet 21 in a planar view. Gate wiring 31 overlaps with nanosheet 25 in a planar view. Gate wiring 32 overlaps with nanosheet 22 in a planar view. Gate wiring 33 overlaps with nanosheets 23a and 23b in a planar view. Gate wiring 36 overlaps with nanosheets 26a and 26b in a planar view. Gate wiring 37 overlaps with nanosheet 27 in a planar view. Gate wiring 38 overlaps with nanosheet 24 in a planar view. Gate wiring 39 overlaps with nanosheet 28 in a planar view.

[0228] Gate wiring 30 is connected to gate wiring 30 of a 2-port SRAM cell arranged on the left side of the 2-port SRAM cell in the drawing via bridge portion 12. Gate wirings 32 and 33 are connected to each other via bridge portion 10. Gate wirings 36 and 37 are connected to each other via bridge portion 11. Gate wiring 39 is connected to gate wiring 39 of a 2-port SRAM cell arranged on the right side of the 2-port SRAM cell in the drawing via bridge portion 15.

[0229] In FIG. 16, access transistor PG3 is formed by nanosheet 21, gate wiring 30, and pads 401 and 404a. Access transistor PG1 is formed by nanosheet 25, gate wiring 31, and pads 403 and 404b. Load transistor PU2 is formed by nanosheet 22, gate wiring 32, and pads 411 and 412. Transistor PD21 is formed by nanosheet 23a, gate wiring 33, and pads 406a and 407a. Transistor PD22 is formed by nanosheet 23b, gate wiring 33, and pads 406b and 407b. Transistor PD11 is formed by nanosheet 26a, gate wiring 36, and pads 404a and 405a. Transistor PD12 is formed by nanosheet 26b, gate wiring 36, and pads 404b and 405b. Load transistor PU1 is formed by nanosheet 27, gate wiring 37, and pads 413 and 414. The nanosheet 24, the gate wiring 38, and the pads 407a and 408 form an access transistor PG4. The nanosheet 28, the gate wiring 39, and the pads 407b and 410 form an access transistor PG2.

[0230] Therefore, the access transistors PG3 and PG1, the load transistor PU2, and the transistors PD21 and PD22 are arranged side by side in the X direction. The transistors PD11 and PD12, the load transistor PU1, and the access transistors PG4 and PG2 are arranged side by side in the X direction. The access transistor PG3 and the transistor PD11 are arranged side by side in the Y direction. The access transistor PG1 and the transistor PD12 are arranged side by side in the Y direction. The transistor PD21 and the access transistor PG4 are arranged side by side in the Y direction. The transistor PD22 and the access transistor PG2 are arranged side by side in the Y direction.

[0231] 16(a), a line 71d serving as the first bit line BLA and a line 71e serving as the third bit line BLB are spaced apart in the X direction, with a line 71b supplying a power supply voltage VSS therebetween. A line 71f serving as the second bit line BLAX and a line 71g serving as the fourth bit line BLBX are spaced apart in the X direction, with a line 71c supplying a power supply voltage VSS therebetween.

[0232] Furthermore, the wiring 71j is formed to extend in the Y direction and is disposed between the wirings 71b and 71d. The wiring 71i is formed to extend in the Y direction and is disposed between the wirings 71g and 71c. The wirings 71j and 71i are connected to the gate wirings 31 and 38 via contacts 82c and 82b, respectively.

[0233] 16, the surfaces of nanosheets 25, 22, 23b, 26b, and 28 on the right side of the drawing are not covered by gate wirings 31, 32, 33, 36, and 39, respectively, and are exposed from gate wirings 31, 32, 33, 36, and 39, respectively. The surfaces of nanosheets 21, 23a, 26a, 27, and 24 on the left side of the drawing are not covered by gate wirings 30, 33, 36, 37, and 38, respectively, and are exposed from gate wirings 30, 33, 36, 37, and 38, respectively.

[0234] That is, the surfaces of the nanosheets 22 and 23a that face each other in the X direction are exposed from the gate wirings 32 and 33, respectively. The surfaces of the nanosheets 26b and 27 that face each other in the X direction are exposed from the gate wirings 36 and 37, respectively.

[0235] In plan view, the nanosheets 21 and 26a are arranged close to the cell boundary on the left side of the drawing. In plan view, the nanosheets 23b and 28 are arranged close to the cell boundary on the right side of the drawing. In the two-port SRAM cell of FIG. 16, two-port SRAM cells inverted in the X direction are arranged on both the left and right sides of the drawing. That is, in the two-port SRAM cells arranged side by side in the X direction, the surfaces of the nanosheets 21 facing each other in the X direction are exposed from the gate wiring 30. The surfaces of the nanosheets 23b facing each other in the X direction are exposed from the gate wiring 33. The surfaces of the nanosheets 26a facing each other in the X direction are exposed from the gate wiring 36. The surfaces of the nanosheets 28 facing each other in the X direction are exposed from the gate wiring 39.

[0236] With the above configuration, the surfaces of the nanosheets 22 and 23a that face each other in the X direction are exposed from the gate wirings 32 and 33, respectively. The surfaces of the nanosheets 26b and 27 that face each other in the X direction are exposed from the gate wirings 36 and 37, respectively. This reduces the distance d1 in the X direction between the load transistor PU2 and the transistor PD21, and the distance d1 in the X direction between the transistor PD12 and the load transistor PU1. This allows the area of ​​the semiconductor memory device to be reduced.

[0237] Furthermore, in the two-port SRAM cells arranged side by side in the X direction, the surfaces of the nanosheets 21 facing each other in the X direction are exposed from the gate wiring 30. The surfaces of the nanosheets 23b facing each other in the X direction are exposed from the gate wiring 33. The surfaces of the nanosheets 26a facing each other in the X direction are exposed from the gate wiring 36. The surfaces of the nanosheets 28 facing each other in the X direction are exposed from the gate wiring 39. This makes it possible to reduce the distance d1 in the X direction between the access transistors PG3, the distance d1 in the X direction between the transistors PD22, the distance d1 in the X direction between the transistors PD11, and the distance d1 in the X direction between the access transistors PG2. This allows the area of ​​the semiconductor memory device to be reduced.

[0238] In addition, the access transistor PG3 and the transistor PD11 are arranged side by side in the Y direction. The access transistor PG1 and the transistor PD12 are arranged side by side in the Y direction. The transistor PD21 and the access transistor PG4 are arranged side by side in the Y direction. The transistor PD22 and the access transistor PG2 are arranged side by side in the Y direction. This allows the area of ​​the semiconductor memory device to be reduced.

[0239] In addition, the spacing between the first bit line BLA and the third bit line BLB, and between the second bit line BLAX and the fourth bit line BLBX, is widened, and power supply wiring VSS is placed between them, respectively. This reduces the coupling capacitance between the bit lines, suppressing noise due to the coupling capacitance between the bit lines and enabling faster write and read operations to the 2-port SRAM cell.

[0240] (Variation) 17A and 17B are plan views showing another example of the layout structure of a two-port SRAM cell according to the third embodiment. Specifically, FIG. 17A shows the upper part of the cell, and FIG. 17B shows the lower part of the cell. In FIG. 17, compared to FIG. 16, the surface of each nanosheet opposite to that in FIG. 16 in the X direction is exposed from the gate wiring.

[0241] 17(b), gate wirings 33a and 33b extending in the X and Z directions are formed on the right side of gate wiring 32 in the drawing. Gate wirings 36a and 36b extending in the X and Z directions are formed on the left side of gate wiring 37 in the drawing.

[0242] The gate wiring 33a overlaps with the nanosheets 22 and 23a in a planar view. The gate wiring 33b overlaps with the nanosheet 23b in a planar view. The gate wiring 36a overlaps with the nanosheet 26a in a planar view. The gate wiring 36b overlaps with the nanosheets 26b and 27 in a planar view.

[0243] 17, the gate wiring 33a serves as the gate of the load transistor PU2 and the transistor PD21. The gate wiring 33b serves as the gate of the transistor PD22. The gate wiring 36a serves as the gate of the transistor PD11. The gate wiring 36b serves as the gate of the transistor PD12 and the load transistor PU1.

[0244] The gate wirings 32 and 33a are connected to each other via a bridge portion 10. The gate wirings 33a and 33b are connected to each other via a bridge portion 17. The gate wirings 36a and 36b are connected to each other via a bridge portion 18. The gate wirings 36b and 37 are connected to each other via a bridge portion 11. Furthermore, the gate wiring 30 is connected to a wiring 71h via a contact 82a. The gate wiring 39 is connected to a wiring 71k via a contact 82d.

[0245] 17, the surfaces of nanosheets 25, 22, 23b, 26b, and 28 on the left side of the drawing are not covered by gate wirings 31, 33a, 33b, 36b, and 39, respectively, and are exposed from gate wirings 31, 33a, 33b, 36b, and 39, respectively. The surfaces of nanosheets 21, 23a, 26a, 27, and 24 on the right side of the drawing are not covered by gate wirings 30, 33a, 36a, 36b, and 38, respectively, and are exposed from gate wirings 30, 33a, 36a, 36b, and 38, respectively.

[0246] That is, the surfaces of the nanosheets 21 and 25 that face each other in the X direction are exposed from the gate wirings 30 and 31, respectively. The surfaces of the nanosheets 23a and 23b that face each other in the X direction are exposed from the gate wirings 33a and 33b, respectively. The surfaces of the nanosheets 26a and 26b that face each other in the X direction are exposed from the gate wirings 36a and 36b, respectively. The surfaces of the nanosheets 24 and 28 that face each other in the X direction are exposed from the gate wirings 38 and 39, respectively.

[0247] Furthermore, nanosheet 22 is formed above and to the right of nanosheet 27 in the drawing. That is, the surfaces of nanosheets 22 and 27 that face each other in the X direction are exposed from gate wirings 33a and 36b, respectively.

[0248] According to the layout structure of FIG. 17, the surfaces of nanosheets 21 and 25 facing each other in the X direction are exposed from gate wirings 30 and 31, respectively. The surfaces of nanosheets 23a and 23b facing each other in the X direction are exposed from gate wirings 33a and 33b, respectively. The surfaces of nanosheets 26a and 26b facing each other in the X direction are exposed from gate wirings 36a and 36b, respectively. The surfaces of nanosheets 24 and 28 facing each other in the X direction are exposed from gate wirings 38 and 39, respectively. This reduces the distance d1 in the X direction between access transistors PG3 and PG1, the distance d1 in the X direction between transistors PD21 and PD22, the distance d1 in the X direction between transistors PD11 and PD12, and the distance d1 in the X direction between access transistors PG4 and PG2. This allows the area of ​​the semiconductor memory device to be reduced.

[0249] Furthermore, the nanosheets 22 and 27 have their opposing surfaces exposed from the gate wirings 33a and 36b in the X direction, respectively. This reduces the distance d1 between the load transistors PU1 and PU2 in the X direction. This allows the semiconductor memory device to have a smaller area.

[0250] In addition, the same effects as those in FIG. 16 can be obtained.

[0251] In the above-described embodiments and variants, each transistor has three nanosheets, but some or all of the transistors may have one, two, or four or more nanosheets.

[0252] In addition, in each of the above-described embodiments, the cross-sectional shape of the nanosheet is rectangular, but this is not limited to this and may be, for example, square, circular, elliptical, or the like. [Industrial Applicability]

[0253] According to the present disclosure, a two-port SRAM cell using a fork-sheet transistor can be realized, and the area of ​​a semiconductor memory device can be reduced. [Explanation of symbols]

[0254] 21-28, 23a, 23b, 26a, 26b Nanosheets 30~39,30a,30b,31a,31b,33a,33b,36a,36b,38a,38b,39a,39b Gate wiring 401~414,404a,404b,405a,405b,406a,406b,407a,407b Pads 50~59,150,151 Local wiring 61~64 Shared Contact 71a~71k,91,92 wiring PU1, PU2 load transistor PD1, PD2, PD11, PD12, PD21, PD22 drive transistors (transistors) PG1~PG4 access transistors WLA 1st Word Line WLB Second word line BLA 1st bit line BLAX Second bit line BLB 3rd bit line BLBX 4th bit line

Claims

1. A semiconductor memory device including a two-port SRAM cell, The two-port SRAM cell is a first transistor having one node connected to a first power supply that supplies a first voltage, another node connected to the first node, and a gate connected to a second node; a second transistor having one node connected to the first power supply, another node connected to the second node, and a gate connected to the first node; a third transistor having one node connected to the first bit line, another node connected to the first node, and a gate connected to the first word line; a fourth transistor having one node connected to a second bit line forming a first complementary bit line pair with the first bit line, another node connected to the second node, and a gate connected to the first word line; a fifth transistor having one node connected to a third bit line, another node connected to the first node, and a gate connected to a second word line; a sixth transistor having one node connected to a fourth bit line forming a second complementary bit line pair with the third bit line, another node connected to the second node, and a gate connected to the second word line; a seventh transistor having one node connected to the first node, another node connected to a second power supply that supplies a second voltage different from the first voltage, and a gate connected to the second node; an eighth transistor having one node connected to the second node, another node connected to the second power supply, and a gate connected to the first node; Equipped with The first to eighth transistors are: First to eighth nanosheets extending in a first direction; first to eighth gate wirings respectively surrounding the first to eighth nanosheets in a second direction perpendicular to the first direction and in a third direction perpendicular to the first and second directions; Each of them has The second, fifth, sixth, and eighth nanosheets are formed side by side in the second direction in the order of the fifth, second, eighth, and sixth nanosheets, the first, third, fourth, and seventh nanosheets are formed side by side in the second direction in the order of the third, seventh, first, and fourth nanosheets, the second, fourth, sixth, and seventh nanosheets have first-side surfaces, which are one side in the second direction, exposed from the second, fourth, sixth, and seventh gate wirings, respectively; the first, third, fifth, and eighth nanosheets have second-side surfaces, which are the other sides in the second direction, exposed from the first, third, fifth, and eighth gate wirings, respectively; the fourth and sixth nanosheets are formed adjacent to a cell boundary on the first side of the two-port SRAM cell; the third and fifth nanosheets are formed adjacent to the cell boundary on the second side of the two-port SRAM cell; the first side is a side of the second nanosheet facing the eighth nanosheet and a side of the seventh nanosheet facing the first nanosheet; The second side is a side of the eighth nanosheet facing the second nanosheet and a side of the first nanosheet facing the seventh nanosheet. A semiconductor memory device characterized by:

2. 2. The semiconductor memory device according to claim 1, the third and fifth nanosheets are aligned in the first direction, The fourth and sixth nanosheets are aligned in the first direction. A semiconductor memory device characterized by:

3. 2. The semiconductor memory device according to claim 1, The two-port SRAM cell is first and second power supply wirings extending in the first direction and supplying the second voltage; a first wiring extending in the first direction and serving as the first bit line; a second wiring extending in the first direction and serving as the second bit line; a third wiring extending in the first direction and serving as the third bit line; a fourth wiring extending in the first direction and serving as the fourth bit line; Furthermore, the first and second power supply wirings and the first to fourth wirings are formed in the same wiring layer above the first to tenth transistors, respectively; the first power supply wiring is formed between the first wiring and the second wiring, The second power supply wiring is formed between the third wiring and the fourth wiring. A semiconductor memory device characterized by:

4. A semiconductor memory device including a two-port SRAM cell, The two-port SRAM cell is a first transistor having one node connected to a first power supply that supplies a first voltage, another node connected to the first node, and a gate connected to a second node; a second transistor having one node connected to the first power supply, another node connected to the second node, and a gate connected to the first node; a third transistor having one node connected to the first bit line, another node connected to the first node, and a gate connected to the first word line; a fourth transistor having one node connected to a second bit line forming a first complementary bit line pair with the first bit line, another node connected to the second node, and a gate connected to the first word line; a fifth transistor having one node connected to a third bit line, another node connected to the first node, and a gate connected to a second word line; a sixth transistor having one node connected to a fourth bit line forming a second complementary bit line pair with the third bit line, another node connected to the second node, and a gate connected to the second word line; a seventh transistor having one node connected to the first node, another node connected to a second power supply that supplies a second voltage different from the first voltage, and a gate connected to the second node; an eighth transistor having one node connected to the second node, another node connected to the second power supply, and a gate connected to the first node; Equipped with The first to sixth transistors are First to sixth nanosheets extending in a first direction; first to sixth gate wirings respectively surrounding the first to sixth nanosheets in a second direction perpendicular to the first direction and in a third direction perpendicular to the first and second directions; Each of them has The seventh transistor is Seventh and eighth nanosheets extending in the first direction; seventh and eighth gate wirings surrounding the seventh and eighth nanosheets in the second and third directions, respectively; Equipped with The eighth transistor is ninth and tenth nanosheets extending in the first direction; ninth and tenth gate wirings surrounding the ninth and tenth nanosheets in the second and third directions, respectively; Equipped with The second, fifth, sixth, ninth, and tenth nanosheets are formed side by side in the second direction in the order of the fifth, second, ninth, tenth, and sixth nanosheets, The first, third, fourth, seventh, and eighth nanosheets are formed in the second direction in the order of the third, seventh, eighth, first, and fourth nanosheets, the first, sixth, seventh, and ninth nanosheets have first-side surfaces, which are one side in the second direction, exposed from the first, sixth, seventh, and ninth gate wirings, respectively; the second, third, eighth, and tenth nanosheets have second-side surfaces, which are the other sides in the second direction, exposed from the second, third, eighth, and tenth gate wirings, respectively; a surface of the fourth nanosheet on either the first side or the second side is exposed from a fourth gate wiring; The fifth nanosheet has a surface on either the first side or the second side exposed from the fifth gate wiring. A semiconductor memory device characterized by:

5. 5. The semiconductor memory device according to claim 4, The first side is The ninth nanosheet is on a side facing the second nanosheet, The sixth nanosheet is on a side facing the tenth nanosheet, The seventh nanosheet is on the side facing the third nanosheet, and the first nanosheet on a side facing the eighth nanosheet, The second side is the second nanosheet on the side facing the ninth nanosheet, The tenth nanosheet is on a side facing the sixth nanosheet, The third nanosheet is on the side facing the seventh nanosheet, and The eighth nanosheet is on the side facing the first nanosheet. A semiconductor memory device characterized by:

6. 6. The semiconductor memory device according to claim 5, the third and fifth nanosheets are aligned in the first direction, the fourth and sixth nanosheets are aligned in the first direction, the fourth nanosheet has a surface on the first side exposed from a fourth gate wiring, The fifth nanosheet has a surface on the second side exposed from the fifth gate wiring. A semiconductor memory device characterized by:

7. 6. The semiconductor memory device according to claim 5, the fifth and seventh nanosheets are aligned in the first direction, the fourth and tenth nanosheets are aligned in the first direction, the fourth nanosheet has a surface on the second side exposed from a fourth gate wiring, The fifth nanosheet has a surface on the first side exposed from the fifth gate wiring. A semiconductor memory device characterized by:

8. 6. The semiconductor memory device according to claim 5, the fifth and eighth nanosheets are aligned in the first direction, the fourth and ninth nanosheets are aligned in the first direction, the fourth nanosheet has a surface on the first side exposed from a fourth gate wiring, The fifth nanosheet has a surface on the second side exposed from the fifth gate wiring. A semiconductor memory device characterized by:

9. 5. The semiconductor memory device according to claim 4, the sixth nanosheet is formed adjacent to a cell boundary on the first side of the two-port SRAM cell, the third nanosheet is formed adjacent to the cell boundary on the second side of the two-port SRAM cell; The first side is a side of the seventh nanosheet facing the eighth nanosheet and a side of the ninth nanosheet facing the tenth nanosheet, The second side is the side of the eighth nanosheet facing the seventh nanosheet and the side of the tenth nanosheet facing the ninth nanosheet. A semiconductor memory device characterized by:

10. 10. The semiconductor memory device according to claim 9, the fourth nanosheet is formed adjacent to a cell boundary on the first side of the two-port SRAM cell; the fifth nanosheet is formed adjacent to the cell boundary on the second side of the two-port SRAM cell, the third and fifth nanosheets are aligned in the first direction, the fourth and sixth nanosheets are aligned in the first direction, the fourth nanosheet has a surface on the first side exposed from a fourth gate wiring, The fifth nanosheet has a surface on the second side exposed from the fifth gate wiring. A semiconductor memory device characterized by:

11. 10. The semiconductor memory device according to claim 9, the fifth and seventh nanosheets are aligned in the first direction, the fourth and tenth nanosheets are aligned in the first direction, the fourth nanosheet has a surface on the second side exposed from a fourth gate wiring, The fifth nanosheet has a surface on the first side exposed from the fifth gate wiring. A semiconductor memory device characterized by:

12. 10. The semiconductor memory device according to claim 9, the fifth and eighth nanosheets are aligned in the first direction, the fourth and ninth nanosheets are aligned in the first direction, the fourth nanosheet has a surface on the first side exposed from a fourth gate wiring, The fifth nanosheet has a surface on the second side exposed from the fifth gate wiring. A semiconductor memory device characterized by:

13. 5. The semiconductor memory device according to claim 4, The two-port SRAM cell is first and second power supply wirings extending in the first direction and supplying the second voltage; a first wiring extending in the first direction and serving as the first bit line; a second wiring extending in the first direction and serving as the second bit line; a third wiring extending in the first direction and serving as the third bit line; a fourth wiring extending in the first direction and serving as the fourth bit line; Furthermore, the first and second power supply wirings and the first to fourth wirings are formed in the same wiring layer above the first to tenth transistors, respectively; the first power supply wiring is formed between the first wiring and the third wiring, The second power supply wiring is formed between the second wiring and the fourth wiring. A semiconductor memory device characterized by:

14. A semiconductor memory device including a two-port SRAM cell, The two-port SRAM cell is a first transistor having one node connected to a first power supply that supplies a first voltage, another node connected to the first node, and a gate connected to a second node; a second transistor having one node connected to the first power supply, another node connected to the second node, and a gate connected to the first node; a third transistor having one node connected to the first bit line, another node connected to the first node, and a gate connected to the first word line; a fourth transistor having one node connected to a second bit line forming a first complementary bit line pair with the first bit line, another node connected to the second node, and a gate connected to the first word line; a fifth transistor having one node connected to a third bit line, another node connected to the first node, and a gate connected to a second word line; a sixth transistor having one node connected to a fourth bit line forming a second complementary bit line pair with the third bit line, another node connected to the second node, and a gate connected to the second word line; a seventh transistor having one node connected to the first node, another node connected to a second power supply that supplies a second voltage different from the first voltage, and a gate connected to the second node; an eighth transistor having one node connected to the second node, another node connected to the second power supply, and a gate connected to the first node; Equipped with The first to sixth transistors are First to sixth nanosheets extending in a first direction; first to sixth gate wirings respectively surrounding the first to sixth nanosheets in a second direction perpendicular to the first direction and in a third direction perpendicular to the first and second directions; Each of them has The seventh transistor is Seventh and eighth nanosheets extending in the first direction; seventh and eighth gate wirings surrounding the seventh and eighth nanosheets in the second and third directions, respectively; Equipped with The eighth transistor is ninth and tenth nanosheets extending in the first direction; ninth and tenth gate wirings surrounding the ninth and tenth nanosheets in the second and third directions, respectively; Equipped with The second, fifth, sixth, ninth, and tenth nanosheets are formed side by side in the second direction in the order of the sixth, fifth, second, ninth, and tenth nanosheets, The first, third, fourth, seventh, and eighth nanosheets are formed side by side in the second direction in the order of the seventh, eighth, first, fourth, and third nanosheets, the second, sixth, eighth, and tenth nanosheets have first-side surfaces, which are one side in the second direction, exposed from the second, sixth, eighth, and tenth gate wirings, respectively; the first, third, seventh, and ninth nanosheets have second-side surfaces, which are the other sides in the second direction, exposed from the first, third, seventh, and ninth gate wirings, respectively; a surface of the fourth nanosheet on either the first side or the second side is exposed from a fourth gate wiring; The fifth nanosheet has a surface on either the first side or the second side exposed from the fifth gate wiring. A semiconductor memory device characterized by:

15. 15. The semiconductor memory device according to claim 14, the third nanosheet is formed adjacent to the cell boundary on the second side of the two-port SRAM cell; the sixth nanosheet is formed adjacent to a cell boundary on the first side of the two-port SRAM cell, The first side is a side of the tenth nanosheet facing the ninth nanosheet and a side of the eighth nanosheet facing the seventh nanosheet, The second side is the side of the ninth nanosheet facing the tenth nanosheet and the side of the seventh nanosheet facing the eighth nanosheet. A semiconductor memory device characterized by:

16. 16. The semiconductor memory device according to claim 15, the fifth and seventh nanosheets are aligned in the first direction, the fourth and tenth nanosheets are aligned in the first direction, the fourth nanosheet has a surface on the first side exposed from a fourth gate wiring, The fifth nanosheet has a surface on the second side exposed from the fifth gate wiring. A semiconductor memory device characterized by:

17. 16. The semiconductor memory device according to claim 15, the fifth and eighth nanosheets are aligned in the first direction, the fourth and ninth nanosheets are aligned in the first direction, the fourth nanosheet has a surface on the second side exposed from a fourth gate wiring, The fifth nanosheet has a surface on the first side exposed from the fifth gate wiring. A semiconductor memory device characterized by:

18. 15. The semiconductor memory device according to claim 14, the first side is a side of the second nanosheet facing the ninth nanosheet and a side of the eighth nanosheet facing the first nanosheet; The second side is a side of the ninth nanosheet facing the second nanosheet and a side of the first nanosheet facing the eighth nanosheet. A semiconductor memory device characterized by:

19. 20. The semiconductor memory device according to claim 18, the fifth and seventh nanosheets are aligned in the first direction, the fourth and tenth nanosheets are aligned in the first direction, the fourth nanosheet has a surface on the first side exposed from a fourth gate wiring, the fifth nanosheet has a surface on the second side exposed from a fifth gate wiring, the first side is a side of the sixth nanosheet facing the fifth nanosheet and a side of the fourth nanosheet facing the third nanosheet; The second side is a side of the fifth nanosheet facing the sixth nanosheet and a side of the third nanosheet facing the fourth nanosheet. A semiconductor memory device characterized by:

20. 20. The semiconductor memory device according to claim 18, the fifth and eighth nanosheets are aligned in the first direction, the fourth and ninth nanosheets are aligned in the first direction, the fourth nanosheet has a surface on the second side exposed from a fourth gate wiring, The fifth nanosheet has a surface on the first side exposed from the fifth gate wiring. A semiconductor memory device characterized by:

21. 15. The semiconductor memory device according to claim 14, The two-port SRAM cell is first and second power supply wirings extending in the first direction and supplying the second voltage; a first wiring extending in the first direction and serving as the first bit line; a second wiring extending in the first direction and serving as the second bit line; a third wiring extending in the first direction and serving as the third bit line; a fourth wiring extending in the first direction and serving as the fourth bit line; Furthermore, the first and second power supply wirings and the first to fourth wirings are formed in the same wiring layer above the first to tenth transistors, respectively; the first power supply wiring is formed between the first wiring and the second wiring, The second power supply wiring is formed between the third wiring and the fourth wiring. A semiconductor memory device characterized by:

22. A semiconductor memory device including a two-port SRAM cell, The two-port SRAM cell is a first transistor having one node connected to a first power supply that supplies a first voltage, another node connected to the first node, and a gate connected to a second node; a second transistor having one node connected to the first power supply, another node connected to the second node, and a gate connected to the first node; a third transistor having one node connected to the first bit line, another node connected to the first node, and a gate connected to the first word line; a fourth transistor having one node connected to a second bit line forming a first complementary bit line pair with the first bit line, another node connected to the second node, and a gate connected to the first word line; a fifth transistor having one node connected to a third bit line, another node connected to the first node, and a gate connected to a second word line; a sixth transistor having one node connected to a fourth bit line forming a second complementary bit line pair with the third bit line, another node connected to the second node, and a gate connected to the second word line; a seventh transistor having one node connected to the first node, another node connected to a second power supply that supplies a second voltage different from the first voltage, and a gate connected to the second node; an eighth transistor having one node connected to the second node, another node connected to the second power supply, and a gate connected to the first node; Equipped with The first to sixth transistors are First to sixth nanosheets extending in a first direction; first to sixth gate wirings respectively surrounding the first to sixth nanosheets in a second direction perpendicular to the first direction and in a third direction perpendicular to the first and second directions; Each of them has The seventh transistor is Seventh and eighth nanosheets extending in the first direction; seventh and eighth gate wirings surrounding the seventh and eighth nanosheets in the second and third directions, respectively; Equipped with The eighth transistor is ninth and tenth nanosheets extending in the first direction; ninth and tenth gate wirings surrounding the ninth and tenth nanosheets in the second and third directions, respectively; Equipped with The second, third, fifth, ninth, and tenth nanosheets are formed side by side in the second direction in the order of the fifth, third, second, ninth, and tenth nanosheets, The first, fourth, sixth, seventh, and eighth nanosheets are formed side by side in the second direction in the order of the seventh, eighth, first, sixth, and fourth nanosheets, the first, fifth, sixth, seventh, and ninth nanosheets have first-side surfaces, which are one side in the second direction, exposed from the first, fifth, sixth, seventh, and ninth gate wirings, respectively; The second, third, fourth, eighth, and tenth nanosheets have second-side surfaces, which are the other sides in the second direction, exposed from the second, third, fourth, eighth, and tenth gate wirings, respectively. A semiconductor memory device characterized by:

23. 23. The semiconductor memory device according to claim 22, the first side is a side of the ninth nanosheet facing the second nanosheet and a side of the first nanosheet facing the eighth nanosheet; the second side is a side of the second nanosheet facing the ninth nanosheet and a side of the eighth nanosheet facing the first nanosheet; the fifth and seventh nanosheets are formed adjacent to the cell boundary of the two-port SRAM cell on the first side, The fourth and tenth nanosheets are formed adjacent to the cell boundary on the second side of the two-port SRAM cell. A semiconductor memory device characterized by:

24. 23. The semiconductor memory device according to claim 22, The first side is the fifth nanosheet on the side facing the third nanosheet, The ninth nanosheet is on the side facing the tenth nanosheet, the seventh nanosheet on the side facing the eighth nanosheet; and the sixth nanosheet on the side facing the fourth nanosheet, The second side is the side of the third nanosheet facing the fifth nanosheet, The 10th nanosheet is on the side facing the 9th nanosheet, the eighth nanosheet on the side facing the seventh nanosheet; and The side of the fourth nanosheet facing the sixth nanosheet A semiconductor memory device characterized by:

25. 23. The semiconductor memory device according to claim 22, The two-port SRAM cell is first and second power supply wirings extending in the first direction and supplying the second voltage; a first wiring extending in the first direction and serving as the first bit line; a second wiring extending in the first direction and serving as the second bit line; a third wiring extending in the first direction and serving as the third bit line; a fourth wiring extending in the first direction and serving as the fourth bit line; Furthermore, the first and second power supply wirings and the first to fourth wirings are formed in the same wiring layer above the first to tenth transistors, respectively; the first power supply wiring is formed between the first wiring and the third wiring, The second power supply wiring is formed between the second wiring and the fourth wiring. A semiconductor memory device characterized by:

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