Phase change material switch and method of manufacturing same

Abstract

The phase change material switch includes a phase change layer disposed on a metal liner, a gate dielectric layer disposed on the phase change layer, and a metal gate liner disposed on the gate dielectric layer.

Description

[Technical Field]

[0001] The present disclosure relates generally to memory devices. The present disclosure relates generally to phase change material switches, and more particularly to nonvolatile four-terminal phase change material switches. [Background technology]

[0002] A new and emerging memory device technology is phase change memory technology. Phase change memory (PCM) is a type of nonvolatile random-access memory (RAM). PCM utilizes the behavior of phase change materials, which can transition between crystalline and amorphous phases in response to an electric current passing through them. Typically, the phase change materials used in the fabrication of PCM include chalcogenide compounds such as germanium-antimony-tellurium (GST).

[0003] A PCM contains a region of phase-change material disposed between a bottom electrode contact and a top electrode contact. Phase-change materials have low resistance in the crystalline phase and high resistance in the amorphous phase. To place a PCM in the amorphous phase, the phase-change material is first melted and then rapidly quenched by applying a short, high-current pulse, leaving a region of amorphous, highly resistive material within the PCM cell. To place a PCM in the crystalline phase, a moderate current pulse is applied, annealing the phase-change material at a temperature between its crystallization temperature and melting temperature for a time long enough to crystallize the relatively low-resistivity phase-change material. To read the state of a PCM, the cell's resistance is measured by passing a low-current electrical signal through the cell, which does not disturb the state of the phase-change material. Additionally, PCM technology has the ability to achieve many different intermediate states, giving PCMs the ability to store multiple bits in a single cell, resulting in increased memory density. Summary of the Invention [Means for solving the problem]

[0004] Viewed from a first aspect, the present invention provides a phase change material switch including a phase change layer disposed on a metal liner, a gate dielectric layer disposed on the phase change layer, and a metal gate liner disposed on the gate dielectric layer.

[0005] Viewed from a further aspect, the present invention provides a phase change material bridge device comprising: a phase change material switch of the present invention; an electrode including an intermetal dielectric layer and at least two metal contact vias within the intermetal dielectric layer; and a metal liner disposed on a portion of the intermetal dielectric layer and the at least two metal contact vias; a gate dielectric layer further disposed on the metal liner and phase change layer and on remaining portions of the intermetal dielectric layer and the at least two metal contact vias; and the metal liner and phase change layer comprising a horizontal bridge between the at least two metal contact vias.

[0006] Viewed from a further aspect, the present invention provides a semiconductor structure comprising a phase change material switch of the present invention; a semiconductor substrate; an electrode disposed on the semiconductor substrate, the electrode comprising an intermetal dielectric layer and at least two metal contact vias in the intermetal dielectric layer; and a metal liner disposed in the intermetal dielectric layer and a portion of the at least two metal contact vias, the metal liner and the phase change layer comprising a horizontal bridge between the at least two metal contact vias.

[0007] Viewed from a further aspect, the present invention provides a phase change material bridge device comprising: an electrode including an intermetal dielectric layer and at least two metal contact vias in the intermetal dielectric layer; a metal liner disposed on a portion of the intermetal dielectric layer and the at least two metal contact vias; a phase change layer disposed on the metal liner; a gate dielectric layer disposed on the metal liner and the phase change layer and on remaining portions of the intermetal dielectric layer and the at least two metal contact vias, wherein the metal liner and the phase change layer comprise a horizontal bridge between the at least two metal contact vias; and a metal gate liner disposed on the gate dielectric layer.

[0008] Viewed from a further aspect, the present invention provides a semiconductor structure comprising: a semiconductor substrate; an electrode disposed on the semiconductor substrate, the electrode including an intermetal dielectric layer and at least two metal contact vias in the intermetal dielectric layer; a metal liner disposed in the intermetal dielectric layer and a portion of the at least two metal contact vias; a phase change layer disposed on the metal liner, the metal liner and phase change layer including a horizontal bridge between the at least two metal contact vias; a gate dielectric layer disposed on the phase change layer; and a metal gate liner disposed on the gate dielectric layer.

[0009] Viewed from a further aspect, the present invention provides a method including: forming a metal liner over an electrode including an inter-metal dielectric layer and at least two metal contact vias in the inter-metal dielectric layer; forming a phase change layer over the metal liner; forming a first hard mask over the phase change layer; selectively removing portions of the metal liner, the phase change layer, and the first hard mask to expose portions of the inter-metal dielectric layer and each of the at least two metal contact vias, wherein the remaining portions of the metal liner, the phase change layer, and the first hard mask form a horizontal bridge between the at least two metal contact vias; forming a gate dielectric layer on outer surfaces of the metal liner, the phase change layer, and the first hard mask, as well as on the exposed portions of the inter-metal dielectric layer and each of the at least two metal contact vias; and forming a metal gate liner over the gate dielectric layer.

[0010] Viewed from a further aspect, the present invention provides a method for fabricating a gate dielectric layer over an electrode including an intermetal dielectric layer and at least two metal contact vias in the intermetal dielectric layer; forming a metal liner over the metal liner; forming a sacrificial layer over the metal liner; forming a first hard mask over the sacrificial layer; selectively removing portions of the metal liner, the sacrificial layer, and the first hard mask to expose portions of the intermetal dielectric layer and each of the at least two metal contact vias, wherein remaining portions of the metal liner, the sacrificial layer, and the first hard mask form a bridge between the at least two metal contact vias; removing the first hard mask; forming a gate dielectric layer over the metal liner and the exposed portions of the intermetal dielectric layer and each of the at least two metal contact vias; forming a metal gate liner on a body layer; forming a second hard mask on the metal gate liner; etching the second hard mask to expose a portion of the metal gate liner; removing the exposed portion of the metal gate liner to expose a gate dielectric layer; removing the exposed portion of the gate dielectric layer to expose a sacrificial layer, and a portion of an inter-metal dielectric layer and each of at least two metal contact vias; removing the sacrificial layer to expose the metal liner, forming an air gap defined between an upper surface of the metal liner and a lower surface of the gate dielectric layer; and depositing a phase change layer in the air gap and on the exposed portions of the metal liner, the inter-metal dielectric layer, and each of the at least two metal contact vias.

[0011] Exemplary embodiments of the present application include techniques used in semiconductor manufacturing. In one exemplary embodiment, a phase change material switch includes a phase change layer disposed on a metal liner. The phase change material switch further includes a gate dielectric layer disposed on the phase change layer. The phase change material switch further includes a metal gate liner disposed on the gate dielectric layer.

[0012] In another exemplary embodiment, a phase change material bridge device includes an electrode including an intermetal dielectric layer and at least two metal contact vias in the intermetal dielectric layer. The phase change material bridge device further includes a metal liner disposed over the intermetal dielectric layer and portions of the at least two metal contact vias. The phase change material bridge device further includes a phase change layer disposed over the metal liner. The phase change material bridge device further includes a gate dielectric layer disposed over the metal liner and phase change layer and over remaining portions of the intermetal dielectric layer and the at least two metal contact vias. The metal liner and phase change layer include a horizontal bridge between the at least two metal contact vias. The phase change material bridge device further includes a metal gate liner disposed over the gate dielectric layer.

[0013] In another exemplary embodiment, a semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an electrode disposed on the semiconductor substrate. The electrode includes an inter-metal dielectric layer and at least two metal contact vias within the inter-metal dielectric layer. The semiconductor structure further includes a metal liner disposed on the inter-metal dielectric layer and portions of the at least two metal contact vias. The semiconductor structure further includes a phase change layer disposed on the metal liner. The metal liner and the phase change layer include a horizontal bridge between the at least two metal contact vias. The semiconductor structure further includes a gate dielectric layer disposed on the phase change layer. The semiconductor structure further includes a metal gate liner disposed on the gate dielectric layer.

[0014] In another exemplary embodiment, a method includes forming a metal liner over an electrode having an intermetal dielectric layer and at least two metal contact vias. The method further includes forming a phase change layer over the metal liner. The method further includes forming a first hard mask over the phase change layer. The method further includes selectively removing portions of the metal liner, the phase change layer, and the first hard mask to expose portions of the intermetal dielectric layer and each of the at least two metal contact vias. The remaining portions of the metal liner, the phase change layer, and the first hard mask form a horizontal bridge between the at least two metal contact vias. The method further includes forming a gate dielectric layer over outer surfaces of the metal liner, the phase change layer, and the first hard mask, as well as over the exposed portions of the intermetal dielectric layer and each of the at least two metal contact vias. The method further includes forming a metal gate liner over the gate dielectric layer.

[0015] In another illustrative embodiment, a method includes forming an electrode including an inter-metal dielectric layer and at least two metal contact vias in the inter-metal dielectric layer. The method further includes forming a metal liner on the electrode. The method further includes forming a sacrificial layer on the metal liner. The method further includes forming a first hard mask on the sacrificial layer. The method further includes selectively removing the metal liner, the sacrificial layer, and portions of the first hard mask to expose portions of the inter-metal dielectric layer and each of the at least two metal contact vias. The remaining portions of the metal liner, the sacrificial layer, and the first hard mask form a bridge between the at least two metal contact vias. The method further includes removing the first hard mask. The method further includes forming a gate dielectric layer on the metal liner and the exposed portions of the inter-metal dielectric layer and each of the at least two metal contact vias. The method further includes forming a metal gate liner on the gate dielectric layer. The method further includes forming a second hard mask on the metal gate liner. The method further includes etching the second hard mask to expose portions of the metal gate liner. The method further includes removing exposed portions of the metal gate liner to expose the gate dielectric layer. The method further includes removing exposed portions of the gate dielectric layer to expose the sacrificial layer and a portion of each of the inter-metal dielectric layer and at least two metal contact vias. The method further includes removing the sacrificial layer to expose the metal liner, forming an air gap defined between an upper surface of the metal liner and a lower surface of the gate dielectric layer. The method further includes depositing a phase change layer in the air gap and on the exposed portions of the metal liner, the inter-metal dielectric layer, and each of the at least two metal contact vias.

[0016] Other embodiments are described in the following detailed description of embodiments, which should be read in conjunction with the accompanying drawings.

[0017] The present invention will now be described, by way of example only, with reference to preferred embodiments as illustrated in the following figures. [Brief explanation of the drawings]

[0018] [Figure 1] The following diagrams show plan views of the structure, indicating the X and Y cross-sectional positions of each figure. [Figure 2] 2 is a cross-sectional view of the structure of FIG. 1 at a first intermediate manufacturing stage, according to an exemplary embodiment. [Figure 3] 2 is a cross-sectional view of the structure of FIG. 1 at a second intermediate manufacturing stage, according to an exemplary embodiment. [Figure 4] 1 at a third intermediate manufacturing stage, according to an exemplary embodiment. [Figure 5] 1 at a fourth intermediate manufacturing stage, according to an exemplary embodiment. [Figure 6] 2 is a cross-sectional view of the structure of FIG. 1 at a first intermediate manufacturing stage according to an alternative exemplary embodiment. [Figure 7] 1 at a second intermediate manufacturing stage according to an alternative exemplary embodiment. [Figure 8] 1 at a third intermediate manufacturing stage according to an alternative exemplary embodiment. [Figure 9] 1 at a fourth intermediate manufacturing stage according to an alternative exemplary embodiment. [Figure 10] 1 at a fifth intermediate manufacturing stage according to an alternative exemplary embodiment. FIG. [Figure 11] FIG. 2 is a cross-sectional view of the structure of FIG. 1 at a sixth intermediate manufacturing stage according to an alternative exemplary embodiment. [Figure 12] FIG. 2 is a cross-sectional view of the structure of FIG. 1 at a seventh intermediate manufacturing stage according to an alternative exemplary embodiment. [Figure 13] FIG. 2 is a cross-sectional view of the structure of FIG. 1 at an eighth intermediate manufacturing stage according to an alternative exemplary embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0019] Exemplary embodiments of the present invention will now be described in more detail with respect to phase-change material switches. Phase-change materials are used in nonvolatile memory devices due to the difference in resistance between different phase states caused by Joule heating. When amorphized, the phase-change material exhibits high resistance (open circuit), and when recrystallized, the phase-change material exhibits low resistance (closed circuit). Thus, the threshold voltage is a function of the amorphized volume. Current structures utilize only two terminals, used for both programming and reading, making them unusable as electrical switching devices.

[0020] Thus, exemplary embodiments provide a single four-terminal switching device that uses at least a phase-change material, a wrap-around gate dielectric layer, and a metal gate liner (also referred to as a heater), with the gate dielectric layer between the phase-change material and the metal gate liner. The metal gate liner and gate dielectric layer are configured orthogonal to the phase-change layer, thereby forming a four-terminal switching device. Forming such a device allows for complete separation of the control and signal circuits, thus allowing for a wider range of applications.

[0021] It should be understood that the various layers, structures, and regions illustrated in the accompanying figures are schematic and not drawn to scale. Additionally, for ease of illustration, one or more layers, structures, and regions of the type commonly used in forming semiconductor devices or structures may not be explicitly shown in a given figure. This does not imply that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structure.

[0022] Furthermore, it should be understood that the embodiments described herein are not limited to the specific materials, features, and process steps shown and described herein. In particular, with respect to semiconductor process steps, it should be emphasized that the descriptions provided herein are not intended to be inclusive of all of the process steps that may be required to form a functional semiconductor integrated circuit device. Rather, specific process steps commonly used to form such devices have been purposely not described herein for purposes of brevity.

[0023] It should be noted that the same or similar reference numbers are used throughout the drawings to represent the same or similar features, elements, or structures. Therefore, detailed descriptions of the same or similar features, elements, or structures will not be repeated in each drawing. As used herein, the terms "about" or "substantially" with respect to thickness, width, percentage, range, etc., should be understood to mean close or approximate, but not exact. For example, as used herein, the terms "about" or "substantially" mean that there may be a small margin of error, for example, 1% or less of the specified amount.

[0024] References herein to "one embodiment" or "an embodiment" of the present principles, as well as other variations thereof, mean that a particular feature, structure, characteristic, etc. described with respect to an embodiment is included in at least one embodiment of the present principles. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification, as well as any other variations, do not necessarily refer to the same embodiment. The term "disposed on" means that a first element, such as a first structure, is on a second element, such as a second structure, and there may be an intervening element, such as an interface structure, e.g., an interface layer, between the first and second elements. The term "directly contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive, insulating, or semiconducting layer at the interface between the two elements.

[0025] Although terms such as "first," "second," and the like may be used herein to describe various elements, it should be understood that these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. Thus, a first element described below could be referred to as a second element without departing from the scope of the present concepts.

[0026] As used herein, "height" refers to the vertical dimension of an element (e.g., a layer, trench, hole, opening, etc.) in a cross-sectional view measured from the lower surface to the upper surface of the element, as well as relative to the surface in which the element is located, or both. Conversely, "depth" refers to the vertical dimension of an element (e.g., a layer, trench, hole, opening, etc.) in a cross-sectional view measured from the upper surface to the lower surface of the element. Where indicated, terms such as "thickness," "thickness," "thinness," or derivatives thereof may be used interchangeably with "height."

[0027] As used herein, "width" or "length" refers to the dimension of an element (e.g., a layer, trench, hole, opening, etc.) in a drawing measured from the side of the element to the opposing surface. Where indicated, terms such as "thickness," "thickness," "thinness," or derivatives thereof may be used interchangeably with "width" or "length."

[0028] An exemplary embodiment for fabricating a phase change material switching device is described below with reference to FIGS. 1-13. Note that the same reference numeral (100) is used to designate the structure through the various intermediate manufacturing stages illustrated in FIGS. 1-5, and the same reference numeral (200) is used to designate the structure through the various intermediate manufacturing stages illustrated in FIGS. 6-13. The phase change material switching devices described herein may also be considered semiconductor devices and / or integrated circuits, or portions thereof. For clarity, some manufacturing steps leading to the production of the phase change material switching device illustrated in FIGS. 1-13 have been omitted. In other words, one or more well-known process steps not shown but well-known to those skilled in the art are not included in the figures.

[0029] Figures 1-5 illustrate one embodiment of the present invention. Figure 1 illustrates a portion of structure 100 (plan view) showing hard mask 112, with X and Y cross-sectional locations indicated for identification. Figure 2 illustrates structure 100 of Figure 1 at a first intermediate manufacturing stage. Structure 100 initially includes substrate 102. Generally, substrate 102 can include one or more different types of semiconductor substrate structures and materials, as well as any previously processed layers. For example, in one embodiment, the substrate 102 may be a bulk semiconductor substrate (e.g., a wafer) formed by silicon (Si) or germanium (Ge), or other types of substrate materials commonly used in bulk semiconductor fabrication processes, such as silicon-germanium alloys, compound semiconductor materials (e.g., III-V), an SOI (silicon-on-insulator) substrate including an insulating layer (e.g., an oxide layer) disposed between a base substrate layer (e.g., a silicon substrate) and an active semiconductor layer (e.g., Si, Ge, etc.), a GeOI (germanium-on-insulator) substrate, or other types of semiconductor-on-insulator substrate active semiconductor layers, where active circuit components are formed as part of the FEOL and some BEOL layers prior to forming the switch devices.

[0030] The structure 100 further includes a memory electrode 103 formed on the substrate 102. The memory electrode 103 includes a wiring 106 within a dielectric layer 104. The dielectric layer 104 functions, for example, as an interconnect dielectric (ICD) layer in which the wiring is formed. A lower etch stop layer (not shown) may be provided directly below the ICD layer. The lower etch stop layer may include various types of materials. In one embodiment, the lower etch stop layer includes a dielectric material. In one embodiment, the lower etch stop layer may include a nitrogen-doped BLOK (NBLOK) or a low-k NBLOK. Other types of etch stop materials, such as silicon nitride, may also be useful.

[0031] In one embodiment, the ICD includes a lower portion and an upper portion. The lower portion functions as an interlevel dielectric (ILD) layer, while the upper portion functions as an intrametal dielectric (IMD) layer. The dielectric layer may be a single layer or a multi-layer stack. For example, a single layer may be used to function as both the ILD and the IMD, or separate layers may be used for the ILD and the IMD. Optionally, an etch stop layer may be formed between the ILD and the IMD.

[0032] The dielectric layer can include, for example, silicon oxide. Other types of dielectric materials are also useful. For example, the dielectric layer can include silicon nitride, silicon dioxide, silicon oxynitride, SiCN, SiOCN, SiOC, SiBCN, dielectric metal oxides, dielectric metal nitrides, doped silicon oxides such as fluorinated silicon oxide (FSG), undoped or doped silicate glasses such as boron phosphate silicate glass (BPSG) and phosphate silicate glass (PSG), undoped or doped thermally grown silicon oxide, undoped or doped TEOS-deposited silicon oxide, as well as low-k and ultra-low-k dielectric materials. Low-k dielectric materials have a nominal dielectric constant less than that of SiO2, which is approximately 4 (e.g., the dielectric constant of thermally grown silicon dioxide can range from 3.9 to 4.0). In one embodiment, the low-k dielectric material can have a dielectric constant less than 3.7. Suitable low-k dielectric materials include, for example, fluorinated silicon glass (FSG), carbon-doped oxides, polymers, SiCOH-containing low-k materials, non-porous low-k materials, porous low-k materials, spin-on dielectric (SOD) low-k materials, or any other suitable low-k dielectric material. Ultra-low-k dielectric materials have a nominal dielectric constant of less than 2.5. Suitable ultra-low-k dielectric materials include, for example, SiOCH, porous pSiCOH, pSiCNO, carbon-rich silicon carbonitride (C-rich SiCN), porous silicon carbonitride (pSiCN), boron- and phosphorus-doped SiCOH / pSiCOH, etc. In one exemplary embodiment, at least the IMD layer comprises a low-k or ultra-low-k dielectric material.

[0033] The interconnect 106 is formed in the ICD layer. The interconnect may include multiple interconnects. In one embodiment, the interconnect includes a conductive line 106a in the upper portion, i.e., the IMD, while a contact 106b is formed in the lower portion, i.e., the ILD. The interconnect comprises a conductive material. For example, the conductive material may be any metal or alloy. In one embodiment, the interconnect may include copper, aluminum, tungsten, alloys thereof, or combinations thereof. It is understood that the contact and the conductive line may comprise the same or different materials. The contact connects the conductive line to a contact region below it. Depending on the ICD level, the contact region may be another metal line, or a device such as a diffusion region or gate of a transistor, or a plate of a capacitor.

[0034] A metal liner 108 is formed over the dielectric layer 104 and the interconnect 106. The metal liner 108 is a highly resistive metal liner. Suitable materials for the metal liner 108 include, for example, TaN, TiN, and the like. The metal liner 108 can be deposited by conventional techniques, such as, for example, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), sputtering deposition, physical vapor deposition (PVD), atomic layer deposition (ALD), plating, and other similar processes. In one exemplary embodiment, the metal liner 108 can have a thickness ranging from about 1 nanometer (nm) to about 10 nm.

[0035] A phase change layer 110 comprising a phase change material is formed on the metal liner 108 by conventional techniques, such as CVD, pulsed CVD, and ALD. Phase change memory stores information in a material that can be processed into different phases. Each of these phases exhibits different electrical properties that can be used to store information. Typically, the amorphous and crystalline phases are the two phases used to store bits (1 or 0) due to detectable differences in electrical resistance. Specifically, the amorphous phase has a higher resistance than the crystalline phase.

[0036] In one embodiment, suitable phase-change materials include chalcogenide glasses. This family of materials includes chalcogens (Group 16 / VIA of the Periodic Table) and additional electropositive elements. For example, selenium (Se) and tellurium (Te) are the two most common semiconductors in this family used to make chalcogenide glasses when creating a phase-change layer. Typical examples are Ge2Sb2Te5 (GST), SbTe, and In2Se3. However, some phase-change materials do not use chalcogens, such as GeSb. Therefore, a variety of materials can be used as the phase-change material layer as long as they can maintain the amorphous and crystalline states separately.

[0037] A hard mask 112 is formed on the phase-change layer 110 by any conventional technique. For example, the hard mask 112 can be deposited by, for example, CVD, PECVD, PVD, ALD, and other similar processes. The hard mask 112 may then be subjected to a planarization process, such as a chemical mechanical planarization (CMP) process.

[0038] The hard mask 112 is then patterned to form fins, as illustrated in FIG. 2 . The patterning of the hard mask 112 is achieved by first applying a conventional photoresist (not shown) to the hard mask 112. After applying the photoresist to the hard mask 112, the photoresist is subjected to a lithography process, which involves pattern-exposing the photoresist to a desired radiation pattern and developing the exposed photoresist using a conventional resist developer. The patterned photoresist protects portions of the hard mask 112 while leaving at least one other portion unprotected. The unprotected portions of the hard mask 112 that do not contain the patterned resist, along with the phase-change layer 110 and the metal liner 108, are then etched away. Any etching process that is selective to the patterned resist and removes the unprotected portions of the hard mask 112 may be used. Typically, a reactive ion etching (RIE) process or another similar dry etching process is used. As shown, the etching process stops on top of the dielectric layer 104 and a portion of the top surface of the interconnects 106, such that the remaining portions of the metal liner 108 and phase-change layer 110 below the hard mask 112 form a bridge 111 (see FIG. 1) between the two interconnects 106. The photoresist used to form the patterned hard mask 112 is typically removed after the etching process.

[0039] FIG. 3 illustrates structure 100 at a second intermediate stage. During this stage, gate dielectric layer 114 is formed on the exposed surfaces of dielectric layer 104, interconnect 106, metal liner 108, phase-change layer 110, and hard mask 112. Advantageously, gate dielectric layer 114 protects the sidewalls of phase-change layer 110. Suitable gate dielectric materials for gate dielectric layer 114 include, for example, the same or different dielectric material as dielectric layer 104. Typically, dielectric layer 104 and dielectric layer 114 are composed of an oxide of silicon. Gate dielectric layer 114 is typically formed using a conventional deposition process, such as CVD. In one embodiment, gate dielectric layer 114 has a thickness ranging from about 1 nm to about 5 nm.

[0040] Next, a metal gate liner 116 is formed on the gate dielectric layer 114 using a conventional deposition process, such as CVD, ALD, electroplating, and other similar processes. In one embodiment, the metal gate liner 116 and the gate dielectric layer 114 are configured orthogonal to the phase change layer 110. The metal gate liner 116 is configured as a resistive heater, for example, including a metal or alloy material that is resistive and exhibits substantially high thermal conductivity. For example, the metal gate liner 116 can be formed from niobium (Nb), tungsten (W), platinum (Pt), nickel chromium (NiCr), titanium tungsten (TiW), TaN, TiN, or TaSiN, or any of a variety of similar metals or alloys. The metal gate liner 116 is thus configured to receive an electric current, allowing the phase change layer 110 to be switched between a crystalline state and an amorphous state. In this case, the phase change is achieved by passing a current through a metal gate liner 116 disposed over the phase change layer 110 and electrically insulated from the phase change layer 110 by a gate dielectric layer 114. Passing a current through this "resistive heater" causes the heater to heat up via the Joule effect, and the thermal conduction caused by the "resistive heater" indirectly changes the state of the phase change layer 110. The metal gate liner 116 has a thickness in the range of about 4 nm to about 10 nm.

[0041] Next, a hard mask 118 is formed on the metal gate liner 116 by any conventional technique, such as CVD, PECVD, PVD, ALD, and other similar processes. Suitable materials for the hard mask 118 may be SiN, TEOS, or any other non-conductive film. The hard mask 118 may then be subjected to a planarization process, such as a CMP process. The hard mask 118 is then patterned and subjected to an etching process, such as RIE, to remove portions of the hard mask 118 and expose portions of the metal gate liner 116.

[0042] 4 illustrates the structure 100 at a third intermediate stage. During this stage, exposed portions of the metal gate liner 116 are selectively removed, leaving a portion of the metal gate liner 116 on the gate dielectric layer 114 below the lower surface of the hard mask 118. Removal of the metal gate liner 116 may include applying an etchant selective to the dielectric layer 114 during an etch process, such as an RIE process. For example, etching the exposed portions of the metal gate liner 116 may be a dry etch using an etchant gas. In an exemplary embodiment, the etchant gas used in the dry etch process may include a gas containing fluorine and HO vapor, which may be, for example, CxFy, CHxFy, or the like.

[0043] FIG. 5 illustrates the structure 100 at a fourth intermediate stage. During this stage, a dielectric fill 120 is formed on the gate dielectric layer 114 and over the hard mask layer 118. The dielectric fill 120 may be made of any known dielectric material, such as, for example, silicon oxide, silicon nitride, hydrogenated silicon carbon oxide, low-k dielectric, ultra-low-k dielectric, flowable oxide, porous dielectric, or organic dielectric, including porous organic dielectric. The low-k and ultra-low-k dielectric materials may be any of those described above with respect to the dielectric layer. The dielectric fill 120 may be formed by any suitable deposition technique known in the art, including ALD, CVD, PECVD, PVD, or other similar processes. The dielectric fill 120 may then be subjected to a planarization process, such as a CMP process.

[0044] Next, metal contacts are formed, including metal gate contacts 122. For example, the metal gate contacts 122 are electrically connected to the gate. The metal gate contacts 122 are formed by first forming conductive vias or trenches by methods known in the art, for example, by selectively etching, for example, by RIE, through the hard mask 118, such that the vias or trenches communicate with the conductive vias or trenches of the metal gate contacts 122, which communicate with the respective components, for example, the respective metal gate liners 116. Next, a conductive material is deposited in the vias or trenches. The conductive material of the metal gate contact 122 can include any suitable conductive material, such as, for example, polycrystalline or amorphous silicon, germanium, silicon germanium, metals (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, gold), conductive metal compound materials (e.g., tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, titanium aluminum carbide, tungsten silicide, tungsten nitride, ruthenium oxide, cobalt silicide, nickel silicide), carbon nanotubes, conductive carbon, graphene, or any suitable combination of these materials. The conductive material can further include dopants incorporated during or after deposition. The deposition step can be followed by or combined with an annealing step.

[0045] FIGS. 6-13 illustrate alternative embodiments starting with structure 200. FIG. 6 illustrates structure 200 at a first intermediate fabrication stage. Structure 200 initially includes substrate 202. Generally, substrate 202 can include one or more of the different types of semiconductor substrate structures and materials described above for substrate 102. Structure 200 further includes memory electrodes 203 formed on substrate 202. Memory electrodes 203 include interconnects 206 within dielectric layer 204. Similar to dielectric layer 104 described above, dielectric layer 204 functions as an ICD layer, for example, with interconnects formed therein. In one embodiment, the ICD includes a lower and upper portion. The lower portion functions as an ILD layer, while the upper portion functions as an IMD layer. The dielectric layer can be a single layer or a multi-layer stack. For example, a single layer can be used to function as both an ILD and an IMD, or separate layers can be used for the ILD and IMD. Optionally, an etch stop layer can be formed between the ILD and IMD.

[0046] The dielectric layer 204 may be deposited in a manner similar to that described above for the dielectric layer 104, and may be the same material. The interconnect 206 is formed in the ICD layer. The interconnect may include multiple interconnects. In one embodiment, the interconnect includes a conductive line 206a in the upper portion, i.e., the IMD, while a contact 206b is formed in the lower portion, i.e., the ILD. The interconnect 206 includes a conductive material such as that described above for the interconnect 106.

[0047] A metal liner 208 is formed over the dielectric layer 204 and the interconnect 206. The metal liner 208 is a highly resistive metal liner. The metal liner 208 may be deposited in a manner similar to that described above for the metal liner 108, and may be the same material. In one exemplary embodiment, the metal liner 208 may have a thickness ranging from about 1 nm to about 10 nm.

[0048] A sacrificial layer 210 is formed on the metal liner 208 by conventional techniques, such as CVD and ALD. Suitable materials for the sacrificial layer 210 include any amorphous material, such as, for example, an amorphous silicon (a-Si) material or an amorphous silicon-germanium material (a-SiGe). In one embodiment, the amorphous layer 210 can have a thickness ranging from about 10 nm to about 100 nm.

[0049] A hard mask 212 is formed on the sacrificial layer 210 by any conventional technique, such as described above for the hard mask 112. The hard mask 212 may then be subjected to a planarization process, such as a CMP process. The hard mask 212 is then patterned to form fins, as illustrated in FIG. 6 . The patterning of the hard mask 212 is accomplished as described above. As illustrated, the etching process stops on top of the dielectric layer 204 and a portion of the top surface of the interconnect 206, such that the metal liner 208 and remaining portions of the sacrificial layer 210 below the hard mask 212 form a bridge, such as bridge 111 (see FIG. 1 ), between the two interconnects 206. The photoresist used to form the patterned hard mask 212 is typically removed after the etching process.

[0050] 7 illustrates structure 200 at a second intermediate stage. During this stage, hard mask 212 is first removed by conventional techniques. Next, gate dielectric layer 214 is formed on the exposed surfaces of dielectric layer 204, interconnect 206, metal liner 208, and sacrificial layer 210. Gate dielectric layer 214 may be deposited in a manner similar to that described above for gate dielectric layer 114, and may be the same material. In one embodiment, gate dielectric layer 214 is a relatively thin layer, for example, having a thickness in the range of about 1 nm to about 5 nm.

[0051] FIG. 8 illustrates structure 200 at a third intermediate stage. During this stage, a metal gate liner 216 is formed on gate dielectric layer 214. Metal gate liner 216 may be deposited in a manner similar to, and may be made of, the same material as, metal gate liner 116 described above. Like metal gate liner 116, metal gate liner 216 may be configured as a resistive heater, for example, comprising a metal or alloy material that is resistive and exhibits substantially high thermal conductivity. Thus, metal gate liner 216 may be configured to receive an electric current, as described below, allowing phase change layer 224 to be switched between a crystalline state and an amorphous state. In one embodiment, metal gate liner 216 is a relatively thin layer, for example, having a thickness ranging from about 4 nm to about 10 nm.

[0052] Next, a hard mask 218 is formed on the metal gate liner 216 by any conventional technique, such as CVD, PECVD, PVD, ALD, and other similar processes. The hard mask 218 may be deposited in a manner similar to, and may be the same material as, the hard mask 118 described above. The hard mask 218 may then undergo a planarization process, such as a CMP process. The hard mask 218 is then patterned and subjected to an etching process, such as RIE, to remove portions of the hard mask 218 and expose portions of the metal gate liner 216. The exposed portions of the metal gate liner 216 are selectively removed along with the gate dielectric layer 214, leaving portions of the metal gate liner 216 on the gate dielectric layer 214 below the lower surface of the hard mask 218. Removal of the metal gate liner 216 may include applying an etchant selective to the dielectric layer 214 during an isotropic etch process, such as an RIE process. The dielectric layer 214 is then removed by applying an etchant selective to the dielectric layer 204, the interconnects 206, and the sacrificial layer 210 during an isotropic etch process, such as an RIE process.

[0053] FIG. 9 illustrates the structure 200 at a fourth intermediate stage. It should be understood that dashed lines indicate supports for connecting the elements 214, 216, and 220 illustrated in the structure 200 depicted in the X-section to the structure 200 in the Y-section. During this stage, gate spacers 220 are formed on the sidewalls of at least the gate dielectric layer 214, the metal gate liner 216, and the hard mask 218. Suitable materials for the gate spacers 220 include, for example, Si3N4, SiBCN, SiNC, SiN, SiCO, SiO2, and SiNOC. The gate spacers 220 can be formed by any conventional technique, such as, for example, CVD, PECVD, PVD, or ALD. Next, the sacrificial layer 210 is selectively removed, leaving an air gap 222 defined between the metal liner 208 and the gate dielectric layer 214. If the sacrificial material is an a-Si compound, the sacrificial layer 210 is selectively removed by, for example, hot ammonia or tetramethylammonium hydroxide (TMAH).

[0054] 10 illustrates structure 200 at a fifth intermediate stage. During this stage, phase change layer 224, comprising a phase change material, is formed on the exposed surfaces of dielectric layer 204, interconnect 206, and the sidewalls of gate spacer 220 by conventional techniques, such as CVD. Phase change layer 224 is also formed in air gap 222 defined between metal liner 208 and gate dielectric layer 214. Phase change layer 224 may be the same phase change material as described above for phase change layer 110. Phase change layer 224 may then be subjected to a planarization process, such as a CMP process.

[0055] 11 illustrates structure 200 at a sixth intermediate stage. During this stage, phase change layer 224 is first recessed, for example, by RIE. Dielectric cap 226 is formed on the exposed surface of phase change layer 224 and the sidewalls of gate spacer 220 by blanket or non-selective CVD. Suitable materials for dielectric cap 226 include, for example, silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiNO), or amorphous silicon carbonitride (SiCyNx:H). In one embodiment, dielectric cap 226 has a thickness ranging from about 5 nm to about 50 nm.

[0056] FIG. 12 illustrates structure 200 at a seventh intermediate stage. During this stage, an organic planarization layer (OPL) 228 is deposited on dielectric cap 226 using, for example, a spin-on coating process. OPL 228 may be a self-planarizing organic material containing carbon, hydrogen, oxygen, and optionally nitrogen, fluorine, and silicon. In one embodiment, the self-planarizing organic material may be a polymer with sufficiently low viscosity that the upper surface of the applied polymer forms a flat, horizontal surface. In one embodiment, OPL 228 may comprise a transparent organic polymer. In one embodiment, the OPL may be a standard CxHy polymer. Non-limiting examples of OPL materials include, but are not limited to, CHM701B available from Cheil Chemical, HM8006 and HM8014 available from JSR, or ODL-102 or ODL-401 available from Shin-Etsu Chemical Co., Ltd.

[0057] OPL 228 is then patterned and subjected to standard lithography to remove portions of OPL 228, dielectric cap 226, phase change layer 224, and metal liner 208, exposing portions of dielectric layer 204 and interconnect 206 such that phase change layer 224 and dielectric cap 226 underneath OPL 228 form a bridge between two interconnects 206.

[0058] FIG. 13 illustrates the structure 200 at an eighth intermediate stage. During this stage, the OPL 228 is removed (not shown) by ashing with a standard O2 or N2 / H2-based OPL. A dielectric fill 230 is formed over the dielectric layer 204 and interconnect 206 and over the dielectric cap 226. The dielectric fill may be deposited in a manner similar to, or even the same material as, the dielectric fill 120. The dielectric fill 220 may then be subjected to a planarization process, such as a CMP process. Next, metal contacts, including a metal gate contact 232, are formed. For example, the metal gate contact 232 is electrically connected to the gate. The metal contact 232 is formed by first forming a conductive via or trench using methods known in the art, for example, by selectively etching, for example, by RIE, through the hard mask 218, so that the via communicates with the conductive via or trench of the metal contact 232, which communicates with the respective component, e.g., the respective metal gate liner 216. A conductive material is then deposited in the via. The conductive material of the metal gate contact 232 may be any of those described above for the metal gate contact 122. The deposition step may be performed after or in conjunction with the annealing step.

[0059] It should be understood that the methods described herein for fabricating low-resistivity metal interconnect structures (e.g., copper BEOL interconnect structures) can be incorporated into semiconductor process flows for fabricating other types of semiconductor structures, as well as integrated circuits, including various analog and digital or mixed-signal circuits. In particular, integrated circuit dies can be fabricated that include various devices, such as field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, capacitors, and inductors. Integrated circuits according to the present invention can be used in applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing the present invention may include, but are not limited to, personal computers, communications networks, electronic commerce systems, portable communications devices (e.g., mobile phones), solid-state media storage devices, functional circuits, and the like. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein. Given the teachings of the present invention provided herein, those skilled in the art will be able to envision other implementations and applications of the present technology.

[0060] Although illustrative embodiments have been described herein with reference to the accompanying drawings, it should be understood that the invention is not limited to these detailed embodiments, and that various other changes and modifications may be made thereto by those skilled in the art without departing from the scope of the appended claims.

Claims

1. a phase change layer disposed on the metal liner; a gate dielectric layer disposed on the phase change layer; a metal gate liner disposed on the gate dielectric layer and electrically insulated from the phase change layer by the gate dielectric layer; a bridge formed by the phase change layer and the metal liner connects to a first contact and a second contact, and the metal gate liner connects to a third contact and a fourth contact and is disposed between the third contact and the fourth contact, intersecting a portion of the phase change layer between the first contact and the second contact, and configured so that heat generated by a flowing current is conducted to cause a phase change in the phase change layer.

2. The phase change material switch of claim 1 , wherein the phase change layer comprises a phase change material.

3. The phase change material switch of claim 2 , wherein the phase change material comprises one of selenium and tellurium.

4. The phase change material is Ge ２ Sb ２ Te ５ 3. The phase change material switch of claim 2, wherein the phase change material is GST.

5. a hard mask disposed on the metal gate liner; a first trench and a second trench disposed in the hard mask and configured to expose the metal gate liner; a first conductive material and a second conductive material disposed within the first trench and the second trench, respectively; 5. The phase change material switch of claim 1, further comprising: a first conductive material and a second conductive material providing the third contact and the fourth contact, respectively.

6. The phase change material switch of claim 5 further comprising sidewall spacers disposed on the hardmask, the metal gate liner, and the gate dielectric layer.

7. The phase change material switch of any one of claims 1 to 6, wherein the metal gate liner and the gate dielectric layer are configured orthogonal to the phase change layer.

8. 8. The phase change material switch of claim 7 in the form of a four-terminal phase change material switch having terminals connected to the first contact, the second contact, the third contact, and the fourth contact, respectively.

9. A phase change material switch according to any one of claims 1 to 8; an electrode including an intermetal dielectric layer and a first metal contact via and a second metal contact via in the intermetal dielectric layer, the first metal contact via and the second metal contact via providing the first contact and the second contact, respectively; the metal liner disposed on a portion of the intermetal dielectric layer, a portion of the first metal contact via, and a portion of the second metal contact via; 1. A phase change material bridge device comprising: a phase change material bridge device, wherein the gate dielectric layer is further disposed on the metal liner and the phase change layer, as well as on the intermetal dielectric layer and remaining portions of the first metal contact via and the second metal contact via, and the metal liner and the phase change layer include a horizontal bridge between the first metal contact via and the second metal contact via.

10. A phase change material switch according to any one of claims 1 to 8; a semiconductor substrate; an electrode disposed on the semiconductor substrate, the electrode including an intermetal dielectric layer and a first metal contact via and a second metal contact via in the intermetal dielectric layer, the first metal contact via and the second metal contact via providing the first contact and the second contact, respectively; the metal liner disposed on a portion of the intermetal dielectric layer, a portion of the first metal contact via, and a portion of the second metal contact via; 10. A semiconductor structure comprising: wherein the metal liner and the phase change layer comprise a horizontal bridge between the first metal contact via and the second metal contact via.

11. forming a metal liner over the electrode, including the intermetal dielectric layer and the first and second metal contact vias in the intermetal dielectric layer; forming a phase change layer on the metal liner; forming a first hard mask over the phase change layer; selectively removing the metal liner, the phase change layer, and a portion of the first hard mask to expose a portion of the intermetal dielectric layer and a portion of the first metal contact via and a portion of the second metal contact via, wherein the remaining portions of the metal liner, the phase change layer, and the first hard mask form a horizontal bridge between the first metal contact via and the second metal contact via; forming a gate dielectric layer on the metal liner, the phase change layer, and an outer surface of the first hard mask, as well as on exposed portions of the intermetal dielectric layer and each of the first and second metal contact vias; forming a resistive metal gate liner on the gate dielectric layer, electrically insulated from the phase change layer by the gate dielectric layer, such that the resistive metal gate liner intersects with the bridge portion of the phase change layer; forming a first metal gate contact and a second metal gate contact connecting to the metal gate liner on one side and the other side of the bridge portion of the phase change layer, respectively; wherein the metal gate liner is configured to conduct heat generated by a flow of electrical current to cause a phase change in the phase-change layer.

12. forming a second hard mask on the metal gate liner; Etching the second hard mask to expose a portion of the metal gate liner; removing the exposed portion of the metal gate liner to expose the gate dielectric layer, leaving a remaining portion of the metal gate liner intersecting the bridge portion of the phase-change layer; The method of claim 11 further comprising:

13. forming a first trench and a second trench in the second hard mask to expose the metal gate liner; depositing a first conductive material and a second conductive material in the first trench and the second trench, respectively; 13. The method of claim 12, further comprising: wherein the first conductive material and the second conductive material provide the first metal gate contact and the second metal gate contact, respectively.

14. The phase change layer is Ge ２ Sb ２ Te ５ The method according to any one of claims 11 to 13, comprising (GST).

15. forming a metal liner over the electrode, including the intermetal dielectric layer and the first and second metal contact vias in the intermetal dielectric layer; forming a sacrificial layer on the metal liner; forming a first hard mask on the sacrificial layer; selectively removing the metal liner, the sacrificial layer, and a portion of the first hard mask to expose a portion of the intermetal dielectric layer and a portion of the first metal contact via and a portion of the second metal contact via, wherein the remaining portions of the metal liner, the sacrificial layer, and the first hard mask form a bridge between the first metal contact via and the second metal contact via; removing the first hard mask; forming a gate dielectric layer on the sacrificial layer, the metal liner, and exposed portions of the intermetal dielectric layer and each of the first and second metal contact vias; forming a resistive metal gate liner on the gate dielectric layer; forming a second hard mask on the metal gate liner; Etching the second hard mask to expose a portion of the metal gate liner; removing the exposed portion of the metal gate liner to expose the gate dielectric layer and leaving a remaining portion of the metal gate liner intersecting the bridge portion of the sacrificial layer; removing the exposed portion of the gate dielectric layer to expose the sacrificial layer and a portion of the intermetal dielectric layer and a portion of the first metal contact via and a portion of the second metal contact via; removing the sacrificial layer to expose the metal liner and form an air gap defined between an upper surface of the metal liner and a lower surface of the gate dielectric layer; depositing a phase change layer in the air gap and on the exposed portions of the metal liner, the intermetal dielectric layer, and each of the first and second metal contact vias, wherein the phase change layer is electrically insulated from the metal gate liner by the gate dielectric layer; forming a first metal gate contact and a second metal gate contact connected to the metal gate liner on one side and the other side of the portion of the phase change layer corresponding to the bridge, respectively; wherein the metal gate liner is configured to conduct heat generated by a flow of electrical current to cause a phase change in the phase-change layer.

16. 16. The method of claim 15, further comprising forming sidewall spacers on sidewalls of the second hardmask and on the metal gate liner and the gate dielectric layer below the second hardmask before removing the sacrificial layer.

17. removing a portion of the metal liner, the intermetal dielectric layer, and the phase change layer on the exposed portions of each of the first and second metal contact vias; forming a dielectric cap layer on the partially removed phase change layer; forming an organic planarization layer over the dielectric cap layer; patterning the organic planarization layer to expose a portion of the intermetal dielectric layer, a portion of the first metal contact via, and a portion of the second metal contact via; forming a first trench and a second trench in the second hard mask to expose the metal gate liner; depositing a first conductive material and a second conductive material in the first trench and the second trench, respectively; 17. The method of claim 16, further comprising: wherein the first conductive material and the second conductive material provide the first metal gate contact and the second metal gate contact, respectively.

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