Semiconductor Devices

Abstract

To suppress electric field concentration in a semiconductor substrate.SOLUTION: A semiconductor device has a semiconductor substrate with an element region and a peripheral region. The semiconductor substrate has: an n-type high-concentration layer straddled from the element region over the peripheral region and in contact with a lower electrode, having a thin plate part and a thick plate part; an n-type drift layer that is in contact with the top face of the thick plate part; and an n-type low-concentration layer straddled from the element region over the peripheral region and in contact with the top face of the thin plate part and a lateral face of a step part. When a potential of the lower electrode is raised, a half or more of a quadrilateral region formed by the lateral face of the step part, a virtual line obtained by shifting the lateral face of the step part by a height of the step part toward the peripheral region, the top face of the thin plate part, and a virtual line obtained by shifting the top face of the thin plate part upward by the height, is not depleted.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a semiconductor device.

[0002] In the semiconductor device disclosed in Patent Document 1, a semiconductor substrate has an element region and a peripheral region. A recess is provided on the upper surface of the semiconductor substrate in the peripheral region. Therefore, the upper surface of the semiconductor substrate protrudes more in the element region than in the peripheral region. The semiconductor device has an upper electrode, a lower electrode, an insulating layer, and a field plate. The upper electrode contacts the upper surface of the semiconductor substrate in the element region. The lower electrode contacts the lower surface of the semiconductor substrate in both the element region and the peripheral region. The insulating layer covers the side and bottom surfaces of the recess. The field plate extends from the upper electrode to the top of the peripheral region and faces the side and bottom surfaces of the recess via the insulating layer. The semiconductor substrate has an n-type high-concentration layer, an n-type drift layer, and an n-type low-concentration layer. The high-concentration layer is distributed across the element region and the peripheral region and is in contact with the lower electrode. The high-concentration layer has a thin plate portion and a thick plate portion. The top surface of the thick plate portion protrudes more than the top surface of the thin plate portion. The thick plate portion is disposed within the element region. The thin plate portion is distributed across the element region and the peripheral region. The drift layer is disposed in the element region and is in contact with the upper surface of the thick plate portion. The drift layer is in Schottky contact with the upper electrode. The drift layer may be connected to the upper electrode via a p-layer. A diode (e.g., a Schottky barrier diode, a pn diode, etc.) is formed between the drift layer and the upper electrode. The low-concentration layer is in contact with the side surface of the drift layer, the upper surface of the thin plate portion, and the side surface of a step portion formed at the boundary between the thick plate portion and the thin plate portion. In this semiconductor device, the field plate and the low-concentration layer suppress electric field concentration in the peripheral region. Furthermore, in this semiconductor device, the high-concentration layer has a thin plate portion in the peripheral region, which ensures the thickness of the low-concentration layer above the thin plate portion. This improves the breakdown voltage of the peripheral region. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2017-139289 Summary of the Invention [Problem to be solved by the invention]

[0004] As described above, in the semiconductor device of Patent Document 1, the high-concentration layer has a thick portion and a thin portion, and a step portion is formed at the boundary between the thick portion and the thin portion. The semiconductor device of Patent Document 1 has a problem in that when the drift layer and the low-concentration layer are depleted, an electric field is likely to concentrate around the upper end of the step portion. This specification proposes a semiconductor device that can effectively suppress electric field concentration inside the semiconductor substrate. [Means for solving the problem]

[0005] A first semiconductor device disclosed in this specification includes a semiconductor substrate, an upper electrode, a lower electrode, an insulating layer, and a field plate. The semiconductor substrate includes an element region and a peripheral region arranged around the element region. A recess is provided in the upper surface of the semiconductor substrate in the peripheral region so that the upper surface of the semiconductor substrate protrudes more in the element region than in the peripheral region. The upper electrode contacts the upper surface of the semiconductor substrate in the element region. The lower electrode contacts the lower surface of the semiconductor substrate in the element region and in the peripheral region. The insulating layer covers the side and bottom surfaces of the recess. The field plate extends from the upper electrode to the top of the peripheral region and faces the side and bottom surfaces of the recess via the insulating layer. The semiconductor substrate includes a high-concentration layer, a drift layer, and a low-concentration layer. The high-concentration layer is an n-type layer distributed across the device region and the peripheral region, in contact with the lower electrode, has a thin plate portion and a thick plate portion, the top surface of the thick plate portion protruding beyond the top surface of the thin plate portion, the thick plate portion is disposed within the device region, and the thin plate portion is distributed across the device region and the peripheral region. The drift layer is disposed within the device region, in contact with the top surface of the thick plate portion, and is an n-type layer with a lower n-type impurity concentration than the high-concentration layer. The low-concentration layer is distributed across the device region and the peripheral region, in contact with the side surface of the drift layer, the top surface of the thin plate portion, the side surface of a step portion formed at the boundary between the thick plate portion and the thin plate portion, and the side surface and bottom surface of the recess are in contact with the insulating layer, and is an n-type layer with a lower n-type impurity concentration than the drift layer. The drift layer is connected to the upper electrode via at least one of a pn junction and a Schottky junction. When the potential of the lower electrode relative to the upper electrode is raised to a potential at which avalanche breakdown occurs within the semiconductor substrate, in a cross section perpendicularly intersecting the step portion, more than half of the rectangular region formed by the side of the step portion, an imaginary line obtained by shifting the side of the step portion toward the peripheral region by the height of the step portion, the top surface of the thin plate portion, and an imaginary line obtained by shifting the top surface of the thin plate portion upward by the height is not depleted.

[0006] In this semiconductor device, when a high voltage is applied, more than half of the rectangular region is not depleted, thereby suppressing electric field concentration around the upper end of the step portion. With this structure, electric field concentration inside the semiconductor substrate can be effectively suppressed, and the breakdown voltage of the semiconductor device can be improved. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view of a semiconductor device 10. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Figure 3] FIG. 3 is a cross-sectional view showing the distribution of a depletion layer in a cross section corresponding to FIG. 2; [Figure 4] 4 is a graph showing the electric field distribution along lines AA and BB in FIG. 3; [Figure 5] FIG. 3 is a cross-sectional view showing the distribution of a depletion layer around a step portion 21. [Figure 6] FIG. 10 is a cross-sectional view showing the distribution of a depletion layer around a step portion 21 in a comparative example. [Figure 7] FIG. 4 is a cross-sectional view showing a modified example of the first embodiment. [Figure 8] FIG. 4 is a cross-sectional view showing a modified example of the first embodiment. [Figure 9] FIG. [Figure 10] FIG. 10 is a cross-sectional view showing a third embodiment. [Figure 11] FIG. 4 is a cross-sectional view showing a modified example of the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] In the first semiconductor device, when the potential of the lower electrode relative to the upper electrode is increased to a potential at which avalanche breakdown occurs in the semiconductor substrate, the region of the low concentration layer below a straight line extending at a 45-degree angle from the upper end of the step portion toward the upper surface of the thin plate portion does not need to be depleted.

[0009] This configuration can further improve the breakdown voltage of the semiconductor device.

[0010] The present specification also discloses a second semiconductor device comprising a semiconductor substrate, an upper electrode, a lower electrode, an insulating layer, and a field plate. The semiconductor substrate comprises an element region and a peripheral region arranged around the element region. A recess is provided in the upper surface of the semiconductor substrate so that the upper surface of the semiconductor substrate protrudes in the element region relative to the peripheral region. The upper electrode contacts the upper surface of the semiconductor substrate in the element region. The lower electrode contacts the lower surface of the semiconductor substrate in the element region and the peripheral region. The insulating layer covers the side and bottom surfaces of the recess. The field plate extends from the upper electrode to the top of the peripheral region and faces the side and bottom surfaces of the recess via the insulating layer. The semiconductor substrate comprises a high-concentration layer, a drift layer, and a low-concentration layer. The high-concentration layer is an n-type layer distributed across the device region and the peripheral region, in contact with the lower electrode, has a thin plate portion and a thick plate portion, the top surface of the thick plate portion protruding beyond the top surface of the thin plate portion, the thick plate portion is disposed within the device region, and the thin plate portion is distributed across the device region and the peripheral region. The drift layer is disposed within the device region, in contact with the top surface of the thick plate portion, and is an n-type layer with a lower n-type impurity concentration than the high-concentration layer. The low-concentration layer is an n-type layer distributed across the device region and the peripheral region, in contact with the side surfaces of the drift layer, in contact with the top surface of the thin plate portion, and in contact with the insulating layer at the side surfaces and bottom surfaces of the recess, and is an n-type layer with a lower n-type impurity concentration than the drift layer. The drift layer is connected to the upper electrode via at least one of a pn junction and a Schottky junction. A displacement portion is formed at the boundary between the thick plate portion and the thin plate portion, where the upper surface of the high-concentration layer is gradually displaced downward from the thick plate portion toward the thin plate portion, and the low-concentration layer is in contact with the upper surface of the high-concentration layer within the displacement portion.

[0011] In this semiconductor device, when a high voltage is applied, the depletion layer is distributed smoothly along the upper surface of the high-concentration layer at the boundary between the thick and thin portions (i.e., the displacement portion). This suppresses electric field concentration near the boundary between the thick and thin portions. This structure effectively suppresses electric field concentration inside the semiconductor substrate, thereby improving the breakdown voltage of the semiconductor device.

[0012] In the first or second semiconductor device, the insulating layer may include a first insulating layer in contact with the bottom surface of the recess, and a second insulating layer disposed on the first insulating layer and having a dielectric constant different from that of the first insulating layer. The first insulating layer and the second insulating layer may be disposed between the field plate and the bottom surface of the recess.

[0013] This configuration allows the two insulating layers to widen the gap between the field plate and the semiconductor substrate, thereby suppressing electric field concentration in the low-concentration layer. Furthermore, the dielectric constant of one of the insulating layers can be increased, thereby suppressing electric field concentration in that insulating layer.

[0014] The first insulating layer may have a higher dielectric constant than the second insulating layer, and the second insulating layer may have a higher breakdown voltage than the first insulating layer.

[0015] With this configuration, the breakdown voltage of the second insulating layer close to the field plate is high, so that breakdown of the insulating layer due to electric field concentration at the edge of the field plate can be suppressed.

[0016] The insulating layer between the field plate and the side surface of the recess may be formed of a single layer of the first insulating layer or the second insulating layer.

[0017] This configuration can reduce the concentration of the electric field at the periphery of the element region.

[0018] The insulating layer between the field plate and the side surface of the recess may be made of the first insulating layer or the second insulating layer, whichever has a higher dielectric constant.

[0019] This configuration can further reduce the electric field concentration in the outer periphery of the element region. [Example]

[0020] The semiconductor device 10 of Example 1 shown in FIG. 1 includes a semiconductor substrate 12. The semiconductor substrate 12 is made of a semiconductor material such as Si, SiC, GaN, or Ga2O3. When viewed from above, the semiconductor substrate 12 has an element region 30 in the center thereof, and a peripheral region 40 surrounding the element region 30. The element region 30 is a region where semiconductor elements such as diodes and switching elements are provided. The peripheral region 40 is a region for ensuring a breakdown voltage around the element region 30. As shown in FIG. 2, a recess 42 is provided in the upper surface 12a of the semiconductor substrate 12. The recess 42 is provided throughout the entire peripheral region 40 of the upper surface 12a. The recess 42 extends from a position adjacent to the element region 30 to the outer peripheral end surface 12c of the semiconductor substrate 12. Therefore, the upper surface 12a in the element region 30 protrudes above the upper surface 12a in the peripheral region 40 (i.e., the bottom surface 42a of the recess 42).

[0021] A lower electrode 60 is provided on the lower part of the semiconductor substrate 12. The lower electrode 60 covers almost the entire lower surface 12b of the semiconductor substrate 12. That is, the lower electrode 60 is in contact with the lower surface 12b in a range spanning from the element region 30 to the peripheral region 40.

[0022] On the upper part of the semiconductor substrate 12, an upper electrode 62, a peripheral insulating layer 64, a field plate 66, and a protective insulating layer 68 are provided.

[0023] The upper electrode 62 has a first metal layer 62a and a second metal layer 62b. The first metal layer 62a is in contact with the upper surface 12a of the semiconductor substrate 12 in the element region 30. The second metal layer 62b is made of a metal different from that of the first metal layer 62a. The second metal layer 62b covers the upper surface of the first metal layer 62a.

[0024] The peripheral insulating layer 64 covers the bottom surface 42a and the side surface 42b of the recess 42. The peripheral insulating layer 64 also covers the outer periphery of the upper surface 12a in the element region 30. In the first embodiment, the peripheral insulating layer 64 is made of silicon oxide.

[0025] The field plate 66 is a portion of the second metal layer 62b of the upper electrode 62 that extends to the top of the peripheral region 40. The field plate 66 extends from the upper electrode 62 along the surface of the peripheral insulating layer 64 to the top of the recess 42. The field plate 66 faces the bottom surface 42a and side surface 42b of the recess 42 with the peripheral insulating layer 64 interposed therebetween.

[0026] The protective insulating layer 68 covers the outer periphery of the upper electrode 62 , the field plate 66 , and the outer periphery of the peripheral insulating layer 64 .

[0027] The semiconductor substrate 12 includes a cathode layer 20, a drift layer 22, an anode layer 24, and a high resistivity layer .

[0028] The cathode layer 20 is an n-type layer with a high concentration of n-type impurities. The cathode layer 20 is distributed over an area including the entire lower surface 12b. That is, the cathode layer 20 is distributed across the element region 30 and the peripheral region 40. The cathode layer 20 is in ohmic contact with the lower electrode 60 over an area spanning the element region 30 and the peripheral region 40. The cathode layer 20 has a thick plate portion 20a and a thin plate portion 20b. The thick plate portion 20a is located in the center of the element region 30. The thin plate portion 20b is distributed across the periphery of the element region 30 and the peripheral region 40. The top surface of the thick plate portion 20a protrudes above the top surface of the thin plate portion 20b. Therefore, a step portion 21 exists between the top surface of the thick plate portion 20a and the top surface of the thin plate portion 20b. The step portion 21 is located at the boundary between the thick plate portion 20a and the thin plate portion 20b. 1, the step portion 21 extends parallel to the outer peripheral end surface 12c of the semiconductor substrate 12 so as to surround the center of the element region 30. As indicated by line II-II in FIG. 1, the cross section of FIG. 2 is a cross section perpendicular to the step portion 21.

[0029] The drift layer 22 is an n-type layer having a lower n-type impurity concentration than the cathode layer 20. The drift layer 22 is disposed in the element region 30. The drift layer 22 is disposed above the thick plate portion 20a and is in contact with the upper surface of the thick plate portion 20a.

[0030] The high resistivity layer 26 is an n-type layer having a lower n-type impurity concentration than the drift layer 22. Because the high resistivity layer 26 has a lower n-type impurity concentration than the drift layer 22, the high resistivity layer 26 has a higher resistivity than the drift layer 22. The high resistivity layer 26 is distributed across the outer periphery of the element region 30 and the peripheral region 40. The high resistivity layer 26 is disposed on top of the thin plate portion 20b and is in contact with the upper surface of the thin plate portion 20b. The high resistivity layer 26 is in contact with the side surface of the step portion 21. The high resistivity layer 26 is in contact with the side surface of the drift layer 22. The high resistivity layer 26 is in contact with the peripheral insulating layer 64 at the bottom surface 42a and side surface 42b of the recess 42.

[0031] The anode layer 24 is a p-type layer. The anode layer 24 is disposed in the element region 30. The anode layer 24 is distributed over an area including the entire upper surface 12a in the element region 30. The anode layer 24 is in contact with the upper surface of the drift layer 22 and the upper surface of the high resistivity layer 26 in the element region 30. The central portion of the anode layer 24 is in ohmic contact with the first metal layer 62a of the upper electrode 62. Therefore, the drift layer 22 is connected to the upper electrode 62 via a p-n junction (i.e., a p-n junction between the drift layer 22 and the anode layer 24). The outer periphery of the anode layer 24 is covered with a peripheral insulating layer 64 and faces a field plate 66 via the peripheral insulating layer 64.

[0032] A PIN diode is formed by the anode layer 24, drift layer 22, and cathode layer 20 in the element region 30. When the potential of the upper electrode 62 is made higher than the potential of the lower electrode 60, the PIN diode turns on, and a current flows from the upper electrode 62 to the lower electrode 60 via the anode layer 24, drift layer 22, and cathode layer 20.

[0033] When the potential of the lower electrode 60 is increased above that of the upper electrode 62, a reverse voltage is applied to the pn junction. As a result, a depletion layer extends from the pn junction to the drift layer 22 and the high-resistivity layer 26. The dashed line 70 in FIG. 3 indicates the distribution range of the depletion layer when a predetermined potential higher than that of the upper electrode 62 is applied to the lower electrode 60. Because the n-type impurity concentration of the high-resistivity layer 26 is low, the depletion layer easily spreads within the high-resistivity layer 26. In addition, the field plate 66 suppresses the generation of a lateral potential difference within the high-resistivity layer 26. As a result, the lateral expansion of the depletion layer within the high-resistivity layer 26 is promoted. As a result, electric field concentration around the side surface 42b of the recess 42 is suppressed. The dashed line 72 in FIG. 3 indicates the distribution range of the depletion layer when the potential of the lower electrode 60 is increased compared to the case of the dashed line 70. As indicated by the dashed line 72, the distribution range of the depletion layer expands when the potential of the lower electrode 60 is increased. In the state indicated by the dashed line 72, the depletion layer has almost reached the cathode layer 20. Therefore, if the potential of the lower electrode 60 is further increased from the state indicated by the dashed line 72, an avalanche breakdown occurs in the semiconductor substrate 12.

[0034] FIG. 4 shows the electric field distributions at the positions of lines AA and BB in FIG. 3 in a state where a depletion layer is distributed as indicated by the dashed line 72. Graph A in FIG. 4 shows the electric field distribution at the position of line AA, with the origin of graph A being the position of the pn junction. Graph B in FIG. 4 shows the electric field distribution at the position of line BB, with the origin of graph B being the position of the bottom surface 42a of the recess 42. At the position of line AA (i.e., within the drift layer 22), the electric field gradually decreases from the maximum electric field Ec from the upper end to the lower end of the drift layer 22 due to the influence of fixed charges present in the depletion layer. Because the n-type impurity concentration of the high resistivity layer 26 is low, the fixed charges present in the high resistivity layer 26 are extremely small. Therefore, at the position of line BB (i.e., within the high resistivity layer 26), an electric field substantially equal to the maximum electric field Ec is generated from the upper end to the lower end of the high resistivity layer 26. The areas S1 and S2 of the shaded portions of graphs A and B in FIG. 4 correspond to the voltages held in the drift layer 22 and the high resistivity layer 26. As is clear from FIG. 4 , the voltage that can be held by the drift layer 22 is the area S1 of the triangular region defined by graph A, and the voltage that can be held by the high resistivity layer 26 is the area S2 of the approximately rectangular region defined by graph B. When the thickness of the drift layer 22 is T1, the area S1 satisfies the relationship S1 ≈ T1·Ec / 2. When the thickness of the high resistivity layer 26 is T2, the area S2 satisfies the relationship S2 ≈ T2·Ec. Therefore, if the thickness T2 is greater than half the thickness T1, the high resistivity layer 26 can hold a higher voltage than the drift layer 22. In this embodiment, the stepped portion 21 is provided, and therefore the thickness T2 of the high resistivity layer 26 is greater than half the thickness T1 of the drift layer 22. Therefore, the high resistivity layer 26 can hold a higher voltage than the drift layer 22. Therefore, if the potential of the lower electrode 60 is further increased from the state indicated by the dashed line 72 in FIG. 3 , an avalanche breakdown occurs in the drift layer 22. Since the upper electrode 62 is provided over the entire upper portion of the drift layer 22, when avalanche breakdown occurs in the drift layer 22, the avalanche current is quickly discharged to the upper electrode 62. This reduces the stress applied to the semiconductor device 10 by the avalanche current.

[0035] FIG. 5 shows an enlarged view of the step portion 21 in a state where the depletion layer is distributed as indicated by the dashed line 72 (i.e., the state at the moment when avalanche breakdown occurs). FIG. 5 also shows a cross section perpendicularly intersecting the step portion 21. The imaginary line 80 in FIG. 5 is a line obtained by shifting the side surface of the step portion 21 toward the peripheral region 40 by a distance equal to the height H1 of the step portion 21. The imaginary line 82 in FIG. 5 is a line obtained by shifting the top surface of the thin plate portion 20b upward by a distance equal to the height H1 of the step portion 21 (in other words, an extension of the top surface of the thick plate portion 20a). Region X in FIG. 5 is a rectangular region surrounded by the side surface of the step portion 21, the top surface of the thin plate portion 20b, the imaginary line 80, and the imaginary line 82. 5 is a straight line extending at a 45-degree angle from the upper end of the step portion 21 toward the upper surface of the thin plate portion 20b (in other words, a diagonal line of the rectangular region X). As indicated by the dashed line 72 in FIG. 5, at the moment when the avalanche breakdown occurs, more than half of the region X is not depleted. In particular, the region below the virtual line 84 is not depleted.

[0036] FIG. 6 shows the distribution of the depletion layer in a semiconductor device of a comparative example. In FIG. 6, the dashed line 72 extends below the imaginary line 84, and more than half of region X is depleted. When the depletion layer penetrates deep into region X, the upper end of the step portion 21 protrudes into the depletion layer, causing electric field concentration around the upper end of the step portion 21. In contrast, when the depletion layer is prevented from penetrating region X as shown in FIG. 5, electric field concentration near the upper end of the step portion 21 is suppressed. In this embodiment, the thickness and n-type impurity concentration of the drift layer 22, the thickness and n-type impurity concentration of the high resistivity layer 26, and the height of the step portion 21 are appropriately set, so that more than half of region X is not depleted before avalanche breakdown occurs. This suppresses electric field concentration at the upper end of the step portion 21, improving the breakdown voltage of the semiconductor device 10. As described above, according to the semiconductor device 10 of the first embodiment, the stepped portion 21 can ensure the thickness of the high resistivity layer 26, and electric field concentration at the upper end of the stepped portion 21 can be suppressed.

[0037] In the first embodiment described above, the drift layer 22 is connected to the upper electrode 62 via a pn junction. However, as shown in FIG. 7 , the semiconductor substrate 12 may not have an anode layer 24, and the drift layer 22 may be connected to the upper electrode 62 via a Schottky junction. In this case, the element region 30 operates as a Schottky barrier diode (hereinafter referred to as an SBD). In the semiconductor device of FIG. 7 , when a reverse voltage is applied to the SBD, a depletion layer spreads from the Schottky junction (i.e., the interface between the upper electrode 62 and the drift layer 22) to the drift layer 22 and the high-resistivity layer 26. Even in the semiconductor device of FIG. 7 , the breakdown voltage can be improved by distributing the depletion layer as shown in FIG. 5 . Alternatively, as shown in FIG. 8 , the anode layer 24 may be partially provided in a range facing the upper surface 12 a in the element region 30, and the drift layer 22 may be Schottky-junctioned to the upper electrode 62 in a range where the anode layer 24 is not provided. Alternatively, the semiconductor element provided in the element region 30 may be a switching element such as a MOSFET. Similarly, in the second and third embodiments described later, any semiconductor element can be provided in the element region 30. [Example]

[0038] 9, a displacement portion 21x is formed at the boundary between a thick portion 20a and a thin portion 20b instead of a step portion 21. Other configurations of the semiconductor device 100 of the second embodiment are the same as those of the semiconductor device 10 of the first embodiment.

[0039] As shown in FIG. 9, in the displacement portion 21x, the upper surface of the cathode layer 20 gradually displaces downward from the thick portion 20a toward the thin portion 20b. Therefore, the upper surfaces of the thick portion 20a and the thin portion 20b are smoothly connected by the displacement portion 21x. Within the displacement portion 21x, the high resistivity layer 26 contacts the upper surface of the cathode layer 20. The dashed line 72 in FIG. 9 indicates the distribution of the depletion layer immediately before avalanche breakdown occurs. As shown by the dashed line 72, in the semiconductor device 100 of Example 2, the lower end of the depletion layer is distributed along the displacement portion 21x. This prevents the depletion layer from being distributed as shown in FIG. 6. Therefore, the configuration of Example 2 can suppress electric field concentration at the boundary between the thick portion 20a and the thin portion 20b. In this way, in the semiconductor device 100 of the second embodiment, the displacement portion 21x ensures the thickness of the high resistivity layer 26, and also suppresses electric field concentration at the boundary between the thick portion 20a and the thin portion 20b. [Example]

[0040] In the semiconductor device 200 of Example 3 shown in FIG. 10 , the peripheral insulating layer 64 includes a first insulating layer 64a and a second insulating layer 64b. The first insulating layer 64a is made of hafnium oxide. The first insulating layer 64a covers the bottom surface 42a of the recess 42, the side surface 42b of the recess 42, and the outer periphery of the top surface 12a within the element region 30. The second insulating layer 64b is made of silicon oxide. The dielectric constant of silicon oxide is lower than that of hafnium oxide. The breakdown voltage of silicon oxide is higher than that of hafnium oxide. The second insulating layer 64b is disposed on the first insulating layer 64a. The top surface of the second insulating layer 64b is covered by a field plate 66. Therefore, the first insulating layer 64a and the second insulating layer 64b are disposed between the field plate 66 and the bottom surface 42a of the recess 42. An outer peripheral edge 66x of the field plate 66 is disposed on the second insulating layer 64b. The peripheral insulating layer 64 between the field plate 66 and the side surface 42b of the recess 42 is composed of a single layer of the first insulating layer 64a.

[0041] An electric field is likely to concentrate near the outer peripheral edge 66x of the field plate 66. According to the configuration of the third embodiment, two insulating layers (i.e., the first insulating layer 64a and the second insulating layer 64b) are provided between the field plate 66 and the bottom surface 42a of the recess 42, thereby making it possible to widen the gap between the field plate 66 and the bottom surface 42a. This allows the outer peripheral edge 66x of the field plate 66, where electric field concentration is likely to occur, to be located away from the high resistivity layer 26. This makes it possible to prevent a high electric field from being generated within the high resistivity layer 26. Furthermore, since a portion of the peripheral insulating layer 64 is made of the first insulating layer 64a (i.e., hafnium oxide, which has a high dielectric constant), the electric field within the first insulating layer 64a can be alleviated. Furthermore, at the position in contact with the outer peripheral edge 66x of the field plate 66 where electric field concentration is likely to occur, the peripheral insulating layer 64 is made of the second insulating layer 64b (i.e., silicon oxide with a high breakdown voltage), so that breakdown can be prevented from occurring in the peripheral insulating layer 64 near the outer peripheral edge 66x of the field plate 66.

[0042] Furthermore, the peripheral insulating layer 64 between the field plate 66 and the side surface 42b of the recess 42 is composed of a single layer of the first insulating layer 64a. This allows the field plate 66 to be disposed near the side surface 42b (i.e., the outer periphery of the element region 30). Electric field concentration is likely to occur in the outer periphery of the element region 30, but by disposing the field plate 66 near the outer periphery of the element region 30, electric field concentration in the outer periphery of the element region 30 can be suppressed. Furthermore, because the peripheral insulating layer 64 between the field plate 66 and the side surface 42b is composed of the first insulating layer 64a (i.e., hafnium oxide, which has a high dielectric constant), electric field concentration in the outer periphery of the element region 30 can be more effectively suppressed.

[0043] The structure of the peripheral insulating layer 64 of the third embodiment may be applied to the semiconductor device 100 of the second embodiment.

[0044] Furthermore, in the third embodiment, the first insulating layer 64a has a higher dielectric constant than the second insulating layer 64b, but the second insulating layer 64b may have a higher dielectric constant than the first insulating layer 64a.

[0045] In the above-described first to third embodiments, the peripheral region 40 (i.e., the recess 42) is provided in the outer periphery of the semiconductor substrate 12. However, at least a part of the peripheral region 40 may be provided between the element region 30 and another region. For example, as shown in FIG. 11 , a part of the peripheral region 40 may be provided between the element region 30 in which the diode is provided and a region 90 in which the switching element is provided.

[0046] The cathode layer 20 of the embodiment is an example of a high concentration layer, and the high resistivity layer of the embodiment is an example of a low concentration layer.

[0047] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0048] 10: semiconductor device, 12: semiconductor substrate, 20: cathode layer, 20a: thick plate portion, 20b: thin plate portion, 21: step portion, 22: drift layer, 26: high resistivity layer, 30: element region, 40: peripheral region, 42: recess, 64: peripheral insulating layer, 66: field plate

Claims

1. A semiconductor device, a semiconductor substrate including an element region and a peripheral region disposed around the element region, wherein a recess is provided in the upper surface of the semiconductor substrate in the peripheral region so that the upper surface of the semiconductor substrate protrudes more in the element region than in the peripheral region; an upper electrode in contact with the upper surface of the semiconductor substrate within the element region; a lower electrode in contact with a lower surface of the semiconductor substrate in the element region and the peripheral region; an insulating layer covering the side and bottom surfaces of the recess; a field plate extending from the upper electrode to an upper portion of the peripheral region and facing the side surface and the bottom surface of the recessed portion via the insulating layer; and The semiconductor substrate is an n-type high concentration layer distributed across the element region and the peripheral region, in contact with the lower electrode, having a thin plate portion and a thick plate portion, the upper surface of the thick plate portion protruding beyond the upper surface of the thin plate portion, the thick plate portion being disposed within the element region, and the thin plate portion being distributed across the element region and the peripheral region; an n-type drift layer disposed in the element region, in contact with the upper surface of the thick plate portion, and having an n-type impurity concentration lower than that of the high-concentration layer; an n-type low concentration layer that is distributed across the element region and the peripheral region, that is in contact with a side surface of the drift layer, that is in contact with the top surface of the thin plate portion, that is in contact with a side surface of a step portion formed at a boundary between the thick plate portion and the thin plate portion, that is in contact with the insulating layer at the side surface and the bottom surface of the recess, and that has an n-type impurity concentration lower than that of the drift layer; the drift layer is connected to the upper electrode via at least one of a pn junction and a Schottky junction, when the potential of the lower electrode relative to the upper electrode is increased to a potential at which avalanche breakdown occurs in the semiconductor substrate, in a cross section perpendicularly intersecting the step portion, more than half of a rectangular region formed by the side surface of the step portion, an imaginary line obtained by shifting the side surface of the step portion toward the peripheral region by the height of the step portion, the top surface of the thin plate portion, and an imaginary line obtained by shifting the top surface of the thin plate portion upward by the height is not depleted. Semiconductor device.

2. 2. The semiconductor device according to claim 1, wherein when the potential of the lower electrode relative to the upper electrode is increased to a potential at which avalanche breakdown occurs in the semiconductor substrate, a region of the low concentration layer below a straight line extending at an angle of 45 degrees from the upper end of the step portion toward the upper surface of the thin plate portion is not depleted.

3. A semiconductor device, a semiconductor substrate including an element region and a peripheral region disposed around the element region, wherein a recess is provided in the upper surface of the semiconductor substrate so that the upper surface of the semiconductor substrate protrudes in the element region more than in the peripheral region; an upper electrode in contact with the upper surface of the semiconductor substrate within the element region; a lower electrode in contact with a lower surface of the semiconductor substrate in the element region and the peripheral region; an insulating layer covering the side and bottom surfaces of the recess; a field plate extending from the upper electrode to an upper portion of the peripheral region and facing the side surface and the bottom surface of the recessed portion via the insulating layer; and The semiconductor substrate is an n-type high concentration layer distributed across the element region and the peripheral region, in contact with the lower electrode, having a thin plate portion and a thick plate portion, the upper surface of the thick plate portion protruding beyond the upper surface of the thin plate portion, the thick plate portion being disposed within the element region, and the thin plate portion being distributed across the element region and the peripheral region; an n-type drift layer disposed in the element region, in contact with the upper surface of the thick plate portion, and having an n-type impurity concentration lower than that of the high-concentration layer; an n-type low concentration layer that is distributed across the element region and the peripheral region, that is in contact with a side surface of the drift layer, that is in contact with the top surface of the thin plate portion, and that is in contact with the insulating layer at the side surface and the bottom surface of the recess, and that has an n-type impurity concentration lower than that of the drift layer; the drift layer is connected to the upper electrode via at least one of a pn junction and a Schottky junction, a displacement portion is formed at a boundary between the thick plate portion and the thin plate portion, in which an upper surface of the high-concentration layer is gradually displaced downward from the thick plate portion toward the thin plate portion, the low concentration layer is in contact with the upper surface of the high concentration layer within the displacement portion; Semiconductor device.

4. The insulating layer is a first insulating layer in contact with the bottom surface of the recess; a second insulating layer disposed on the first insulating layer and having a dielectric constant different from the dielectric constant of the first insulating layer; and the first insulating layer and the second insulating layer are disposed between the field plate and the bottom surface of the recess. The semiconductor device according to any one of claims 1 to 3.

5. the dielectric constant of the first insulating layer is higher than the dielectric constant of the second insulating layer; The breakdown voltage of the second insulating layer is higher than the breakdown voltage of the first insulating layer. The semiconductor device according to claim 4 .

6. 5. The semiconductor device according to claim 4, wherein the insulating layer between the field plate and the side surface of the recess is formed of a single layer of the first insulating layer or the second insulating layer.

7. 7. The semiconductor device according to claim 6, wherein the insulating layer between the field plate and the side surface of the recess is made of the first insulating layer or the second insulating layer, whichever has a higher dielectric constant.

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