semiconductor memory device

Abstract

A semiconductor memory device is provided that stores data by accumulating majority carriers in the electrically floating body of a MOSFET. [Solution] In a memory device using semiconductor elements, plate lines PLL0 and PLR0, capacitively coupled to the floating bodies of memory cells MCL and MCR, are wired parallel to word lines WLL0 and WLR0, separated for each word line, and majority carrier erase operations are performed simultaneously along the word lines by applying a voltage to the plate lines. In a refresh operation, data along the selected word line is read and latched into a sense amplifier S / A, and then the bit lines BLL and BLR are separated from the sense amplifier to simultaneously erase majority carriers from the floating bodies of cells on the selected word line. Depending on the state of the sense amplifier, majority carriers are then injected into cells that originally had a large number of majority carriers stored. In addition, a write operation simultaneously extracts majority carriers from the selected cells while simultaneously writing data to the sense amplifier from an external source.

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