Systems, methods, devices, and data structures for digital pixel sensors

Abstract

Some embodiments relate to an imaging system including an active pixel and an analog-to-digital conversion (ADC) circuit including a comparator. The comparator may be operably coupled to the active pixel and configured to receive an output of the active pixel. A back-end ADC and memory circuit may be operably coupled to the active pixel. The back-end ADC and memory circuit may include a write control circuit, an ADC memory operably coupled to a read / write data bus and the write control circuit, and a state latch operably coupled to the write control circuit.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application No. 63,029,057, filed May 22, 2020, and entitled "System, Method, Device and Data Structure for Digital Pixel Sensors," the disclosure of which is incorporated herein by reference in its entirety. [Background technology]

[0002] Digital pixel sensors (DPSs) used in image sensing applications are well known. Image sensor systems utilizing complementary metal-oxide semiconductor (CMOS) photodiodes used in active pixel structures with multiple transfer gates in the pixel area are also well known. However, these known DPS systems are unable to achieve full charge transfer from the pixel area when scaling pixel size. The lack of full charge transfer can adversely affect the noise, aperture ratio, lag, and other attributes of the DPS. Summary of the Invention [Problem to be solved by the invention]

[0003] DPS systems including an optical conversion unit and an application specific integrated circuit (ASIC) unit for signal processing are also known. However, because these DPS systems implement flag bits separated from analog-to-digital conversion (ADC) data bits, these DPS systems have a technical problem in that they require the use of a complex readout procedure due to the need for independent readout control signals for the flag bits for write control and readout. Another technical problem that arises in these DPS systems is that the complex readout procedure causes an increase in the number of wires used, which may hinder DPS systems with small pixel sizes. [Means for solving the problem]

[0004] Accordingly, one or more aspects of the present disclosure relate to an image sensor system. The image sensor system includes one or more active pixels each coupled to an analog-to-digital converter (ADC). In some embodiments, the ADC includes a comparator, a memory coupled to a data bus, and a write control circuit. Some aspects relate to a solid-state device for use in a DPS imaging system. In some embodiments, the solid-state device includes at least one pixel area configured for bidirectional charge transfer. The solid-state device includes a first transfer gate and a second transfer gate having a first poly layer and a first charge well layer, and is configured to induce electron drift current from a first side of the pixel area to a second side of the pixel area, thereby providing bidirectional charge transfer based on operation of the first transfer gate and the second transfer gate.

[0005] Another aspect of the present disclosure relates to an apparatus for use in a DPS image sensor comprising a pixel circuit. In some embodiments, the pixel circuit includes at least two transfer gates, a photodiode region, and a floating diffusion region. In some embodiments, the pixel circuit is configured for optimized charge transfer from the photodiode region to the floating diffusion region by induced electric fields of the first and second transfer gates.

[0006] Another aspect of the present disclosure relates to a method for forming a DPS semiconductor device. In some embodiments, the method includes providing a substrate layer and forming a first implantation layer having a first conductivity type on the substrate layer. In some embodiments, the method includes forming a second implantation layer having a second conductivity type over at least a portion of the first layer, and forming at least a first transfer gate and a second transfer gate on the second implantation layer. In some embodiments, operation of the first transfer gate and the second transfer gate causes an electron drift current from the first implantation layer to the second implantation layer. In some embodiments, the electron drift current corresponds to bidirectional charge transfer from the substrate layer to the first implantation layer and from the first implantation layer to the first gate or the second gate.

[0007] Yet another aspect of the present disclosure relates to a DPS device for use in indirect time-of-flight measurements. In some embodiments, the DPS device includes a photodiode, a first floating diffusion, a second floating diffusion, a first transfer gate, and a second transfer gate. In some embodiments, the DPS device is configured to implement a method for determining a physical distance to an object proximate to the DPS device. In some embodiments, the method includes transferring charge collected by the photodiode to the first floating diffusion or the second floating diffusion by switching either the first transfer gate or the second transfer gate, and determining a delay of a received impulse based on the charge in the first floating diffusion or the second floating diffusion. In some embodiments, determining the distance to the physical object is based on the delay.

[0008] Some aspects of the present disclosure relate to a data structure for use in an image sensor system having at least one ADC, a write control circuit, a state latch, and an ADC memory. In some embodiments, the data structure includes a flag bit and an ADC bit. In some embodiments, the flag bit is configured for state control for the at least one ADC that utilizes the write control circuit and the data latch to communicate the data structure.

[0009] These and other objects, features, and characteristics of the present disclosure, as well as the method of operation and function of the related elements of structure, and combination of parts and economies of manufacture, will become more apparent from a consideration of the following description and the appended claims, taken in conjunction with the accompanying drawings. The following description, the appended claims, and the accompanying drawings, all form a part of this specification, and like reference numerals indicate corresponding parts in the various views. It is to be expressly understood, however, that the drawings are for the purpose of illustration and description only and are not intended as a definition of the limits of the disclosure. [Brief explanation of the drawings]

[0010] [Figure 1A] 1 is a schematic representation of an exemplary DPS image sensing system, according to one or more embodiments.

[0011] [Figure 1B] 1 is a schematic representation of another exemplary DPS image sensing system, according to one or more embodiments.

[0012] [Figure 2A] 1 is a schematic representation of an exemplary active pixel according to one or more embodiments. [Figure 2B] 1 is a schematic representation of an exemplary active pixel according to one or more embodiments.

[0013] [Figure 3A]FIG. 3 is a circuit diagram of the example active pixel of FIGS. 2A-2B, according to one or more embodiments. [Figure 3B] FIG. 3 is a circuit diagram of the example active pixel of FIGS. 2A-2B, according to one or more embodiments.

[0014] [Figure 4A] 1 is a schematic representation of an exemplary active pixel according to one or more embodiments. [Figure 4B] 1 is a schematic representation of an exemplary active pixel according to one or more embodiments.

[0015] [Figure 5A] FIG. 4C is a circuit diagram of the example active pixel of FIGS. 4A-4B, according to one or more embodiments. [Figure 5B] FIG. 4C is a circuit diagram of the example active pixel of FIGS. 4A-4B, according to one or more embodiments.

[0016] [Figure 6A] 1 is a schematic representation of an exemplary active pixel according to one or more embodiments. [Figure 6B] 1 is a schematic representation of an exemplary active pixel according to one or more embodiments.

[0017] [Figure 7A] FIG. 6C is a circuit diagram of the example active pixel of FIGS. 6A-6B, according to one or more embodiments. [Figure 7B] FIG. 6C is a circuit diagram of the example active pixel of FIGS. 6A-6B, according to one or more embodiments.

[0018] [Figure 8A] 1 is a schematic representation of a top view of an exemplary active pixel according to one or more embodiments. [Figure 8B] 1 is a schematic representation of a side view of an exemplary active pixel according to one or more embodiments.

[0019] [Figure 9A] 1 is a schematic representation of a top view of an exemplary active pixel according to one or more embodiments. [Figure 9B] 1 is a schematic representation of a side view of an exemplary active pixel according to one or more embodiments.

[0020] [Figure 10A] FIG. 10 is a charge potential diagram illustrating simulation results for an exemplary active pixel, according to one or more embodiments. [Figure 10B] 1 is a schematic representation of a top view of an exemplary active pixel according to one or more embodiments.

[0021] [Figure 11A] 1 is a schematic representation of a top view of an exemplary active pixel according to one or more embodiments. [Figure 11B] 1 is a schematic representation of a top view of an exemplary active pixel according to one or more embodiments. [Figure 11C] 1 is a schematic representation of a side view of an exemplary active pixel according to one or more embodiments.

[0022] [Figure 12A] 1 is a schematic representation of an exemplary non-shared active pixel system according to one or more embodiments. [Figure 12B] 1 is a schematic representation of an exemplary shared active pixel system, according to one or more embodiments.

[0023] [Figure 13] 1 is a schematic representation of an exemplary shared active pixel system, according to one or more embodiments.

[0024] [Figure 14] 14A-14C are exemplary timing diagrams corresponding to the active pixel systems of FIGS. 12A-12B and 13, according to one or more embodiments.

[0025] [Figure 15] 1 is a schematic representation of an exemplary back-end ADC and memory circuit, according to one or more embodiments.

[0026] [Figure 16] 1 is a schematic representation of an exemplary back-end ADC and memory circuit, according to one or more embodiments.

[0027] [Figure 17] FIG. 1 is a timing diagram of an exemplary operation of a back-end ADC and memory circuit in accordance with one or more embodiments.

[0028] [Figure 18A] 1 is a schematic representation of an exemplary data structure according to one or more embodiments. [Figure 18B] 1 is a schematic representation of an exemplary data structure according to one or more embodiments.

[0029] [Figure 18C] 1 is a schematic representation of an exemplary memory array according to one or more embodiments.

[0030] [Figure 19] FIG. 1 is a timing diagram of an exemplary operation of a back-end ADC and memory circuit in accordance with one or more embodiments.

[0031] [Figure 20] 1 is a schematic representation of an exemplary DPS image sensing system, according to one or more embodiments.

[0032] [Figure 21] 1 is a schematic representation of an exemplary system including a read / write control circuit and a data memory, according to one or more embodiments.

[0033] [Figure 22]FIG. 2 is a timing diagram of an example operation of an ADC in accordance with one or more embodiments.

[0034] [Figure 23A] 1 is a schematic representation of an exemplary data structure according to one or more embodiments. [Figure 23B] 1 is a schematic representation of an exemplary data structure according to one or more embodiments. [Figure 23C] 1 is a schematic representation of an exemplary data structure according to one or more embodiments.

[0035] [Figure 24] FIG. 2 is a timing diagram of an example operation of an ADC in accordance with one or more embodiments.

[0036] [Figure 25] 1 is a schematic representation of an exemplary system including a read / write control circuit and a state latch, according to one or more embodiments.

[0037] [Figure 26] 1 is a schematic representation of an exemplary system including a read / write control circuit and a state latch, according to one or more embodiments.

[0038] [Figure 27] FIG. 2 is a timing diagram of an example operation of an ADC in accordance with one or more embodiments.

[0039] [Figure 28A] 1 is a schematic representation of an exemplary data structure according to one or more embodiments. [Figure 28B] 1 is a schematic representation of an exemplary data structure according to one or more embodiments. [Figure 28C] 1 is a schematic representation of an exemplary data structure according to one or more embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0040] The present application will now be described in detail with reference to the drawings, which are provided as illustrative examples of the present invention to enable those skilled in the art to practice the invention. In particular, the following figures and examples are not meant to limit the scope of the present invention to a single embodiment, as other embodiments are possible by exchanging some or all of the elements described or shown.

[0041] Furthermore, where some elements of the present invention can be partially or completely implemented using known components, only those portions of such known components necessary for understanding the present application will be described, and detailed descriptions of other portions of such known components will be omitted so as not to obscure the present invention. As used herein, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. As used herein, a statement that two or more parts or components are "coupled" shall mean that the parts are joined or operate together, either directly or indirectly (i.e., through one or more intermediate parts or components, where a link occurs).

[0042] Unless otherwise specified herein, as would be apparent to one skilled in the art, embodiments described as being implemented in hardware should not be limited thereto and can include embodiments implemented in software or a combination of software and hardware, and vice versa. In the exemplary embodiments described herein, an embodiment showing a singular component should not be considered limiting. Rather, unless expressly stated otherwise herein, other embodiments including multiple of the same component are encompassed, and vice versa. Furthermore, any term in this specification or claims is not intended to have an unusual or special meaning unless expressly stated as such. Furthermore, this application encompasses both presently and future-known equivalents of known components referred to as exemplary herein.

[0043] As used herein, "directly coupled" means that two elements are in direct contact with each other. As used herein, "fixedly coupled" or "fixed" means that two components are joined so that they move as one while maintaining a constant orientation relative to each other. As used herein, "operably coupled" means that two elements are joined in such a way that they function together. It should be understood that two elements being "operably coupled" does not require a direct or permanent connection between them.

[0044] As used herein, the term "integral" means that a component is made as a single piece or unit. That is, a component that includes parts made separately and then joined together as a unit is not an "integral" component or body. As used herein, a statement that two or more parts or components "engage" with each other shall mean that the parts exert a force on each other, either directly or through one or more intermediate parts or components. As used herein, the term "number" shall mean one or an integer greater than one (i.e., plural). For example, but not limited to, directional phrases used herein, such as top, bottom, left, right, upper, lower, front, back, and derivatives thereof, relate to the orientation of the elements as shown in the drawings and are not limitations thereon unless expressly stated in the claims.

[0045] As described in further detail below, the methods, systems, devices, and apparatus of the embodiments described herein may include an active pixel sensor (e.g., a complementary metal-oxide semiconductor (CMOS) sensor) configured for complete charge transfer within a photodiode via the generation of an electric field. As described in further detail below, the generated electric field may be facilitated by the operation of two transfer gates. The operation of the two transfer gates may induce drift currents in two directions, thereby providing complete charge transfer in both directions from the photodiode to the floating diffusion region. Thus, the technical effect of reducing lag may be achieved.

[0046] FIG. 1A is a schematic representation of an exemplary DPS image sensing system 100A according to one or more embodiments. The DPS image sensing system 100A may include a sensing front-end circuit 112 operably coupled to a back-end ADC and memory circuit 115. The back-end ADC and memory circuit may be referred to interchangeably herein as a back-end ADC and memory circuit. In some embodiments, the sensing front-end circuit 112 may be operably coupled to the back-end ADC and memory circuit 115 via a coupling capacitor Cc. In some embodiments, the sensing front-end circuit 112 may include an active pixel 110. As described herein, the term “active pixel” may be referred to interchangeably with the term “pixel device.” In some embodiments, the back-end ADC and memory circuit 115 may include a comparator 120, a write control circuit 130, a state latch 140, one or more instances of ADC memory 150, a coupling capacitor Cc, or other components. As described herein, the terms "pixel sensor," "pixel," "digital pixel," and "pixel portion" refer to one or more instances of one or more photodetectors, photodiodes, photovoltaic devices, solid-state transistor devices, or other image sensing components, and may be used interchangeably herein. Additionally, as described herein, the terms "photodiode" and "photodetector" refer to a two-terminal photovoltaic solid-state semiconductor device having electrical properties that are photosensitive, and may be used interchangeably herein.

[0047] In some embodiments, the DPS image sensing system 100A may be utilized in a 2D array of active pixels, each having dedicated signal processing circuitry (e.g., comparator 120, write control circuit 130, ADC memory 150) coupled to a read / write data bus line 160. A time code may be provided to the read / write data bus line 160 from a time code generator (not shown). The time code is a count value, as will be understood by those skilled in the art. The time code corresponds to an ADC code, which will be described further below. In some embodiments, the 2D array of active pixels with dedicated signal processing circuitry may be packaged as a DPS-on-chip. The DPS-on-chip package may include bonding components, protective glass, and / or other components. For example, the DPS-on-chip package may include contact pads for operably coupling the DPS-on-chip to a printed circuit board (PCB).

[0048] Comparator 120 may include a 1-bit comparator coupled to a latch (e.g., state latch 140). In some embodiments, comparator 120 may provide an ADC function by converting an input voltage (e.g., Vsig) to a corresponding digital value (e.g., the intermediate value of VRAMP shown at inlet 107 in FIG. 1A). In some embodiments, state latch 140 and write control circuit 130 of back-end ADC and memory circuit 115 may communicate with ADC memory 150. In some embodiments, the output of state latch 140 is used to control ADC operation. For example, ADC operation may be controlled using a 1-bit Boolean control signal that may be latched in and output from state latch 140. ADC operation may include one or more different modes. For example, ADC operation may include a timestamp ADC operation, a high conversion gain ADC (HCG ADC), and a low conversion gain ADC (LCG ADC).

[0049] Additional details regarding the state latch 140 and its functionality may be described below with reference to FIG.

[0050] ADC memory 150 may be configured to store data bits corresponding to state data (e.g., STATE_DATA 142) held in state latch 140. In some embodiments, ADC memory 150 may include a Gray code counter. In some embodiments, ADC memory 150 includes flag bits and data bits, which may utilize a DPS data structure, described in more detail below.

[0051] The write control circuit 130 may include a positive feedback circuit 131 and an initialization circuit 132. In some embodiments, the positive feedback circuit 131 is a multi-input logic gate configured to receive the output from the comparator 120 as a first input and the output from the positive feedback circuit 131 as a second input. For example, the logic gate may be a NOR. The positive feedback circuit 131 may also include an inverter configured to receive the output of the logic gate (e.g., a NOR gate) as an input. In some embodiments, the initialization circuit 132 may include a pair of transistors configured to function as a NAND gate. For example, the pair of transistors may be a pair of pMOS transistors, which will be described in more detail with reference to FIG. 15 . In some embodiments, when the signal (FB) from the positive feedback circuit 131 is FB=1, the positive feedback circuit 131 is locked. The initialization circuit 132 may be used to release the positive feedback circuit 131 from being locked using a control signal received from the state latch 140.

[0052] 1B is a schematic representation of another exemplary DPS image sensing system 100B according to one or more embodiments. In some embodiments, active pixels 110 may be formed in a first substrate 111, and elements included in a back-end ADC and memory circuit 115 (e.g., comparator 120, write control circuit 130, state latch 140, ADC memory 150) may be formed in a second substrate 106. The term "active pixel" may be referred to interchangeably herein as a "photoelectric conversion readout unit." The active pixels 110 of the DPS image sensing system 100B may include a photodiode (photoelectric conversion element) and an in-pixel amplifier. More specifically, the active pixels 110 may include, for example, a photodiode PD1, which is a photoelectric conversion element. For the photodiode PD1, one transfer transistor TG1-Tr serving as a transfer element, one reset transistor RST1-Tr serving as a reset element, one source follower transistor SF1-Tr serving as a source follower element, one current transistor IC1-Tr serving as a current source element, one storage transistor CG1-Tr, one storage capacitor CS1 serving as a storage capacitor element, one floating diffusion FD1 serving as an output node ND1, and one readout node ND2 are provided. As described above, the active pixel 110 may include five transistors (5Tr), namely, the transfer transistor TG1-Tr, the reset transistor RST1-Tr, the source follower transistor SF1-Tr, the current transistor IC1-Tr, and the storage transistor CG1-Tr.

[0053] In some embodiments, the source follower transistor SF1-Tr, the current transistor IC1-Tr, and the read node ND2 together constitute the output buffer section 103. In some embodiments, the storage transistor CG1-Tr and the storage capacitor CS1 acting as a storage capacitor element together constitute the charge storage section 102.

[0054] In some embodiments, the readout node ND2 of the output buffer portion 103 of the active pixel 110 is connected to the input portion of the back-end ADC and memory circuit 115. In some embodiments, the active pixel 110 may convert the charge in the floating diffusion FD1, which serves as the output node, into a voltage signal at a level corresponding to the amount of charge and output this voltage signal Vsig to the back-end ADC and memory circuit 115.

[0055] During the first comparison operation period of the back-end ADC and memory circuit 115, the active pixel 110 can output a voltage signal Vsig corresponding to the overflow charge that has overflowed from the photodiode PD1, which is a photoelectric conversion element, to the floating diffusion FD1, which acts as an output node, during the accumulation period.

[0056] In some embodiments, the active pixel 110 may output a voltage signal Vsig corresponding to the charge accumulated in the photodiode PD1 transferred to the floating diffusion FD1, which serves as an output node, during a transfer period following the accumulation period, during a second comparison operation period of the back-end ADC and memory circuit 115. The active pixel 110 may output a readout reset signal (signal voltage) and a readout signal (signal voltage) as pixel signals to the back-end ADC and memory circuit 115 during the second comparison operation period.

[0057] Moreover, the active pixel 110 may output a voltage signal Vsig corresponding to the sum of the charge accumulated in the charge storage unit 102 during the transfer period following the accumulation period and the charge accumulated in the photodiode PD1 transferred to the floating diffusion FD1 serving as the output node during the third comparison operation period of the back-end ADC and memory circuit 115. During the third comparison operation period, the active pixel 110 may output a readout reset signal (signal voltage) and a readout signal (signal voltage) as a pixel signal to the back-end ADC and memory circuit 115.

[0058] In some embodiments, the active pixel 110 may perform a first conversion gain reset read operation within a first reset period to read out from the output buffer unit 103 a first readout reset signal obtained by conversion with a first conversion gain (e.g., high conversion gain: HCG) determined by a first amount of charge in the floating diffusion FD1 that is the output node ND1. The active pixel 110 may perform a first conversion gain signal read operation within a readout period following a transfer period after the first reset period to read out from the output buffer unit 103 a first readout signal obtained by conversion with a first conversion gain (HCG) determined by a first amount of charge in the floating diffusion FD1 that is the output node ND1.

[0059] Thereafter, the active pixel 110 may perform a second conversion gain signal read operation to read out from the output buffer unit 103 a second read signal obtained by conversion with a second conversion gain (e.g., low conversion gain: LCG) determined by a second amount of charge equal to the sum of the charge in the storage capacitor CS1 and the charge in the floating diffusion FD1 at the output node ND1. Thereafter, the active pixel 110 may perform a second conversion gain reset read operation within a second reset period to read out from the output buffer unit 103 a second read reset signal obtained by conversion with a second conversion gain (LCG) determined by the second amount of charge.

[0060] As described above, in some embodiments, the DPS image sensing system 100B, which may be a solid-state imaging device, may operate in a timestamp (TS) mode during a first comparison operation period of the back-end ADC and memory circuit 115, in an HCG (first conversion gain) mode during a second comparison operation period, and in an LCG (second conversion gain) mode during a third comparison operation period.

[0061] Photodiode PD1 may generate and store signal charge (electrons) in an amount determined by the amount of incident light. A description is given below of the case where the signal charge is electrons and each transistor may be an n-type transistor. However, it is also possible that the signal charge can be holes or that each transistor can be a p-type transistor. Furthermore, in some embodiments, multiple photodiodes and transfer transistors may share a transistor.

[0062] In some embodiments, the photodiode (PD) in each active pixel 110 may be a buried photodiode (PPD). The surface of the substrate for forming the photodiode (PD) may have surface states due to dangling bonds or other defects, which may cause a large amount of charge (dark current) to be generated by thermal energy, resulting in an inaccurate signal readout. In a buried photodiode (PPD), the surface of the charge storage portion of the photodiode (PD) may be buried to reduce the mixing of dark current into the signal.

[0063] The transfer transistor TG1-Tr of the active pixel 110 is connected between the photodiode PD1 and the floating diffusion FD1 and can be controlled by a control signal TG applied to its gate via a control line. The transfer transistor TG1-Tr can be selected and remain in a conductive state during a transfer period when the control signal TG is high (H) to transfer charge (electrons) generated by photoelectric conversion and then accumulated in the photodiode PD1 to the floating diffusion FD1. After the photodiode PD1 and the floating diffusion FD1 are reset to a predetermined reset potential, the transfer transistor TG1-Tr can enter a non-conductive state when the control signal TG is set to low (L), and the photodiode PD1 enters an accumulation period. Under these circumstances, if the intensity of incident light is very high (e.g., the amount of incident light is very large), overflow charge can pass under the transfer transistor TG1-Tr, causing charge exceeding the saturation charge amount to overflow into the floating diffusion FD1. When the incident light has a very high illuminance, for example, the charge exceeding the saturation charge amount in the floating diffusion FD1 may overflow into the storage capacitor CS1 as the overflow charge passes under the storage transistor CG1-Tr.

[0064] The reset transistor RST1-Tr may be connected between a power supply line Vaapix of the power supply voltage VAAPIX and the floating diffusion FD1, and may be controlled by a control signal RST applied to its gate through a control line. The reset transistor RST1-Tr may be selected and remain in a conductive state during a reset period when the control signal RST is at an H level, in order to reset the floating diffusion FD1 to the potential of the power supply line Vaapix of the power supply voltage VAAPIX.

[0065] The storage transistor CG1-Tr may be connected between the floating diffusion FD1 and the reset transistor RST1-Tr, and the storage capacitor CS1 may be connected between (i) a connection node ND3 between the floating diffusion FD1 and the reset transistor RST1-Tr and (ii) a reference potential VSS. The storage transistor CG1-Tr may be controlled by a control signal DCG applied to its gate through a control line. The storage transistor CG1-Tr may be selected and remain in a conductive state during a reset period when the control signal DCG is at an H level to connect the floating diffusion FD1 and the storage capacitor CS1. Here, the DPS image sensing system 100B may be configured so that the active pixel 110 can selectively connect (couple) the floating diffusion FD1, which serves as an output node, to the storage capacitor CS1 in response to the illuminance of a signal.

[0066] The source follower transistor SF1-Tr, which functions as a source follower element, may have its source connected to the read node ND2, its drain connected to a power supply line Vaapix, and its gate connected to the floating diffusion FD1. The drain and source of the current transistor IC1-Tr, which functions as a current source element, may be connected between the read node ND2 and a reference potential VSS (e.g., GND). The gate of the current transistor IC1-Tr may be connected to a supply line of a control signal VBNPIX. The signal line LSGN1 between the read node ND2 and the input of the back-end ADC and memory circuit 115 may be driven by the source follower transistor SF1-Tr and / or the current transistor IC1-Tr, which functions as a current source element.

[0067] 2A-2B are schematic representations of exemplary active pixels 210 and 260, respectively, according to one or more embodiments. FIG. 2A shows a schematic representation of a top view 200 of active pixel 210. FIG. 2B shows a schematic representation of a top view 250 of active pixel 260. In some embodiments, active pixel 210 may be the same as or similar to active pixel 110 of FIG. 1A. Alternatively, active pixel 210 may be the same as or similar to active pixel 110 of FIG. 1B with appropriate modifications, such as the inclusion of a single transfer gate rather than two transfer gates. In some embodiments, active pixel 210 corresponds to a non-shared floating diffusion structure including a bidirectional charge-transfer photodiode (PD) 212. In some embodiments, active pixel 210 implements a back-illuminated recessed photodiode. The phrase "non-shared" refers to floating diffusion nodes 224 and 226 being configured to receive charge transferred from a single instance of PD 212. In some embodiments, the DPS image sensing system 100A of FIG. 1A or the DPS image sensing system 100B of FIG. 1B may process signals from a shared floating diffusion node, which is discussed in further detail below.

[0068] The active pixel 210 may include a PD 212 operably coupled to transfer gates 214 and 216, which may be referred to interchangeably herein as TDs 214 and 216. In some embodiments, the transfer gates 214 and 216 are asymmetrically located on opposite sides of the PD 212. For example, the transfer gate 214 may be located in the upper right corner of the PD 212, and the transfer gate 216 may be located in the lower right corner of the PD 212. The transfer gates 214 and 216 may include floating diffusion nodes 224 and 226, respectively. In some embodiments, the transfer gates 214 and 216 may include active layers intersecting poly and charge well layers configured as floating diffusion layers. FIG. 2B is an exemplary diagram of an active pixel 260, which is similar to the active pixel 210 of FIG. 2A, except that the transfer gate 216 outputs charge to the drain 227 rather than the floating diffusion node 226.

[0069] In some embodiments, the transfer gates 214 and 216 can facilitate full-pixel charge transfer within the PD 212 by generating an electron drift current. An electron flow 219 corresponding to the electron drift current is shown in FIGS. 2A and 2B . The electron flow 219 can be directed from a first side 218 of the PD 212 to a second side 220 of the PD 212 region (e.g., from point X to point X′). In that case, the drift current can be directed from the second side 220 of the PD 212 to the first side 218 of the PD 212 region (e.g., from point X′ to point X). The electron drift current can be caused by an electric field. An electric field applied to the active pixel 210 causes electrons in the PD 212 to move in a particular direction based on the applied electric field. In some embodiments, the electric field is generated by an impurity concentration gradient in the PD 212, which will be discussed in more detail below. Also, by forming an electric field within PD 212 (e.g., via implementing an impurity concentration gradient in PD 212) and by operation of two (2) transfer gates (e.g., transfer gates 214 and 216), bidirectional charge transfer of electrons in PD 212 can be achieved. As described herein, "bidirectional charge transfer" refers to the number of charge transfer directions being two (2). The bidirectional charge transfer function can be used for various applications along with the full in-pixel charge transfer function of active pixel 210. Some examples of applications in which the bidirectional charge transfer function and the full in-pixel charge transfer function can be implemented include, but are not limited to (this list is not intended to imply that the other lists are limiting), high dynamic range readout and Time of Flight (ToF) readout, which are described in further detail below.

[0070] In some embodiments, the transfer gates 214 and 216 may be configured to generate an electron flow 219 corresponding to the electron drift current in a direction from the first side 218 of the PD 212 to the second side 220 of the PD 212 (e.g., from point X to point X′). Thus, the electron flow 219 may cause a bidirectional charge transfer 221. In some embodiments, the electron drift current, such as the electron drift current corresponding to the electron flow 219 formed by applying an electric field to the active pixel 210, can increase the conductivity in the region surrounding the first side 218 of the PD 212 and the region surrounding the second side 220 of the PD 212. For example, the increased conductivity may induce a charge transfer of charge particles (e.g., electrons) from point X on the first side 218 of the PD 212 to point X′ on the second side 220 of the PD 212. The electric field that generates the electron flow 219 may attract electrons from the second side 220 of the PD 212. When the operation of transfer gates 214 and 216 modulates the electric field near transfer gates 214 and 216, electrons may transfer from transfer gates 214 and 216 to floating diffusion node 224 or floating diffusion node 226, respectively. However, within active pixel 260, electrons may transfer from transfer gates 214 and 216 to floating diffusion node 224 or drain 227, respectively.

[0071] 3A-3B are circuit diagrams of the exemplary active pixel of FIGS. 2A-2B in accordance with one or more embodiments. FIG. 3A includes active pixel 310, which may be the same as or similar to active pixel 210 of FIG. 2A. FIG. 3B includes active pixel 360, which may be the same as or similar to active pixel 260 of FIG. 2B. Active pixel 210 may include PD 212 operably coupled to floating diffusion nodes 224 and 226. FIG. 3B differs from FIG. 3A in that transfer gate 216 is operably coupled to drain 227. In some embodiments, PD 212 utilizes a back-side illuminated (BSI) embedded photodiode or a front-side illuminated (FSI) embedded photodiode.

[0072] In some embodiments, charge collected by PD 212 is transferred to floating diffusion node 224. The voltage potential of floating diffusion node 224 may be monitored by source follower (SF) 225 of active pixel 310. Floating diffusion nodes 224 and 226 may be reset or filled by a transistor reset signal (RST) or a filling transistor (BIN) before charge transfer (e.g., charge is transferred from a region of active pixel 310 or 360 to transfer gates 214 and 216 and then to floating diffusion nodes 224 and 226, respectively, or from transfer gate 214 to floating diffusion node 224 and from transfer gate 216 to drain 227). In some embodiments, pixel filling of active pixel 310 or 360 may be performed by BIN as part of a clocking scheme used to combine charges collected by several adjacent pixels. This may have the technical effect of reducing noise and improving the signal-to-noise ratio and frame rate of DPS image sensing system 100A or DPS image sensing system 100B. In some embodiments, a row select transistor (SEL) 229 may be included within active pixels 310 and 360. Row select transistor 229 may be operably coupled to source follower 225 using a read / write data bus line via Vsig.

[0073] FIGS. 4A-4B are schematic representations of exemplary active pixels 410 and 460, respectively, according to one or more embodiments. FIGS. 5A-5B are exemplary circuit diagrams of the active pixels 410 and 460 of FIGS. 4A-4B, respectively. Specifically, FIG. 4A is a top view 400 of an example active pixel 410. In some embodiments, the active pixel 410 may be included in the DPS image sensing system 100A of FIG. 1A (e.g., used to replace or in addition to the active pixel 110). Alternatively, with appropriate modifications, such as including a single transfer gate rather than two transfer gates, the active pixel 410 may be the same as or similar to the active pixel 110 of FIG. 1B. FIG. 4B includes a top view 450 of an example active pixel 460, which may alternatively or additionally be utilized as the active pixel (e.g., the active pixel 110) in the DPS image sensing system 100A or 100B of FIG. 1A or 1B, respectively.

[0074] In some embodiments, active pixel 410 may include two (2) photodiodes (PDs) 412A and 412B. PD 412A may be operably coupled to transfer gates 414A and 416A, and PD 412B may be operably coupled to transfer gates 414B and 416B. Transfer gates 414A and 416A may be asymmetrically located on either side of PD 412A, and transfer gates 414B and 416B may be asymmetrically located on either side of PD 412B. In some embodiments, transfer gates 414A, 414B, 416A, and 416B include active layers intersecting poly and charge well layers configured as floating diffusion layers. Transfer gates 414A and 416A may include floating diffusion nodes 424 and 426, respectively. Transfer gates 414B and 416B also include floating diffusion nodes 424 and 426, respectively. Thus, floating diffusion node 424 may be “shared” by transfer gates 414A and 414B, and floating diffusion node 426 may be “shared” by transfer gates 416A and 416B. Transfer gates 414A, 414B, 416A, and 416B may provide charge transfer to floating diffusion nodes 424 and 426. FIG. 4B is an exemplary diagram of active pixel 460, which is similar to active pixel 410 of FIG. 4A, except that transfer gates 416A and 416B output charge to drain 427 rather than to a floating diffusion node (e.g., floating diffusion node 426).

[0075] In some embodiments, the active pixels 410 and 460 can perform bidirectional charge transfer and full-pixel charge transfer within the PDs 412A and 412B by generating or applying an electric field to the PDs 412A and 412B. The application of the electric field can cause an electron drift current to be generated within the PDs 412A and 412B, respectively. FIGS. 4A and 4B show an electron flow 419A corresponding to the electron drift current generated within the PDs 412A and 412B, respectively. For example, the electron flow 419A can be generated within the PDs 412A in response to the application of an electric field to the PDs 412A. The electron flow 419A can be directed from a first side 418A of the PDs 412A to a second side 420A of the PDs 412A (e.g., from point XA to point X1). Similarly, electron flow 419B may be generated within PD 412B in response to application of an electric field to PD 412B. Electron flow 419B may be directed from a first side 418B of PD 412B to a second side 420B of PD 412B (e.g., from point XB to point X2). In some embodiments, the same electric field may be applied to both PD 412A and 412B, while in other embodiments, different electric fields may be applied to PD 412A and 412B. The applied electric field may generate electron flows 419A and 419B, where electron flows 419A and 419B have different directions. For example, electron drift currents corresponding to electron flows 419A and 419B may have equal magnitudes but opposite directions. Electron flow 419A and 419B can be caused by an electric field applied to active pixel 410 (or active pixel 460), which causes electrons in PD 412A and PD 412B to move in a particular direction based on the applied electric field. In some embodiments, the electric field is generated by an impurity concentration gradient in PD 412A and PD 412B, which will be discussed in more detail below.Also, by forming an electric field within PD 412A and PD 412B (e.g., via implementing an impurity concentration gradient in PD 412) and by operation of two (2) transfer gates (e.g., transfer gates 414A and 416A, and transfer gates 414B and 416B), bidirectional charge transfer of electrons to each of PD 412A and 412B can be achieved. The bidirectional charge transfer function can be used for a variety of applications along with the full in-pixel charge transfer function of active pixels 410 and 460. Some examples of applications in which the bidirectional charge transfer function and the full in-pixel charge transfer function can be implemented include, but are not limited to (this list is not intended to imply that the other lists are limiting), high dynamic range readout and Time of Flight (ToF) readout, which are described in further detail below.

[0076] In some embodiments, electron flow 419A and electron flow 419B can cause bidirectional charge transfer 421A and 421B, respectively. In some embodiments, electron flow, such as electron flow 419A and 419B, formed by applying an electric field to active pixel 410 or active pixel 460 can increase the conductivity in the region surrounding the first side 418A of PD 412A and the region surrounding the second side 420A of PD 412A, as well as in the region surrounding the first side 418B of PD 412B and the region surrounding the second side 420B of PD 412B. For example, the increased conductivity can induce a charge transfer of charged particles (e.g., electrons) from point XA on the first side 418A of PD 412A to point X1 on the second side 420A of PD 412A (and similarly with respect to PD 412B). The electric field causes the generation of electron currents 419A and 419B, which may attract electrons from the second side 420A of PD 412A and the second side 420B of PD 412B, respectively. When operation of transfer gates 414A, 414B, 416A, and 416B modulates the electric field near transfer gates 414A, 414B, 416A, and 416B, electrons may transfer from transfer gates 414A and 414B to floating diffusion node 424, and electrons may transfer from transfer gates 416A and 416B to floating diffusion node 426. However, within active pixel 460, electrons may transfer from transfer gates 414A and 414B to floating diffusion node 424 and from transfer gates 416A and 416B to drain 427.

[0077] 5A-5B are circuit diagrams of active pixels 410 and 460 of FIGS. 4A-4B according to one or more embodiments. FIG. 5A includes active pixel 510, which may be the same as or similar to active pixel 410 of FIG. 4A. FIG. 5B includes active pixel 560, which may be the same as or similar to active pixel 460 of FIG. 4B. Active pixel 510 may include PDs 412A and 412B operably coupled to floating diffusion nodes 424 and 426. FIG. 5B differs from FIG. 5A in that transfer gates 416A and 416B are operably coupled to drain 427. In some embodiments, PDs 412A and 412B utilize backside illuminated (BSI) or frontside illuminated (FSI) embedded photodiodes.

[0078] In some embodiments, charge collected by PD 412A and / or 412B is transferred to floating diffusion nodes 424 and 426. The voltage potentials of the floating diffusion nodes 424 and 426 may be monitored by a source follower (SF) 425 of the active pixel 510. The floating diffusion nodes 424 and 426 may be reset or buried by a transistor reset signal (RST) or a buried transistor (BIN) before the charge transfer (e.g., charge is transferred from the region of PD 412A or PD 412B, respectively, to transfer gates 414A, 414B, 416A, and 416B, and then to the floating diffusion nodes 424 and 426). 5B , charge may be transferred from the region of PD 412A or 412B to transfer gates 414A and 414B, then to floating diffusion node 424, and from transfer gates 416A and 416B to drain 427. In some embodiments, pixel padding of active pixel 510 or 560 may be performed by a BIN as part of a clocking scheme used to combine charge collected by several adjacent pixels. This may have the technical effect of reducing noise and improving the signal-to-noise ratio and frame rate of DPS image sensing system 100A or DPS image sensing system 100B (e.g., when active pixel 510 or 560 is used in DPS image sensing system 100A or 100B).

[0079] In some embodiments, a row select transistor (SEL) 429 may be included in the active pixels 510 and 560. The row select transistor 429 may be operably coupled to the source follower 425 using the read / write data bus lines via Vsig.

[0080] 6A-6B are schematic representations of exemplary active pixels 610 and 660 according to one or more embodiments. FIGS. 7A-7B are circuit diagrams of the exemplary active pixels of FIGS. 6A-6B according to one or more embodiments. As shown in FIGS. 6A-6B, active pixels 610 and 660 include four (4) PD / FD-shared structures that implement full bidirectional charge transfer of the photodiodes, which is similar or identical to the bidirectional charge transfer and drift current generation of active pixels 210, 260, 410, and 460 discussed above. In some embodiments, active pixel 610 of FIG. 6A may be included in DPS image sensing system 100A of FIG. 1A (e.g., used to replace or in addition to active pixel 110). Alternatively, active pixel 610 may be the same as or similar to active pixel 110 of FIG. 1B with appropriate modifications, such as including a single transfer gate instead of two transfer gates. Active pixel 660 of FIG. 6B may alternatively or additionally be utilized as an active pixel (eg, active pixel 110) in DPS image sensing system 100B of FIG. 1B.

[0081] In some embodiments, active pixel 610 may include four (2) photodiodes (PDs) 612A-612D. For simplicity, only a single instance of active pixel 610 is included in FIG. 6A , but additional instances of active pixel 610 may be operably coupled to each other. In some embodiments, PD 612A may be operably coupled to transfer gates 614A and 616A, PD 612B may be operably coupled to transfer gates 614B and 616B, PD 612C may be operably coupled to transfer gates 614C and 616C, and PD 612D may be operably coupled to transfer gates 614D and 616D. Transfer gates 614A and 616A may be asymmetrically located on either side of PD 612A, transfer gates 614B and 616B may be asymmetrically located on either side of PD 612B, transfer gates 614C and 616C may be asymmetrically located on either side of PD 612C, and transfer gates 614D and 616D may be asymmetrically located on either side of PD 612D. In some embodiments, transfer gates 614A-D and transfer gates 616A-D may each include active layers intersecting poly layers and charge well layers configured as floating diffusion layers.

[0082] 6B , transfer gates 614A and 616A of PD 612A and transfer gates 614C and 616C of PD 612C may include floating diffusion nodes 624 and 626, respectively, and transfer gates 614B and 616B of PD 612B and transfer gates 614D and 616D of PD 612D may include floating diffusion nodes 626 and 628, respectively. Thus, floating diffusion node 624 may be “shared” by transfer gates 614A and 614C, floating diffusion node 626 may be “shared” by transfer gates 616A and 616C and transfer gates 614B and 614D, and floating diffusion node 628 may be shared by transfer gates 616B and 616D. Transfer gates 614A-614D and 616A-616D can provide charge transfer to floating diffusion nodes 624, 626, and 628. Figure 6A is an example diagram of active pixel 610, which is similar to active pixel 660 of Figure 6B, except that transfer gates 614A-614D output charge to drain 627 rather than to a floating diffusion node (e.g., floating diffusion node 624).

[0083] In some embodiments, active pixels 610 and 660 can implement bidirectional charge transfer and full-pixel charge transfer within PDs 612A-612D by generating or applying an electric field to PDs 612A-612D. The application of an electric field can cause electron drift currents to be generated within PDs 612A-612D, respectively. Electron currents 619A, 619B, 619C, and 619D corresponding to the electron drift currents generated within PDs 612A, 612B, 612C, and 612D are shown in FIGS. 6A and 6B. For example, electron current 619A can be generated within PD 612A in response to the application of an electric field to PD 612A. Electron current 619A can be directed from a first side of PD 612A to a second side of PD 612A, which can have a similar effect on each of PDs 612B-612D. In some embodiments, the same electric field may be applied to each of the PDs 612A-612D, while in other embodiments, different electric fields may be applied to the PDs 612A-612D. For example, the electric field applied to the PD 612A may be different from the electric field applied to the PD 612C. The applied electric field may generate electron flows 619A and 619B, which differ in directionality from the electron flows 619C and 619D. For example, the electron flows 619A and 619C may have equal magnitudes but opposite directions. The electron flows 619A-619D may be caused by an electric field applied to the active pixel 610 (or the active pixel 660), which causes electrons in the PDs 612A-612D to move in a particular direction based on the applied electric field. In some embodiments, the electric field is generated by an impurity concentration gradient in the PDs 612A-612D, which will be discussed in further detail below. Additionally, by forming an electric field within PDs 612A-612D (e.g., through the implementation of an impurity concentration gradient in PDs 612A-612D) and by the operation of two (2) transfer gates (e.g., transfer gates 614A, 616A; transfer gates 614B, 616B; transfer gates 614C, 616C; and transfer gates 614D, 616D), bidirectional charge transfer of electrons to each of PDs 612A-612D can be achieved.The bidirectional charge transfer functionality can be used for a variety of applications, along with the full in-pixel charge transfer functionality of active pixels 610 and 660. Some examples of applications in which the bidirectional charge transfer functionality and the full in-pixel charge transfer functionality can be implemented include, but are not limited to (and this is not to imply that the other lists are limiting), high dynamic range readout and Time of Flight (ToF) readout, which are described in more detail below.

[0084] In some embodiments, electron flows 619A-619D can cause bidirectional charge transfer 621A-621D, respectively. In some embodiments, electron drift currents, such as electron flows 619A-619D, formed by applying an electric field to active pixel 610 or active pixel 660 can increase the conductivity in the region surrounding the first side of each of PDs 612A-612D and the region surrounding the second side of each of PDs 612A-612D, as well as in the region surrounding the first side of each of PDs 612A-612D and the region surrounding the second side of each of PDs 612A-612D. For example, the increased conductivity can induce charge transfer of charged particles (e.g., electrons) from one side of PD 612A to another side of PD 612A. The electric field causes the generation of electron currents 619A-619D, which may attract electrons from the second side of each of PDs 612A-612D. When operation of transfer gates 614A-614D and 616A-616D modulates the electric field near transfer gates 614A-614D and 616A-616D, electrons may transfer from transfer gates 614A and 614C to floating diffusion node 624, electrons may transfer from transfer gates 616A, 616C, 614B, and 614D to floating diffusion node 626, and electrons may transfer from transfer gates 616B and 616D to floating diffusion node 628. However, within active pixel 610, electrons may transfer from transfer gates 614A, 614C, 616A, 616C, 614B, and 614D to drain 627.

[0085] In some embodiments, PDs 612A-612D correspond to a single active pixel (e.g., active pixel 610). As shown in Figures 6A-6B, each PD 610A-D transfers charge to at least one shared floating diffusion node (e.g., FD 624). In some embodiments, active pixel 610 and / or active pixel 660 may be operatively coupled to multiple adjacent active pixels, which may be the same as or similar to active pixel 610 and / or 660, to form a pixel array.

[0086] 7A-7B are circuit diagrams of active pixels 610 and 660 of FIGS. 6A-6B according to one or more embodiments. FIG. 7A includes active pixel 710, which may be the same as or similar to active pixel 610 of FIG. 6A. FIG. 7B includes active pixel 760, which may be the same as or similar to active pixel 660 of FIG. 6B. Active pixel 760 may include PDs 612A-612D operably coupled to floating diffusion nodes 624 and 626. FIG. 7A differs from FIG. 7B in that transfer gates 616A-616D are operably coupled to drain 627. In some embodiments, PDs 612A-612D utilize back-side illuminated (BSI) or front-side illuminated (FSI) embedded photodiodes.

[0087] In some embodiments, charge collected by PDs 612A-612D is transferred to floating diffusion nodes 624 and 626. The voltage potentials of floating diffusion nodes 624 and 626 may be monitored by source followers (SFs) 625 of active pixel 710 and active pixel 760. Floating diffusion nodes 624 and 626 may be reset or buried by a transistor reset signal (RST) or a buried transistor (BIN) prior to charge transfer (e.g., charge is transferred from the region of PD 612A to transfer gates 614A and 616A and then to floating diffusion nodes 624 and 626, respectively). Alternatively, as shown in FIG. 7A , charge may be transferred from the region of PDs 612A-612D to transfer gates 616A-616D to drain 627. In some embodiments, pixel padding of active pixel 710 or 760 may be implemented by a BIN as part of a clocking scheme used to combine charge collected by several adjacent pixels, which may have the technical effect of reducing noise and improving the signal-to-noise ratio and frame rate of DPS image sensing system 100A or DPS image sensing system 100B (e.g., when active pixel 710 or 760 is used within DPS image sensing system 100A or DPS image sensing system 100B).

[0088] In some embodiments, a row select transistor (SEL) 629 may be included in the active pixels 710 and 760. The row select transistor 629 may be operably coupled to the source follower 625 using the read / write data bus lines via Vsig.

[0089] 8A-8B are schematic representations of a top view 800 and a side view 850 of an exemplary active pixel 810, according to one or more embodiments. Specifically, the side view 850 of FIG. 8B includes a semiconductor substrate 813 of the active pixel 810. In some embodiments, the active pixel 810 may be the same as or similar to the active pixel 210 or 260 of FIGS. 2A and 2B. In some embodiments, the semiconductor substrate 813 may include a varying gradient of impurity concentrations.

[0090] The active pixel 810 may include a semiconductor substrate 813. The semiconductor substrate 813 may utilize staggered implant concentrations for each iteration of the n-layer implant region of the photodiode (PD) 812. In this manner, facilitating full in-pixel charge transfer to the transfer gates 814 and 816 and to the floating diffusion node or drain may be achieved. In some embodiments, as shown in FIG. 8B , the implant concentration for each n-layer of the semiconductor substrate 813 may be increased compared to the previous layer. This may increase the conductivity of each additional layer of the n-layer of the semiconductor substrate 813, which may have the technical effect of providing full in-pixel charge transfer from the PD 812 by operation of the transfer gates 814 and 816.

[0091] In some embodiments, semiconductor substrate 813 includes substrate base 811, N1 layer 818, and N1+N2 layer 820. Layers 818 and 820 may include photovoltaic materials configured to convert incident light into electric charges, as known in the art. For example, N1 layer 818 and N1+N2 layer 820 may include materials such as silicon, gallium, arsenide, or other materials. PD 812 includes a first electron transfer region (e.g., N1 layer 818) having an N1 implant concentration and a second charge transfer region (e.g., N1+N2 layer 820) having an N1+N2 implant concentration. As described herein, implant concentration refers to the amount and type of dopant utilized in the substrate.

[0092] In some embodiments, the implantation concentration gradient may refer to different dopant materials and different doping concentrations. For example, N1 layer 818 may include N-type dopants such as P, As, and / or Sb due to their low ionization energy at appropriate concentrations. In some embodiments, N2 may include a higher concentration of the same dopant used in N1. In some embodiments, N2 may be the same concentration of a different dopant. For example, N1 may be doped with a first dopant at a first concentration, and N2 may include a second dopant having the same concentration as the first dopant. In some embodiments, N1 may correspond to a concentration of approximately 1×10 16 - 17 per cm 3 As for Si, and N2 may correspond to a concentration of approximately 1×10 16 - 17 per cm 3 As for Si. Approximately means that the difference is negligible. In some embodiments, N1 may have a concentration of 2.5-3.5×10 17 [per cm 3 ] As relative to Si, and N2 may correspond to a concentration of about 0.5-1.5×10 17 [per cm 3 ] As relative to Si.

[0093] In some embodiments, the active pixel 810 may use front-of-the-line (FEOL) processing to form transistors directly on the semiconductor substrate 813. The semiconductor substrate 813 may include a wafer fabricated by growing pure silicon layers, for example, using an epitaxy process. In some embodiments, silicon variants may be deposited in one or more layers (e.g., N1 layer 818, N1+N2 layer 820) of the active pixel 810. In some embodiments, prior to epitaxy, further processing may be performed to increase the performance of the transistors that will be utilized on the semiconductor substrate 813.

[0094] In some embodiments, the FEOL process may include a straining step, whereby a silicon variant is deposited within the semiconductor substrate 813 to improve the electron mobility of the substrate base 811. In some embodiments, the impurity concentration and / or material may be modified for further improvement of electron mobility. In some embodiments, the FEOL process may include the growth of a gate dielectric (e.g., the transfer gates 214 and 216 of FIGS. 2A and 2B). For example, this may include patterning the gate, patterning the source and drain regions, and subsequent dopant application or diffusion to obtain desired complementary electrical properties. For example, in some embodiments, N-type dopants such as P, As, and / or Sb are utilized due to their low ionization energy (20-300 keV), low diffusivity, and suitable solid solubility in Si.

[0095] 9A-9B are schematic representations of a top view 900 and a side view 950 of an exemplary active pixel 910 according to one or more embodiments. In some embodiments, the active pixel 910 may be configured for use in DPS image sensing system 100A or, with appropriate modifications, for use in DPS image sensing system 100B. In some embodiments, the active pixel 910 is an exemplary embodiment of the active pixel 210 of FIGS. 2A and 2B. As described in further detail below, the active pixel 910 may be formed using a method of fabrication that implements concentration gradients and repetitive n-implantation layer methods to create various impurity concentration grading effects within various layers of the photodiode (PD) 912 of the active pixel 910.

[0096] In some embodiments, the various impurity concentration grading features of the active pixel 910 result in increased charge conductivity within the PD 912. Operation of the transfer gates 914 and 916 can generate an electric field that induces an electron drift current from a first side of the PD 912 to a second side of the PD 912. For example, the electron drift current may be directed from point X to point X'. The inclusion of two (2) transfer gates 914 and 916 provides an electric field that causes a full in-pixel charge transfer of electrons from the N1 layer 918 to the N1+N2 layer 920 and then to the floating diffusion node or drain.

[0097] The active pixel 910 may include a semiconductor substrate 913. The semiconductor substrate 913 may utilize staggered implant concentrations for each iteration of the n-layer implant region of the PD 912. In this manner, facilitating full in-pixel charge transfer to the transfer gates 914 and 916 and to the floating diffusion node or drain may be achieved. In some embodiments, as shown in FIG. 9B , the implant concentration for each n-layer of the semiconductor substrate 913 may be increased compared to the previous layer. This may increase the conductivity of each additional layer of the n-layer of the semiconductor substrate 913, which may have the technical effect of providing full in-pixel charge transfer from the PD 912 by operation of the transfer gates 914 and 916.

[0098] In some embodiments, semiconductor substrate 913 includes a substrate base 911, an N1 layer 918, and an N1+N2 layer 920. Layers 918 and 920 may include photovoltaic materials configured to convert incident light into electric charges, as known in the art. For example, N1 layer 918 and N1+N2 layer 920 may include materials such as silicon, gallium, arsenide, or other materials. PD 912 includes a first electron transfer region (e.g., N1 layer 918) having an N1 implant concentration and a second charge transfer region (e.g., N1+N2 layer 920) having an N1+N2 implant concentration. As described herein, implant concentration refers to the amount and type of dopant utilized in the substrate.

[0099] 9A and 9B may differ from PD 812 of FIGS. 8A and 8B in that the pattern used to distinguish N1 layer 918 from N1+N2 layer 920 is different compared to N1 layer 818 and N1+N2 layer 820. For example, N1 layer 818 and N1+N2 layer 820 may encompass rectangular shapes when viewed from the top view 800, but N1 layer 918 may increase in size approximately linearly across the axis from point X to point X'. Similarly, N1+N2 layer 920 may decrease in size approximately linearly across the axis from point X' to point X when viewed from the top view 900. In some embodiments, N1+N2 layer 920 may be present on a portion of N1 layer 918 that may extend beyond the surface of substrate base 911 of semiconductor substrate 913.

[0100] 9A and 9B may be the same as or similar to the material composition and configuration of PD812 in FIGS. 8A and 8B. For example, N1 layer 918 may also include ArGe doped with aluminum, and N2 may include a higher concentration of the same dopant used in N1. As another example, N2 may be the same concentration of a different dopant.

[0101] In some embodiments, the active pixel 910 may use a front-end-of-line (FEOL) process to form transistors directly on the semiconductor substrate 913. The semiconductor substrate 913 may include a wafer fabricated by growing pure silicon layers, for example, using an epitaxy process. In some embodiments, silicon variants may be deposited in one or more layers of the active pixel 910 (e.g., the N1 layer 918, the N1+N2 layer 920). In some embodiments, prior to epitaxy, further processing may be performed to increase the performance of the transistors to be utilized on the semiconductor substrate 913. Additionally, similar to the active pixel 810, the FEOL process may include a strain formation step in which silicon variants are deposited in the semiconductor substrate 913 to thereby improve the electron mobility of the substrate base 911. In some embodiments, the impurity concentration and / or material may be modified to further improve electron mobility. In some embodiments, the FEOL process may include the growth of a gate dielectric (e.g., the transfer gates 214 and 216 of FIGS. 2A and 2B). For example, this can include patterning the gate, patterning the source and drain regions, and subsequent implementation or diffusion of dopants to obtain desired complementary electrical properties. For example, in some embodiments, N-type dopants such as P, As, and / or Sb are utilized due to their low ionization energy (20-300 keV), low diffusivity, and suitable solid solubility in Si.

[0102] 10A-10B are charge potential diagrams illustrating simulation results for exemplary active pixels according to one or more embodiments. Specifically, FIGS. 10A-10B illustrate charge potential diagrams for active pixels such as active pixel 810 of FIGS. 8A-8B and active pixel 910 of FIGS. 9A-9B that are capable of achieving full in-pixel charge transfer to the floating diffusion node as confirmed via simulation. FIG. 10A includes a table 1000 illustrating simulation results of the operation of active pixel 810 of FIGS. 8A-8B and active pixel 910 of FIGS. 9A-9B compared to a reference active pixel 1010 shown in FIG. 10B. Reference active pixel 1010 includes a homogenous photodiode region 1001 having a uniform implant composition. In contrast, active pixel 810 includes two n-layer implant regions, namely, N1 layer 818 and N1+N2 layer 820, and active pixel 910 includes two n-layer implant regions, namely, N1 layer 918 and N1+N2 layer 920, with N2 of active pixel 910 configured to narrow the channel effect utilizing the tapered n-layer implant shown in FIG. 10B.

[0103] In a first operation, the first transfer gate TG1 of each of active pixels 810, 910, and 1010 is turned on, and the second transfer gate TG2 of each of active pixels 810, 910, and 1010 is turned off. In FIGS. 10A-10B, the first transfer gate TG1 refers to the transfer gate 814 of active pixel 810, the transfer gate 914 of active pixel 910, and the transfer gate 1014 of reference active pixel 1010, and the second transfer gate TG2 refers to the transfer gate 816 of active pixel 810, the transfer gate 916 of active pixel 910, and the transfer gate 1016 of reference active pixel 1010. In a second operation, the first transfer gate TG1 is turned off, and the second transfer gate TG2 is turned on. As shown in FIG. 10A, a strong potential pocket remains within the photodiode region of reference active pixel 1010 for both the first and second operations. The potential pocket within the reference active pixel 1010 is evidenced by the (three) thick lines near transfer gate TG2 or TG1, depending on whether transfer gate TG1 or transfer gate TG2 is turned on, representing charge accumulation within the photodiode region of the reference active pixel 1010.

[0104] As discussed above, active pixels 810 and 910 utilize various implant materials and doping concentrations that facilitate full in-pixel charge transfer to the floating diffusion nodes of those active pixels. Having full charge transfer has the technical effect of reducing image lag when processing images, thereby improving the processing time of the imaging system. Using two transfer gates TG1 and TG2 located on the same side of the active pixel, full in-pixel charge transfer is achieved by applying a strong electric field to the photodiode region of the active pixel.

[0105] As shown in table 1000, under the operating conditions of both transfer gates TG1 and TG2, active pixel 810 achieves significantly more charge transfer from the photodiode region when compared to reference active pixel 1010. Additionally, as discussed above, active pixel 910, which implements various implant materials (e.g., various impurity concentration gradients) to achieve electron drift current, exhibits even more complete charge transfer of the photodiode region when compared to reference active pixel 1010 and active pixel 810. This is indicated by the single thick line near the active transfer gate. In this manner, active pixels 810 and 910 achieve complete charge transfer to the floating diffusion node with no potential pockets within the photodiode region of the active pixel.

[0106] 11A-11C are schematic representations of top views 1100, 1150, and side views 1160 of exemplary active pixels according to one or more embodiments. As shown in FIGS. 11A and 11B, in some embodiments, additional N-layer implants may be used to enable the active pixel to achieve a strong electric field. For example, active pixel 1110A may include four (4) N-layer regions, as shown in FIG. 11A. As another example, active pixel 1110B may also use four N-layer regions implemented as various impurity concentration grading effects through the four N layers. Compared to active pixel 810 of FIGS. 8A-8B and active pixel 910 of FIGS. 9A-9B, the use of active pixels 1110A and 1110B in DPS image sensing system 100A or DPS image sensing system 100B may allow for the formation of even stronger electric fields due to the use of additional N-layer implant regions in active pixels 1110A and 1110B.

[0107] 11B includes a photodiode (PD) 1190 that may incorporate a diverse impurity concentration gradient effect structure that includes four N layer regions. For example, N1 layer 1118 corresponds to a first diverse impurity concentration gradient region that includes an implant profile N1, N1+N2 layer 1119 corresponds to a second diverse impurity concentration gradient region that includes an implant profile N1+N2, N1+N2+N3 layer 1120 corresponds to a third diverse impurity concentration gradient region that includes an implant profile N1+N2+N3, and N1+N2+N3+N4 layer 1121 corresponds to a fourth diverse impurity concentration gradient region that includes an implant profile N1+N2+N3+N4.

[0108] In some embodiments, the PD 1180 of active pixel 1110A and the PD 1190 of active pixel 1110B may include additional N layer regions, such as five (5) N layer regions, six (6) N layer regions, seven (7) N layer regions, or more. In some embodiments, each successive N layer may have the same width or may have varying widths. Varying the shape of each region can help reduce manufacturing costs because the number of photomasks can be reduced when not only using rectangular shaped masks. In some embodiments, the angle of incidence formed by each N layer in the narrow field effect method may be different from one successive character to the next. For example, as can be seen from the top view 1100 of FIG. 11A , the PD 1180 of active pixel 1110A has four N layers with increasing impurity concentrations from a minimum concentration at point X to a maximum concentration at point X′. Additionally, the four N layers of the PD 1180 of active pixel 1110A are distributed along the X-X′ axis in approximately vertical blocks. As another example, as can be seen from the top view 1150 of FIG. 11B, the PD 1190 of the active pixel 1110B also includes four N layers of increasing impurity concentration, but these layers extend along an angle of approximately 45 degrees from the X-X′ axis toward the edge of the PD 1190 of the active pixel 1110B.

[0109] In some embodiments, active pixels 1110A and 1110B include transfer gates 1114 and 1116, which may be asymmetrically positioned on either side of PDs 1180 and 1190, respectively. Operation of the transfer gates 1114 and 1116 of active pixel 1110A may generate an electric field that induces an electron drift current from a first side of PD 1180 to a second side of PD 1180. Operation of the transfer gates 1114 and 1116 of active pixel 1110B may generate an electric field that induces an electron drift current from a first side of PD 1190 to a second side of PD 1190. For example, the electron drift current may be directed from point X to point X'. The inclusion of two (2) transfer gates 1114 and 1116 provides an electric field that causes a complete in-pixel charge transfer of electrons from N1 layer 1118 to N1+N2 layer 1119 to N1+N2+N3 layer 1120 to N1+N2+N3+N4 layer 1121 (and so on) to the floating diffusion node or drain.

[0110] As can be seen in FIG. 11C , a side view 1160 shows an active pixel 1110, which may be the same as or similar to active pixel 1110A or 1110B of FIGS. 11A and 11B, respectively. Active pixel 1110 may include a semiconductor substrate 1113. Semiconductor substrate 1113 may utilize alternating implant concentrations for each iteration of n-layer implant regions. In this manner, facilitating full in-pixel charge transfer to transfer gates 1114 and 1116 and to the floating diffusion node or drain may be achieved. In some embodiments, the implant concentration for each n-layer of semiconductor substrate 1113 may be increased compared to the previous layer. This may increase the conductivity of each additional layer of n-layer of semiconductor substrate 1113, which may have the technical effect of providing full in-pixel charge transfer through operation of transfer gates 1114 and 1116.

[0111] In some embodiments, the semiconductor substrate 1113 includes a substrate base 1111, an N1 layer 1118, an N1+N2 layer 1119, an N1+N2+N3 layer 1120, and an N1+N2+N3+N4 layer 1121. Each of the layers 1118-1121 may include a photovoltaic material configured to convert incident light into an electric charge, as known in the art. For example, the layers of the active pixel 1110 may include materials such as silicon, gallium, arsenide, or other materials. The active pixel 1110 may include a first electron transfer region (e.g., N1 layer 1118) having an N1 implant concentration, a second charge transfer region (e.g., N1+N2 layer 1119) having an N1+N2 implant concentration, a third charge transfer region (e.g., N1+N2+N3 layer 1120) having an N1+N2+N3 implant concentration, and a fourth charge transfer region (e.g., N1+N2+N3+N4 layer 1121) having an N1+N2+N3+N4 implant concentration. As described herein, implant concentration refers to the amount and type of dopant utilized in the substrate.

[0112] In some embodiments, the material composition and configuration of PD1180 of active pixel 1110A and PD1190 of active pixel 1110B may be the same as or similar to the material composition and configuration of PD912 of active pixel 910 and PD812 of active pixel 810. For example, N1 layer 1118 may also include a first concentration of an N-type dopant such as P, As, and / or Sb, N1+N2 layer 1119 may include a higher concentration of the same dopant used in N1 layer 1118, N1+N2+N3 layer 1120 may include an even higher concentration of the same dopant used in N1 layer 1118 and N1+N2 layer 1119, and N1+N2+N3+N4 layer 1121 may include an even higher concentration of the same dopant used in N1 layer 1118, N1+N2 layer 1119, and N1+N2+N3 layer 1120. As another example, the N1+N2 layer 1119, the N1+N2+N3 layer 1120, and / or the N1+N2+N3+N4 layer 1121 may be the same concentration of different dopants, followed by the N1 layer 1118 at the same concentration.

[0113] In some embodiments, the active pixel 1110 may use end-of-line (FEOL) processing to form transistors directly on the semiconductor substrate 1113. The semiconductor substrate 1113 may include a wafer fabricated by growing pure silicon layers, for example, using an epitaxy process. In some embodiments, silicon variants may be deposited within one or more layers of the active pixel 1110 (e.g., N1 layer 1118, N1+N2 layer 1119, N1+N2+N3 layer 1120, N1+N2+N3+N4 layer 1121). In some embodiments, prior to epitaxy, further processing may be performed to increase the performance of the transistors to be utilized on the semiconductor substrate 1113. Additionally, similar to active pixels 810 and 910, the FEOL processing may include a strain formation step in which silicon variants are deposited within the semiconductor substrate 1113 to thereby improve the electron mobility of the substrate base 1111. In some embodiments, the impurity concentration and / or material may be modified to further improve electron mobility. In some embodiments, FEOL processing may include the growth of a gate dielectric (e.g., transfer gates 214 and 216 in FIGS. 2A and 2B). For example, this may include patterning the gate, patterning the source and drain regions, and subsequent dopant application or diffusion to obtain desired complementary electrical properties. For example, in some embodiments, N-type dopants such as P, As, and / or Sb are utilized due to their low ionization energy (e.g., 20-300 keV), low diffusivity, and suitable solid solubility in Si.

[0114] 12A-12B are schematic representations of an exemplary non-shared active pixel system 1200 and an exemplary shared active pixel system 1250, according to one or more embodiments. FIGS. 12A and 12B illustrate exemplary implementations for providing a high dynamic range readout. The high dynamic range readout may be implemented by either the non-shared active pixel system 1200 including a first active pixel 1210A or the shared active pixel system 1250 including a first active pixel 1210A and a second active pixel 1210B. In some embodiments, the non-shared active pixel system 1200 including the first active pixel 1210A may be used in place of or in addition to the active pixel 210 of FIGS. 2A and 2B. The shared active pixel system 1250 including the first active pixel 1210A and a second active pixel 1210B may be used in place of or in addition to the active pixel 410 of FIGS. 4A and 4B.

[0115] In some embodiments, as shown by FIG. 12A , the non-shared active pixel system 1200 includes a first active pixel 1210A. The first active pixel 1210A may include and be operably coupled to a first transfer gate 1214A and a second transfer gate 1216A. The transfer gates 1214A and 1216A may be operably coupled to floating diffusion nodes 1224 and 1226, respectively. In some embodiments, application of an electric field to the first active pixel 1210A may cause an electron drift current to be generated in PD 1212A. FIGS. 12A and 12B show electron current 1219A corresponding to the electron drift current generated in PD 1212A and electron current 1219B corresponding to the electron drift current generated in PD 1212B. In some embodiments, transfer gates 1214A and 1216A may be configured to generate electron flow 1219A in a direction from a first side of PD 1212A to a second side of PD 1212A. Thus, electron flow 1219A may cause bidirectional charge transfer 1221A. In some embodiments, an electron drift current, such as electron flow 1219A, formed by applying an electric field to active pixel 1210A can increase the conductivity within PD 1212A. For example, the increased conductivity may induce charge transfer of charge particles (e.g., electrons) from one side of PD 1212A to the other side of PD 1212A. When operation of transfer gates 1214A and 1216A modulates the electric field near transfer gates 1214A and 1216A, electrons may transfer from transfer gates 1214A and 1216A to floating diffusion node 1224 or floating diffusion node 1226, respectively. In some embodiments, electrons may alternatively transfer from transfer gates 1214A and / or 1216A to the drain.

[0116] 12B , the shared active pixel system 1250 includes a first active pixel 1210A and a second active pixel 1210B. The first active pixel 1210A may include and be operably coupled to a first transfer gate 1214A and a second transfer gate 1216A. The second active pixel 1210B may include and be operably coupled to a first transfer gate 1214B and a second transfer gate 1216B. The transfer gates 1214A and 1214B may be operably coupled to a floating diffusion node 1224, and the transfer gates 1216A and 1216B may be operably coupled to a floating diffusion node 1226. In some embodiments, application of an electric field to the first active pixel 1210A and the second active pixel 1210B may cause electron flow 1219A to be generated in PD 1212A and electron flow 1219B to be generated in PD 1212B. In some embodiments, transfer gates 1214A, 1214B, 1216A, and 1216B may be configured to generate electron flow 1219A and 1219B in directions from a first side of PD 1212A to a second side of PD 1212A and from a first side of PD 1212B to a second side of PD 1212B. In some embodiments, electron flow 1219A and electron flow 1219B may be equal in magnitude but opposite in direction. In some embodiments, the same electric field may be applied to both PD 1212A and 1212B to generate electron flow 1219A and 1219B therein, respectively. In some embodiments, different electric fields may be applied to each of PD 1212A and PD 1212B. Thus, electron flow 1219A may cause bidirectional charge transfer 1221A, and electron flow 1219B may cause bidirectional charge transfer 1221B. In some embodiments, electron drift currents, such as electron flow 1219A and / or electron flow 1219B, created by applying electric fields to active pixels 1210A and 1210B can increase the conductivity in PDs 1212A and 1212B.For example, an increase in conductivity may induce charge transfer of charged particles (e.g., electrons) from one side of PD 1212A to the other side of PD 1212A and from one side of PD 1212B to the other side of PD 1212B. When operation of transfer gates 1214A and 1216A modulates the electric field near transfer gates 1214A and 1216A, electrons may transfer from transfer gates 1214A and 1216A to floating diffusion node 1224 or floating diffusion node 1226, respectively. Similarly, when operation of transfer gates 1214B and 1216B modulates the electric field near transfer gates 1214B and 1216B, electrons may transfer from transfer gates 1214B and 1216B to floating diffusion node 1224 or floating diffusion node 1226, respectively. In some embodiments, electrons may alternatively transfer from transfer gates 1214A, 1214B, 1216A and / or 1216B to the drain.

[0117] The active pixel 1210A of the non-shared active pixel system 1200 may include a first transfer gate 1214A and a floating diffusion node 1224 for a high conversion gain (HCG) signal, and a second transfer gate 1216A and a floating diffusion node 1226 for a low conversion gain (LSG) signal. High dynamic range readout may function by utilizing a first transfer to the floating diffusion node 1224 and a second transfer to the floating diffusion node 1226. The shared active pixel system 1250 may include an active pixel 1210A including a first transfer gate 1214A and a floating diffusion node 1224, and an active pixel 1210B including a first transfer gate 1214B and a floating diffusion node 1224 (shared by transfer gates 1214A and 1214B) for a high conversion gain (HCG) signal, and an active pixel 1210A including a second transfer gate 1216A and a floating diffusion node 1226, and an active pixel 1210B including a second transfer gate 1216B (shared by transfer gates 1216A and 1216B) and a floating diffusion node 1226 for a low conversion gain (LSG) signal. High dynamic range readout may function by utilizing a first transfer to the floating diffusion node 1224 and a second transfer to the floating diffusion node 1226.

[0118] In some embodiments, at low brightness levels of incident light, there is some charge in floating diffusion node 1224 and no charge or less than a threshold amount of charge in floating diffusion node 1226. In some embodiments, a single floating diffusion node is used for high-gain readout, although alternatively, two floating diffusion nodes may be used for high-gain readout. At high brightness levels of incident light, there is charge on both floating diffusion node 1224 and floating diffusion node 1226. In some embodiments, to use both floating diffusion nodes 1224 and 1226 for low-gain readout, a charge-adding processing technique for floating diffusion nodes 1224 and 1226 is required. As described herein, charge-adding refers to a digital binning operation that combines floating diffusion nodes 1224 and 1226 in the digital domain. In this manner, a single-exposure high-dynamic-range signal is achieved. For example, the floating diffusion node 1226 may be coupled to a capacitor 1240 via a connecting wire 1230. The capacitor 1240 may include a metal-oxide-semiconductor (MOS) capacitor, a metal-insulator-metal (MIM) capacitor, a metal-oxide-metal (MOM) capacitor, or other types of capacitors or other sensors.

[0119] FIG. 13 is a schematic representation of an exemplary shared active pixel system 1300 according to one or more embodiments. The shared active pixel system 1300 may be used to implement a high dynamic range readout for high gain / high resolution readout, as well as a high full well capacity (FWC) and low resolution readout. As used herein, “high dynamic range readout” may include a high gain for high resolution readout and a high FWC for low resolution readout. In some embodiments, the shared active pixel system 1300 may include a first active pixel 1310A and a second active pixel 1310B. The active pixels 1310A and 1310B may be substantially similar to the active pixel 410 of FIGS. 4A and 4B , and the previous description may apply.

[0120] In some embodiments, the shared active pixel system 1300 is configured for high-gain / high-resolution readout and high-FWC / low-resolution readout through the use of an overflow path during overflow operation, as described in further detail below. The first active pixel 1310A may include a photodiode (PD) 1312A, and the second active pixel 1310B may include a photodiode (PD) 1312B. Both PD 1312A and PD 1312B may share a floating diffusion node 1324, which is configured to receive transferred electrons from transfer gates 1314A and 1314B, respectively, for the high-conversion gain (HCG) signal. PD 1312A and PD 1312B may share a floating diffusion node 1326, which may be configured to receive transferred electrons from transfer gates 1316A and 1316B, respectively, for the low-conversion (LCG) signal. Application of an electric field can generate electron drift currents in PD 1312A and PD 1312B, respectively. FIG. 13 shows electron current 1319A, corresponding to the electron drift current generated in PD 1312A, and electron current 1319B, corresponding to the electron drift current generated in PD 1312B. Electron current 1319A can generate bidirectional charge transfer 1321A, and electron current 1319B can generate bidirectional charge transfer 1321B. In some embodiments, electron drift currents, such as electron current 1319A and electron current 1319B, generated by application of an electric field to active pixels 1310A and 1310B can increase the conductivity in active pixels 1310A and 1310B. In some embodiments, active pixels 1310A and 1310B can be coupled to capacitor 1340 via connecting wire 1330 for charge addition processing. Capacitor 1340 may be the same as or similar to capacitor 1240 of FIG. 12B, and the previous description may apply.

[0121] In some embodiments, high gain / high resolution operation may include a first transfer of charge from PD 1312A of active pixel 1310A and PD 1312B of active pixel 1310B to floating diffusion node 1324. During operation in a low brightness environment, there may be some charge in floating diffusion node 1324 and no charge or less than a threshold amount of charge in floating diffusion node 1326. During operation in a high brightness environment, there may be some charge in floating diffusion node 1324 and some charge in floating diffusion node 1326 due to overflow operation. During overflow operation, floating diffusion node 1324 may generate excess electrons from high brightness conditions. An overflow path may be created below the transfer gate (e.g., transfer gate 1316A and / or transfer gate 1316B), and excess charge may be transferred to floating diffusion node 1326, thereby providing overflow operation. In some embodiments, both floating diffusion nodes 1324 and 1326 may be utilized for high full well capacity (FWC) / low resolution readout. Additional charge handling of floating diffusion nodes 1324 and 1326 may be required to achieve high FWC and low resolution readout.

[0122] FIG. 14 is an exemplary timing diagram 1400 corresponding to the active pixel systems of FIGS. 12A-12B and 13 , according to one or more embodiments. In some embodiments, the non-shared active pixel system 1200 and the shared active pixel system 1250 of FIGS. 12A-12B , respectively, or the shared active pixel system 1300 of FIG. 13 may be applied to a Time of Flight (ToF) readout using an indirect Time of Flight method. In some embodiments, the indirect ToF operation may be performed using active pixel 1210A of the non-shared active pixel system 1200. In some embodiments, the ToF operation may be performed using active pixels 1210A and 1210B of the shared active pixel system 1250 and / or active pixels 1310A and 1310B of the shared active pixel system 1300.

[0123] Timing diagram 1400 may describe the operation of active pixel 1210A of non-shared active pixel system 1200, active pixels 1210A and 1210B of shared active pixel system 1250, and / or active pixels 1310A and 1310B of shared active pixel system 1300 to achieve indirect Time of Flight measurements. A time of flight method according to one or more embodiments described herein initiates a first transfer of electronic charge from one or more photodiodes to a floating diffusion node (e.g., from PD1212A to floating diffusion node 1224, from PD1212A and PD1212B to floating diffusion node 1224, from PD1312A and PD1312B to floating diffusion node 1324), and a second transfer of electronic charge may occur from one or more photodiodes to another floating diffusion node (e.g., from PD1212A to floating diffusion node 1226, from PD1212A and PD1212B to floating diffusion node 1226, from PD1312A and PD1312B to floating diffusion node 1326). For example, at time T1, charge may be detected as being transferred from the photodiode to a first transfer gate, while at time T3, charge may be detected as being transferred from the photodiode to a second transfer gate. Some charge (e.g., electrons) may be transferred to one floating diffusion node (e.g., floating diffusion node 1224, floating diffusion node 1324), while other charge may be transferred to another floating diffusion node (e.g., floating diffusion node 1226, floating diffusion node 1326). The amount of charge transferred to the floating diffusion node corresponds to the reflection time. The reflection time can be used to determine the distance from the LED plus sensor to the target.For example, the time difference TDelay shown in timing diagram 1400 may indicate the amount of time between when a signal, such as an LED pulse, is emitted from a source (e.g., time T1) and when the signal is received (e.g., detected) by an active pixel (e.g., time T2). Time of Flight systems have many practical applications, including particle physics measurement systems, signal processing, image processing, etc.

[0124] Any one or more of the active pixels described by the embodiments from Figures 2A-14 may be implemented as active pixel 110 of Figure 1A or active pixel 110 of Figure 1B, as long as appropriate modifications of the circuitry of DPS image sensing system 100A or 100B, respectively, are made as would be understood by one skilled in the art.

[0125] FIG. 15 is a schematic representation of an exemplary back-end ADC and memory circuit 1500 according to one or more embodiments. The back-end ADC and memory circuit 1500 may represent a transistor-level circuit diagram of the back-end ADC and memory circuit 115 of FIG. 1. The multiple ADC scheme is advantageous for a wide dynamic range of operation. In some embodiments, the back-end ADC and memory circuit 1500 provides a write control scheme and circuitry for multiple ADC operation within a small-area DPS device. Additionally, the back-end ADC and memory circuit 1500 can efficiently utilize memory.

[0126] For each pixel in a digital processing system (e.g., DPS image sensing system 100A of FIG. 1A or DPS image sensing system 100B of FIG. 1B), a back-end ADC and memory circuit and digital memory are required. In some embodiments, back-end ADC and memory circuit 1500 may be operably coupled to active pixel 1510. Back-end ADC and memory circuit 1500 may include comparator 1520 and write control circuit 1530. In some embodiments, active pixel 1510, comparator 1520, and write control circuit 1530 are substantially similar to active pixel 110, comparator 120, and write control circuit 130 of FIG. 1A, and the previous description may apply. In some embodiments, back-end ADC and memory circuit 1500 may also include a state latch 1540. State latch 1540 may be effective for multiple ADC operations, which are described in further detail below. 1 , and the previous description may apply. In some embodiments, back-end ADC and memory circuit 1500 represents an example of back-end ADC and memory circuit 115 of DPS image sensing system 100A or similar components of DPS image sensing system 100B. Write control circuit 1530 may include a positive feedback circuit 1531 at the output stage of write control circuit 1530, as well as an initialization circuit 1532. In some embodiments, positive feedback circuit 1531 and initialization circuit 1532 may be the same as or similar to positive feedback circuit 131 and initialization circuit 132 of FIG. 1 , respectively, and the previous description may apply.

[0127] In response to the output (e.g., “OutA”) of the comparator 1520 flipping from a particular logic value (e.g., logic 0) to the opposite logic value (e.g., logic 1), the positive feedback output FB of the positive feedback circuit 1531 becomes FB=1. FB=1 may be maintained regardless of the output (e.g., “OutA”) of the comparator 1520 (e.g., the positive feedback circuit 1531 may be “locked”) until an initialization operation is performed using COMP_SET_n=0. In some embodiments, COMP_SET_n=0 may be used for an initialization operation, which may be required to set OutB=1 and FB=0. In some embodiments, the initialization operation of the comparator 1520 is used to begin ADC conversion. The initialization operation may be performed using a minimum VRAMP voltage, which causes OutA to become OutA=0 and switches the output “Init” of the initialization circuit 1532 for connection to a node, as shown in more detail with reference to FIG. 1 . The initialization operation may also apply COMP_SET_n=0. In the use case where State=0, the output of the positive feedback circuit 1531 in the write control circuit 1530 is FB=0 and OutB=1. It should be noted that, unlike in Figure 1, COMP_SET_n and State may be used by the positive feedback circuit 1531 and the initialization circuit 1532 instead of COMP_SET and State_n used in Figure 1. COMP_SET_n may be obtained by inverting COMP_SET, and State may be obtained by inverting State_n.

[0128] Next, the comparator 1520 and the positive feedback circuit 1531 may be initialized with their states (i.e., COMP_SET_n=0 and State=0). Once the comparator 1520 and the positive feedback circuit 1531 are initialized, the ADC operation may begin with COMP_SET_n=1, allowing write operations to be performed to the ADC memory 1550. In the use case where State=1, FB=1 (OutB=0) is kept even when OutA=0 using the minimum VRAMP voltage and even when COMP_SET_n=0. After flipping COMP_SET_n=1, the memory is not written because WL=0. In this way, the state latch 1540 may output “State” to control activation of the back-end ADC and memory circuit 1500. In some embodiments, data may be written to memory (e.g., the ADC memory 1550) using the comparator 1520 when State=0.

[0129] In some embodiments, the comparator 1520 may be configured to facilitate the following operations. 1) Perform auto-zero operation by setting COMP_RST_n=0, and VRAMP equals the reset level. 2) Initialize the comparator 1520 by changing the positive feedback circuit 1531 from a locked state (e.g., FB=1) to an unlocked state (e.g., FB=0) using COMP_SET_n=0. The positive feedback circuit 1531 becomes unlocked (e.g., FB=0) when State=0, but the positive feedback circuit 1531 remains locked (e.g., FB=1) when State=1. In the latter scenario, no data is written to memory (e.g., ADC memory 1550) because WL=0. 3) Perform a ramp-up operation using the VRAMP signal. The ADC data is stored in the comparator 1520 and may flip only when FB=1. In some embodiments, "WL_SEL=0" is used for the read operation of the ADC memory 1550. WL_SEL=0 may also be used to initialize State=0 before the first ADC operation in a multiple ADC operation scenario.

[0130] As shown in FIG. 15, write control circuit 1530 may include a positive feedback circuit 1531 and an initialization circuit 1532 combined with a constant current inverter of the comparator second stage. In some embodiments, COMP_SET_n and State have the opposite polarity of COMP_SET and State_n in FIG. 1, respectively, for pMOS gates. In FIG. 1, OutA of comparator 120 is OutA=0 for the COMP_SET switch in FIG. 1, but in some embodiments, it may be removed. In some embodiments, OutA=0 may be set to ground (GND) for comparator 1520 to perform an initialization operation using an appropriate VRAMP voltage after auto-zero operation without a switch.

[0131] In some embodiments, STATE_DATA is connected to the state latch 1540 circuit through an nMOS transistor pair. When the comparator 1520 switches the word line selection from WL=1 to WL=0, the state latch 1540 may be fixed as State=STATE_DATA at the flipping time. The ADC memory 1550 may simultaneously store the bit line data. STATE_DATA=1 may be intentionally provided for any suitable ADC range for each operation of the back-end ADC and memory circuit 1500.

[0132] Any one or more of the active pixels described by the embodiments from Figures 2A-14 may be implemented as active pixel 1510 of Figure 15, as long as appropriate modifications of the circuitry of back-end ADC and memory circuit 1500 are made as would be understood by one skilled in the art.

[0133] FIG. 16 is a schematic representation of an exemplary back-end ADC and memory circuit 1600 according to one or more embodiments. The back-end ADC and memory circuit 1600 may be the same as or similar to the back-end ADC and memory circuit 1500 of FIG. 15 , and the previous description may apply. For example, the back-end ADC and memory circuit 1600 may include a comparator 1620 and a write control circuit 1630, which may be the same as or similar to the comparator 1520 and the write control circuit 1530 of FIG. 15 . The write control circuit 1630 may include a positive feedback circuit 1631 and an initialization circuit 1632. The back-end ADC and memory circuit 1600 may differ from the back-end ADC and memory circuit 1500 in that an nMOS transistor pair 1633 may be added to the positive feedback circuit 1631 to implement CMOS structures for both the COMP_SET_n and the output signal of the positive feedback circuit 1631, respectively. In this way, the flipping speed of the positive feedback circuit 1631 can be accelerated using the nMOS transistor pair 1633. Additionally, advantageously, the write control circuit 1630 may allow less current to pass during flipping. The comparator 1620 of the back-end ADC and memory circuit 1600 may also include a COMP_SET nMOS switch 1621 to achieve additional device performance, such as preventing long initialization delays when the capacitor CL is large. In some embodiments, the nMOS switch 1621 may be implemented as a pair of transistors (e.g., nMOS transistors). In this way, the nMOS switch 1621 may be effective for faster initialization of the ADC operation.

[0134] Any one or more of the active pixels described by the embodiments from Figures 2A-14 may be implemented as an active pixel for the back-end ADC and memory circuit 1600, as would be understood by one of ordinary skill in the art.

[0135] 17 is a timing diagram 1700 of an example operation of a back-end ADC and memory circuit according to one or more embodiments. Timing diagram 1700 may apply to each circuit shown in FIG. 1, FIG. 15, or FIG. 16, with the note that for the circuits shown in FIG. 15 and FIG. 16, COMP_SET_n is used in place of COMP_SET and State is used in place of State_n. COMP_SET_n may be obtained by inverting COMP_SET, and State may be obtained by inverting State_n.

[0136] Timing diagram 1700 may show an example of overlapped 3Q operation. In some embodiments, WL_SEL may be set to 1 (WL_SEL=1) so that WL has the same value as OutB throughout the ADC operation. In some embodiments, when WL is flipped from logic 1 to logic 0, a time code (i.e., an ADC code) is written to memory (e.g., ADC memory 150, 1550, 1650). In some embodiments, the time code written and stored in memory indicates the time when WL is flipped (i.e., the time when a comparator, such as comparator 120, 1520, 1620, is flipped). That is, the time code stored in memory may be a digitized light intensity value. In addition to writing the time code to memory when WL is flipped from logic 1 to logic 0, STATE_DATA may be written to a state latch (e.g., state latch 140, 1540, 1640).

[0137] In some embodiments, an auto-zero operation may be performed before every ADC operation. To perform the auto-zero operation, COMP_RST may be set to 1 (e.g., COMP_RST=1). In some embodiments, the comparator (e.g., comparator 120) may perform an initialization operation of setting COMP_SET to 1 (e.g., COMP_SET=1) after each auto-zero operation, which may release the positive feedback circuit (e.g., positive feedback circuit 131, 1531, 1631) from a locked status. In some embodiments, the comparator (e.g., comparator 120, 1520, 1620) may perform an initialization operation of setting COMP_SET_n to 0 (e.g., COMP_SET_n=0). During the time period when STATE_DATA is set to logic 1, the time code (i.e., ADC code) written to memory when the comparator is flipped may be held for the remainder of one ADC cycle. The waveform of STATE_DATA may be designed according to the time range over which it is desired to hold the time code written to memory for the remainder of one ADC operating cycle. The time period during which STATE_DATA is set to logic 0 is not limited to a particular time period during a given ADC operating cycle.

[0138] The timing diagram 1700 shows three cases.

[0139] Case 1 - Output OutB flips once,

[0140] Case 2 - Output OutB flips twice, and

[0141] Case 3 - Output OutB flips three times.

[0142] As seen in timing diagram 1700, when output OutB(WL) is inverted from logic 1 to logic 0, State is kept at the same value as STATE DATA (i.e., State=STATE_DATA). In the current ADC operation cycle beginning at time t1 shown in FIG. 17, for example, at time t2 when STATE DATA=1 as shown by Case 1, if OutB(WL) is inverted from logic 1 to logic 0 during timestamp ADC, the time code (i.e., ADC code) at time t2 is written to memory (e.g., ADC memory 150, 1550, 1650), and State is set to logic 1 (i.e., State=1). In some cases, setting State to logic 1 puts comparators (e.g., comparators 120, 1520, 1620) and positive feedback circuits (e.g., positive feedback circuits 131, 1531, 1631) into a locked state. If State is held at logic 1 for the remainder of the current cycle of ADC operation (i.e., State=1), the ADC code stored in memory will be held until the current cycle of ADC operation ends at time t9, even when COMP_SET is made logic 1 before entering the HCG ADC or LCG ADC.

[0143] If OutB(WL) is inverted from logic 1 to logic 0 while STATE DATA=0 during the timestamp ADC, for example, at time t4 shown by Case 2 and Case 3, the time code (i.e., ADC code) at time t4 is written to memory (e.g., ADC memory 150, 1550, 1650), and State is set to logic 0 (i.e., State=0) because STATE DATA=0. Thus, in Case 2 or Case 3, when COMP_SET is set to logic 1 (or COMP_SET_n is set to logic 0) at time t5 when the immediately preceding HCG ADC starts, the initialization circuit (e.g., initialization circuit 132, 1532, 1632) unlocks the comparator (e.g., comparator 120, 1520, 1620) and the positive feedback circuit (e.g., positive feedback circuit 131, 1531, 1631), and the HCG ADC starts.

[0144] In Case 2, OutB(WL) is inverted from logic 1 to logic 0 during HCG ADC. For example, at time t6, when STATE DATA=1, the time code at time t6 (i.e., the ADC code) may be written to memory (e.g., ADC memory 150, 1550, 1650) and State is set to logic 1 (i.e., State=1), which causes the comparators (e.g., comparators 120, 1520, 1620) and positive feedback circuits (e.g., positive feedback circuits 131, 1531, 1631) to lock again. In Case 2, because State is kept at logic 1 (i.e., State=1) for the remainder of the current cycle of ADC operation, the ADC code stored in memory during HCG ADC is kept until the current cycle of ADC operation ends at time t9, even when COMP_SET is made logic 1 before entering LCG ADC.

[0145] In Case 3, OutB(WL) is inverted from logic 1 to logic 0 during the LCG ADC, for example at time t8, and when STATE DATA=1, the time code (i.e., the ADC code) at time t8 is written to memory (e.g., ADC memory 150, 1550, 1650) and State is set to logic 1 (i.e., State=1), which further re-locks the comparator and positive feedback circuit. In Case 3, because State is kept at logic 1 (i.e., State=1) for the remainder of the current cycle of ADC operation, the ADC code stored in memory during the LCG ADC is kept until the current cycle of ADC operation ends at time t9. Thus, OutB(WL) is inverted from logic 1 to logic 0 while STATE DATE=1, the time code (i.e., ADC code) at the time OutB(WL) was inverted is written to memory (e.g., ADC memory 150, 1550, 1650), and the state latch (e.g., state latch 140, 1540, 1640) holds State=1. This may keep the comparators (e.g., comparators 120, 1520, 1620) and positive feedback circuits (e.g., positive feedback circuits 131, 1531, 1631) locked for the remainder of the current ADC operation cycle. In some embodiments, STATE_DATA may be set to logic 1 only once in each of the timestamp ADC, HCG ADC, and LCG ADC, as shown in FIG. 17. In some embodiments, STATE_DATA may alternate between logic 1 and logic 0 to perform complex ADC operations.

[0146] 18A-18B are schematic representations of exemplary data structures 1800 and 1820 according to one or more embodiments. In some embodiments, data for ADC memory 150 may be used in place of a state latch (e.g., state latch 140, 1540, 1640). In some embodiments in which ADC memory 150 is used in place of a state latch, State (or State_n) may be stored in ADC memory 150, as described below. Data for ADC memory 150 may be organized with flag bits and data bits, as shown in FIG. 1. While the flag bit arrangements described herein may be suitable for implementing the embodiments described above, those skilled in the art will recognize that other flag bit arrangements may be used in addition or alternatively.

[0147] As shown in FIG. 18A , the data structure 1800 may be applicable to an ADC operation, such as a three-stage ADC operation including a timestamp ADC operation (ADC1), an HCG ADC operation (ADC2), and an LCG ADC (ADC3) operation. In some embodiments, the data structure 1800 may include data strings 1802-1806, each of which may include a flag bit and an ADC bit. For example, the first data string 1802 is a 6-bit string including a flag bit 1808 and a data bit (ADC bit) 1810. The first data string 1802 may correspond to a time code written to a memory (e.g., ADC memory 150, 1550, 1650) at a given time during a first ADC operation (e.g., the timestamp ADC of FIG. 19 ). As described above, a time code may be provided to the read / write data bus lines 160 from a time code generator (not shown) and may be written to a memory (e.g., ADC memory 150, 1550, 1650). The flag bit 1808 of the first data string 1802 may include the most significant bit (MSB) of a time code (or ADC code) that may be written to a memory (e.g., ADC memory 150, 1550, 1650) at a certain time during the timestamp ADC. The MSB of the first data string 1802 may be assigned to be a logic one so that the memory may hold the ADC code in response to the output of a comparator (e.g., comparator 120, 1520, 1620) flipping from a particular logic value (e.g., logic zero) to the opposite logic value (e.g., logic one). As shown in Figure 19, the first data string 1802 starts with "100000" and increments to "101111" during the timestamp ADC. In Figure 19, the lower 5 bits of the first data string 1802 are referred to as the ADC code <4:0>.

[0148] The second data string 1804 is also a 6-bit data string including a flag bit 1812 and a data bit (ADC bit) 1814. The second data string 1804 may correspond to a time code that is written to a memory (e.g., ADC memory 150, 1550, 1650) at a given time during a second ADC operation (e.g., the HCG ADC of FIG. 19 ). The flag bit 1812 of the second data string 1804 may include the most significant bit (MSB) of a time code (or ADC code) that may be written to a memory (e.g., ADC memory 150, 1550, 1650) at a certain time during the HCG ADC. The MSB of the second data string 1804 may be assigned to be a logic 1 so that the memory may hold the ADC code in response to the output of a comparator (e.g., comparator 120, 1520, 1620) flipping from a particular logic value (e.g., logic 0) to the opposite logic value (e.g., logic 1). As shown in FIG. 19, the second data string 1804 starts with "110000" and increments to "111111" during HCG ADC.

[0149] The third data string 1806 is also a 6-bit data string including a flag bit 1816 and a data bit (ADC bit) 1818. The third data string 1806 may correspond to a time code that is written to a memory (e.g., ADC memory 150, 1550, 1650) at a given time during a third ADC operation (e.g., the LCG ADC of FIG. 19 ). The flag bit 1816 of the third data string 1806 may include the most significant bit (MSB) of a time code (or ADC code) that may be written to a memory (e.g., ADC memory 150, 1550, 1650) at a certain time during the LCG ADC operation. The MSB of the third data string 1806 may be assigned to be a logic 0. Thus, the MSB of the third data string 1806 may not hold the ADC code by keeping the positive feedback circuit (e.g., the positive feedback circuit 131, 1531, 1631) in a locked state. 19, the ADC code once written to memory (e.g., ADC memory 150, 1550, 1650) is not overwritten in response to the output of a comparator (e.g., comparator 120, 1520, 1620) flipping from a particular logic value (e.g., logic 0) to the opposite logic value (e.g., logic 1) in a later ADC operation of the cycle. The third data string 1806 starts with "000000" and increments to "011111" during the LCG ADC.

[0150] In some embodiments in which one cycle of ADC operation includes the four stages shown in FIG. 18B , data structure 1820 may include data strings 1822-1828, each of which may include a flag bit and an ADC bit. The most significant bit (MSB) of the last ADC (ADC4), i.e., data string 1828, may be assigned to be a logic 0. The most significant bit (MSB) of each of the previous ADCs (e.g., ADC1, ADC2, ADC3) corresponding to data strings 1822-1826 may be assigned to be a logic 1. For example, first data string 1822 may include flag bit 1830 and data bit (ADC bit) 1832. Second data string 1824 may include flag bit 1834 and data bit (ADC bit) 1836. The third data string 1826 may include flag bits 1838 and data bits (ADC bits) 1840. The fourth data string 1828 may include flag bits 1842 and data bits (ADC bits) 1844.

[0151] 18C is a schematic representation of an exemplary memory array 1850, according to one or more embodiments. As shown in FIG. 18C, the memory array 1850 may use the MSBs of memory from data structures to achieve advantages that are outside of known memory layout arrangements, which are discussed in more detail below.

[0152] The memory array 1850 shows two instances of the remaining elements of the memory arrangement 1854 and the back-end ADC and memory circuit (e.g., back-end ADC and memory circuit 115) in a two-pixel configuration. In some embodiments, the memory array 1850 may include, for example, two instances of the comparator and write control circuit 1852 (e.g., the comparator 120 and the write control circuit 130 including the positive feedback circuit 131), as shown in FIG. 18C . In some embodiments, each pixel has an instance of the comparator and write control circuit 1852 and the 6-bit memory arrangement 1854 having D0-D5 in communication with bit lines B0-B5. In some embodiments, the MSB, i.e., D5, may be arranged to be directly or indirectly coupled to a corresponding instance of the write control circuit. In this way, communication and wiring of the States is relatively efficient for drawing from the memory array 1850 without alignment modifications to the memory arrangement 1854 for memories with CMOS level outputs. This can achieve the technical effect of having a DPS imaging system with lower power consumption, faster operation, and also allows for smaller pixel sizes in some types of memory devices.

[0153] FIG. 19 is a timing diagram 1900 of an exemplary operation of a back-end ADC and memory circuit according to one or more embodiments. The timing diagram may apply to circuits similar to those shown in FIG. 1, FIG. 15, or FIG. 16. In some embodiments, the circuit to which the timing diagram applies may be the same as any one of the circuits shown in FIG. 1, FIG. 15, or FIG. 16, except that such circuit need not have a state latch (e.g., state latch 140, 1540, 1640) and instead uses the most significant bit (MSB) of the ADC code as State (or State_n). Additionally, the timing diagram 1900 may be applicable to the data structures 1800 and 1820 of FIG. 18A and the memory array 1850 of FIG. 18C.

[0154] Timing diagram 1900 illustrates an example of an overlapped 3Q operation that applies state control to the data structure of memory array 1850. For example, the MSB of the time code (e.g., the MSB of flag bits 1808, 1812, 1816) may be used as the State to control the initialization operation. A separate flag bit may not be needed for state control, but may be used to distinguish ADC1, ADC2, and ADC3 from each other. The operations and timing illustrated in timing diagram 1900 of FIG. 19 may be used in conjunction with STATE_DATA (or ADC code) in FIG. <5> ) is set to logic 0 throughout the LCG ADC. As shown in timing diagram 1900 of FIG. 19, the time code (or ADC code) <5> ) is used as STATE_DATA. STATE_DATA=0 may be kept in the last ADC operation (i.e., LCG ADC). In Figure 19, STATE DATA in LCG ADC is set to logic 0.

[0155] In some embodiments, an auto-zero operation may be performed before every ADC operation. To perform an auto-zero operation, COMP_RST may be set to 1 (e.g., COMP_RST=1). In some embodiments, a comparator (e.g., comparator 120, 1520, 1620) may perform an initialization operation of setting COMP_SET to 1 (e.g., COMP_SET=1) after each auto-zero operation, which may release a positive feedback circuit (e.g., positive feedback circuit 131, 1531, 1631) from a locked status. In some embodiments, a comparator (e.g., comparator 120, 1520, 1620) may perform an initialization operation of setting COMP_SET_n to 0 (e.g., COMP_SET_n=0). During the time period when STATE_DATA is set to logic 1, the time code (i.e., ADC code) written to memory when the comparator is flipped may be held for the remainder of one ADC cycle. STATE_DATA(ADC code <5> ) may be set to logic 1 while the ADC code <4:0> increments from "100000" to "101111". The comparator initialization operation to release from the locked state and the ADC operation may be performed similarly to the operations described above with reference to timing diagram 1700 of FIG. 17.

[0156] The timing diagram 1900 shows three cases.

[0157] Case 1 - Output OutB flips once,

[0158] Case 2 - Output OutB flips twice, and

[0159] Case 3 - Output OutB flips three times.

[0160] As can be seen in timing diagram 1900, for Case 1, at time t2, when output OutB(WL) is inverted from logic 1 to logic 0, State is (ADC code <5> (i.e., when OutB is inverted, the MSB of the time code) is kept at the same value. In the current ADC operation cycle starting at time t1 shown in FIG. 19, for example, the ADC code <5> If OutB(WL) is inverted from logic 1 to logic 0 during timestamp ADC at time t2 when COMP_SET is set to logic 1 (i.e., MSB=1), the time code (i.e., ADC code) at time t2 is written to memory (e.g., ADC memory 150, 1550, 1650), the MSB of the time code written to memory at time t2 is output from the memory as State, and State is set to logic 1 (i.e., State=1). In some cases, setting State to logic 1 locks the comparators (e.g., comparators 120, 1520, 1620) and positive feedback circuits (e.g., positive feedback circuits 131, 1531, 1631). If State is kept at logic 1 (i.e., State=1) for the remainder of the current cycle of ADC operation, the ADC code stored in memory is kept until the current cycle of ADC operation ends at time t9, even when COMP_SET is set to logic 1 before entering the HCG ADC or LCG ADC.

[0161] For Case 2 and Case 3, the ADC code during the timestamp ADC <5> = 0, for example, at time t3 shown by case 2 or at time t4 shown by case 3, if OutB(WL) is inverted from logic 1 to logic 0, the time code (i.e., ADC code) at time t3 or time t4 is written to memory (e.g., ADC memory 150, 1550, 1650), and the ADC code <5> =0, State is set to logic 0 (i.e., State=0). Thus, in Case 2 or Case 3, when COMP_SET is set to logic 1 (or COMP_SET_n is set to logic 0) at time t5 when the immediately preceding HCG ADC starts, the initialization circuit (e.g., initialization circuit 132, 1532, 1632) unlocks the comparator (e.g., comparator 120, 1520, 1620) and the positive feedback circuit (e.g., positive feedback circuit 131, 1531, 1631), and the HCG ADC starts.

[0162] In case 2, OutB(WL) is inverted from logic 1 to logic 0 during HCG ADC. For example, at time t7, the ADC code <5> =1, the time code (i.e., ADC code) at time t7 may be written to memory (e.g., ADC memory 150, 1550, 1650) and State is set to logic 1 (i.e., State=1), which causes the comparators (e.g., comparators 120, 1520, 1620) and positive feedback circuits (e.g., positive feedback circuits 131, 1531, 1631) to lock again. In Case 2, if State is kept at logic 1 (i.e., State=1) for the remainder of the current cycle of ADC operation, the ADC code stored in memory during HCG ADC will be kept until the current cycle of ADC operation ends at time t9, even when COMP_SET is made logic 1 before entering LCG ADC.

[0163] In Case 3, OutB(WL) is inverted from logic 1 to logic 0 during the LCG ADC, for example, at time t. At time t, STATE DATA=0, so data is written to memory (e.g., ADC memory 150, 1550, 1650) and State is set to logic 0 (i.e., State=0).

[0164] FIG. 20 is a schematic representation of an exemplary DPS image sensing system 2000 according to one or more embodiments. Any of the active pixels and their components described above may be incorporated into the DPS image sensing system 2000. In some embodiments, the DPS image sensing system 2000 includes some features and components similar to those of the DPS image sensing system 100A of FIG. 1A, and the previous description may apply. In some embodiments, the DPS image sensing system 2000 may be modified to include some features and components similar to those of the DPS image sensing system 100B of FIG. 1B, and the previous description may also apply. The DPS image sensing system 2000 may occupy a small area while having high-density memory, which can improve efficiency and is easily deployable. In some embodiments, write control may be performed with a single latch circuit, even when many iterations of the ADC are applied. In this way, the DPS image sensing system 2000 provides a simple yet robust arrangement with independently located comparators and memory areas, and can provide efficient memory utilization with a small footprint. Additionally, the flexible combination of flag bits and ADC data can efficiently allocate memory, as discussed in further detail below.

[0165] In some embodiments, the DPS image sensing system 2000 includes an active pixel 2010, a comparator 2020, a write control circuit 2030 including a state latch 2040, and an ADC memory 2050 operably coupled to a read / write data bus 2060. In some embodiments, the active pixel 2010 includes a lateral in-pixel overflow accumulation capacitance (LOFIC). In some embodiments, the active pixel 2010 may function similarly to the active pixel 210 of FIGS. 2A and 2B, and the previous description may apply. The active pixel 2010 may be configured for bidirectional charge transfer and full charge transfer via induced electron drift current, as discussed above. In some embodiments, the active pixel 2010 includes a photodiode (PD), a transfer gate (TG), a floating diffusion node (FD), and one or more control transistors (e.g., RST, DCG, Vbn_sf). Active pixel 2010 may be referred to interchangeably herein as a first tier sensor-on-chip (SOC) pixel, a first tier SOC active pixel, and / or a SOC active pixel.

[0166] In some embodiments, the comparator 2020, the write control circuit 2030, the state latch 2040, and the ADC memory 2050 may form a second tier application specific integrated circuit (ASIC) active pixel, which may be referred to interchangeably herein as a second tier active pixel and / or a second tier ASIC pixel.

[0167] In some embodiments, the write control circuit 2030 and / or the state latch 2040 may facilitate state control for the ADC memory 2050. As discussed in further detail below, the DPS image sensing system 2000 may implement a novel write control scheme implemented on the write control circuit 2030 for multiple ADC operations within a DPS with efficient memory usage and small pixel area. For example, in some embodiments, the state latch 2040 works independently of the n-bit ADC memory 2050 to control the comparator 2020 operation. The flag bits 2052 may be implemented as an ADC ID. In some embodiments, the flag bits 2052 may be written as part of the n-bit ADC memory 2050 combined with the ADC data bits 2054.

[0168] In some embodiments, the write control implemented via the write control circuitry 2030 for multiple ADC operations may be applied according to the following method. (1) In the first case, when state=0 is output from the state latch 2040, a write operation to write to memory (e.g., ADC memory 2050) may be activated and data may be written via the comparator 2020 flipping. (2) In the second case, when state=1 is output from the state latch 2040, write operations may be disabled.

[0169] In some embodiments, the state latch 2040 may operate according to the following write scheme. (1) Initialize the state to state=0. (2) Provides a control signal COMP_CHECK as a working window term for each ADC operation. (3) Determine state=0 or state=1 based on the comparator (e.g., comparator 2020) output during the window term. (4) When state becomes state=1, the memory (e.g., ADC memory 2050) cannot be written and the memory holds the last ADC data. (5) Flag bits for ADC ID are combined with ADC data for each ADC operation.

[0170] As described herein, only one latch circuit (e.g., state latch 2040) is used to control multiple iterations of the ADC operation, and the latch circuit is effective in using more iterations of the ADC operation. In some embodiments, flag bits 2052 may be flexibly combined with ADC data bits 2054 in ADC memory 2050 to obtain the most efficient memory usage. Moreover, control signal COMP_CHECK may also be referred to interchangeably herein as "COMP_CHECK" and / or a comparator check signal.

[0171] The ADC memory 2050 may include word lines (WL) and N bit lines (BL) (e.g., bit line m through bit line N), where the Nth bit line may operate as a read / write data bus 2060. The structure of the word lines and bit lines may depend on the type of memory implemented by the DPS image sensing system 2000. For example, the ADC memory 2050 may implement an SRAM memory structure, such that the bit lines are differential pairs of wires. In some embodiments, the ADC memory 2050 may utilize a flash memory structure, a DRAM memory structure, a non-volatile memory device, a volatile memory, other types of solid-state memory devices, and / or a disk drive memory device.

[0172] In some embodiments, ADC operations may be performed as write operations on ADC memory 2050. Write control circuit 2030 may control word line WL based on the output of comparator 2020 (e.g., output COMP_OUT). Read / write data bus 2060 may provide counter data synchronized with ramp waveform VRAMP. The counter data at the flipping of output COMP_OUT may be stored in ADC memory 2050. The written memory data may be read and controlled by signal WL_READ.

[0173] In some embodiments, digital pixel sensors require efficient use of physical area (e.g., on-chip space) due to small pixel size. Multiple ADC operations with different sensitivities to the active pixel can be effective for high dynamic range. To conserve memory area, the ADC data may be stored in memory (e.g., ADC memory 2050) along with a flag bit 2052 used as an identifier to distinguish each ADC operation. In some embodiments, a one-bit state latch (e.g., state latch 2040) may be applied for efficient memory usage. The state latch 2040 may be independently located as part of the write control circuit 2030 within the DPS image sensing system 2000. Doing so may provide a robust architecture and an improvement over known memory write schemes in which the flag bit memory is separated from the data bit memory, and may also be used as part of the write control circuit 2030.

[0174] Any one or more of the active pixels described by the embodiments from Figures 2A-14 may be implemented as active pixel 2010 of Figure 20, provided that appropriate modifications to the circuitry of DPS image sensing system 2000 are made as would be understood by one skilled in the art.

[0175] FIG. 21 is a schematic representation of an exemplary DPS image sensing system 2100 including a write control circuit 2130 and a data memory according to one or more embodiments. The DPS image sensing system 2100 is an exemplary embodiment of the DPS image sensing system 2000 of FIG. 20, and the previous description may apply. In some embodiments, the write control circuit 2130 may include a state latch 2140 and one or more write control transistors 2142. The write control circuit 2130 may be initialized with a zero state (e.g., state=0) by setting STATE_RST=1 and a signal from COMP_OUT by connecting the word line (WL) to WL_WRITE. In some embodiments, COMP_CHECK may be set to 1 (e.g., COMP_CHECK=1) and applied to determine whether COMP_OUT has flipped (e.g., COMP_OUT=1) or not (e.g., COMP_OUT=0) at appropriate times during each ADC operation, which will be discussed in further detail below.

[0176] Any one or more of the active pixels described by the embodiments from Figures 2A-14 may be implemented as active pixels of the DPS image sensing system 2100 of Figure 21, as long as appropriate modifications to the circuitry of the DPS image sensing system 2100 are made as would be understood by one skilled in the art.

[0177] FIG. 22 is a timing diagram 2200 of an example operation of an ADC according to one or more embodiments. The timing diagram 2200 may illustrate 2Q ADC operation. For example, a 5-bit memory may be allocated as one flag bit and four ADC data bits. In some embodiments, the 2Q operation may be combined with a timestamp ADC and a linear ADC. This achieves the technical effect of reducing the complexity of the read operation and circuitry because state latch data is not required to perform the read. Additionally, one memory bank is used to read the combined flag bits and ADC data bits. This facilitates the additional technical effect of improving small pixels when pixel size is limited by the number of wires. Memory arrays are typically very dense, so simplifying the wiring scheme results in a smaller pixel size, even if additional state latches are required.

[0178] In timing diagram 2200, for Case 1, COMP_CHECK=1 may be applied, including the end timing for the timestamp ADC portion of the ADC cycle. When comparator 2120 flips at time t2 during the first ADC of the timestamp ADC, the output of comparator 2120 becomes COMP_OUT=1 at the end of the first ADC, and the state value also becomes state=1. As shown by Case 1, any time up to and including COMP_CHECK=1 at the end of the first ADC at time t3 may be used for COMP_CHECK. The state=1 indicates that word line WL is connected to WL_READ. This means that memory will not be overwritten after state=1. At time t4, comparator 2120 flips from the logic 1 state to the logic 0 state, but the state remains at the logic 1 state. At time t5, comparator 2120 flips back to the logic 1 state (e.g., COMP_OUT=1) during the linear ADC portion of the ADC operation. However, in Case 1, State remains fixed at State=1 throughout the linear ADC portion until the end of the ADC operation at time t8.

[0179] In timing diagram 2200, for Case 2, when comparator 2120 is not flipped during the first ADC of the timestamp ADC, write control circuit 2130 may remain at state=0 and word line WL may still be connected to WL_WRITE. At time t7, during the linear ADC portion, comparator 2120 flips from logic 0 to logic 1 (e.g., COMP_OUT=1) and state also flips to State=1. In some cases, memory may then be written during the next (e.g., subsequent) linear ADC.

[0180] 23A-23C are schematic representations of exemplary data structures 2300, 2320, and 2340, according to one or more embodiments. Data structures 2300, 2320, and 2340 may represent ADC data structures having a combination of flag bits and ADC data bits. Some embodiments include a four-ADC case, as illustrated by data structures 2320 and 2340 in FIGS. 23B and 23C, respectively. In some embodiments, three ADCs have fewer advantages than the four-ADC case.

[0181] The data structure 2300 in FIG. 23A corresponds to a three-ADC case. In FIG. 23A, the data structure 2300 may include two flag bits if the flag bits are independently positioned. The ADC data bits for the ADCs may be N−2 bits in the data structure 2300. In some embodiments, a digital pixel sensor system may enable the use of 1.5 flag bits as shown by the data structure 2300. Each flag bit may be assigned as “00” for ADC1, “01” for ADC2, and “1” for ADC3. Thus, N−1 bits may be assigned to ADC3. Therefore, higher resolution is available for the same memory bit, and a one-state latch for write control can be efficient given the physical area of ​​the system. Furthermore, write control using a one-state latch improves the robustness and simplicity of the pixel structure, which provides a significant technical advantage when increasing the number of ADC operations.

[0182] Data structures 2320 and 2340 in Figures 23B and 23C, respectively, illustrate an example use case including four ADCs. In data structure 2320, two (2) flag bits are allocated equally to each of the four ADC operations, each with a resolution of N-2 bits. In data structure 2340, different flag bit and resolution schemes may be used. For example, in a higher resolution ADC operation (e.g., ADC4), N-1 ADC data bits are available with one flag bit. Because ADC4 includes N-1 ADC data bits and one flag bit in the example data structure 2340, lower resolution ADC operations (e.g., ADC1 and ADC2) may have N-3 ADC data bits with three flag bits as a tradeoff. This may allow data structure 2340 to still achieve higher resolution even when using one ADC, which may be advantageous for multiple ADC operations in a digital pixel sensor (e.g., sensing front-end circuit 112). The flexible flag bit arrangement of data structures 2320 and 2340 may provide the technical effect of improving memory usage efficiency.

[0183] FIG. 24 is a timing diagram 2400 of an example operation of an ADC according to one or more embodiments. In some embodiments, the timing diagram 2400 illustrates three ADC quantization operations utilizing a write control circuit, such as the write control circuit 2130 of FIG. 21. In the timing diagram 2400, the ADC states include a timestamp ADC operation and two linear ADC operations. In some embodiments, one of the two linear ADC operations may be configured for a low conversion gain (LCG), and one of the two linear ADC operations may be configured for a high conversion gain (HCG). The three ADC operations may occur during one exposure period (e.g., the period of time during which a pixel of the DPS image sensing system 2100 is exposed to incident light). In some embodiments, a 5-bit memory case may be implemented along with a flag bit, as indicated by the ADC codes in the timing diagram 2400.

[0184] Timing diagram 2400 includes three use cases illustrating three different behaviors of comparator 2120. In the first case, "Case 1," a large signal level is present. In Case 1, a comparator (e.g., comparator 2120) flips from logic 0 to logic 1 (e.g., COMP_OUT=1) at time t3 during a first ADC operation (e.g., a timestamp ADC operation). Then, state flips from State=0 to State=1. After state becomes State=1, no memory is written to ADC memory 2150 and the first ADC data bit is preserved throughout the duration of the ADC operation.

[0185] In the second case, "Case 2," there is an intermediate signal level. In Case 2, a comparator (e.g., comparator 2120) flips from logic 0 to logic 1 (e.g., COMP_OUT=1) at time t5 during a second ADC operation (e.g., an LCG ADC operation). The state then flips from State=0 to State=1. Additionally, during the second ADC operation (e.g., an LCG ADC operation), a second ADC data bit is stored when COMP_CHECK=1.

[0186] In the third case, "Case 3," there is a low signal level. In Case 3, a comparator (e.g., comparator 2120) flips from logic 0 to logic 1 (e.g., COMP_OUT=1) at time t7 during the second ADC operation. However, in Case 3, COMP_CHECK=0 when the comparator flips, so the state may be kept as State=0. COMP_CHECK=0 may be assigned to a very small signal term in an LCG ADC operation. The memory (e.g., ADC memory 2150) may be rewritten during the third ADC operation (e.g., an HCG ADC operation).

[0187] 25 is a schematic representation of an exemplary system 2500 including a comparator 2520, a write control circuit 2530, and a state latch 2540, according to one or more embodiments. In some embodiments, one or more components of system 2500 may be included within DPS image sensing system 2000. Write control circuit 2530 includes a positive feedback circuit 2531 that outputs a feedback signal FB. After positive feedback circuit 2531 flips FB from 0 to 1, FB=1 may be maintained regardless of the value of output “OutA” of comparator 2520. COMP_SET_n may then be set to 1 (e.g., COMP_SET_n=1) for an initialization operation to set OutB of write control circuit 2530 to 1 (e.g., OutB=1) and FB to 0 (e.g., FB=0).

[0188] In some embodiments, the initialization operation may begin by setting State=0. When COMP_SET_n is also set to 1 (e.g., COMP_SET_n=0), the initialization is complete because OutB becomes 1 (e.g., OutB=1). The state latch 2540 may output "State" to control the initialization operation, and the comparator 2520 only functions for State set to 0 (e.g., State=0).

[0189] In some embodiments, the operation of the comparator 2520 may be as follows. (1) Perform auto-zero operation using COMP_RST=1 with VRAMP at reset level. (2) After COMP_RST becomes COMP_RST=0, the initialization operation is completed with COMP_SET_n=0 and VRAMP at the start level. Additionally, OutB becomes OutB=1 when State=0, or OutB=0 when State=1. (3) The VRAMP ramp-up operation is performed in the former case, and ADC data can be written to the ADC memory when comparator 2520 flips. Additionally, OutB is kept at OutB=0, and data is not written to the memory because word line WL=0.

[0190] In some embodiments, OutA=0 (e.g., GND) can be set with an appropriate VRAMP voltage after auto-zero operation, so the switch controlled by COMP_SET_n between OutA and GND may be removed. OutB may become OutB=1 when COMP_SET_n=0, and State=0 is added with an appropriate VRAMP voltage. In some embodiments, STATE_DATA may be connected to the state latch 2540 and may be combined with two inverters through an nMOS transistor pair using a switch, as shown in FIG. 25. In this case, when the comparator 2520 causes the word line WL to go from 1 to 0 (e.g., from WL=1 to WL=0), the state node is fixed as State=STATE_DATA upon the flipping of the comparator 2520. The ADC memory (e.g., ADC memory 2050) may also simultaneously store bit line data. STATE_DATA is intentionally controlled to be set to an appropriate state.

[0191] Any one or more of the active pixels described by the embodiments from Figures 2A-14 may be implemented as active pixels of DPS image sensing system 2500 of Figure 25, as long as appropriate modifications to the circuitry of DPS image sensing system 2500 are made as would be understood by one skilled in the art.

[0192] 26 is a schematic representation of an exemplary system 2600 including a comparator 2620, a write control circuit 2630, and a state latch 2640. In some embodiments, an nMOS transistor 2634 may be added to the write control circuit 2630 as a CMOS structure for both the COMP_SET_n signal and the FB signal, compared to the write control circuit 2530 of FIG. 25. In some embodiments, the flipping of the positive feedback circuit of the write control circuit 2630 can be accelerated with the nMOS transistor 2634. An nMOS switch may also be added to the write control circuit 2630 between OutA of the comparator 2620 and ground (GND). This may prevent large delays when performing initialization of the system 2600 for large values ​​of capacitor CL.

[0193] Any one or more of the active pixels described by the embodiments from Figures 2A-14 may be implemented as active pixels in system 2600 of Figure 26, as long as appropriate modifications to the circuitry of DPS image sensing system 2600 are made as would be understood by one skilled in the art.

[0194] 27 is a timing diagram 2700 of an example operation of an ADC according to one or more embodiments. In some embodiments, the timing diagram 2700 may describe three overlapping quantization operations that may use the comparator 2620 of FIG. 26. In some embodiments, the three quantization operations described by the timing diagram 2700 may be the same as or similar to the three quantization operations described in the timing diagram 2400 of FIG. 24, but the order of the HCG ADC and LCG ADC operations is reversed.

[0195] As seen in timing diagram 2700, during HCG ADC operation, a dark signal for flipping to a high VRAMP voltage is preferably stored as HCG ADC data, and a light signal level for flipping to a low VRAMP voltage is preferably overwritten by LCG ADC data. Timing diagram 2700 presents three use cases: Case 1, Case 2, and Case 3. In Case 1, output OutB flips once from logic 0 to logic 1. In Case 2, output OutB flips twice from logic 0 to logic 1. In Case 3, output OutB flips three times from logic 0 to logic 1. When OutB flips from 1 to 0 (e.g., from OutB=1 to OutB=0), if STATE_DATA=1, state can go from 0 to 1 (e.g., from state=0 to state=1).

[0196] In some embodiments, the combination of a positive feedback circuit and a state latch structure (e.g., state latch 2640) shown in FIGS. 25-26 may be versatile. For example, when COMP_CHECK=1, the state latch 2140 sets state to 1 (e.g., state=1) in response to detecting OutA=0, so the comparator 2120 of FIG. 21 cannot perform the aforementioned operation. The data stored in the HCG ADC operation may be pre-flipped rather than overwriting the data using the LCG ADC operation, but the flipping timing is reversed. Therefore, the DPS image sensing system 2100 employs a control scheme that may be problematic in this particular use case. On the other hand, when the comparator 2520 flips, the state signal of the state latch 2540 is STATE_DATA, making the system 2500 more flexible than the DPS image sensing system 2100 for the aforementioned use case, so the system 2500 may be more suitable for this particular use case.

[0197] 28A-28C are schematic representations of exemplary data structures 2800, 2820, and 2840, according to one or more embodiments. One or more embodiments are additionally described herein relating to methods for using data structures 2800, 2820, and / or 2840 to provide efficient memory usage for multiple ADC operations within a digital pixel sensor system. Data structures 2800, 2820, and 2840 are configured for use in systems having pixel structures including active pixels with photodiodes, comparators, n-bit memories, state latches for state control, or other components. For example, data structures 2800, 2820, and 2840 may be used with a DPS imaging sensing system, such as DPS image sensing system 2000. In some embodiments, data structures 2800, 2820, and 2840 may be configured for use within write control circuits, such as write control circuit 130 of FIG. 1, write control circuit 2030 of FIG. 20, and other write control circuits described herein. As discussed above, the state latch circuitry may work independently of the memory to control the comparator operation. In some embodiments, flag bits in the memory that may be used as an ADC identifier may be written as part of the n-bit memory and combined with the ADC data (e.g., ADC data bits).

[0198] Data structure 2800 of Figure 28A may be configured for use in a case where three ADC operations are performed. Data structures 2820 and 2840 may each be configured for use in a case where four ADC operations are performed. For many DPS systems, the majority of the area is consumed by the memory portion, regardless of the type of memory implemented (e.g., SRAM, DRAM, etc.). This can be particularly true in cases where multiple ADC operations are performed, since each ADC operation requires at least N bits of memory.

[0199] In some embodiments, a write control circuit (e.g., write control circuit 2030) used for multiple ADC operations may utilize data structures 2800, 2820, and / or 2840. In some embodiments, data structures 2800, 2820, and 2840 may combine flag bits and ADC data bits. Data structures 2800, 2820, and 2840 provide efficient memory usage by providing flexibility for various resolution allocations. Using combinations of flag bits and ADC data bits of different lengths, different ADC resolutions can be applied to each ADC operation, providing the technical effect of providing flexible communication of flag bits and ADC data bits that can be allocated to memory in an efficient manner. Higher resolutions may be allocated to N-1 ADC data bits regardless of how many ADC operations are performed. Additionally, using the most significant bit (MSB) for state control can save several memory bits.

[0200] In some embodiments, data structure 2800 may allow 1.5 flag bits to be used. For data structure 2800, the flag bits associated with the first ADC operation (e.g., ADC1) may be assigned a value of “0 0,” the flag bits associated with the second ADC operation (e.g., ADC2) may be assigned a value of “0 1,” and the flag bits associated with the third ADC operation (e.g., ADC3) may be assigned a value of “1.” Data structure 2800 allows N−1 bits to be assigned to the last ADC operation (e.g., ADC3), allowing higher resolution to be available on the same memory bit. In some embodiments, one state latch is included for write control, which may be area efficient. Some embodiments may include two flag bits and logic circuitry for one write control signal. In some embodiments, a write control circuit with one state latch allows for an improved, simpler, and simplified pixel structure that is efficient for an increased amount of ADC operations.

[0201] In some embodiments, the data structure 2820 includes four ADC operations. For the data structure 2820, the flag bits associated with the first ADC operation (e.g., ADC1) may be assigned values ​​“0 0 0,” the flag bits associated with the second ADC operation (e.g., ADC2) may be assigned values ​​“0 0 1,” the flag bits associated with the third ADC operation (e.g., ADC3) may be assigned values ​​“0 1,” and the flag bits associated with the fourth ADC operation (e.g., ADC4) may be assigned values ​​“1.” The data structure 2820 includes a 3-bit flag bit for the first and second ADC operations, a 2-bit flag bit for the third ADC operation, and a 1-bit flag bit for the fourth ADC operation. Additionally, the ADC data bits may be N-3 bits for the first ADC operation and the second ADC operation, and N-2 bits for the third ADC operation and the fourth ADC operation.

[0202] In some embodiments, data structure 2840 includes four ADC operations, each with a resolution (e.g., the resolution of each ADC operation) of N-2 bits. For data structure 2840, the flag bits associated with the first ADC operation (e.g., ADC1) may be assigned a value of “0 0”, the flag bits associated with the second ADC operation (e.g., ADC2) may be assigned a value of “0 1”, the flag bits associated with the third ADC operation (e.g., ADC3) may be assigned a value of “1 0”, and the flag bits associated with the fourth ADC operation (e.g., ADC4) may be assigned a value of “1 1”.

[0203] When flag bits are assigned similarly to data structures 2820 and 2840, the most significant bit can be used as a status signal. For example, the most significant bit of the last ADC operation stored by data structure 2820 is "1." The most significant bit of each of the other ADC operations stored by data structure 2820 is "0." Data structures 2820 and 2840 allow for flexible flag bit arrangements, which provides the technical effect of improving the efficiency of memory usage by the digital pixel sensing system.

[0204] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprises" or "includes" does not exclude the presence of elements or steps other than those listed in a claim. In a device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. In any device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that several elements are recited in mutually different dependent claims does not indicate that these elements cannot be used in combination.

[0205] While the description provided above provides details for illustrative purposes based on what are presently believed to be the most practical and preferred embodiments, it should be understood that such details are for that purpose only, and that the present disclosure is not limited to the explicitly disclosed embodiments, but on the contrary, is intended to cover modifications and equivalent arrangements that are within the spirit and scope of the appended claims. For example, it should be understood that the present disclosure contemplates that, to the extent possible, one or more features of any embodiment can be combined with one or more features of any other embodiment.

[0206] Additional exemplary embodiments comprise reference to the enumerated embodiments below. A1. A back-end analog-to-digital conversion (ADC) and memory circuit, the back-end ADC and memory circuit comprising: a comparator operatively coupled to the active pixel and configured to receive the output of the active pixel; a write control circuit; an ADC memory operably coupled to the write control circuit; a state latch operably coupled to the write control circuit, the state latch configured to control whether writing to the ADC memory is enabled or disabled; Equipped with. A2. The back-end ADC and memory circuit of embodiment A1, wherein the ADC operation is controlled using a state latch. A3. The back-end ADC and memory circuit of embodiment A2, wherein the state latch is configured to output a 1-bit Boolean control signal to control the ADC operation. A4. The back-end ADC and memory circuit of any one of embodiments A1-A3, wherein the ADC operation includes at least one of a timestamp ADC operation, a high conversion gain ADC operation, or a low conversion gain ADC operation. A5. The back-end ADC and memory circuit of any one of embodiments A1 to A4, wherein the control signal output from the state latch controls whether writing to the ADC memory is enabled or disabled by flipping a word line operably coupled to the ADC memory. A6. The back-end ADC and memory circuit of any one of embodiments A1 to A5, wherein the write control circuitry comprises: a positive feedback circuit configured to receive as a first input the output from the comparator and as a second input the output of the positive feedback circuit; Equipped with. A7. The back-end ADC and memory circuit of embodiment A6, wherein the positive feedback circuit comprises an inverter. A8. The back-end ADC and memory circuit of any one of embodiments A1-A7, wherein the write control circuitry includes an initialization circuit comprising a pair of transistors configured to function as a NAND gate. A9. The back-end ADC and memory circuit of any one of embodiments A7-A8, wherein the positive feedback circuit is in a locked state when the output of the positive feedback circuit is at a first value. A10. The back-end ADC and memory circuit of embodiment A9, wherein the first value comprises a logic zero or a logic one. A11. The back-end ADC and memory circuit of embodiments A8-A10, wherein the initialization circuit is configured to unlock the positive feedback circuit using the control signal output from the state latch. A12. The back-end ADC and memory circuit of any one of embodiments A1 to A10, wherein the write control circuitry comprises: a first transistor associated with the output of the comparator; a positive feedback circuit comprising a second transistor associated with the output of the positive feedback circuit; an initialization circuit including a transistor pair formed of a third transistor and a fourth transistor; Equipped with. A13. The back-end ADC and memory circuit of embodiment A12, wherein when the logic state of the gate of the first transistor or the logic state of the gate of the second transistor is high, the output of the write control circuit is a first value, and when both the logic state of the gate of the third transistor and the logic state of the gate of the fourth transistor are low, the output of the write control circuit is a second value. A14. The back-end ADC and memory circuit of any one of embodiments A12 to A13, wherein the output of the write control circuit is a first value when the logic state of the gate of the third transistor or the logic state of the gate of the fourth transistor is high, or the output of the write control circuit is a second value when both the logic state of the gate of the third transistor and the logic state of the gate of the fourth transistor are low. A15. The back-end ADC and memory circuit of any one of embodiments A13 to A14, wherein the first value comprises a logical one and the second value comprises a logical zero, or the first value comprises a logical zero and the second value comprises a logical one. A16. The back-end ADC and memory circuit of any one of embodiments A1-A15, wherein the write control circuitry comprises a read / write control circuitry configured to perform a read operation. A17. An imaging system, An active pixel; the back-end ADC and memory circuit of any one of embodiments A1 to A16; Equipped with. A18. The imaging system of embodiment A16, wherein the comparator is operatively coupled to the active pixel. B1. An imaging system, An active pixel; a comparator operatively coupled to the active pixel and configured to receive the output of the active pixel; a back-end ADC analog-to-digital conversion (ADC) and memory circuit operably coupled to the active pixel; and the back-end ADC and memory circuitry comprises: a read / write control circuit; an ADC memory operably coupled to a read / write data bus and a read / write control circuit; A state latch operably coupled to the read / write control circuit and the ADC memory It is equipped with: B2. The imaging system of embodiment B1, wherein the read / write control circuitry comprises: a NAND gate operatively coupled to the state latch; a NOR gate operatively coupled to the comparator; a switch configured to couple a NAND gate and a NOR gate; Equipped with The NAND gate receives as inputs the first signal output from the state latch and the second signal for setting the read / write control circuit, and the NOR gate receives as inputs the comparator output signal output from the comparator and the NAND output signal output by the NAND gate. B3. The imaging system of embodiment B2, an inverter device operably coupled to the NOR gate and the ADC memory such that the inverter device inverts the value of the output of the NOR gate; Further provided are: B4. The imaging system of embodiment B3, wherein to begin the analog-to-digital conversion process, the second signal is set to a first value, coupling the switch to the NAND gate and the NOR gate, and the comparator output signal has an output value. B5. The imaging system of any one of embodiments B3 to B4, wherein, in response to the first signal being set to a second value, the output of the NAND gate has a value of zero, the output of the NOR gate has a value of one, and the comparator (i) is initialized by the node at the output of the inverter device having a value of zero, and (ii) causes the second signal to have a value of zero. B6. The imaging system of embodiment B4, wherein the first value is a logical one or a logical zero, the second value is a logical zero or a logical one, and the output value is zero, respectively. B7. The imaging system of any one of embodiments B3 to B6, wherein in response to the first signal being set to a value of zero, the node at the output of the inverter device is held at a value of one after the second signal is set to have a value of zero. B8. The imaging system of any one of embodiments B3 through B7, wherein data is written to the ADC memory by the comparator in response to the first signal being set to a value of one. B9. The imaging system of any one of embodiments B3 to B8, wherein the auto-zero operation is performed on the comparator by setting a comparator reset signal to have a value of 1, and the comparator receives as inputs: (i) the comparator reset signal or the output of the active pixel, and (ii) a ramp voltage set to a reset level. B10. The imaging system of embodiment B9, wherein an auto-zero operation is performed before each ADC operation by setting the comparator reset signal to have a value of one. B11. The imaging system of any one of embodiments B9 to B10, wherein an initialization operation is performed on the comparator after the auto-zero operation, the initialization operation including a node at the output of the inverter device going from a value of one to a value of zero in response to the second signal being set to a value of the value. B12. The imaging system of embodiment B11, wherein the node at the output of the inverter has a value of zero for the first signal output from the state latch being set to a value of one, and the node at the output of the inverter is maintained at a value of one for the first signal output from the state latch being set to a value of zero. B13. The imaging system of any one of embodiments B3 to B12, a pair of nMOS transistors operatively coupled to a state latch Further provided are: B14. The imaging system of any one of embodiments B3 to B13, wherein the read / write control circuitry further comprises an nMOS transistor that increases the speed at which the value of the node at the output of the inverter device switches. B15. The imaging system of any one of embodiments B1 through B14, wherein the data structure used to store data in the ADC memory includes configured flag bits used to control the state of the back-end ADC and memory circuitry. C1. A back-end analog-to-digital conversion (ADC) and memory circuit, a read / write control circuit; an ADC memory operably coupled to a read / write data bus and a read / write control circuit; a state latch operably coupled to the read / write control circuit and the ADC memory, the back-end ADC and memory circuit operably coupled to a comparator configured to receive outputs of the active pixels, the read / write control circuit comprising: a NAND gate operably coupled to the state latch; a NOR gate operably coupled to the comparator; and a switch configured to couple the NAND gate and the NOR gate, the NAND gate receiving as inputs a first signal output from the state latch and a second signal for setting the read / write control circuit, the NOR gate receiving as inputs a comparator output signal output from the comparator and a NAND output signal output by the NAND gate; an inverter device operably coupled to the NOR gate and the ADC memory such that the inverter device inverts the value of the output of the NOR gate; Equipped with. C2. The back-end ADC and memory circuit of embodiment C1, wherein to begin the analog-to-digital conversion process, the second signal is set to a value of 1, coupling the switches to the NAND gate and the NOR gate, and the comparator output signal outputs to have a value of zero. C3. The back-end ADC and memory circuit of any one of embodiments C1 to C2, wherein, in response to the first signal being set to a value of one, the output of the NAND gate has a value of zero, the output of the NOR gate has a value of one, and the comparator (i) is initialized with the node at the output of the inverter device having a value of zero, and (ii) causes the second signal to have a value of zero. C4. The back-end ADC and memory circuit of any one of embodiments C1 to C3, wherein in response to the first signal being set to a value of zero, the node at the output of the inverter device is held at a value of one after the second signal is set to have a value of zero. C5. The back-end ADC and memory circuit of any one of embodiments C1 to C4, wherein an auto-zero operation is performed on the comparator by setting a comparator reset signal to have a value of 1, the comparator receiving as inputs (i) the comparator reset signal or the output of an active pixel, and (ii) a ramp voltage set to a reset level, and wherein the auto-zero operation is performed before each ADC operation by setting the comparator reset signal to have a value of 1. C6. The back-end ADC and memory circuit of any one of embodiments C1 to C5, wherein the node at the output of the inverter has a value of zero for the first signal output from the state latch being set to a value of one, and the node at the output of the inverter is maintained at a value of one for the first signal output from the state latch being set to a value of zero. D1. An active pixel for use in a digital pixel sensor (DPS) imaging system having full in-pixel charge transfer, comprising: a first photodiode; a first transfer gate operably coupled to the first photodiode; a second transfer gate operably coupled to the first photodiode; Equipped with The first and second transfer gates are on opposite sides of the first photodiode, and an electron drift current in the first photodiode causes a bidirectional charge transfer of the charge of the first photodiode to the first and second transfer gates. D2. The active pixel of embodiment D1, wherein an electron flow corresponding to the electron drift current is directed from a first side of the first photodiode to a second side of the first photodiode, and the first transfer gate and the second transfer gate are located on the second side of the first photodiode. D3. The active pixel of any one of embodiments D1-D2, wherein the first transfer gate and the second transfer gate include an active layer configured as a floating diffusion layer, intersecting the poly layer and the charge well layer. D4. The active pixel of any one of embodiments D1-D3, a first floating diffusion node operably coupled to the first transfer gate; a second floating diffusion node operably coupled to the second transfer gate; Further provided are: D5. The active pixel of any one of embodiments D1-D3, a floating diffusion node operably coupled to the first transfer gate; a drain operatively coupled to the second transfer gate and configured to receive the charge output by the second transfer gate; Further provided are: D6. The active pixel of any one of embodiments D1 through D5, wherein the electron drift current is generated in response to an electric field being applied to the active pixel based on an impurity concentration gradient in the first photodiode. D7. The active pixel of any one of embodiments D1 to D3 and D6, a second photodiode; and a third transfer gate operably coupled to the second photodiode; a fourth transfer gate operably coupled to the second photodiode; Furthermore, A third transfer gate and a fourth transfer gate are present on either side of the second photodiode, and an electron drift current in the second photodiode causes a bidirectional charge transfer of the charge of the second photodiode to the third transfer gate and the fourth transfer gate. D8. The active pixel of embodiment D7, wherein the electron drift current is directed from a first side of the second photodiode to a second side of the second photodiode, the direction of the electron drift current in the first photodiode is opposite to the direction of the electron drift current in the second photodiode, and the third transfer gate and the fourth transfer gate are located on the second side of the second photodiode. D9. The active pixel of any one of embodiments D7-D8, wherein the third transfer gate and the fourth transfer gate are asymmetrically on opposite sides of the second photodiode. D10. The active pixel of any one of embodiments D8 to D9, a first floating diffusion node operably coupled to the first transfer gate and the third transfer gate; a second floating diffusion node operably coupled to the second transfer gate and the fourth transfer gate; Further provided are: D11. The active pixel of any one of embodiments D8 to D9, a first floating diffusion node operably coupled to the first transfer gate and the third transfer gate; a drain operably coupled to the second transfer gate and the fourth transfer gate; Further provided are: D12. The active pixel of embodiments D7-D8, a third photodiode; and a fourth photodiode; and a fifth transfer gate operably coupled to the third photodiode; a sixth transfer gate operably coupled to the third photodiode; a seventh transfer gate operably coupled to the fourth photodiode; an eighth transfer gate operably coupled to the fourth photodiode; Furthermore, The fifth and sixth transfer gates are on either side of the third photodiode, and the seventh and eighth transfer gates are on either side of the fourth photodiode. D13. The active pixel of embodiment D12, wherein the fifth and sixth transfer gates are asymmetrically on opposite sides of the third photodiode. D14. The active pixel of any one of embodiments D12-D13, wherein the seventh and eighth transfer gates are asymmetrically on opposite sides of the fourth photodiode. D15. The active pixel of any one of embodiments D11 to D14, wherein an electron flow corresponding to an electron drift current in the third photodiode causes a bidirectional charge transfer of the charge of the third photodiode to the fifth transfer gate and the sixth transfer gate, and an electron drift current in the fourth photodiode causes a bidirectional charge transfer of the charge of the fourth photodiode to the seventh transfer gate and the eighth transfer gate. D16. An active pixel of any one of claims D11 to D15, a first drain operably coupled to the first transfer gate of the first photodiode and the third transfer gate of the second photodiode; a second drain operably coupled to the sixth transfer gate of the third photodiode and the eighth transfer gate of the fourth photodiode; a floating diffusion node operably coupled to the second transfer gate of the first photodiode, the fourth transfer gate of the second photodiode, the fifth transfer gate of the third photodiode, and the seventh transfer gate of the fourth photodiode; Further provided are: D17. An active pixel of any one of claims D11 to D15, a first floating diffusion node operably coupled to the first transfer gate of the first photodiode and the third transfer gate of the second photodiode; a second floating diffusion node operably coupled to the second transfer gate of the first photodiode, the fourth transfer gate of the second photodiode, the fifth transfer gate of the third photodiode, and the seventh transfer gate of the fourth photodiode; a third floating diffusion node operably coupled to the sixth transfer gate of the third photodiode and the eighth transfer gate of the fourth photodiode; Further provided are: D18. The active pixel of any one of embodiments D1 to D17, wherein an electron drift current causes a bidirectional charge transfer of charge in the first photodiode to the first transfer gate and the second transfer gate, the electron drift current being formed in response to an electric field being generated in the first photodiode. D19. The active pixel of embodiment D15, wherein the first photodiode comprises a first layer and a second layer, and the electric field is generated within the first photodiode based on the first photodiode having an impurity concentration gradient resulting from the first layer and the second layer, each having a different impurity concentration. D20. The active pixel of embodiment D19, wherein the first photodiode includes at least one additional layer having an impurity concentration different from the first and second layers, and the magnitude and direction of the electric field are adjusted based on the number of layers included in the first photodiode. D21. The active pixel of any one of embodiments D1 through D20, wherein the first photodiode is a bidirectional charge transfer photodiode. D22. The active pixel of any one of embodiments D1 to D21, wherein the active pixel implements backside illumination and a buried photodiode. D23. The active pixel of any one of embodiments D1 to D20, wherein a Time of Flight (ToF) measurement is determined using the active pixel. D24. The active pixel of any one of embodiments D1-D23, wherein the first transfer gate and the second transfer gate are asymmetrically on opposite sides of the first photodiode. D25. A digital pixel sensor (DPS) imaging system for full in-pixel charge transfer function, the DPS imaging system comprising: One or more active pixels Equipped with Each of the one or more active pixels comprises an active pixel of any one of embodiments D1 to D24. D26. The DPS imaging system of claim D25, a capacitor operably coupled to the second floating diffusion node or the drain; Further provided are: E1. An application specific integrated circuit (ASIC) active pixel, a comparator configured to receive the output of the photodiode of the SOC active pixel; a read / write control circuit operably coupled to the comparator and the state latch, the read / write control circuit configured to receive an output from the comparator and determine whether a read operation or a write operation should occur based on the output from the comparator and the state of the state latch; an analog-to-digital conversion (ADC) memory operably coupled to the read / write control circuit and the read / write data bus; Equipped with. E2. The ASIC active pixel of embodiment E1, wherein the ADC memory comprises a word line and a plurality of bit lines, and the read / write control circuit is configured to control the word line based on the output from the comparator. E3. The ASIC active pixel of any one of embodiments E1 to E2, wherein during initialization of the ASIC active pixel, the reset signal is used to initialize the state of the state latch to zero, and the word line is configured to couple the ADC memory to the word line write connection, the word line write connection having a value based on the output from the comparator. E4. The ASIC active pixel of any one of embodiments E1 to E3, wherein during each analog-to-digital conversion (ADC) operation, a comparator check signal is applied to the output of the comparator to determine whether the comparator flipped from a value of one to a value of zero or from a value of zero to a value of one. E5. The ASIC active pixel of any one of embodiments E1 to E4, wherein for a comparator flipping during a first analog-to-digital conversion (ADC) operation, a comparator check signal having a value of 1 is applied to the read / write control circuit at the end of the first ADC operation, the value of the state of the state latch is 1, and the word line of the ADC memory is connected to the word line read connection so that data is not overwritten in the ADC memory. E6. The ASIC active pixel of any one of embodiments E1 to E5, wherein the comparator does not flip during a first analog-to-digital conversion (ADC) operation, the value of the state of the state latch is kept at zero, and the word line of the ADC memory is connected to the word line write connection such that data is written to the ADC memory during a second ADC operation. E7. The ASIC active pixel of any one of embodiments E1 to E6, wherein the ADC memory comprises a 5-bit memory having one flag bit and 4-bit ADC data. E8. The ASIC active pixel of any one of embodiments E1 to E7, wherein for three ADC operations, the ADC memory comprises 1.5 flag bits. E9. The ASIC active pixel of embodiment E8, wherein the flag bit for a first ADC operation of the three ADC operations is assigned a value of 00, the flag bit for a second ADC operation of the three ADC operations is assigned a value of 01, the flag bit for a third ADC operation of the three ADC operations is assigned a value of 1, the ADC memory comprises N-2 bits of ADC data for the first ADC operation and the second ADC operation, and the ADC memory comprises N-1 bits of ADC data for the third ADC operation. E10. The ASIC active pixel of any one of embodiments E1 to E7, wherein for four ADC operations, the ADC memory comprises two flag bits and N-2 bits of ADC data for each of the four ADC operations. E11. The ASIC active pixel of any one of embodiments E1 to E7, wherein for four ADC operation, the ADC memory: three flag bits and N-3 bits of ADC data for the first ADC operation and the second ADC operation; two flag bits and N-2 bits of ADC data for a third ADC operation; One flag bit for the fourth ADC operation and N-1 bits of ADC data Equipped with. E12. The ASIC active pixel of any one of embodiments E1 to E11, wherein data provided by the read / write data bus is synchronized with a ramp function waveform provided as input to a comparator, and data is stored in the ADC memory based on the output of the comparator flipping. E13. The ASIC active pixel of any one of embodiments E1 to E12, wherein the ADC data is stored in an ADC memory, and the ADC data comprises one or more flag bits configured to be used as an identifier for each ADC operation performed. E14. The ASIC active pixel of any one of embodiments E1 to E13, wherein the ASIC active pixel is operatively coupled to a system-on-chip (SOC) active pixel comprising one or more photodiodes. E15. An imaging system comprising an ASIC active pixel of any one of embodiments E1 to E14. E16. An analog-to-digital conversion (ADC) circuit comprising the ASIC active pixel of any one of embodiments E1 to E14. E17. A digital pixel sensing (DPS) imaging system comprising an ASIC active pixel of any one of embodiments E1 to E14. F1. An imaging system, an active pixel comprising a photodiode and a plurality of transistors; a comparator operatively coupled to the active pixel and configured to receive the output of the active pixel; a write control circuit operably coupled to the comparator, the write control circuit configured to receive an output from the comparator; an analog-to-digital conversion (ADC) memory operably coupled to the write control circuit; Equipped with The data structure is stored in the ADC memory, the data structure configured to store at least a first data string, the first data string including a set of flag bits for identifying each ADC operation to be performed and a set of ADC data bits. F2. An imaging system of embodiment F1, wherein a write operation for writing data to the ADC memory is activated based on the most significant bit of the first data string, and the data is written to the ADC memory in response to the output of the comparator flipping. F3. The imaging system of embodiment F2, wherein the most significant bit of the first data string is assigned a first value, and the ADC memory is configured to hold an ADC code in response to an output of the comparator flipping. F4. The imaging system of any one of embodiments F2 to F3, wherein the data written to the ADC memory includes a time code written to the ADC memory during ADC operation. F5. The imaging system of any one of embodiments F1 to F4, wherein the data structure is further configured to store a second data string corresponding to a time code written to the memory during an ADC operation, the second data string including a set of flag bits for identifying each ADC operation performed and a set of ADC data bits, and the flag bit of the set of flag bits of the second data string includes the most significant bit of the time code written to the ADC memory. F6. The imaging system of embodiment F5, wherein the write control circuitry comprises: Positive feedback circuit Equipped with The ADC code is not held by the second data string due to the positive feedback circuit being held in a locked state. F7. The imaging system of embodiment F6, wherein the ADC operation comprises a final ADC operation of an ADC cycle, and wherein the ADC code written to the ADC memory is not overwritten in response to a comparator flipping. F8. The imaging system of any one of embodiments F1-F7, wherein the ADC memory comprises a memory array including a memory location having a most significant bit coupled to the write control circuit. F9. The imaging system of any one of embodiments F1 to F8, wherein the data structure includes a first data string and at least a second data string, the first data string corresponding to a first ADC operation, the second data string corresponding to a second ADC operation performed after the first ADC operation, the second data string including an additional set of flag bits and an additional set of ADC data bits, and the number of ADC data bits included in the additional set of ADC data bits of the second data string is greater than the number of ADC data bits included in the set of ADC data bits of the first data string. F10. The imaging system of any one of embodiments F1 to F9, wherein the set of flag bits and the set of ADC data bits are flexibly arranged to allow different amounts of flag bits and ADC data bits to be stored by the data structure. F11. The imaging system of any one of embodiments F1 to F10, wherein the most significant bit of the set of flag bits is used as a status signal, and when the most significant bit of the last ADC operation has a first value, the most significant bit of each subsequent ADC operation has a second value. F12. The imaging system of embodiment F11, wherein the first value comprises a logical one and the second value comprises a logical zero, or the first value comprises a logical zero and the second value comprises a logical one. F13. The imaging system of any one of embodiments F1 to F12, wherein the write control circuitry is further configured to determine whether writing is enabled or disabled based on a most significant bit of the ADC code written to the memory during the final ADC operation. G1. A back-end analog-to-digital conversion (ADC) and memory circuit, a comparator operatively coupled to the active pixel and configured to receive the output of the active pixel; a write control circuit operably coupled to the comparator and the state latch, the write control circuit configured to receive an output from the comparator; an analog-to-digital conversion (ADC) memory operably coupled to the write control circuit; Equipped with The data structure is stored in the ADC memory, the data structure configured to store at least a first data string, the first data string including a set of flag bits for identifying each ADC operation to be performed and a set of ADC data bits. G2. The back-end ADC and memory circuit of embodiment G1, wherein a write operation for writing data to the ADC memory is activated based on the most significant bit of the first data string, and the data is written to the ADC memory in response to the output of the comparator flipping. G3. The back-end ADC and memory circuit of embodiment G2, wherein the most significant bit of the first data string is assigned a first value, and the ADC memory is configured to hold an ADC code in response to the output of the comparator flipping. G4. The back-end ADC and memory circuit of any one of embodiments G2 to G3, wherein the data written to the ADC memory includes a time code that is written to the ADC memory during ADC operation. G5. The back-end ADC and memory circuit of any one of embodiments G1 to G4, wherein the data structure is further configured to store a second data string corresponding to a time code written to the memory during an ADC operation, the second data string including a set of flag bits for identifying each ADC operation performed and a set of ADC data bits, and a flag bit of the set of flag bits of the second data string including a most significant bit of the time code written to the ADC memory. G6. The back-end ADC and memory circuit of embodiment G5, wherein the write control circuitry comprises: Positive feedback circuit Furthermore, The ADC code is not held by the second data string due to the positive feedback circuit being held in a locked state. G7. The back-end ADC and memory circuit of embodiment G6, wherein the ADC operation comprises a final ADC operation of an ADC cycle, and wherein the ADC code written to the ADC memory is not overwritten in response to a comparator flipping. G8. The back-end ADC and memory circuit of any one of embodiments G1 to G7, wherein the ADC memory comprises a memory array including a memory location having a most significant bit coupled to the write control circuit. G9. The back-end ADC and memory circuit of any one of embodiments G1 to G8, wherein the data structure includes a first data string and at least a second data string, the first data string corresponding to a first ADC operation, the second data string corresponding to a second ADC operation performed after the first ADC operation, the second data string including an additional set of flag bits and an additional set of ADC data bits, and a number of ADC data bits included in the additional set of ADC data bits of the second data string is greater than the number of ADC data bits included in the set of ADC data bits of the first data string. G10. The back-end ADC and memory circuit of any one of embodiments G1 to G9, wherein the set of flag bits and the set of ADC data bits are flexibly arranged to allow different amounts of flag bits and ADC data bits to be stored by the data structure. G11. The back-end ADC and memory circuit of any one of embodiments G1 to G10, wherein the most significant bit of the set of flag bits is used as a state signal for a state latch, and when the most significant bit of the last ADC operation has a first value, the most significant bit of each subsequent ADC operation has a second value. G12. The back-end ADC and memory circuit of embodiment G11, wherein the first value comprises a logical one and the second value comprises a logical zero, or the first value comprises a logical zero and the second value comprises a logical one. G13. The back-end ADC and memory circuit of any one of claims G1 to G12, wherein the write control circuit is further configured to determine whether writing is enabled or disabled based on the most significant bit of the ADC code written to the memory during the final ADC operation. G14. An imaging system comprising the back-end ADC and memory circuitry of any one of embodiments G1 to G13. G15. The imaging system of embodiment G14, Active Pixels Furthermore, The active pixel comprises a photodiode. G16. The imaging system of any one of embodiments G14 to G15, Multiple transistors Further provided are:

Claims

1. 1. An imaging system, comprising: An active pixel; a back-end analog-to-digital conversion (ADC) and memory circuit operatively coupled to the active pixel; Equipped with The back-end ADC and memory circuit a comparator operatively coupled to the active pixel and configured to receive the output of the active pixel; a write control circuit; an ADC memory operably coupled to the write control circuit; a state latch operably coupled to the write control circuitry, the state latch configured to control whether writing to the ADC memory is enabled or disabled; Equipped with In the imaging system, the write control circuit comprises: a positive feedback circuit configured to receive as a first input the output from the comparator and as a second input the output of a positive feedback circuit; Equipped with The write control circuit and an initialization circuit comprising a pair of transistors configured to function as a NAND gate. Imaging system.

2. 2. The imaging system of claim 1, wherein the positive feedback circuit is in a locked state when the output of the positive feedback circuit is at a first value. The imaging system according to claim 1 .

3. 3. The imaging system according to claim 2, wherein the initialization circuit is configured to release the locked state of the positive feedback circuit using the control signal output from the state latch. The imaging system according to claim 2 .

4. 10. The imaging system of claim 1, wherein the positive feedback circuit comprises an inverter. The imaging system according to claim 1 .

5. 10. The imaging system of claim 1, wherein ADC operations performed by the imaging system are controlled using the state latch, the state latch being configured to output a 1-bit Boolean control signal to control the ADC operations. The imaging system according to claim 1 .

6. 6. The imaging system of claim 5, wherein the ADC operation includes at least one of a timestamp ADC operation, a high conversion gain ADC operation, or a low conversion gain ADC operation. The imaging system according to claim 5 .

7. 2. The imaging system of claim 1, wherein the control signal output from the state latch controls whether the writing to the ADC memory is enabled or disabled by flipping a word line operably coupled to the ADC memory.

8. 1. An imaging system, comprising: An active pixel; a back-end analog-to-digital conversion (ADC) and memory circuit operatively coupled to the active pixel; Equipped with The back-end ADC and memory circuit a comparator operatively coupled to the active pixel and configured to receive the output of the active pixel; a write control circuit; an ADC memory operably coupled to the write control circuit; a state latch operably coupled to the write control circuitry, the state latch configured to control whether writing to the ADC memory is enabled or disabled; Equipped with In the imaging system, the write control circuit comprises: a positive feedback circuit comprising a first transistor associated with the output of the comparator and a second transistor associated with the output of the positive feedback circuit; an initialization circuit including a transistor pair formed of a third transistor and a fourth transistor; Equipped with Imaging system.

9. 9. The imaging system according to claim 8, when the logic state of the gate of the first transistor or the logic state of the gate of the second transistor is high, the output of the write control circuit is a first value; When the logic state of the gate of the third transistor and the logic state of the gate of the fourth transistor are both low, the output of the write control circuit is a second value. The imaging system according to claim 8.

10. 9. The imaging system according to claim 8, when the logic state of the gate of the third transistor or the logic state of the gate of the fourth transistor is high, the output of the write control circuit is a first value; or When the logic state of the gate of the third transistor and the logic state of the gate of the fourth transistor are both low, the output of the write control circuit is a second value. The imaging system according to claim 8 .

11. 1. A back-end analog-to-digital conversion (ADC) and memory circuit for an imaging system, the back-end ADC and memory circuit comprising: a comparator operatively coupled to the active pixel and configured to receive the output of said active pixel; a write control circuit; an ADC memory operably coupled to the write control circuit; a state latch operably coupled to the write control circuitry, the state latch configured to control whether writing to the ADC memory is enabled or disabled; Equipped with the write control circuit is a positive feedback circuit configured to receive an output from the comparator as a first input and an output of a positive feedback circuit as a second input, wherein the positive feedback circuit is in a locked state when the output of the positive feedback circuit is a first value; and an initialization circuit configured to release the locked state of the positive feedback circuit using the control signal output from the state latch.

12. 12. The back-end ADC and memory circuit of claim 11, wherein ADC operation is controlled using the state latch, the state latch configured to output a 1-bit Boolean control signal to control the ADC operation. The imaging system according to claim 11 .

13. 12. The back-end ADC and memory circuit of claim 11, wherein a control signal output from the state latch controls whether the writes to the ADC memory are enabled or disabled by flipping a word line operably coupled to the ADC memory. The imaging system according to claim 11 .

14. 12. The back-end ADC and memory circuit of claim 11, wherein the initialization circuit comprises a pair of transistors, the pair of transistors configured to function as a NAND gate. The imaging system according to claim 11 .

15. 12. The back-end ADC and memory circuit of claim 11, wherein the write control circuitry comprises: a positive feedback circuit comprising a first transistor associated with the output of the comparator and a second transistor associated with the output of the positive feedback circuit; an initialization circuit including a transistor pair formed of a third transistor and a fourth transistor; Equipped with The imaging system according to claim 11 .

16. 16. The back-end ADC and memory circuit of claim 15, an output of the write control circuit is a first value when the logic state of the gate of the first transistor or the logic state of the gate of the second transistor is high; The logic state of the gate of the third transistor and the logic state of the gate of the fourth transistor When both of the states are low, the output of the write control circuit is a second value. The imaging system of claim 15.

17. 16. The back-end ADC and memory circuit of claim 15, The logic state of the gate of the third transistor or the logic state of the gate of the fourth transistor When the logic state is high, the output of the write control circuit is a first value; or When the logic state of the gate of the third transistor and the logic state of the gate of the fourth transistor are both low, the write control circuit output of the write control circuit is at a second value. The imaging system of claim 15.

Images