Light-emitting device and method for manufacturing the same

Abstract

To provide a light-emitting device and a manufacturing method thereof.SOLUTION: A light-emitting device includes a substrate 111, a reflective layer 109 located above the substrate, an insulating layer 106 located above the reflective layer and having an opening 106h, a light emitting stack 104 located above the insulating layer, including an active region 104b, and having an upper surface, and a non-transparent layer 114 covering a first portion of the top surface of the light emitting stack and exposing a second portion of the top surface, and the second portion is located directly above the opening.SELECTED DRAWING: Figure 1T

Description

[Technical Field]

[0001] The present invention relates to a light-emitting device and a method for manufacturing the same. [Background technology]

[0002] Light-emitting diodes (LEDs) have various applications due to their low energy consumption, long operating life, shock resistance, small volume, fast response speed, and stable wavelength of light they emit. Recently, in addition to their use in general lighting, LEDs have been increasingly used in industrial applications, such as industrial counters and sensors. Summary of the Invention [Problem to be solved by the invention]

[0003] A light emitting device and a method for manufacturing the same are provided. [Means for solving the problem]

[0004] The light-emitting device includes a substrate, a reflective layer located above the substrate, an insulating layer located above the reflective layer and having a first opening, a light-emitting stack located above the insulating layer, including an active region, and having an upper surface, and a non-light-transmitting layer covering a first portion of the upper surface of the light-emitting stack and exposing a second portion of the upper surface, the second portion being located directly above the first opening.

[0005] A method for manufacturing a light-emitting device includes the steps of forming a light-emitting stack including an active region, forming an insulating layer located above the light-emitting stack and having a first opening, forming a reflective layer located above the insulating layer, providing a substrate, bonding the substrate to the light-emitting stack so that the reflective layer is located between the substrate and the light-emitting stack, and forming a non-light-transmitting layer on the side opposite to the direction in which the light-emitting stack is bonded to the substrate, so as to cover a first portion of a surface of the light-emitting stack and expose a second portion of the surface, the position of the second portion corresponding to the position of the first opening in the insulating layer. [Brief explanation of the drawings]

[0006] [Figure 1A] 1A to 1C are schematic diagrams illustrating a light-emitting device and a method for manufacturing the same according to a first embodiment of the present invention. [Figure 1B] 1A to 1C are schematic diagrams illustrating a light-emitting device and a method for manufacturing the same according to a first embodiment of the present invention. [Figure 1C] 1A to 1C are schematic diagrams illustrating a light-emitting device and a method for manufacturing the same according to a first embodiment of the present invention. [Figure 1D] 1A to 1C are schematic diagrams illustrating a light-emitting device and a method for manufacturing the same according to a first embodiment of the present invention. [Figure 1E] 1A to 1C are schematic diagrams illustrating a light-emitting device and a method for manufacturing the same according to a first embodiment of the present invention. [Figure 1F] 1A to 1C are schematic diagrams illustrating a light-emitting device and a method for manufacturing the same according to a first embodiment of the present invention. [Figure 1G] 1A to 1C are schematic diagrams illustrating a light-emitting device and a method for manufacturing the same according to a first embodiment of the present invention. [Figure 1H] 1A to 1C are schematic diagrams illustrating a light-emitting device and a method for manufacturing the same according to a first embodiment of the present invention. [Figure 1I] 1A to 1C are schematic diagrams illustrating a light-emitting device and a method for manufacturing the same according to a first embodiment of the present invention. [Figure 1J] 1A to 1C are schematic diagrams illustrating a light-emitting device and a method for manufacturing the same according to a first embodiment of the present invention. [Figure 1K]1A to 1C are schematic diagrams illustrating a light-emitting device and a method for manufacturing the same according to a first embodiment of the present invention. [Figure 1L] 1A to 1C are schematic diagrams illustrating a light-emitting device and a method for manufacturing the same according to a first embodiment of the present invention. [Figure 1M] 1A to 1C are schematic diagrams illustrating a light-emitting device and a method for manufacturing the same according to a first embodiment of the present invention. [Figure 1N] 1A to 1C are schematic diagrams illustrating a light-emitting device and a method for manufacturing the same according to a first embodiment of the present invention. [Figure 1O] 1A to 1C are schematic diagrams illustrating a light-emitting device and a method for manufacturing the same according to a first embodiment of the present invention. [Figure 1P] 1A to 1C are schematic diagrams illustrating a light-emitting device and a method for manufacturing the same according to a first embodiment of the present invention. [Figure 1Q] 1A to 1C are schematic diagrams illustrating a light-emitting device and a method for manufacturing the same according to a first embodiment of the present invention. [Figure 1R] 1A to 1C are schematic diagrams illustrating a light-emitting device and a method for manufacturing the same according to a first embodiment of the present invention. [Figure 1S] 1A to 1C are schematic diagrams illustrating a light-emitting device and a method for manufacturing the same according to a first embodiment of the present invention. [Figure 1T] 1A to 1C are schematic diagrams illustrating a light-emitting device and a method for manufacturing the same according to a first embodiment of the present invention. [Figure 2] 1 is a schematic top view illustrating a light-emitting device according to a first embodiment of the present invention. [Figure 3] FIG. 1 is a distribution diagram showing the luminous power (Po, vertical axis on the left) and forward voltage (Vf, vertical axis on the right) of the light-emitting device corresponding to each condition of the diameter size (horizontal axis) of the first opening when the thickness of the second contact layer is 0.2 μm and 1 μm, respectively, in the first embodiment of the present invention. [Figure 4] FIG. 1 shows a distribution diagram of the luminous power (Po, right vertical axis) and the luminous power proportional (left vertical axis) at a relatively high current (300 mA) for the first embodiment of the present invention, where the multiple quantum well structure includes 18, 38, and 48 well layers, respectively, when the light-emitting device emits light in the same pulse mode. [Figure 5]FIG. 1 is a graph showing the luminous power (Po, vertical axis on the right) and the luminous power ratio (vertical axis on the left) at a relatively high current (300 mA) corresponding to the condition that the barrier layers (Barriers) included in the multiple quantum well structure have different aluminum (Al) contents when the light-emitting device emits light in the same pulse mode in the first embodiment of the present invention. [Figure 6] FIG. 2 is a cross-sectional schematic view showing a light-emitting device according to a second embodiment of the present invention. [Figure 7] FIG. 2 is a cross-sectional schematic view showing a light-emitting device according to a third embodiment of the present invention. [Figure 8A] FIG. 10 is a schematic cross-sectional view showing a light-emitting device according to a fourth embodiment of the present invention. [Figure 8B] FIG. 10 is a schematic top view illustrating a light-emitting device according to a fourth embodiment of the present invention. [Figure 9] FIG. 10 is a schematic cross-sectional view showing a light-emitting device according to a fifth embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0007] In the following examples, the concept of the invention will be described with reference to the drawings, in which similar or identical parts in the drawings or description are given the same reference numerals, and the shapes or thicknesses of elements in the drawings may be enlarged or reduced. It should be particularly noted that elements not shown in the drawings or described in the specification may be of a type known to those skilled in the art.

[0008] 1A to 1T illustrate a light-emitting device and a method for fabricating the same according to a first embodiment of the present invention. As shown in FIG. 1A, a growth substrate 101, such as gallium arsenide (GaAs), is first provided. A buffer layer 102, a first contact layer 103, and a light-emitting stack 104 are then sequentially formed on the growth substrate 101. The buffer layer 102 can be etch-resistant or more resistant to etching than the growth substrate 101 during the subsequent growth substrate 101 removal step. Depending on the etching method, for example, wet etching, a material with a relatively large difference in etching rate from the growth substrate 101 can be selected for the buffer layer 102. For example, if the growth substrate 101 is a gallium arsenide substrate, the buffer layer 102 can be made of indium gallium phosphide (InGaP) or aluminum gallium arsenide (AlGaAs). In some embodiments of the present invention, this buffer layer 102 may be omitted if there is a significant difference in the etching rates of the growth substrate 101 and the first contact layer 103 with respect to the same etchant, for example, if the etching rate of the growth substrate 101 is at least two numerical orders higher than the etching rate of the first contact layer 103, or if the etching rate of the first contact layer 103 is at least two numerical orders higher than the etching rate of the growth substrate 101. The first contact layer 103 may be, for example, 10 ‐3 It is possible to provide a low contact resistance of less than Ω-cm, and the material is, for example, n-type doped gallium arsenide (GaAs), and the doping concentration is 1×10 18 ( / cm 3 ) The light emitting stack 104 includes a first polarity semiconductor layer 104a, a second polarity semiconductor layer 104c, and an active region 104b located between the first polarity semiconductor layer 104a and the second polarity semiconductor layer 104c. The first polarity semiconductor layer 104a and the second polarity semiconductor layer 104c have different polarities, for example, the first polarity semiconductor layer 104a is an n-type semiconductor layer and the second polarity semiconductor layer 104c is a p-type semiconductor layer. The first polarity semiconductor layer 104a, the active region 104b, and the second polarity semiconductor layer 104c are formed of III-V group materials, for example, aluminum gallium indium phosphide-based materials (Al y Ga (1-y) ) 1-x In xP, and 0≦x≦1, 0≦y≦1).

[0009] Next, as shown in FIG. 1B, a second contact layer 105 having low contact resistance is formed on the light-emitting stack 104, e.g., 10 ‐3 The resistivity of the second contact layer 105 is less than Ω-cm, and the material thereof is, for example, gallium phosphide (GaP). In this embodiment, the thickness of the second contact layer 105 should not be too thick, for example, not more than 1.5 μm, or the thickness of the second contact layer 105 is between about 0.1 μm and 0.5 μm. Next, as shown in FIG. 1C, an insulating layer 106 is formed on the second contact layer 105, and the refractive index of the insulating layer 106 may be smaller than the equivalent refractive index of the light emitting stack 104. The material of the insulating layer 106 is silicon oxide (SiO x ), magnesium fluoride (MgF2), and silicon nitride (SiN x 1D , a first opening 106h is formed in the insulating layer 106 by a yellow light and etching process, penetrating the insulating layer 106, and the first opening 106h has a substantially circular shape (not shown) and a diameter D1, which is between about 20 μm and 150 μm, or between about 40 μm and 90 μm, when viewed from the insulating layer 106 toward the light-emitting stack 104.

[0010] Next, as shown in FIG. 1E, a first transparent conductive layer 107 is formed on the insulating layer 106 to cover the first opening 106h. The first opening 106h electrically connects the first transparent conductive layer 107 and the light-emitting stack 104. The magnitude of the current supplied to the light-emitting stack 104 can be controlled by adjusting the size of the first opening 106h. Then, as shown in FIG. 1F, a second transparent conductive layer 108 is formed on the first transparent conductive layer 107. The second transparent conductive layer 108 may be made of a material different from that of the first transparent conductive layer 107 and may be formed by a different method. The second transparent conductive layer 108 may have the function of promoting current diffusion in the lateral direction (i.e., the direction perpendicular to the stacking direction of the light-emitting stack 104) or function as a translucent layer. Taking into account its function as a translucent layer, the second transparent conductive layer 108 may be made of a material having a lower refractive index than the light-emitting stack 104. In order to provide the function of lateral current spreading, the thickness of second transparent conductive layer 108 is thicker than that of first transparent conductive layer 107. For example, when viewed from insulating layer 106 toward second transparent conductive layer 108, the thickness of first transparent conductive layer 107 may be between about 25 Å and 200 Å, or between 40 Å and 60 Å, and the thickness of second transparent conductive layer 108 may be between about 25 Å and 2000 Å, or between 600 Å and 1000 Å. In another embodiment of the present invention, second transparent conductive layer 108 may not be formed, and the function of second transparent conductive layer 108 may be replaced by increasing the thickness of first transparent conductive layer 107. The first transparent conductive layer 107 and the second transparent conductive layer 108 each include one material selected from the group consisting of indium tin oxide (ITO), aluminum zinc oxide (AZO), cadmium tin oxide, antimony tin oxide, zinc oxide (ZnO), zinc tin oxide, indium zinc oxide (IZO), and graphene. In this embodiment, the material of the first transparent conductive layer 107 is indium tin oxide (ITO), and the material of the second transparent conductive layer 108 is indium zinc oxide (IZO).The first transparent conductive layer 107 may be formed by an electron gun (E-gun), and the second transparent conductive layer 108 may be formed by sputtering, but the present invention is not limited thereto. In another embodiment, the first transparent conductive layer 107 and the second transparent conductive layer 108 may be formed by the same method. In addition, the density of the second transparent conductive layer 108 may be the same as or different from the density of the first transparent conductive layer 107. In this embodiment, the second transparent conductive layer 108 is denser than the first transparent conductive layer 107, i.e., the density of the second transparent conductive layer 108 is higher than the density of the first transparent conductive layer 107, which is advantageous for the lateral current diffusion.

[0011] Next, as shown in FIG. 1G, a reflective layer 109 is formed on the second transparent conductive layer 108 to reflect the light emitted by the light emitting stack 104. In this embodiment, the reflective layer 109 has a reflectivity of more than 85% to the light emitted by the light emitting stack, and the reflective layer 109 may include a metal material, such as gold (Au) or silver (Ag).

[0012] Next, as shown in FIG. 1H, a first bonding layer 110a is formed on the reflective layer 109, and a second bonding layer 110b is formed on the first bonding layer 110a. FIG. 1I shows the reversed state of FIG. 1H. Next, as shown in FIG. 1J, a permanent substrate 111 is provided, and a third bonding layer 110c is formed on the permanent substrate 111. The third bonding layer 110c and the second bonding layer 110b are then bonded together, as shown in FIG. 1K. The first bonding layer 110a, the second bonding layer 110b, and the third bonding layer 110c form a bonding structure 110. The bonding structure 110 may include a low-temperature fusion material with a melting point of 300°C or less, such as indium (In) or tin (Sn). In this embodiment, the first bonding layer 110a is made of gold (Au), the second bonding layer 110b is made of a low-temperature fusion material indium (In), and the third bonding layer 110c is made of gold (Au). At a low temperature, for example, a temperature below 300°C, the first bonding layer 110a, the second bonding layer 110b, and the third bonding layer 110c form an alloy through a eutectic reaction and bond together to form the bonding structure 110. The bonding structure 110 includes an alloy of indium (In) and gold (Au). In another embodiment, the second bonding layer 110b may be formed on the third bonding layer 110c and then bonded to the first bonding layer 110a to form the bonding structure 110. Subsequently, as shown in FIG. 1L, the growth substrate 101 is removed. In this example, the growth substrate 101 is removed by wet etching. When an etching solution of, for example, aqueous ammonia (NH3·H2O) and hydrogen peroxide (H2O2) is selected, indium gallium phosphide (In x Ga 1-x The buffer layer 102 containing indium gallium phosphide (InP, 0≦x≦1) is less susceptible to etching than the growth substrate 101, so that the light-emitting stack 104 can be prevented from being damaged during the process of removing the growth substrate 101. x Ga 1-x The buffer layer 102, which includes P, 0≦x≦1, may be further removed because it may absorb light emitted by the light-emitting stack 104. The resulting state is shown in FIG. 1M.

[0013] Next, as shown in FIG. 1N, a second opening H1 is formed on the first contact layer 103, penetrating the first contact layer 103. When viewed from the first contact layer 103 toward the permanent substrate 111, the second opening H1 is generally circular (see FIG. 2, which will be described in detail later) and has a diameter D2. The diameter D2 is approximately between 20 μm and 150 μm, or between 40 μm and 90 μm. Specifically, the second opening H1 has a cross-sectional area along line A-A' (i.e., a direction perpendicular to the stacking direction of the light-emitting stack 104). In this embodiment, the second opening H1 is formed using a yellow light and an etching method. Next, as shown in FIG. 1O, a top contact layer 112 is formed on the first contact layer 103, and the second opening H1 is extended until it penetrates the top contact layer 112. In this embodiment, the top contact layer 112 includes an alloy, for example, an alloy of three metals, such as germanium (Ge), gold (Au), and nickel (Ni). As shown in FIG. 1O, a yellow light and etching process is used to remove a portion of the periphery of each layer from the top contact layer 112 to the second contact layer 105, exposing a portion of the insulating layer 106. Next, as shown in FIG. 1P, a sidewall insulating layer 113 is formed on the sidewalls of the structure formed by removing the portion of the periphery. The sidewall insulating layer 113 includes an insulating material, such as silicon nitride (Si3N4) or silicon oxide (SiO2). In this embodiment, the sidewall insulating layer 113 is a stacked layer including silicon nitride (Si3N4) and silicon oxide (SiO2). The formation method involves first forming a stacked layer of silicon nitride (Si3N4) and silicon oxide (SiO2) on the structure, and then removing a portion of it using a yellow light and etching process, leaving or forming at least the sidewall insulating layer 113 on the sidewalls. As shown in FIG. 1P, in this embodiment, the sidewall insulating layer 113 is formed on the exposed insulating layer 106 and also on a portion of the top contact layer 112.

[0014] Next, as shown in FIG. 1Q, an upper electrode 114 is formed on the structure of FIG. 1P. The material of the upper electrode 114 includes a metal material. In this embodiment, the upper electrode 114 is a titanium (Ti) / platinum (Pt) stack formed by electron beam evaporation. In another embodiment, the upper electrode 114 does not include platinum (Pt). In yet another embodiment, the upper electrode 114 is composed of titanium (Ti). After formation, a portion of the titanium (Ti) / platinum (Pt) stack roughly corresponding to the second opening H1 is removed, and the second opening H1 extends through the upper electrode 114. The upper electrode 114 is both an electrode and a non-transparent layer covering the light-emitting device. Since the upper electrode 114 is located above the light emitting stack 104, the area on the upper surface of the light emitting stack 104 corresponding to the second opening H1 is the light emitting area of ​​the light emitting device, that is, light emitted by the light emitting device of the present invention exits through the second opening H1, which is a light exit hole, and the exposed area on the upper surface of the light emitting stack 104 that is not covered by the upper electrode 114 is the light emitting area of ​​the light emitting device, and the upper electrode 114 covers the other part of the upper surface of the light emitting stack 104. In addition, the non-light-transmitting layer formed by the upper electrode 114 also covers the sidewalls of the light emitting stack 104, and the sidewall insulating layer 113 is located between the non-light-transmitting layer formed by the upper electrode 114 and the sidewalls of the light emitting stack 104 to prevent the light emitting stack 104 from shorting out and failing. In one embodiment, the size, shape, and position of the light exit hole (i.e., the second opening H1) may be preset, and the size, shape, and position of the first opening 106h may be substantially corresponding to those of the second opening H1, so that the first opening 106h is positioned directly below the second opening H1, and the size and / or shape of the first opening 106h may be the same as that of the second opening H1. Specifically, before forming the first opening 106h shown in FIG. 1D , that is, after setting each parameter of the second opening H1 (e.g., the size, shape, position, etc.) in advance, the corresponding parameters of the first opening 106h are determined and formed.

[0015] Furthermore, depending on the material of the upper electrode 114, it may be difficult to form it on the sidewall insulating layer 113, resulting in a thickness of the upper electrode 114 that is too thin. Therefore, in this embodiment, as shown in FIG. 1R, a metal layer 114S is formed on the sidewall insulating layer 113 to compensate for the insufficient thickness of the upper electrode 114. The metal layer 114S may be formed on the upper electrode 114 using a chemical plating method. For example, the metal layer 114S may include a metal material layer formed by immersing the structure shown in FIG. 1Q in a solution containing a metal material (e.g., gold (Au), silver (Ag), titanium (Ti), or platinum (Pt), gold (Au) in this embodiment) and then performing an oxidation-reduction reaction. That is, the metal layer 114S may include a gold (Au) layer. Then, a portion of the gold (Au) layer approximately corresponding to the second opening H1 is removed, and the second opening H1 is extended until it penetrates the metal layer 114S. In one embodiment of the present invention, the thickness of the upper electrode 114 must be at least 100 Å to serve as a non-transmitting layer covering the light-emitting device. In this embodiment, the thicknesses of the titanium (Ti), platinum (Pt) layer of the upper electrode 114 and the gold (Au) layer of the metal layer 114S are between about 200 Å and 400 Å, between 2 μm and 4 μm, and between 2000 Å and 4000 Å, respectively.

[0016] Next, as shown in FIG. 1S, a protective layer 115 is formed on the structure shown in FIG. 1R. The protective layer 115 is formed within the second opening H1 along the sidewall surrounding the second opening H1, and the diameter of the hole defined by the inner diameter of the protective layer 115 is D3. The material of the protective layer 115 is an insulating material, such as silicon nitride (Si3N4) or silicon oxide (SiO2). After formation, as shown in FIG. 1T, a portion of the protective layer 115 is removed to form a third opening 115h, and a lower electrode 111E is formed on the permanent substrate 111. The third opening 115h exposes a portion of the metal layer 114S (in another embodiment of the present invention that does not include the metal layer 114S, a portion of the upper electrode 114 would be exposed), and serves as a solder pad for connecting the metal layer 114S (or the upper electrode 114) to wiring connected to an external power source.

[0017] 1T is a schematic diagram of a light-emitting device according to a first embodiment of the present invention, and FIG. 2 is a schematic top view of FIG. 1T. Referring to both figures simultaneously, the light-emitting device includes a permanent substrate 111, a bonding structure 110 located above the permanent substrate 111, a reflective layer 109 located above the bonding structure 110, and an insulating layer 106 located above the reflective layer 109. The insulating layer 106 has a first opening 106h, and a first transparent conductive layer 107 is formed in the first opening 106h of the insulating layer 106, and is in direct contact with the second contact layer 105 through the first opening 106h, thereby electrically connecting with the light-emitting stack 104. The first transparent conductive layer 107 located in the first opening 106h and in direct contact with the second contact layer 105 is a current-conducting region, which is located directly below the second opening H1 and the second portion of the upper surface of the light-emitting stack 104, and allows current to flow to the light-emitting stack 104. Specifically, the contact resistance between the first transparent conductive layer 107 and the second contact layer 105 is smaller than the contact resistance between the insulating layer 106 and the second contact layer 105, for example, by 2 or 5 numerical classes. Preferably, the contact resistance between the first transparent conductive layer 107 and the second contact layer 105 is 10 or 2 numerical classes smaller. ‐3 From 10 ‐5 Ωcm 2The second contact layer 105 is located between the first and second contact layers 105 and 105. The insulating layer 106, which is a non-current-conducting region, surrounds the second contact layer 105. The light-emitting stack 104 is located above the insulating layer 106. The light-emitting stack 104 includes an active region 104b and has an upper surface (see FIG. 2, the rectangular region indicated by the dashed line). A non-light-transmitting layer formed by the upper electrode 114 is located above the light-emitting stack. The non-light-transmitting layer formed by the upper electrode 114 covers a first portion of the upper surface of the light-emitting stack 104, i.e., a portion other than the second opening H1 (see FIG. 2, the non-circular region indicated by the dashed line), and exposes a second portion of the upper surface, which is the portion directly below the second opening H1 (see FIG. 2, the circular region indicated by the dashed line). That is, the entire upper surface of the light-emitting stack 104 except for the second portion directly below the second opening H1 is covered by the non-light-transmitting layer formed by the upper electrode 114. Light emitted by the light-emitting stack 104 exits through the second portion of its upper surface and the second opening H1. The ratio of the cross-sectional area of ​​the second opening H1 to the area of ​​the upper surface of the light-emitting stack 104 is approximately 1.5 to 5%. As shown in FIG. 2 , a solder pad is typically formed on the first portion covered by the upper electrode 114. Specifically, the solder pad is formed in the third opening 115h to electrically connect to the light-emitting stack 104, and the solder pad is generally rectangular or square. The third opening 115h has a shorter side of the rectangle or any side of the square at least approximately 80 μm. Specifically, the area of ​​the first portion of the upper surface of the light-emitting stack 104 is larger than the area of ​​the second portion. The first transparent conductive layer 107 is filled in the first opening 106h of the insulating layer 106 and is in direct contact with the second contact layer 105, thereby electrically connecting to the light-emitting stack 104. The size, shape and position of the first opening 106h in the insulating layer 106 are formed to substantially correspond to those of the second opening H1, so that the ratio of the cross-sectional area of ​​the first opening 106h to the area of ​​the upper surface of the light emitting stack 104 is approximately 1.5 to 5%.

[0018] FIG. 3 shows the luminous power (Po, vertical axis on the left) and forward voltage (Vf, vertical axis on the right) of a light-emitting device corresponding to the diameter size (horizontal axis) of the first opening 106h when the thickness of the second contact layer 105 of the light-emitting device is 0.2 μm and 1 μm, respectively, in an embodiment of the present invention. As shown in FIG. 3, the luminous power and forward voltage of the light-emitting device vary with the size of the first opening 106h, which means that the device design is predictable and controllable, and different needs can be met by adjusting the size of the first opening 106h. Further experimental results show that a thickness of the second contact layer 105 greater than 1.5 μm is undesirable. If the thickness of the second contact layer 105 is too thick, for example 1.5 μm, the effect of the current resistance of the insulating layer 106 will be difficult to change according to the diameter size of the first opening 106h, in which case it will be unclear whether the luminous power and forward voltage of the light-emitting device will change according to the diameter size of the first opening 106h, and it will be difficult to control or predict the luminous power and forward voltage of the light-emitting device by adjusting the diameter size of the first opening 106h.

[0019] In addition, while light-emitting devices can be operated at a normal current (e.g., 50 mA in this embodiment), some applications require light-emitting devices to be operated at a relatively high current (e.g., 300 mA in this embodiment) and to emit light in a pulsed mode (i.e., the light emitted by the light-emitting device varies intermittently over time, i.e., is discontinuous). The light-emitting device structure of this embodiment can satisfy both of these requirements. FIG. 4 shows the luminous power (Po, right vertical axis) and luminous power ratio (left vertical axis, the ratio of the luminous power at a relatively high current (300 mA) to the luminous power at a normal current, when the light-emitting device has an active region 104b with a multiple quantum well (MQW) structure and the MQW structure contains 18, 38, and 48 well layers, respectively, in the same pulsed mode. As shown in Figure 4, when the multiple quantum well structures contain 38 and 48 well layers, the light emission power ratio increases to 2.8 or more. Further experimental results show that when the multiple quantum well (MQW) structures contain 30 to 50 well layers, the light emission power ratio reaches 2.6 or more.

[0020] FIG. 5 shows the results of the light emitting device of the above embodiment, in which the active region 104b of the light emitting device has a multiple quantum well (MQW) structure, when the light emitting device emits light in the same pulse mode. y Ga (1-y) ) 1-x In xThe graph shows the luminous power (Po, right vertical axis) and luminous power ratio (Factor, the ratio of the luminous power at a relatively high current to the luminous power at a normal current for the same pulsed light-emitting device, left vertical axis) at a relatively high current (300 mA) for barrier layers of a material (P, 0≦x<1, 0≦y≦1) with 30%, 50%, and 70% aluminum (Al) content (referring to the ratio of aluminum (Al) to gallium (Ga) composition, corresponding to y in the above formula), respectively, and with multiple barrier layers. As shown in Figure 5, the luminous power ratio increases to over 3.1 when the barrier layers in the multiple quantum well structure have 50% and 70% aluminum (Al) content. Taking into consideration other electrical requirements of the light-emitting device, such as the appropriate range of forward voltage, further experiments have shown that when the barrier layers in the multiple quantum well structure each have an aluminum (Al) content of about 40% to 60%, a good proportionality of light-emitting power and forward voltage can be simultaneously obtained. In another embodiment, two of the barrier layers have different aluminum contents, and the aluminum content of the barrier layer closer to the first polarity semiconductor layer 104a is lower than the aluminum content of the barrier layer further away from the first polarity semiconductor layer 104a. Preferably, the aluminum content of at least half of the barrier layers closer to the first polarity semiconductor layer 104a (i.e., n-type semiconductor layer) is lower than the aluminum content of the other barrier layers closer to the second polarity semiconductor layer 104c (i.e., p-type semiconductor layer). Specifically, the barrier layer closer to the first polarity semiconductor layer 104a has an aluminum (Al) content of about 40% to 60%. a Ga 1-a ) 1-b In b The barrier layer containing P and close to the second polarity semiconductor layer 104c is (Al c Ga 1-c ) 1-d In d P, and when b≈d, c>a. In one embodiment, the multiple quantum well structure includes 38 barrier layers, and the first 20 barrier layers relatively close to the first polarity semiconductor layer 104a are (Al 0.5 Ga 0.5 )1-b In b The other 18 barrier layers containing P and relatively far from the first polarity semiconductor layer 104a, i.e., the 18 barrier layers relatively close to the second polarity semiconductor layer 104c, are (Al 0.7 Ga 0.3 ) 1-d In d In one embodiment, the multiple quantum well structure includes 38 barrier layers, and the first 28 barrier layers that are relatively close to the first polarity semiconductor layer 104a include (Al 0.5 Ga 0.5 ) 1-b In b The first ten barrier layers relatively close to the second polarity semiconductor layer 104c contain P and are (Al 0.7 Ga 0.3 ) 1-d In d In one embodiment, the multiple quantum well structure includes 38 barrier layers, and the first 36 barrier layers that are relatively close to the first polarity semiconductor layer 104a include (Al 0.5 Ga 0.5 ) 1-b In b Two barrier layers relatively close to the second polarity semiconductor layer 104c contain P and are (Al 0.7 Ga 0.3 ) 1-d In dIn one embodiment, the aluminum content in the barrier layers gradually increases from the n-type semiconductor layer to the p-type semiconductor layer, i.e., the aluminum content of each barrier layer relatively closer to the first polarity semiconductor layer 104a (i.e., the n-type semiconductor layer) is lower than the aluminum content of its adjacent barrier layer relatively closer to the second polarity semiconductor layer 104c (i.e., the p-type semiconductor layer). In one embodiment, the additive in the second polarity semiconductor layer 104c includes carbon (C), magnesium (Mg), or zinc (Zn), and preferably includes magnesium. In the present invention, the barrier layers have different aluminum contents, and the aluminum content of the barrier layer relatively closer to the n-type semiconductor layer is lower than the aluminum content of the barrier layer relatively farther from the n-type semiconductor layer. This prevents or reduces the diffusion and intrusion of the p-type additive in the p-type semiconductor layer into the active region 104b, thereby improving the reliability of the light-emitting device without significantly increasing the forward voltage of the light-emitting device.

[0021] FIG. 6 is a cross-sectional schematic diagram of a light-emitting device according to a second embodiment of the present invention. The structure of the light-emitting device according to the second embodiment of the present invention is substantially the same as that of the first embodiment, with the following differences: As shown in FIG. 6, the light-emitting device includes a first semiconductor layer 116 and a second semiconductor layer 117, where the first semiconductor layer 116 is located between the first contact layer 103 and the light-emitting stack 104, and the second semiconductor layer 117 is located between the second contact layer 105 and the light-emitting stack 104. The first semiconductor layer 116 and the second semiconductor layer 117 are intended to promote light extraction and / or current spreading throughout the light-emitting stack 104. The thickness of the first semiconductor layer 116 is thicker than the thickness of the first polarity semiconductor layer 104a. Preferably, the thickness of the first semiconductor layer 116 is greater than 2000 nm, and more preferably, the thickness is between 2500 nm and 7000 nm. The thickness of the second semiconductor layer 117 is thicker than the thickness of the second-polarity semiconductor layer 104c, and preferably the thickness of the second semiconductor layer 117 is greater than 1000 nm, more preferably between 1500 nm and 2000 nm. The first semiconductor layer 116 has an energy level lower than the energy level of the first-polarity semiconductor layer 104a. The second semiconductor layer 117 has an energy level lower than the energy level of the second-polarity semiconductor layer 104c. The energy levels of the first semiconductor layer 116 and the second semiconductor layer 117 are higher than the energy level of the well layer in the active region 104b. Light emitted by the active region 104b can substantially transmit through the first semiconductor layer 116. The first semiconductor layer 116 and the second semiconductor layer 117 each have a thickness of 1×10 17 / cm 3The doping concentration of the first semiconductor layer 116 is lower than the doping concentration of the first contact layer 103, and the doping concentration of the second semiconductor layer 117 is lower than the doping concentration of the second contact layer 105. Preferably, the doping concentration of the first contact layer 103 is at least twice as high as the doping concentration of the first semiconductor layer 116. The doping concentration of the second contact layer 105 is at least twice as high as the doping concentration of the second semiconductor layer 117. The first semiconductor layer 116, the second semiconductor layer 117, the first contact layer 103, and the second contact layer 105 comprise III-V semiconductor materials, such as AlGaAs or AlGaInP. 6, the second contact layer 105 has a width W1, and the ratio of the width of the light-emitting region of the light-emitting device is 0.5 or more and 1.1 or less. That is, in the same cross section, the ratio of the width W1 of the second contact layer 105 to the width of the region not covered by the upper electrode 114 (i.e., the second portion of the upper surface of the light-emitting stack 104) is 0.5 or more and 1.1 or less. In one embodiment, the ratio of the width W1 of the second contact layer 105 to the diameter D2 of the second opening H1 (i.e., W1 / D2) is 0.5 or more and 1.1 or less. Preferably, the ratio of the width W1 of the second contact layer 105 to the width of the light-emitting region of the light-emitting device is 0.55 or more and 0.8 or less. In one embodiment, the ratio of the width W1 of the second contact layer 105 to the diameter D2 of the second opening H1 (i.e., W1 / D2) is 0.55 or more and 0.8 or less. 6 , the second contact layer 105 is located directly below the light-emitting region of the light-emitting device, i.e., directly below the region not covered by the upper electrode 114 (i.e., the second portion of the upper surface of the light-emitting stack 104). The contact resistance between the second contact layer 105 and the first transparent conductive layer 107 is much smaller than the contact resistance between the first transparent conductive layer 107 and the second semiconductor layer 117, for example, by two or five numerical classes. Therefore, the second contact layer 105 having the width W1 is a current-conducting region and can conduct current to the light-emitting stack 104, while the other region of the first transparent conductive layer 107 that is not in contact with and surrounds the second contact layer 105 cannot or does not conduct current to the light-emitting stack 104 easily. In this embodiment, the second contact layer 105 is located directly below the second opening H1.Preferably, the second contact layer 105 does not overlap with the upper contact layer 112 and the upper electrode 114 in the stacking direction of the light emitting stack 104. In this embodiment, as shown in FIG. 6 , the thickness of a portion of the second semiconductor layer 117 is thicker than that of the other portion of the second semiconductor layer 117, and the thicker portion of the second semiconductor layer 117 corresponds to the light-emitting region, i.e., the region not covered by the upper electrode 114 (the second portion of the upper surface of the light emitting stack 104). In this embodiment, the thicker portion of the second semiconductor layer 117 corresponds to the second opening H1. The second contact layer 105 is located on the thicker portion of the second semiconductor layer 117. Specifically, the thinner portion of the second semiconductor layer 117 includes a surface 1171 remote from the light emitting stack 104, and the second contact layer 105 includes a surface 1051 remote from the light emitting stack 104, and the surface 1051 of the second contact layer 105 is farther away from the light emitting stack 104 than the surface 1171 of the thinner portion of the second semiconductor layer 117. Specifically, the height h from the surface 1051 of the second contact layer 105 remote from the light emitting stack 104 to the surface 1171 of the second semiconductor layer 117 remote from the light emitting stack 104 is 50 nm or more and 200 nm or less. In one embodiment, the thickness of the second contact layer 105 is 20 nm or more and 0.5 μm or less, and preferably, the thickness of the second contact layer 105 is 20 nm or more and 0.1 μm or less. In the second embodiment, the light-emitting device includes a second contact layer 105 having a width W1, and the second contact layer 105 is located directly below the light-emitting region. Therefore, when current flows through the light-emitting stack 104, the current tends to concentrate in the region corresponding to the second contact layer 105, which significantly increases the current density and further improves the brightness of the light-emitting device.

[0022] The method for manufacturing a light-emitting device according to the second embodiment of the present invention is substantially the same as that according to the first embodiment, except that it further includes a step of forming a first semiconductor layer 116 on the first contact layer 103 before forming the light-emitting stack 104, and a step of forming a second semiconductor layer 117 after forming the light-emitting stack 104 and before forming the second contact layer 105. After forming the second contact layer 105, the second contact layer 105 is patterned using a yellow light and etching process to provide the second contact layer 105 with a width W1. The method then proceeds to the next steps of forming the first transparent conductive layer 107 and the second transparent conductive layer 108, as in the first embodiment. Compared to the first embodiment, the method for manufacturing a light-emitting device according to the second embodiment does not require the formation of the insulating layer 106 or the formation of the first opening 106h in the insulating layer 106 using a yellow light and etching process, which significantly reduces manufacturing costs and simplifies the process.

[0023] In one embodiment, the light-emitting device does not include the second opening H1, and the second contact layer 105 having width W1 is located directly below the light-emitting area of ​​the light-emitting device, i.e., directly below the area not covered by the upper electrode 114 (i.e., the second portion of the upper surface of the light-emitting stack 104).

[0024] FIG. 7 is a cross-sectional view of a light-emitting device according to a third embodiment of the present invention. Compared with the previous embodiments of the present invention, the light-emitting device according to this embodiment further includes a heat-conducting layer 118 disposed on a second portion of the upper surface of the light-emitting stack 104. Specifically, the heat-conducting layer 118 is disposed on the upper surface of the light-emitting stack 104 exposed through the second opening H1. The heat-conducting layer 118 has a higher thermal conductivity than the light-emitting stack 104. During operation of the light-emitting device, heat generated in the light-emitting stack 104 is dissipated to the outside via conduction or radiation through the heat-conducting layer 118. This reduces heat accumulation in the light-emitting stack 104 below the second opening H1, alleviates material degradation caused by heat within the light-emitting device, and improves the service life and reliability of the light-emitting device. The heat-conducting layer 118 is made of a material with a thermal conductivity of 100 W / (m×K) or more, such as diamond, graphene, or aluminum nitride (AlN) with a thermal conductivity of approximately 140 W / (m×K) to 180 W / (m×K). X), but the present invention is not limited thereto. More specifically, in this embodiment, the heat-conducting layer 118 fills the second opening H1 along the sidewall of the second opening H1, covers the first-polarity semiconductor layer 104a exposed by the second opening H1, and extends around the light-emitting device in a direction away from the second opening H1 and contacts the metal layer 114S or the upper electrode 114, so that heat generated in the light-emitting stack 104 is conducted to the metal layer 114S or the upper electrode 114 through the heat-conducting layer 118. The metal layer 114S and the upper electrode 114 are usually made of metal and have a high thermal conductivity, so that heat inside the light-emitting device is dissipated through the heat-conducting layer 118 and the metal layer 114S or the upper electrode 114. In some embodiments, the heat-conducting layer 118 may not be in contact with the metal layer 114S or the upper electrode 114, and the heat generated in the light-emitting stack 104 may be dissipated to the outside by radiation through the heat-conducting layer 118, or the heat-conducting layer 118 may be connected to an external heat-conducting structure, and the heat generated in the light-emitting stack 104 may be dissipated to the outside by conduction through the heat-conducting layer 118. Compared with the first embodiment, the light-emitting device in this embodiment not only includes a protective layer 115 covering the metal layer 114S, but also the protective layer 115 may cover the heat-conducting layer 118, and in this embodiment, the protective layer 115 may completely cover the heat-conducting layer 118. In detail, in this embodiment, the heat-conducting layer 118 has a top surface 118t and a side surface 118s, the top surface 118t is parallel to the upper surface of the light-emitting stack 104, and the side surface 118s is connected to the top surface 118t and non-parallel to the upper surface of the light-emitting stack 104. The protective layer 115 simultaneously covers the top surface 118t and the side surface 118s of the heat-conducting layer 118, thereby preventing the material of the heat-conducting layer 118 from being altered by contact with the external environment during operation of the light-emitting device, but the present invention is not limited thereto. In another embodiment, to increase the heat-conducting area of ​​the light-emitting device, the heat-conducting layer 118 may be used instead of the protective layer 115, and the heat-conducting layer 118 may cover the entire surface of the upper electrode 114 or the metal layer 114S except for the position of the third opening 115h. In one embodiment, the heat-conducting layer 118 has high transmittance to the light emitted by the light-emitting stack 104, for example, the heat-conducting layer 118 includes a material having a transmittance of more than 85% to the light emitted by the active region 104b.In another embodiment, the thermally conductive layer 118 has a refractive index greater than 1.5 or between 2.1 and 2.5, and the difference in refractive index between the thermally conductive layer 118 and the first-polarity semiconductor layer 104a is less than 1.5, thereby reducing the probability of total reflection at the interface between the first-polarity semiconductor layer 104a and the thermally conductive layer 118 and improving the light extraction efficiency of the light-emitting device. The thickness of the thermally conductive layer 118 is between 300 and 2000 Å. In this embodiment, the thickness of the thermally conductive layer 118 may be, but is not limited to, 1000 Å. The thermally conductive layer 118 is formed after the formation of the upper electrode 114 shown in FIG. 1Q, or after the formation of the metal layer 114S shown in FIG. 1R, and covers the upper electrode 114 or the metal layer 114S.

[0025] 8A and 8B are schematic cross-sectional and top views of a light-emitting device according to a fourth embodiment of the present invention. Compared with the previous embodiments, the light-emitting device according to this embodiment has a heat-conducting layer 118 disposed in the light-emitting stack 104, the heat-conducting layer 118 having a fourth opening H4 substantially corresponding to the second opening H1. When viewed from the insulating layer 106 toward the light-emitting stack 104, the fourth opening H4 has a substantially circular shape (as shown in FIG. 8B ). The top view area of ​​the fourth opening H4 is larger than the top view area of ​​the second portion of the light-emitting stack 104. In other words, the top view area of ​​the fourth opening H4 is larger than the top view area of ​​the second opening H1. In detail, the heat conductive layer 118 is located between the light emitting stack 104, the first contact layer 103 and the insulating layer 106. More specifically, in this embodiment, the heat conductive layer 118 penetrates the first polarity semiconductor layer 104a, the active region 104b, the second polarity semiconductor layer 104c and the second contact layer 105 of the light emitting stack 104, and the heat conductive layer 118 is surrounded by the light emitting stack 104, the first contact layer 103 and the insulating layer 106. In another embodiment, the heat conductive layer 118 penetrates the first polarity semiconductor layer 104a, the active region 104b and the second polarity semiconductor layer 104c but does not penetrate the second contact layer 105, and the heat conductive layer 118 is surrounded by the light emitting stack 104, the first contact layer 103 and the second contact layer 105, but the structure of the heat conductive layer 118 is not limited to the above embodiment. The fourth opening H4 of the heat-conducting layer 118 has a diameter D4 that is larger than the diameter D2 of the second opening H1, and is approximately between 30 μm and 200 μm, or approximately between 50 μm and 120 μm. As shown in FIG. 8B , the heat-conducting layer 118 of this embodiment has an inner contour 118a and an outer contour 118b surrounding the inner contour 118a. The inner contour 118a is annular, surrounding the light-emitting stack 104 below the second opening H1 and forming the fourth opening H4. When viewed from above, the inner contour 118a of this embodiment is circular, with its center approximately corresponding to the center of the second opening H1. The minimum distance d between the outer contour 118b and the inner contour 118a is between 10 μm and 50 μm. In addition, in this embodiment, the thermally conductive layer 118 penetrates the second contact layer 105, and has a thickness W of between 2 μm and 15 μm in a direction parallel to the stacking direction of the light emitting stack 104. In another embodiment, the centers of the inner and outer contours 118a and 118b of the thermally conductive layer 118 are positioned approximately corresponding to the center of the second opening H1.

[0026] FIG. 9 is a cross-sectional schematic diagram of a light-emitting device according to a fifth embodiment of the present invention. Compared with the previous embodiments, the heat-conducting layer 118 of the light-emitting device according to this embodiment is located within the light-emitting stack 104, and the area of ​​the heat-conducting layer 118 is larger than that of the fourth embodiment. Specifically, as shown in FIG. 9, the total area of ​​the heat-conducting layer 118 of the light-emitting device in cross section may be larger than that of the light-emitting stack 104, so that the heat generated during operation of the light-emitting device can be more efficiently transferred to the outside. The light-emitting devices according to the fourth and fifth embodiments of the present invention are formed according to the steps shown in FIGS. 1A-1Q. After forming the second contact layer 105 on the light-emitting stack 104, a portion of the light-emitting stack 104 and the second contact layer 105 thereon at the position where the heat-conducting layer 118 will be formed are removed. The removal method may be, but is not limited to, inductively coupled plasma (ICP) reactive ion etching, and the area of ​​the light-emitting stack 104 removed in this step in the fifth embodiment is larger than that of the light-emitting stack 104 removed in the fourth embodiment. In detail, in one embodiment, before forming the heat-conducting layer 118, a portion of the light-emitting stack 104, such as the second contact layer 105, the active region 104b, the second-polarity semiconductor layer 104c, and the first-polarity semiconductor layer 104a, may be removed from the position where the heat-conducting layer 118 is to be formed. In this case, an etching resist layer (not shown) may be provided between the first contact layer 103 and the first-polarity semiconductor layer 104a to prevent the first contact layer 103 from being damaged when removing the portion of the light-emitting stack 104. Then, the heat-conducting layer 118 is formed in the area where the light-emitting stack 104 has been removed. The heat-conducting layer 118 has a thickness W in a direction parallel to the stacking direction of the light-emitting stack 104. Preferably, the thickness W is such that the top surface 118t of the heat-conducting layer 118 and the second portion of the surface of the light-emitting stack 104 are flat.The thermally conductive layer 118 can be formed by sputtering or evaporation, such as atomic layer chemical vapor deposition (ALD) or electron beam physical vapor deposition (EBPVD). In this embodiment, the thermally conductive layer 118 is formed by a two-step deposition method, that is, first, a relatively dense first portion of the thermally conductive layer 118 is formed by atomic layer chemical vapor deposition, and then a second portion of the thermally conductive layer 118 is subsequently formed on the first portion of the thermally conductive layer 118 by electron beam deposition. However, the method of forming the thermally conductive layer 118 is not limited thereto.

[0027] It should be noted that the embodiments described herein are merely illustrative of the present invention and do not limit the scope of the present invention. Simple and obvious modifications or variations made to the present invention are all within the spirit and scope of the present invention. Identical or similar components in different embodiments, or components designated by the same reference numerals in different embodiments, have the same physical or chemical properties. Furthermore, the above-described embodiments of the present invention may be combined or substituted where appropriate, and the present invention is not limited to the specific embodiments described. The connection relationships of specific components and other components described in detail in the embodiments may also be applied to other embodiments, and these applications also fall within the scope of the claims of the present invention. [Explanation of symbols]

[0028] 101 Growth substrate 102 Buffer layer 103 First contact layer 104 Light-emitting stack 104a First polarity semiconductor layer 104b Active region 104c Second polarity semiconductor layer 105 Second contact layer 106 Insulating layer 106h First opening 107 First transparent conductive layer 108 Second transparent conductive layer 109 Reflective layer 110 Joint structure 110a First bonding layer 110b second bonding layer 110c Third bonding layer 111 Permanent base plate 112 upper contact layer H1 second opening H4 fourth opening 113 Side wall insulation layer 114 Upper electrode 114S metal layer 115 protective layer 115h Third opening 111E lower electrode D1, D2, D3, D4 hole diameter 116 first semiconductor layer 117 second semiconductor layer d Minimum distance W thick W1 h high 1051 Surface 1071 Surface 118 thermal conductive layer 118t top surface 118s side view 118a Inner outline 118b Outer outline

Claims

1. 1. A light emitting device, comprising: A substrate; a light-emitting stack including a first semiconductor layer, an active region, and a second semiconductor layer stacked in this order on the substrate in a stacking direction perpendicular to the substrate, the second semiconductor layer including a first region having a first thickness and a second region having a second thickness greater than the first thickness; an electrode located on the first semiconductor layer and including an opening corresponding to the second region; a first contact layer located between the electrode and the first semiconductor layer and in direct contact with the electrode and the first semiconductor layer; a second contact layer positioned between the second region and the substrate, in direct contact with the second region, and corresponding to the opening in the stacking direction of the light-emitting stack but not overlapping with the electrode.

2. 10. The light emitting device of claim 1, wherein the second contact layer has a thickness of 20 nm or more and 0.5 μm or less.

3. 10. The light emitting device of claim 1 further comprising a first transparent conductive layer in contact with the second contact layer.

4. the first region has a first surface remote from the active region; the second contact layer has a second surface remote from the active region; The light emitting device of claim 1 , wherein the second surface is further from the active region than the first surface.

5. The light-emitting device according to claim 4 , wherein the distance between the first surface and the second surface in the stacking direction is 50 nm or more and 200 nm or less.

6. the second region has a first width; The light emitting device of claim 1 , wherein the second contact layer has a second width that is smaller than the first width.

7. The light emitting device of claim 1 , further comprising a hole formed in the first contact layer, the hole corresponding to the second region.

8. The light emitting device of claim 7 further comprising a protective layer located within the hole.

9. An emitting device as described in claim 1, wherein the first contact layer does not overlap with the second contact layer in the stacking direction.

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