optical semiconductor devices

Abstract

To provide an optical semiconductor element that can improve light-emitting / light-receiving efficiency and improve the reliability.SOLUTION: An optical semiconductor element 1 includes: a substrate 2; a semiconductor stack 3 including an optical layer 31, a first semiconductor layer 32, and a second semiconductor layer 33, in which the optical layer 31 and the first semiconductor layer 32 form a mesa part 34 and the second semiconductor layer 33 includes an outer part 35; a first electrode 4 formed on the mesa part 34 and connected to the first semiconductor layer 32; a first insulating layer 5 formed on the first electrode 4; a second electrode 6 including a first part 61 connected to the second semiconductor layer 33 in the outer part 35 and a second part 62 disposed on the first insulating layer 5 so as to overlap with the first electrode 4; and a second insulating layer 7 formed on the second electrode 6. In the first insulating layer 5, an opening 5a for exposing the first electrode 4 is formed. In the second insulating layer 7, an opening 7b for exposing the second part 62 of the second electrode 6 is formed.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an optical semiconductor element. [Background technology]

[0002] Patent Document 1 describes a light emitting device that includes a substrate, a semiconductor laminate formed on the substrate and having a mesa portion, and a p-side electrode and an n-side electrode formed on the mesa portion. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2017 / 043216 Summary of the Invention [Problem to be solved by the invention]

[0004] In the light-emitting element described above, the p-side electrode and the n-side electrode are disposed close to each other, and therefore, for example, during mounting, there is a risk of a short circuit occurring between the p-side electrode and the n-side electrode. From the viewpoint of improving reliability, it is preferable to suppress such a short circuit. Furthermore, the light-emitting element or the light-receiving element described above is also required to have improved light-emitting efficiency or light-receiving efficiency.

[0005] An object of the present invention is to provide an optical semiconductor element that can improve light emission / reception efficiency and reliability. [Means for solving the problem]

[0006] The optical semiconductor element of the present invention is a semiconductor laminate having a substrate, an optical layer that generates or absorbs light, a first semiconductor layer arranged on the opposite side of the optical layer from the substrate, and a second semiconductor layer arranged on the substrate side from the optical layer, wherein the optical layer and the first semiconductor layer form a mesa portion formed on the second semiconductor layer, and the second semiconductor layer has an outer portion located outside the mesa portion; a first electrode formed on the mesa portion and electrically connected to the first semiconductor layer; a first insulating layer formed on the first electrode; a second electrode having a first portion electrically connected to the second semiconductor layer at the outer portion, a second portion arranged on the first insulating layer so as to overlap with the first electrode in the thickness direction of the substrate, and a third portion electrically connected to the first portion and the second portion; and a second insulating layer formed on the second electrode, wherein a first opening exposing the first electrode is formed in the first insulating layer, and a second opening exposing a second portion of the second electrode is formed in the second insulating layer.

[0007] In this optical semiconductor element, the second electrode has a first portion electrically connected to the second semiconductor layer at its outer portion and a second portion disposed on the first insulating layer so as to overlap the first electrode in the thickness direction of the substrate. This allows the area of ​​the outer portion of the second semiconductor layer to be reduced compared to when the entire second electrode is disposed on the outer portion of the second semiconductor layer, thereby increasing the area of ​​the mesa portion (optical layer). As a result, the light-emitting / receiving efficiency can be improved. Furthermore, in this optical semiconductor element, the first electrode is exposed through a first opening formed in the first insulating layer, and the second electrode is exposed through a second opening formed in the second insulating layer. This allows the first insulating layer and the second insulating layer to improve insulation between the first electrode and the second electrode, thereby preventing short circuits between the first electrode and the second electrode. As a result, reliability can be improved. Furthermore, in this optical semiconductor element, a step is formed by the first insulating layer and the second insulating layer between the portion of the first electrode exposed through the first opening and the portion of the second electrode exposed through the second opening. This step also improves the insulation between the first electrode and the second electrode, and therefore this optical semiconductor element can improve the light emission / reception efficiency as well as the reliability.

[0008] The second insulating layer may be formed so as to extend from above the second electrode to above the first insulating layer, and a third opening connected to the first opening may be formed in the second insulating layer in a region above the first insulating layer, in which case short-circuiting between the first electrode and the second electrode can be more reliably suppressed.

[0009] When viewed from the thickness direction of the substrate, the outer edge of the first electrode may be located inside the outer edge of the top surface of the mesa portion, and a first insulating layer may be disposed on the region on the top surface between the outer edge of the first electrode and the outer edge of the top surface. In this case, the first insulating layer can suppress short circuits between the first electrode and the optical layer, further improving reliability.

[0010] The first portion may have an extension that extends to surround the mesa portion when viewed in the thickness direction of the substrate, which can increase the efficiency of carrier injection / extraction to / from the optical layer and further improve the light emission / reception efficiency.

[0011] The extension portion may extend to surround the entire periphery of the mesa portion when viewed in the thickness direction of the substrate, which can increase the efficiency of carrier injection / extraction to / from the optical layer and further improve the light emission / reception efficiency.

[0012] The optical layer may be an active layer that generates light with a central wavelength of 3 μm or more and 10 μm or less, or an absorption layer that has a maximum sensitivity wavelength of 3 μm or more and 10 μm or less. In this case, it is difficult to increase the area of ​​the element from a cost perspective, and it is important to increase the light emission / reception efficiency per unit area. However, with this optical semiconductor element, as described above, the light emission / reception efficiency per unit area can be improved. [Effects of the Invention]

[0013] According to the present invention, it is possible to provide an optical semiconductor element that can improve the light emitting / receiving efficiency and reliability. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a cross-sectional view of an optical semiconductor element according to an embodiment. [Figure 2] FIG. 2 is a plan view of the optical semiconductor element shown in FIG. [Figure 3] FIG. 10 is a cross-sectional view of an optical semiconductor element according to a first modified example. [Figure 4] FIG. 10 is a cross-sectional view of an optical semiconductor element according to a second modified example. DETAILED DESCRIPTION OF THE INVENTION

[0015] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, the same or equivalent elements are designated by the same reference numerals, and redundant description will be omitted.

[0016] 1 and 2, the optical semiconductor element 1 includes a substrate 2 and a semiconductor stack (light-emitting cell) 3 formed on the substrate 2. The semiconductor stack 3 includes an optical layer 31, a first semiconductor layer 32, and a second semiconductor layer 33. The optical semiconductor element 1 is a light-emitting element or a light-receiving element. In this example, the optical semiconductor element 1 is configured as a light-emitting diode (LED), and light generated in the optical layer 31 is emitted through the substrate 2. The optical semiconductor element 1 is configured as a single-cell LED having only one light-emitting cell.

[0017] The substrate 2 is a light-transmitting semiconductor substrate, and is formed into a rectangular plate shape from, for example, GaAs. The substrate 2 has a main surface 2a. In the following description, the thickness direction of the substrate 2 (direction perpendicular to the main surface 2a) is defined as the Z direction, the length direction of the substrate 2 (direction perpendicular to the Z direction) is defined as the X direction, and the width direction of the substrate 2 (direction perpendicular to the Z direction and the X direction) is defined as the Y direction.

[0018] As described above, the semiconductor laminate 3 has the optical layer 31, the first semiconductor layer 32, and the second semiconductor layer 33. The second semiconductor layer 33, the optical layer 31, and the first semiconductor layer 32 are laminated in this order on the major surface 2a of the substrate 2. That is, the first semiconductor layer 32 is disposed on the opposite side of the optical layer 31 from the substrate 2 (upper side in FIG. 1), and the second semiconductor layer 33 is disposed on the substrate 2 side of the optical layer 31 (lower side in FIG. 1).

[0019] In this example, the optical layer 31 is an active layer that generates light and is configured to generate light with a center wavelength of 3 μm or more and 10 μm or less. The optical layer 31 has a multiple quantum well structure in which barrier layers made of AlInAs and well layers made of InAsSb are alternately stacked. When viewed from the Z direction, the optical layer 31 is formed, for example, in a rectangular shape. In this example, when viewed from the Z direction, the optical layer 31 is formed in a rectangular shape with long sides along the X direction.

[0020] The first semiconductor layer 32 is a semiconductor layer of a first conductivity type (e.g., p-type), and is configured, for example, by stacking a barrier layer, a buffer layer, and a contact layer in this order on the optical layer 31. The second semiconductor layer 33 is a semiconductor layer of a second conductivity type (e.g., n-type), and is configured, for example, by stacking a buffer layer, a contact layer, a current diffusion layer, and a barrier layer in this order on the major surface 2a of the substrate 2. The materials of the layers included in the first semiconductor layer 32 and the second semiconductor layer 33 can be appropriately selected depending on the material of the optical layer 31. As an example, the barrier layer of the first semiconductor layer 32 is Al 0.20 It is made of InAs and the buffer layer is Al 0.05 As an example, the buffer layer of the second semiconductor layer 33 is made of three layers each made of GaAs, GaSb, and InAs, and the contact layer and current diffusion layer are made of Al. 0.05 It is made of InAs, and the barrier layer is Al 0.20 It consists of InAs.

[0021] The optical layer 31 and the first semiconductor layer 32 constitute a mesa portion 34 formed on the second semiconductor layer 33. The mesa portion 34 is formed so as to protrude from the second semiconductor layer 33 toward the opposite side of the substrate 2. The mesa portion 34 is formed, for example, in a trapezoidal shape in a cross section perpendicular to the major surface 2a of the substrate 2 (FIG. 1), and has a rectangular top surface 34a extending parallel to the major surface 2a and a side surface 34b extending at an angle with respect to the Z direction. The top surface 34a is formed by the surface of the first semiconductor layer 32 opposite to the optical layer 31. The mesa portion 34 is formed, for example, by stacking the optical layer 31, the first semiconductor layer 32, and the second semiconductor layer 33 on the substrate 2, and then removing parts of the optical layer 31, the first semiconductor layer 32, and the second semiconductor layer 33 by etching.

[0022] The second semiconductor layer 33 has an outer portion 35 located outside the mesa portion 34. Here, "outside" means the side away from the center of the mesa portion 34 in a direction perpendicular to the Z direction. The outer portion 35 is formed in a rectangular ring shape (a rectangular ring in this example) so as to surround the entire periphery of the mesa portion 34 when viewed from the Z direction, for example.

[0023] The optical semiconductor device 1 further includes a first electrode (anode) 4, a first insulating layer 5, a second electrode (cathode) 6, and a second insulating layer 7. The first electrode 4, the first insulating layer 5, the second electrode 6, and the second insulating layer 7 can also be considered to constitute a light-emitting cell.

[0024] The first electrode 4 is formed over the entire top surface 34a of the mesa portion 34 and is electrically connected to the first semiconductor layer 32. The first electrode 4 is formed in a rectangular shape (rectangular in this example) when viewed from the Z direction. In this example, the outer edge 4a of the first electrode 4 coincides with the outer edge 34c of the top surface 34a when viewed from the Z direction. The first electrode 4 is formed in a layered structure, and is configured by, for example, depositing a first layer made of Ti, a second layer made of Pt, and a third layer made of Au in this order on the top surface 34a by vapor deposition.

[0025] The first insulating layer 5 is formed over the first electrode 4, the side surface 34b of the mesa portion 34, and the outer portion 35. The first insulating layer 5 is made of, for example, Al2O3. An opening (first opening) 5a and an opening 5b are formed in the first insulating layer 5. The opening 5a is formed in a region of the first insulating layer 5 above the first electrode 4. The opening 5a is disposed so as to be located above the center of the first electrode 4 when viewed from the Z direction. The opening 5a is formed, for example, in a circular shape. The opening 5b is formed in a shape (a rectangular ring in this example) corresponding to an extension portion 64 of a first portion 61 of the second electrode 6, which will be described later, when viewed from the Z direction.

[0026] The second electrode 6 is formed in layers and has, for example, a three-layer structure similar to that of the first electrode 4. The second electrode 6 has a first portion (connection portion) 61, a second portion (pad component portion) 62, and a third portion (wiring portion) 63. The first portion 61 is disposed on the outer portion 35, and is electrically connected to the second semiconductor layer 33 in the outer portion 35 via the opening 5b.

[0027] The first portion 61 has an extending portion 64 that extends to surround the mesa portion 34 when viewed from the Z direction. In this example, the extending portion 64 is formed in a rectangular ring shape when viewed from the Z direction and extends to surround the entire periphery of the mesa portion 34. More specifically, the extending portion 64 has four portions 64a, 64b, 64c, and 64d that extend straight along the four sides of the mesa portion 34. The portion 64a is connected to the third portion 63 and extends in the Y direction. The portions 64b and 64c are connected to one end and the other end of the portion 64a, respectively, and extend parallel to each other in the X direction. The portion 64d is connected to the portions 64b and 64c on the side opposite to the portion 64a and extends parallel to the portion 64a. The extending portion 64 is in contact with the outer portion 35 of the second semiconductor layer 33 through the opening 5b.

[0028] The second portion 62 is disposed on the first insulating layer 5 so as to overlap with the first electrode 4 in the Z direction. In this example, the second portion 62 is formed in a rectangular shape when viewed from the Z direction, and is disposed so as to overlap with the opening 5a while partially overlapping with the first electrode 4. The length of the second portion 62 is shorter than the length of the first electrode 4 in both the X direction and the Y direction.

[0029] The third portion 63 is electrically connected to the first portion 61 and the second portion 62. The third portion 63 is disposed on the side surface 34b of the mesa portion 34 and on the outer portion 35, via the first insulating layer 5. The portion of the third portion 63 disposed on the side surface 34b of the mesa portion 34 extends along the side surface 34b at an angle with respect to the Z direction. When viewed from the Z direction, the third portion 63 is formed, for example, in a rectangular shape. The width of the third portion 63 in the Y direction is narrower than the width of the second portion 62 in the Y direction.

[0030] The second insulating layer 7 is formed over the first insulating layer 5 and the second electrode 6. That is, the second insulating layer 7 is formed from above the second electrode 6 to above the first insulating layer 5. The second insulating layer 7 is made of, for example, the same material as the first insulating layer 5. The second insulating layer 7 has an opening (third opening) 7a and an opening (second opening) 7b formed therein.

[0031] The opening 7a is formed in a region of the second insulating layer 7 above the first insulating layer 5. The opening 7a is provided at a position corresponding to the opening 5a when viewed from the Z direction, and is connected to the opening 5a (continuous with the opening 5a). The opening 7a is formed, for example, in the same circular shape as the opening 5a. The opening 7a exposes the first electrode 4 together with the opening 5a. That is, the first electrode 4 is exposed to the outside of the optical semiconductor element 1 through the openings 5a and 7a. The exposed portions of the first electrode 4 from the openings 5a and 7a form first pad portions P1 for electrical connection to external members.

[0032] The opening 7b is positioned so as to overlap the second portion 62 of the second electrode 6 in the Z direction. The opening 7b is positioned, for example, aligned with the opening 7a in the X direction. The opening 7b is formed, for example, in a circular shape. The opening 7b exposes the second portion 62 of the second electrode 6. That is, the second portion 62 of the second electrode 6 is exposed to the outside of the optical semiconductor device 1 through the opening 7b. The exposed portion of the second portion 62 from the opening 7b forms a second pad P2 for electrical connection to an external component. The second insulating layer 7 has a stepped portion 7c. The stepped portion 7c is formed at a position corresponding to the edge of the second electrode 6 because the second insulating layer 7 is formed so as to extend from the first insulating layer 5 onto the second portion 62 of the second electrode 6. The stepped portion 7c is formed at the boundary between the portion of the second insulating layer 7 located on the second portion 62 and the portion of the second insulating layer 7 located on the first insulating layer 5.

[0033] A step portion 8 is formed between the first pad portion P1 and the second pad portion P2 by the first insulating layer 5 and the second insulating layer 7. That is, the exposed portion of the second portion 62 from the opening 7b (second pad portion P2) is located farther from the substrate 2 than the exposed portion of the first electrode 4 from the openings 5a, 7a (first pad portion P1) because the first insulating layer 5 is interposed between the first electrode 4 and the second electrode 6. The first insulating layer 5 and the second insulating layer 7 are disposed between such exposed portions, thereby forming a step portion 8 between the first pad portion P1 and the second pad portion P2. The step portion 8 has a step surface 8a formed by the inner surfaces of the openings 5a, 7a formed in the first insulating layer 5 and the second insulating layer 7.

[0034] The optical semiconductor element 1 is mounted, for example, by electrically connecting it to an external member on which an electric circuit is formed via solder (bumps). During this mounting, each of the first pad portion P1 and the second pad portion P2 is connected to the external member via, for example, solder. Each of the first pad portion P1 and the second pad portion P2 may be connected to the external member via an Au bump or an In bump. During operation of the optical semiconductor element 1, for example, a voltage is applied between the first pad portion P1 (first electrode 4) and the second pad portion P2 (second electrode 6) via the external member. As a result, in the semiconductor laminate 3, carriers are injected into the optical layer 31, generating light, which is then emitted via the substrate 2. [Action and effect]

[0035] In the optical semiconductor element 1, the second electrode 6 has a first portion 61 electrically connected to the second semiconductor layer 33 at the outer portion 35 and a second portion 62 disposed on the first insulating layer 5 so as to overlap the first electrode 4 in the thickness direction of the substrate 2. This allows the area of ​​the outer portion 35 of the second semiconductor layer 33 to be reduced compared to when the entire second electrode 6 is disposed on the outer portion 35 of the second semiconductor layer 33, thereby increasing the area of ​​the mesa portion 34 (optical layer 31). As a result, the light-emitting efficiency can be improved. Furthermore, in the optical semiconductor element 1, the first electrode 4 is exposed through an opening 5a formed in the first insulating layer 5, and the second electrode 6 is exposed through an opening 7b formed in the second insulating layer 7. This allows the first insulating layer 5 and the second insulating layer 7 to improve insulation between the first electrode 4 and the second electrode 6, thereby preventing short circuits between the first electrode 4 and the second electrode 6. As a result, the reliability of the optical semiconductor element 1 can be improved. Furthermore, in the optical semiconductor element 1, a step 8 is formed by the first insulating layer 5 and the second insulating layer 7 between the portion of the first electrode 4 exposed through the opening 5a and the portion of the second electrode 6 exposed through the opening 7b. This step 8 also improves the insulation between the first electrode 4 and the second electrode 6. Therefore, the optical semiconductor element 1 can improve the light emitting efficiency and reliability.

[0036] More specifically, in the optical semiconductor element 1, a first insulating layer 5 is formed between the first electrode 4 and the second electrode 6 on the top surface 34a of the mesa portion 34, and the height from the substrate 2 to the first electrode 4 is different from the height from the substrate 2 to the second electrode 6. This improves the insulation between the first electrode 4 and the second electrode 6, thereby preventing short-circuiting between the first electrode 4 and the second electrode 6. Furthermore, in the optical semiconductor element 1, the first electrode 4 is exposed through openings 5a and 7a formed in the first insulating layer 5 and the second insulating layer 7 on the top surface 34a of the mesa portion 34, and the second electrode 6 is exposed through an opening 7b formed in the second insulating layer 7. This also improves the insulation between the first electrode 4 and the second electrode 6, thereby preventing short-circuiting between the first electrode 4 and the second electrode 6. Furthermore, in the optical semiconductor element 1, the second insulating layer 7 has a step 7c formed at the boundary between the portion of the second insulating layer 7 located on the second portion 62 and the portion of the second insulating layer 7 located on the first insulating layer 5. Therefore, even if the amount of solder placed in openings 5a and 7a exceeds the target amount during mounting of optical semiconductor element 1 and leaks out of opening 7a, the solder is blocked by step portion 7c and is less likely to come into contact with the portion of second electrode 6 exposed through opening 7b. This also improves the insulation between first electrode 4 and second electrode 6, making it possible to prevent short circuits between first electrode 4 and second electrode 6. As a result, the reliability of optical semiconductor element 1 can be improved.

[0037] The second insulating layer 7 is formed so as to extend from above the second electrode 6 to above the first insulating layer 5, and an opening 7a connected to the opening 5a is formed in the second insulating layer 7 in a region above the first insulating layer 5. This allows the opening in the first pad portion P1 to be made deeper, making it possible to more reliably prevent a short circuit between the first electrode 4 and the second electrode 6.

[0038] When viewed from the Z-axis direction, the first portion 61 has an extending portion 64 that extends so as to surround the mesa portion 34. This increases the efficiency of carrier injection into the optical layer 31, thereby further improving the light-emitting efficiency.

[0039] When viewed from the Z-axis direction, the extension portion 64 extends so as to surround the entire periphery of the mesa portion 34. In this case, the efficiency of carrier injection into the optical layer 31 can be increased, and the light emission efficiency can be further improved.

[0040] The optical layer 31 is an active layer that generates light having a central wavelength of 3 μm or more and 10 μm or less. In this case, unlike when light having a central wavelength shorter than 3 μm is generated, it is difficult to increase the area of ​​the element from a cost standpoint, and it is important to increase the light emission efficiency per unit area. However, as described above, the optical semiconductor element 1 can improve the light emission efficiency per unit area. [Variations]

[0041] The optical semiconductor device 1 may be configured as in a first modified example shown in Fig. 3. In the first modified example, when viewed from the Z-axis direction, the outer edge 4a of the first electrode 4 is located inside the outer edge 34c of the top surface 34a of the mesa portion 34 along the entire periphery. In other words, the first electrode 4 is formed slightly smaller than the top surface 34a of the mesa portion 34. A first insulating layer 5 is disposed on a region A between the outer edges 4a and 34c of the top surface 34a. When viewed from the Z-axis direction, the region A extends to surround the entire periphery of the outer edge 4a of the first electrode 4.

[0042] Similar to the above embodiment, the first modification can improve both the light-emitting efficiency and the reliability. Furthermore, in the first modification, when viewed from the Z-axis direction, the outer edge 4a of the first electrode 4 is located inside the outer edge 34c of the top surface 34a of the mesa portion 34, and the first insulating layer 5 is disposed on a region A on the top surface 34a between the outer edge 4a of the first electrode 4 and the outer edge 34c of the top surface 35a. This allows the first insulating layer 5 to suppress short circuits between the first electrode 4 and the optical layer 31, further improving reliability. This configuration is particularly effective when the first semiconductor layer 32 is thin and a short circuit is likely to occur between the first electrode 4 and the optical layer 30.

[0043] The optical semiconductor element 1 may be configured as in a second modified example shown in Fig. 4. In the second modified example, the second insulating layer 7 covers only the region of the first insulating layer 5 on the side of the opening 7b relative to the opening 5a, and does not cover the region of the first insulating layer 5 on the opposite side of the opening 7b relative to the opening 5a. In the second modified example, as in the above embodiment, the second insulating layer 7 is disposed between the openings 5a and 7b, and a step portion 8 is formed between the first pad portion P1 and the second pad portion P2. As in the above embodiment, the second modified example can improve the light-emitting efficiency and reliability.

[0044] The present invention is not limited to the above-described embodiment and modifications. For example, the materials and shapes of each component are not limited to those described above, and various materials and shapes can be used. In the above-described embodiment, the optical layer 31 has a multiple quantum well structure. However, the optical layer 31 may be formed of a single layer. The material of the optical layer 31 is not limited to that of the above-described embodiment. The optical layer 31 may be formed of a material containing at least one of InAsSb, AlInSb, and AlInAs. The optical layer 31 may be formed of a material containing Sb and In. The optical layer 31 may be formed of a material containing Sb. Even in these cases, the optical layer 31 can be configured as an active layer that generates light with a center wavelength of 3 μm to 10 μm. The optical layer 31 may also be an active layer that generates light with a center wavelength of 3 μm to 8 μm. The first electrode 4 and the second electrode 6 may be formed of metal materials other than those described above. The first insulating layer 5 and the second insulating layer 7 may be formed of insulating materials other than those described above. The openings 5a, 5b, 7a, and 7b may be formed in any shape.

[0045] In the above embodiment, the opening 7a connected to the opening 5a is formed in the second insulating layer 7, but the opening 7a does not have to be formed in the second insulating layer 7. In this case, the second insulating layer 7 may be provided, for example, only in a region corresponding to the second electrode 6 when viewed from the Z direction.

[0046] In the above embodiment, the extending portion 64 of the first portion 61 of the second electrode 6 surrounds the entire periphery of the mesa portion 34. However, the extending portion 64 may partially surround the periphery of the mesa portion 34. For example, in the above embodiment, the portions 64c and 64d of the extending portion 64 may not be connected to each other, and a gap may be formed between the portions 64c and 64d. In this case, the extending portion 64 also extends so as to follow at least a portion of each of the four sides of the mesa portion 34 when viewed from the Z direction. Alternatively, the portion 64d may be omitted, and the extending portion 64 may be formed in a U-shape when viewed from the Z direction. When the extending portion 64 partially surrounds the periphery of the mesa portion 34, the extending portion 64 may be formed to surround 50% or more of the periphery of the mesa portion 34 (the periphery of the mesa portion 34) when viewed from the Z direction, or may be formed to surround 80% or more of the periphery of the mesa portion 34. In addition, in the above embodiment, the extending portion 64 extends in two different directions (a direction surrounding the mesa portion 34 clockwise and a direction surrounding the mesa portion 34 counterclockwise in FIG. 2) from the intersection with the third portion 63. However, when the extending portion 64 partially surrounds the periphery of the mesa portion 34, the extending portion 64 may extend in only one direction from the intersection with the third portion 63. When the extending portion 64 extends in two directions starting from the intersection with the third portion 63, the length from the intersection with the third portion 63 to the tip of the extending portion 64 can be made shorter than when the extending portion 64 extends in only one direction. This can increase the efficiency of carrier injection into the optical layer 31, thereby improving the light-emitting efficiency.

[0047] In another modification, the optical semiconductor element 1 may be configured as a light-receiving element. In this modification, the optical semiconductor element 1 is configured as, for example, a photodiode. The optical layer 31 is an absorption layer that absorbs light and is configured to have, for example, a maximum sensitivity wavelength of 3 μm or more and 10 μm or less. The optical layer 31 may also be an absorption layer having a maximum sensitivity wavelength of 3 μm or more and 8 μm or less. The optical layer 31 is configured, for example, similarly to the optical layer 31 in the above embodiment. In the semiconductor laminate 3, light incident through the substrate 2 is absorbed by the optical layer 31, and carriers are generated in the optical layer 31. The generated carriers are extracted via the first pad portion P1 (first electrode 4) and the second pad portion P2 (second electrode 6). According to this modification, for the same reasons as in the above embodiment, it is possible to improve light-receiving efficiency and reliability.

[0048] In the above embodiment, the mesa portion 34 is formed in a trapezoidal shape in a cross section (FIG. 1) perpendicular to the main surface 2a of the substrate 2. However, the mesa portion 34 may be formed in a rectangular shape in a cross section perpendicular to the main surface 2a of the substrate 2. In this case, the side surface 34b may extend along the Z direction.

[0049] The materials of each component are not limited to those mentioned above. For example, the substrate 2 may be made of Si. The barrier layer of the first semiconductor layer 32 may be made of (AlGa). 0.20 In 0.80 The buffer layer and contact layer of the first semiconductor layer 32 are made of In. 0.87 The buffer layers of the second semiconductor layer 33 may be made of GaAs, low-temperature InAs, or In. 0.87 The second semiconductor layer 33 is made of three layers of GaAs. The contact layer and current diffusion layer are made of In. 0.87 The barrier layer of the second semiconductor layer 33 is made of GaAs. 0.20 In 0.80 The first insulating layer 5 and the second insulating layer 7 may be made of SiO2. As another example, the substrate 2 may be made of Si-InP. The barrier layer of the first semiconductor layer 32 may be made of Al.0.15 The buffer layer and contact layer of the first semiconductor layer 32 may be formed from InAs. The buffer layer of the second semiconductor layer 33 is composed of three layers each made of GaAs, low-temperature InAs, and InAs. The contact layer and current diffusion layer of the second semiconductor layer 33 are made from InAs. The barrier layer of the second semiconductor layer 33 is made from Al. 0.15 They may be made of InAs. The first insulating layer 5 and the second insulating layer 7 may be made of SiN.

[0050] The substrate 2 may be formed in a square, circular, or elliptical shape when viewed from the Z direction. The optical layer 31, the first semiconductor layer 32, and the second semiconductor layer 33 may be formed in a square, circular, or elliptical shape when viewed from the Z direction. The first electrode 4 and the second portion 62 of the second electrode 6 may be formed in a square, circular, or elliptical shape when viewed from the Z direction. In addition, the second insulating layer 7 does not have to cover the first portion 61 and the third portion 63 of the second electrode 6.

[0051] In the above embodiment, the openings 5a and 7a are formed so as to be located above the center of the first electrode 4 when viewed from the Z direction. However, the openings 5a and 7a may be formed closer to the edge of the first electrode 4 when viewed from the Z direction. For example, the openings 5a and 7a may be formed farther from the opening 7b than the center of the first electrode 4 when viewed from the Z direction. In this case, a larger distance is ensured between the openings 5a and 7a and the opening 7b than when the openings 5a and 7a are formed so as to be located above the center of the first electrode 4, thereby further suppressing short circuits between the first electrode 4 and the second electrode 6. Furthermore, when the openings 5a and 7a and the opening 7b are each formed closer to the edge of the first electrode 4, the area in which each opening can be formed is increased compared to when one of the openings 5a and 7a and the opening 7b is formed in the center of the first electrode 4. Therefore, the degree of freedom in designing the size and shape of the openings 5a and 7a and the opening 7b can be improved.

[0052] In the above embodiment, the opening 7a is formed in the same circular shape as the opening 5a. However, the opening 7a may have a different size or shape from the opening 5a. As an example, the opening 7a may be formed larger than the opening 5a when viewed from the Z direction. In this case, the step surface 8a has a staircase shape, and the surface area of ​​the step surface 8a is increased compared to when the opening 7a is the same size as the opening 5a. This prevents the solder from leaking out of the opening 7a, even if the amount of solder placed in the openings 5a and 7a during mounting of the optical semiconductor element 1 is greater than the target amount, thereby preventing a short circuit between the first electrode 4 and the second electrode 6. [Explanation of symbols]

[0053] 1... Optical semiconductor element, 2... Substrate, 3... Semiconductor laminate, 4... First electrode, 5... First insulating layer, 5a... Opening (first opening), 6... Second electrode, 7... Second insulating layer, 7a... Opening (third opening), 7b... Opening (second opening) ), 31... optical layer, 32... first semiconductor layer, 33... second semiconductor layer, 34... mesa part, 34a... top surface, 35... outer part, 61... first part, 62... second part, 63... third part, 64... extension part, A... region.

Claims

1. A substrate; a semiconductor laminate including an optical layer that generates or absorbs light, a first semiconductor layer that is disposed on the opposite side of the optical layer from the substrate, and a second semiconductor layer that is disposed on the substrate side of the optical layer, wherein the optical layer and the first semiconductor layer form a mesa portion formed on the second semiconductor layer, and the second semiconductor layer has an outer portion that is located outside the mesa portion; a first electrode formed on the mesa portion and electrically connected to the first semiconductor layer; a first insulating layer formed on the first electrode; a second electrode having a first portion electrically connected to the second semiconductor layer in the outer portion, a second portion disposed on the first insulating layer so as to overlap the first electrode in the thickness direction of the substrate, and a third portion electrically connected to the first portion and the second portion; a second insulating layer formed on the second electrode; a first opening exposing the first electrode is formed in the first insulating layer; a second opening that exposes the second portion of the second electrode is formed in the second insulating layer; The optical semiconductor element, wherein the optical layer is an active layer that generates light having a center wavelength of 3 μm or more and 10 μm or less, or an absorption layer that has a maximum sensitivity wavelength of 3 μm or more and 10 μm or less.

2. the second insulating layer is formed so as to extend from above the second electrode to above the first insulating layer, The optical semiconductor element according to claim 1 , wherein a third opening connected to the first opening is formed in a region of the second insulating layer above the first insulating layer.

3. When viewed in a thickness direction of the substrate, an outer edge of the first electrode is located inside an outer edge of the top surface of the mesa portion, The optical semiconductor element according to claim 1 , wherein the first insulating layer is disposed on a region between the outer edge of the first electrode on the top surface and the outer edge of the top surface.

4. 4. The optical semiconductor element according to claim 1, wherein the first portion has an extending portion that extends so as to surround the mesa portion when viewed in the thickness direction of the substrate.

5. The optical semiconductor element according to claim 4 , wherein the extending portion extends so as to surround the entire periphery of the mesa portion when viewed in the thickness direction of the substrate.

Images