Optoelectronic semiconductor devices, arrays of optoelectronic semiconductor devices, and methods of manufacturing optoelectronic semiconductor devices

Abstract

Optoelectronic semiconductor devices, arrays of optoelectronic semiconductor devices, and methods of fabricating optoelectronic semiconductor devices. An optoelectronic semiconductor device (10) comprising: a semiconductor layer stack (105) including an active zone (115) for generating or receiving electromagnetic radiation, the semiconductor layer stack (105) being patterned to form a mesa (130) having a first laterally measured width w, and a hard mask (123) disposed on the semiconductor layer stack (105) and having a first laterally measured width d, where d>w. The hard mask (123) protrudes from the mesa (130) at a first lateral end and a second lateral end of the mesa (130), the first lateral end and the second lateral end being disposed on opposite sides of the mesa (130) along the first lateral direction. The hard mask (123) includes a conductive layer (125) directly adjacent the semiconductor layer (120) of the semiconductor layer stack (105). The optoelectronic semiconductor device (10) further includes a cover layer (135) disposed on the sidewall (132) of the mesa (130), the cover layer (135) comprising a semiconductor material.

Description

[Background technology]

[0001] An optoelectronic semiconductor device typically includes differently doped semiconductor layers as well as an active zone. For example, when the optoelectronic semiconductor device is implemented as a light-emitting diode (LED), electrons and holes may recombine with each other in the active zone when a corresponding voltage is applied to the optoelectronic semiconductor device. When the electrons and holes recombine with each other, electromagnetic radiation is generated. Mesa etching is typically performed during the fabrication of microLEDs to optically and electrically isolate individual devices or to isolate pixels in an array. Mesa etching is also performed when fabricating photodetectors or other radiation-receiving devices to reduce capacitance and therefore increase speed. Summary of the Invention [Problem to be solved by the invention]

[0002] It is an object of the present invention to provide an improved optoelectronic semiconductor device and an improved method for fabricating an optoelectronic semiconductor device. [Means for solving the problem]

[0003] According to embodiments, the above-mentioned object is achieved by the subject matter claimed in the independent claims. Further developments are defined in the independent claims.

[0004] The optoelectronic semiconductor device includes a semiconductor layer stack including an active zone for generating or receiving electromagnetic radiation, the semiconductor layer stack being patterned to form a mesa having a width w measured in a first laterally direction. The optoelectronic semiconductor device further includes a hard mask disposed on the semiconductor layer stack, the hard mask having a width d measured in a first laterally direction, where d>w. The hard mask protrudes from the mesa at first and second lateral ends of the mesa, the first and second lateral ends being disposed on opposite sides of the mesa along the first lateral direction. The hard mask includes a conductive layer directly adjacent a semiconductor layer of the semiconductor layer stack. The optoelectronic semiconductor device further includes a cover layer disposed over sidewalls of the mesa, the cover layer including a semiconductor material.

[0005] Generally, within this disclosure, the shape of the mesa may be square, circular, square with rounded corners, hexagonal, or hexagonal with rounded corners. For example, the mesa may have a width d measured in a second lateral direction that may intersect the first lateral direction or may be perpendicular to the first lateral direction.

[0006] For example, according to all embodiments, the hard mask may protrude from the mesa at opposite lateral ends of the mesa (e.g., along the second lateral direction). According to embodiments, the hard mask may protrude on any side of the mesa.

[0007] According to all embodiments, the conductive layer may extend from at least one side of the mesa to the other side of the mesa. For example, the conductive layer may protrude at opposite lateral ends of the mesa (e.g., along the second lateral direction). According to embodiments, the conductive layer may protrude on any side of the mesa.

[0008] The hard mask may further include a dielectric layer.

[0009] For example, the width of the cover layer may be at least equal to the difference between d and w, the width being measured in the first lateral direction.

[0010] The band gap of the materials of the cover layers may be larger than the band gap of the active zone (e.g., any layers or quantum well structures that make up the active zone). For example, the band gap of all materials of the cover layers may be larger than the band gap of any layers or quantum well structures that make up the active zone.

[0011] According to an embodiment, the semiconductor layer stack comprises a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type, the active zone being arranged between the first and second semiconductor layers, the second semiconductor layer being directly adjacent to the conductive layer.

[0012] For example, the cover layer may include a first sublayer of a first conductivity type and a second sublayer of a second conductivity type, the first sublayer being immediately adjacent to the sidewall of the mesa. For example, the bandgap of the first sublayer and / or the second sublayer may be larger than the bandgap of the active zone (e.g., any layers or quantum well structures comprising the active zone).

[0013] In an array of optoelectronic semiconductor devices as defined above, adjacent optoelectronic semiconductor devices may be separated from one another by isolation trenches in the cover layer, the isolation trenches extending between the hard masks of adjacent optoelectronic semiconductor devices.

[0014] The array of optoelectronic semiconductor devices includes a semiconductor layer stack including an active zone for generating or receiving electromagnetic radiation, the semiconductor layer stack patterned to form a plurality of mesas having a width w measured in a first laterally direction. The array further includes a hard mask portion disposed on the semiconductor layer stack and having a width d measured in a first laterally direction, where d>w, the hard mask protruding from each mesa at a first lateral end and a second lateral end of each mesa, the first lateral end and the second lateral end being disposed on opposite sides of the mesa along the first lateral direction. The array further includes a cover layer disposed on sidewalls of each mesa, the cover layer including semiconductor material and a plurality of isolation trenches between adjacent optoelectronic semiconductor devices, the isolation trenches extending between and immediately adjacent to the hard mask portions of adjacent optoelectronic semiconductor devices.

[0015] A method for fabricating an optoelectronic semiconductor device includes forming a semiconductor layer stack including an active zone for generating or receiving electromagnetic radiation, forming a hard mask layer over the semiconductor layer stack, patterning the hard mask layer to form a hard mask having a first laterally measured width d, and patterning the semiconductor layer stack to form a mesa having a first laterally measured width w, where d>w. The hard mask protrudes from the mesa at first and second lateral ends of the mesa, the first and second lateral ends being disposed on opposite sides of the mesa along the first lateral direction. The method further includes forming a cover layer on sidewalls of the mesa, the cover layer comprising a semiconductor material, and etching the semiconductor material of the cover layer using the hard mask as an etch mask to form an isolation trench.

[0016] According to an embodiment, patterning the semiconductor layer stack may comprise an anisotropic etching step followed by an isotropic etching step.

[0017] For example, the semiconductor layer stack may include a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type, with the active zone disposed between the first and second semiconductor layers, and the second semiconductor layer formed directly adjacent to the hard mask layer.

[0018] According to an embodiment, forming the hard mask layer includes forming a conductive layer directly adjacent to a second semiconductor layer of the semiconductor layer stack.

[0019] According to a further embodiment, forming the hard mask layer includes forming a dielectric layer directly adjacent to the second semiconductor layer of the semiconductor layer stack.

[0020] The method may further include removing the dielectric layer after forming the isolation trenches.

[0021] According to an embodiment, the method further includes, after forming the isolation trench, forming a passivation layer, removing horizontal portions of the passivation layer to expose a surface of the mesa, and forming a conductive material to cover the surface of the mesa.

[0022] For example, by forming isolation trenches, multiple semiconductor devices can be obtained.

[0023] According to a further embodiment, a portion of the semiconductor layer stack is maintained when forming the isolation trench, in which case adjacent optoelectronic semiconductor devices may be electrically connected by a portion of the semiconductor layer stack.

[0024] An optoelectronic device according to an embodiment includes an optoelectronic semiconductor device or an array of optoelectronic semiconductor devices as previously described.

[0025] The accompanying drawings are included to provide a further understanding of embodiments of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and, together with the description, serve to explain the principles. Other embodiments and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. Elements of the drawings are not necessarily to scale relative to each other. Like reference numerals indicate corresponding like parts. [Brief explanation of the drawings]

[0026] [Figure 1A] 1A-1C illustrate a method of fabricating an optoelectronic semiconductor device. [Figure 1B] 1A-1C illustrate a method of fabricating an optoelectronic semiconductor device. [Figure 1C] 1A-1C illustrate a method of fabricating an optoelectronic semiconductor device. [Figure 1D] 1A-1C illustrate a method of fabricating an optoelectronic semiconductor device. [Figure 1E] 1A-1C illustrate a method of fabricating an optoelectronic semiconductor device. [Figure 1F] 1A-1C illustrate a method of fabricating an optoelectronic semiconductor device. [Figure 1G] 1A-1C illustrate a method of fabricating an optoelectronic semiconductor device. [Figure 1H] 1A-1C illustrate a method of fabricating an optoelectronic semiconductor device. [Figure 1I] 1A-1C illustrate a method of fabricating an optoelectronic semiconductor device. [Figure 1J] 1A-1C illustrate a method of fabricating an optoelectronic semiconductor device. [Figure 1K] 1A-1C illustrate a method of fabricating an optoelectronic semiconductor device and are cross-sectional views of an example optoelectronic semiconductor device. [Figure 2A] 1A-1C illustrate an example of a workpiece as it undergoes further processing steps. [Figure 2B] 1A-1C illustrate an example of a workpiece as it undergoes further processing steps. [Figure 3A] 10A-10C illustrate further processing methods according to embodiments. [Figure 3B] 10A-10C illustrate further processing methods according to embodiments. [Figure 3C] 10A-10C illustrate further processing methods according to embodiments. [Figure 3D] 1A-1C illustrate further processing methods according to embodiments, and are cross-sectional views of optoelectronic semiconductor devices according to further embodiments. [Figure 4A] 5A-5C illustrate processing steps of a method according to a further embodiment. [Figure 4B] 5A-5C illustrate processing steps of a method according to a further embodiment. [Figure 4C] 5A-5C illustrate processing steps of a method according to a further embodiment. [Figure 4D] 5A-5C illustrate processing steps of a method according to a further embodiment. [Figure 4E] 5A-5C illustrate processing steps of a method according to a further embodiment. [Figure 4F] 5A-5C illustrate processing steps of a method according to a further embodiment. [Figure 4G] 5A-5C illustrate processing steps of a method according to a further embodiment. [Figure 5A] 1A-1C are cross-sectional views of a workpiece during processing due to deformation. [Figure 5B] 10 is a cross-sectional view of an optoelectronic semiconductor device according to a further embodiment. [Figure 6] FIG. 1 summarizes a method according to an embodiment. [Figure 7] 1 illustrates an optoelectronic device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0027] In the following detailed description, reference is made to the accompanying drawings, which form a part of this specification and which show, by way of illustration, specific embodiments in which the present invention may be practiced. In this context, directional terminology, such as "top," "bottom," "front," "back," "over," "up," "before," "preceding," and "following," is used with reference to the orientation of the figures being described. Because components of embodiments of the present invention can be positioned in several different orientations, the directional terminology is used for purposes of explanation and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims.

[0028] As used in the following description, the terms "wafer" or "semiconductor substrate" may include any semiconductor-based structure having a semiconductor surface. Wafers and structures should be understood to include doped and undoped semiconductors, epitaxial semiconductor layers (e.g., supported by a base semiconductor substrate), and other semiconductor structures. For example, a layer of a first semiconductor material may be grown on a growth substrate of a second semiconductor material. According to further embodiments, the growth substrate may be an insulating substrate, such as a sapphire substrate. Depending on the intended use, the semiconductor may be based on a direct or indirect semiconductor material. Examples of semiconductor materials that are particularly suitable for generating electromagnetic radiation include nitride compound semiconductors (for example, ultraviolet light or blue light or longer wavelength light can be generated), such as GaN, InGaN, AlN, AlGaN, AlGaInN, phosphide compound semiconductors (for example, green or longer wavelength light can be generated), such as GaAsP, AlGaInP, GaP, AlGaP, and further semiconductor materials, such as AlGaAs, SiC, ZnSe, GaAs, ZnO, Ga2O3, diamond, hexagonal BN, and combinations of these materials. Examples of further semiconductor materials may be silicon, silicon germanium, and germanium. The stoichiometry of compound semiconductor materials may vary. In the context of this specification, the term "semiconductor" also includes organic semiconductor materials.

[0029] The term "vertical" as used herein is intended to describe an orientation that is disposed perpendicular to the first surface of a substrate or semiconductor body.

[0030] The terms "lateral" and "horizontal," as used herein, are intended to describe an orientation parallel to a first surface of a substrate or semiconductor body, which may be, for example, the surface of a wafer or die.

[0031] As used herein, the terms "coupled" and / or "electrically coupled" are not intended to imply that elements must be directly coupled to one another; there may be intervening elements between the "coupled" or "electrically coupled" elements. The term "electrically connected" is intended to describe a low-ohm electrical connection between elements that are electrically connected to one another.

[0032] The term "electrically connected" also includes tunneling contact between the connected elements.

[0033] As used herein, the terms "having," "containing," "including," "comprising," and the like are open-ended terms indicating the presence of stated elements or features, but not the exclusion of additional elements or features. The terms "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0034] The embodiments of the present application will be described with reference to an LED. As will be clearly understood, the optoelectronic semiconductor device according to all embodiments may be implemented as an optical receiving device, for example a photodetector.

[0035] To perform the method according to the embodiment, a semiconductor layer stack 105 is epitaxially grown on a suitable substrate 100. In particular, the substrate 100 may be a growth substrate for certain semiconductor layers of the semiconductor layer stack 105. For example, the semiconductor layer stack 105 may include a first semiconductor layer 110 of a first conductivity type (e.g., n-type), an active zone 115, and a second semiconductor layer 120 of a second conductivity type (e.g., p-type). For example, the semiconductor layers of the semiconductor layer stack 105 may include a phosphide compound semiconductor. For example, the material may be Al n Ga m In 1-n-m P, or In u Ga1-uAs v P 1-v , or mixtures thereof (0≦n≦1, 0≦m≦1, and n+m≦1, 0≦u≦1, 0≦v<1). As will be clearly understood, any other semiconductor material may be used.

[0036] In the context of this specification, the term "active zone" refers to a layer of an optoelectronic device that is configured to generate the electromagnetic radiation emitted by the optoelectronic device. Specific examples include, among others, a pn junction, a double heterostructure, a single quantum well structure (SQW), a multiple quantum well (MQW) structure, and / or a quantum cascade structure, and any combination of these structures. According to further embodiments, the term "active zone" also refers to a layer of an optoelectronic device that absorbs electromagnetic radiation.

[0037] 1A shows an example of the resulting workpiece 20. A conductive layer 125 may then be formed on the semiconductor layer stack 105, as illustrated in FIG. 1B. For example, the conductive layer 125 may be a transparent conductive oxide layer, such as ITO (indium tin oxide). The conductive layer 125 may be formed in direct contact with the second semiconductor layer 120.

[0038] 1C, a dielectric layer 124 may be formed on the conductive layer 125. The dielectric layer 124 may include, for example, silicon oxide or silicon nitride. The material of the dielectric layer 124 may be selected so that the dielectric layer is not etched during etching of the underlying layer. Furthermore, the material of the dielectric layer 124 may be selected so that the dielectric layer 124 can be etched selectively with respect to a passivation layer to be formed in a subsequent step. The dielectric layer 124 may include several sublayers. The dielectric layer 124 and the conductive layer 125 constitute part of the hard mask layer 123. According to an embodiment, the conductive layer 125 may be omitted.

[0039] 1D , a photoresist layer 127 is formed on the hard mask layer 123. The photoresist layer 127 is patterned, for example, using a photolithography method. For example, the photoresist layer 127 may be patterned into squares. The patterned photoresist material 127 is used as an etching mask to pattern the hard mask layer 123. In particular, portions of the dielectric layer 124 and the conductive layer 125 that are not covered by the photoresist material are etched.

[0040] Figure 1E shows an example of the resulting workpiece 20. As shown in Figure 1E, portions of second semiconductor layer 120 are covered by hard mask 123 and photoresist material 127. Other portions of second semiconductor layer 120 are not covered by hard mask 123 and are therefore exposed.

[0041] In the next step, an etching process is performed to etch the semiconductor layer stack 105. Specifically, the etching includes an anisotropic etching step in which the etching rate in the vertical direction is greater than that in the horizontal direction. For example, the etching process may include a dry or plasma etching process. The etching is performed to completely etch the second semiconductor layer 120, the active zone 115, and a portion of the first semiconductor layer 110. Furthermore, an isotropic etching process is performed. For example, the etching process may include a wet etching step. This etching step exposes the portion of the hard mask 123 facing the substrate 100. For example, if the semiconductor layer of the semiconductor layer stack includes a layer in the (In)Ga(Al)P material system, the etching solution may include HCl. For example, this etching may determine the width w of the mesa 130.

[0042] 1F illustrates an example of the resulting workpiece 20. As shown, the hard mask protrudes laterally from the mesa 130 at a first lateral end and a second lateral end of the mesa 130. The first lateral end and the second lateral end are disposed on opposite sides of the mesa 130 along the first lateral direction. The hard mask 123 includes a conductive layer directly adjacent a semiconductor layer of the semiconductor layer stack 105. The hard mask 123 is disposed on the semiconductor layer stack and has a width d measured in the first lateral direction.

[0043] The mesa 130 has two opposing sidewalls 132. The sidewalls 132 extend in a direction intersecting the horizontal direction. For example, the sidewalls 132 may extend vertically. According to further embodiments, the extension direction of the sidewalls 132 may be inclined relative to the vertical direction. For example, the mesa 130 may have a tapered shape such that the diameter of the mesa 130 on the side facing the growth substrate 100 is larger than the diameter of the mesa 130 on the side away from the growth substrate 100.

[0044] The difference between the width d of the hard mask 123 and the width w of the mesa 130 can be determined by an isotropic etching process. For example, the difference can be greater than 0.2 μm. The difference to be set depends on the diffusion length of charge carriers and therefore the specific semiconductor material used. The difference can be designed according to the material parameters and the width of the resulting optoelectronic semiconductor device (pixel).

[0045] 1G shows an example of the resulting workpiece 20 after removing the photoresist material 127. For example, a wet cleaning step may be performed to clean the resulting surface.

[0046] A cover layer 135 is then formed on the sidewalls 132 of the mesa 130. The cover layer comprises a semiconductor material.

[0047] The cover layer 135 may be formed epitaxially, for example, using an MOCVD ("metal organic chemical vapor deposition") process. For example, the material of the cover layer 135 may include a III-V or II-VI semiconductor material. For example, the bandgap of the cover layer 135 may be larger than the bandgap of the active zone 115. For example, the bandgap material of the cover layer 135 may be larger than the bandgap of any layer or quantum well structure that makes up the active zone 115.

[0048] For example, the cover layer 135 may include GaN, AlGaP, InAlP, or ZnSSe. The cover layer 135 may be doped or semi-insulating. For example, the cover layer may include several sublayers of opposite polarity, e.g., n-type, p-type, or semi-insulating. The cover layer 135 may fill the space between adjacent mesas.

[0049] For example, as shown in FIG. 1H , the cover layer may include a first sublayer 1361 and a second sublayer 1362. The first sublayer 1361 may be of a second conductivity type, e.g., p-type in this example. Furthermore, the second sublayer 136 may be of a first conductivity type, e.g., n-type in this example. As a result, current is blocked around the active portion of the mesa 130. By appropriately selecting materials, ohmic contact from the conductive layer 125 to the semiconductor device is limited only to the second semiconductor layer 120. For example, the band gap of the first sublayer 1361 and / or the second sublayer 1362 may be larger than the band gap of the layers of the active zone 115 as well as the upper contact layer of the layer stack 120. As also shown in FIG. 1H , some of the cover material 135 may be formed on the hard mask layer 123.

[0050] In a next step, for example, this additional material of cover layer 135 may be removed from hard mask 123, for example by polishing. According to a further embodiment, this portion of cover material 135 may be removed during a subsequent processing step. An example of the resulting workpiece 20 is shown in FIG. 1I.

[0051] In a next step, isolation trenches 140 are formed to separate adjacent optoelectronic semiconductor devices (pixels) 10 from one another. The isolation trenches 140 are formed using the hard mask 123 as an etching mask. In particular, an etching step is performed to etch the cover layer 135. For example, this may be achieved using an anisotropic etching method, such as dry etching. For example, the isolation trenches 140 may be formed to extend down to the substrate 100. According to a further example, the isolation trenches 140 may be formed so as not to extend down to the substrate 100. For example, a pixel array may be formed by forming isolation trenches 140 that do not completely separate single pixels. In this case, adjacent pixels may be connected by a portion of the first semiconductor layer 110.

[0052] 1J illustrates an example of a resulting workpiece 20 that may be obtained when isolation trenches 140 are formed to extend to the substrate 100. As illustrated, a plurality of optoelectronic semiconductor devices 10 are disposed on the substrate 100, with the optoelectronic semiconductor devices 10 separated from one another by isolation trenches 140. After forming the isolation trenches 140, the cover layer 135 may have a width s at least equal to the difference between d and w, where the width s is measured in a lateral direction, e.g., a first lateral direction. According to an embodiment, the cover layer 135 may have a width s at least equal to the difference between d and w, where the width s is measured in the first lateral direction as well as in a second lateral direction (which may be perpendicular to the first lateral direction).

[0053] The dielectric layer 124 may then be removed from the single optoelectronic semiconductor device 10, for example, using an etching process. According to an embodiment, a further cleaning step may be performed to clean the resulting surface. An example of the resulting structure is shown in Figure 1K.

[0054] 1K illustrates an example of an optoelectronic semiconductor device according to an embodiment. The optoelectronic semiconductor device 10 includes a semiconductor layer stack 105 that includes an active zone 115 for generating or receiving electromagnetic radiation. The semiconductor layer stack 105 is patterned to form a mesa 130 having a width w measured in a first lateral direction (e.g., the x-direction). The mesa 130 may also have a width w measured in a second lateral direction that may be perpendicular to the first lateral direction. For example, the second lateral direction may be the y-direction.

[0055] The semiconductor device 10 further includes a hard mask 123 disposed on the semiconductor layer stack 105 and having a width d (d>w) measured in a first lateral direction. For example, by isotropic etching as described with reference to FIG. 1F , the hard mask 123 protrudes from the mesa 130 at first and second lateral ends of the mesa 130. The first and second lateral ends are disposed on opposite sides of the mesa along the first lateral direction. The hard mask 123 includes a conductive layer 125 directly adjacent a semiconductor layer of the semiconductor layer stack 105. The optoelectronic semiconductor device 10 further includes a cover layer 135 disposed on the sidewalls 132 of the mesa 130. The cover layer 135 includes a semiconductor material.

[0056] For example, the hard mask may protrude from the mesa 130 at opposite lateral ends of the mesa, e.g., along the second lateral direction. According to an embodiment, the hard mask 123 may protrude on any side of the mesa 130.

[0057] 1K, the conductive layer 125 may extend from at least one side of the mesa to the other side of the mesa 130. For example, the conductive layer 125 may protrude at opposing lateral ends of the mesa, e.g., along the second lateral direction. According to an embodiment, the conductive layer 125 may protrude on any side of the mesa 130.

[0058] 1K, the cover layer 135 is disposed below the hard mask layer 123. For example, a portion of the cover layer 135 is not disposed on the horizontal portions of the second semiconductor layer 120. Alternatively, a portion of the cover layer 135 may be disposed on the horizontal portions of the first semiconductor layer 110. For example, as illustrated in FIG. 1K, the cover layer 135 may be flush with the hard mask layer 123. This may be due to the fact that the hard mask was used to define the isolation trench 140. The hard mask 123 and the cover layer 135 may encapsulate the active zone 115, the second semiconductor layer 120, and a portion of the first semiconductor layer 110.

[0059] The cover layer 135 may be epitaxially grown. For example, atoms or molecules of the cover layer may bond to dangling or dangling bonds on the sidewalls of the mesa 130 in the region of the active zone 115. For example, after etching the mesa, the mesa edge may have defects and contain dangling bonds that can serve as recombination centers. As a result, non-radiative bonding of the substrate may occur at the mesa edge. The presence of the cover layer may remove these dangling bonds or bond them to atoms or molecules of the cover layer 135. Therefore, non-radiative recombination may be reduced.

[0060] As previously mentioned, the alignment accuracy of the isolation trenches 140 can be greatly improved because the hard mask 123 used to etch the mesas is also used to define the isolation trenches 140. More specifically, self-aligned formation of the optoelectronic semiconductor device 10 is enabled.

[0061] In particular, when the width of the pixel or optoelectronic semiconductor device is small, e.g., on the order of 1 μm laterally, the alignment of the isolation trenches 140 becomes more accurate, thereby improving performance between the fabricated optoelectronic semiconductor devices on a wafer-wide and wafer-to-wafer scale. Even more particularly, when the size of the optoelectronic semiconductor device is small, the distance from the central portion of the active zone to the edge of the optoelectronic semiconductor device can determine the degree of non-radiative recombination. Therefore, more uniform performance can be achieved when this distance is set to a uniform value across the wafer or on a wafer-to-wafer scale. Also, the additional processing step of photolithography to define the location of the isolation trenches 140 may be omitted.

[0062] For example, the conductive layer 125 may comprise a transparent conductive oxide such as ITO, which is not attacked during wet etching processes and is stable at high temperatures (e.g., the temperatures during the growth of the cover layer 135).

[0063] 1K also illustrates an array 15 of optoelectronic semiconductor devices 10. Array 15 includes a semiconductor layer stack 105 including an active zone 115 for generating or receiving electromagnetic radiation, the semiconductor layer stack 105 being patterned to form a plurality of mesas 130 having a width w measured in a first laterally direction. Array 15 further includes a portion of a hard mask 123 disposed on semiconductor layer stack 105 and having a width d measured in a first laterally direction, where d>w, the hard mask 123 protruding from each mesa 130 at a first lateral end and a second lateral end of each mesa 130, the first lateral end and the second lateral end being disposed on opposite sides of the mesa 130 along the first lateral direction. The array further includes a cover layer 135 disposed on the sidewalls of each mesa 130, the cover layer 135 including a semiconductor material and a plurality of isolation trenches 140 between adjacent optoelectronic semiconductor devices 10, the isolation trenches 140 extending between and directly adjacent to the hard masks 123 of the adjacent optoelectronic semiconductor devices 10.

[0064] According to a further embodiment, the conductive layer 125 may be omitted.

[0065] FIG. 2A shows an example of a workpiece 20. Here, the hard mask does not include a conductive layer 125, but includes a dielectric layer 124. The dielectric layer 124 may be in direct contact with the second semiconductor layer 120. In this case, after etching the isolation trench 140, the workpiece 20 illustrated in FIG. 2A may be obtained. The mesa 130 is covered by the dielectric layer 124. Then, as shown in FIG. 2B, the dielectric layer 124 may be optionally removed, for example, by polishing or etching. As a result, the surface of the second semiconductor layer 120 may be exposed. According to further modifications, the dielectric layer 124 may include two or more sublayers. For example, in this case, only the upper sublayer may be removed, and the sublayer in contact with the first semiconductor layer 120 may be maintained.

[0066] FIG. 2B shows a further example of an optoelectronic semiconductor device 10 or an array 15 of optoelectronic semiconductor devices.

[0067] Starting from either FIG. 2A, 1J, or 1K, the process illustrated in FIGS. 3A-3B may be performed. For example, a passivation layer 143 may be deposited on workpiece 20. For example, passivation layer 143 may be deposited to cover the surface of dielectric layer 124 or conductive layer 125. Furthermore, passivation layer 143 covers cover layer 135, i.e., sidewall 132 of mesa 130. FIG. 3A shows an example of the resulting workpiece 20.

[0068] A polishing step may then be performed to polish the horizontal portions of the passivation layer 143 located on the mesas 130, thereby exposing the surfaces of the dielectric layer 124 or the conductive layer 125.

[0069] As illustrated in FIG. 3B , polishing can expose the surface of the dielectric layer or conductive layer 125 without attacking the passivation layer 143 on the sidewalls. The sidewalls of the isolation trench 140 are covered by the passivation layer 143. For example, the dielectric layer 124 can be removed from the surface of the second semiconductor layer 120 for further processing. After this processing step, the surface of the second semiconductor layer 120 is exposed or covered by the conductive layer 125. A contact layer 145 can then be formed on the surface of the workpiece 20. For example, the contact layer 145 can include a metal or a transparent conductive oxide such as ITO.

[0070] 3C shows an example of the resulting workpiece 20. A contact layer 145 is formed in direct contact with the second semiconductor layer. A passivation layer 143 separates the sidewalls of the mesa 130 from the contact layer 145.

[0071] Thereafter, as illustrated in Figure 3D, a bonding metal 147 may be formed on the surface of the workpiece, followed by a support 149. For example, the bonding metal 147 may include a metal suitable for reflecting light back through the semiconductor and bonding the workpiece 20 to the support 149. Figure 3D shows a cross-sectional view of a plurality of semiconductor devices 10 or an array 15 of semiconductor devices 10 according to a further embodiment.

[0072] Thereafter, for example, the substrate 100 may be removed from the workpiece to allow placement of a second contact to the device. This second contact may be obtained through a groove so that both contacts are formed on the same side. Light emission may be through the side remote from the bonded support. Other processing steps are also possible, such as making the array transfer printable onto an electronic driver (e.g., CMOS) wafer or directly bonded onto a driver wafer.

[0073] For example, starting with a workpiece similar to that described with reference to FIG. 3B, the processes illustrated in FIGS. 4A-4G may be performed. The workpiece 20 shown in FIG. 4A includes an isolation trench 140 that does not extend to the substrate 100. Adjacent optoelectronic semiconductor devices 10 are electrically connected by portions of the first semiconductor layer 110. The workpiece 20 is similar to the workpiece 20 shown in FIG. 3B and includes a dielectric layer 124 on the second semiconductor layer 120. Horizontal portions of the passivation layer 143 are removed to expose portions of the surface of the first semiconductor layer. A conductive material may then be filled into the isolation trench 140. As a result, first contact elements 111 are formed in the isolation trench 140. A planarization step may be performed to remove the conductive material from the planar surface of the workpiece 120 (FIG. 4A). A release layer 150 may then be formed on the resulting surface. An opening 151 is formed in the release layer 150 (FIG. 4B).

[0074] 4C, an intermediate support 154 may then be attached to the release layer 150 via an adhesive layer 152. The adhesive layer 152 fills the openings to form posts 153. The substrate 100 is then removed from the resulting workpiece.

[0075] An example of the resulting workpiece is shown in Figure 4D. The release layer 150 is then removed, leaving the group 103 of optoelectronic semiconductor devices attached to an intermediate support 154 via posts 153 (Figure 4E). As shown in Figure 4F, the group 103 is then transferred to a target support 155. For example, the lateral dimension S4 of the target support 155 may be greater than the lateral dimension S1 of the substrate 100.

[0076] Thereafter, a second contact pad 122 may be formed to connect to the second contact element 121, as shown in FIG. 4G.

[0077] A wiring pattern may then be provided on the target support 155, for example, to electrically connect the second contact elements 121 to the second contact pads 122 and to address the first contact elements 111. Further wiring schemes may be applied to electrically contact the first and second semiconductor layers of each optoelectronic semiconductor device. For example, the first and second contact elements 111, 121 may be formed from opposite sides of the workpiece 20.

[0078] 5A shows a cross-sectional view of workpiece 20 that may be obtained when performing the described process using the workpiece illustrated in FIG. 3B, in which conductive layer 125 is present on the surface of the mesa. As illustrated in FIG. 5A, contact layer 145 is formed in direct contact with conductive layer 125 (e.g., the ITO layer that was part of hard mask layer 123). Passivation layer 143 separates the sidewalls of mesa 130 from contact layer 145.

[0079] Thereafter, as illustrated in Figure 5B, a bonding metal 147 may be formed on the surface of the workpiece illustrated in Figure 5A, followed by a support 149. For example, the bonding metal 147 may include a suitable metal that reflects light back through the semiconductor layer and bonds the workpiece 20 to the support 149. Figure 5B shows a cross-sectional view of a plurality of semiconductor devices 10 or an array 15 of semiconductor devices 10 according to a further embodiment.

[0080] Thereafter, for example, the substrate 100 may be removed from the workpiece to allow placement of a second contact element on the device. This second contact element may be obtained through a groove so that both contacts are formed on the same side. For example, forming the first and second contact elements may be achieved in the manner described with reference to FIGS. 4A-4G. According to further embodiments, the first and second contact elements 111, 121 may be formed from opposite sides of the workpiece 20. Light emission may occur through the side remote from the bonded support. Other processing steps are also possible, such as making the array transfer printable onto an electronic driver (e.g., CMOS) wafer or directly bonded onto the driver wafer.

[0081] The described contacting of the semiconductor layer 120 or the conductive layer 125 may be achieved using lithography and etching processes. For example, instead of polishing the passivation layer 143, the passivation layer 143 over the pixel may be etched to expose the semiconductor layer 120 or the conductive layer 125.

[0082] 6 summarizes a method according to an embodiment. As shown, a method for fabricating an optoelectronic semiconductor device includes forming a semiconductor layer stack (S100) including an active zone for generating electromagnetic radiation, forming a hard mask layer on the semiconductor layer stack (S110), patterning the hard mask layer (S120) to form a hard mask having a first laterally measured width d, and patterning the semiconductor layer stack (S130) to form a mesa having a first laterally measured width w, where d>w. The hard mask layer protrudes from the mesa at first and second lateral ends of the mesa, the first and second lateral ends being disposed on opposite sides of the mesa along the first lateral direction. The method further includes forming (S140) a cover layer on the sidewalls of the mesa, the cover layer including a semiconductor material, and etching (S150) the semiconductor material of the cover layer using the hard mask as an etch mask to form an isolation trench.

[0083] 7 illustrates an optoelectronic device 25 according to an embodiment. The optoelectronic device 25 includes the optoelectronic semiconductor device 10 or an array 15 of optoelectronic semiconductor devices 10 described above. For example, the optoelectronic device may be a display device for augmented reality or virtual reality applications. According to a further embodiment, the optoelectronic device 25 may be a high-speed photodetector.

[0084] While embodiments of the present invention have been described above, it will be apparent that additional embodiments may be practiced. For example, additional embodiments may include any subcombination of the features recited in the claims or any subcombination of the elements recited in the preceding examples. Accordingly, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein. [Explanation of symbols]

[0085] 10 Optoelectronic semiconductor devices Array of 15 optoelectronic semiconductor devices 20 workpieces 25 Optoelectronic devices 100 boards 102 insulating layer Group of 103 optoelectronic semiconductor devices (pixels) 105 semiconductor layer stack 110 first semiconductor layer 111 first contact element 115 active zones 120 second semiconductor layer 121 second contact element 122 second contact pad 123 Hard Mask 124 dielectric layers 125 Conductive Layer 127 Photoresist materials 130 Mesa Sidewall of Mesa 132 135 cover layers 1361 first sublayer of cover material 1362 second sublayer of cover material 140 separation groove 143 Passivation Layer 145 contact layer 147 joining metal 149 support 150 peeling layers 151 Opening 152 bonding layer 153 posts 154 intermediate support 155 target support

Claims

1. A method for manufacturing an optoelectronic semiconductor device (10), comprising: forming (S100) a semiconductor layer stack (105) including an active zone (115) for generating or receiving electromagnetic radiation; Then, forming a hard mask layer on the semiconductor layer stack (105) (S110); Thereafter, patterning the hard mask layer (S120) to form a hard mask (123) having a first lateral width d; thereafter, patterning (S130) the semiconductor layer stack (105) to form a mesa (130) having a width w measured in a first lateral direction, d>w, wherein the hard mask (123) protrudes from the mesa at a first lateral end and a second lateral end of the mesa, the first lateral end and the second lateral end being disposed on opposite sides of the mesa (130) along the first lateral direction; Then, forming a cover layer (135) on the sidewall (132) of the mesa (130) (S140), the cover layer (135) including a semiconductor material; Thereafter, etching (S150) the semiconductor material of the cover layer (135) using the hard mask (123) as an etching mask to form isolation trenches (140).

2. 10. The method of claim 1, wherein patterning (S130) the semiconductor layer stack (105) comprises an anisotropic etching step followed by an isotropic etching step.

3. 3. The method of claim 1, wherein the semiconductor layer stack (105) comprises a first semiconductor layer (110) of a first conductivity type and a second semiconductor layer (120) of a second conductivity type, the active zone (115) being disposed between the first semiconductor layer (110) and the second semiconductor layer (120), and the second semiconductor layer (120) being formed directly adjacent to the hard mask layer (123).

4. 4. The method of claim 3, wherein forming the hard mask layer (123) comprises forming a conductive layer (125) directly adjacent the second semiconductor layer (120) of the semiconductor layer stack (105).

5. 4. The method of claim 3, wherein forming the hard mask layer (123) comprises forming a dielectric layer (124) directly adjacent the second semiconductor layer (120) of the semiconductor layer stack (105).

6. The method of claim 5, further comprising removing the dielectric layer (124) after forming the isolation trench (140).

7. forming a passivation layer (143) after forming the isolation trench; removing horizontal portions of the passivation layer (143) to expose a surface of the mesa (130); The method of claim 1 further comprising forming a conductive material (145) overlying the surface of the mesa.

8. The method of claim 1, wherein forming the isolation trenches (140) results in a plurality of semiconductor devices (10).

9. The method of claim 1 , wherein a portion of the semiconductor layer stack (105) is maintained when forming the isolation trench (140).

10. An optoelectronic semiconductor device (10), comprising: a semiconductor layer stack (105) including an active zone (115) for generating or receiving electromagnetic radiation, the semiconductor layer stack (105) being patterned to form a mesa (130) having a first laterally measured width w; a hard mask (123) disposed on the semiconductor layer stack (105) and having a width d measured in the first lateral direction, where d>w, the hard mask (123) protruding from the mesa (130) at a first lateral end and a second lateral end of the mesa (130), the first lateral end and the second lateral end being disposed on opposite sides of the mesa along the first lateral direction, the hard mask (123) including: a conductive layer (125) having a width d measured in the first lateral direction directly adjacent a semiconductor layer (120) of the semiconductor layer stack (105); and a dielectric layer (124) disposed on the conductive layer and having a width d measured in the first lateral direction; a cover layer (135) disposed on a sidewall (132) of the mesa (130), the cover layer (135) comprising a semiconductor material.

11. 11. The optoelectronic semiconductor device (10) of claim 10, wherein the width s of the cover layer (135) is at least equal to the difference between d and w, said width s being measured in said first lateral direction.

12. 12. An optoelectronic semiconductor device (10) according to claim 10 or 11, wherein the bandgap of the material of said cover layer (135) is larger than the bandgap of said active zone.

13. 11. The optoelectronic semiconductor device of claim 10, wherein the semiconductor layer stack (105) comprises a first semiconductor layer (110) of a first conductivity type and a second semiconductor layer (120) of a second conductivity type, the active zone (115) being disposed between the first semiconductor layer (110) and the second semiconductor layer (120), and the second semiconductor layer (120) being directly adjacent to the conductive layer (125).

14. The cover layer includes a first sublayer (136) of the second conductivity type. １ ) and a second sublayer (136) of said first conductivity type ２ ), and said first sublayer (136 １ 14. The optoelectronic semiconductor device (10) of claim 13, wherein a lateral surface (132) of the mesa (130) is directly adjacent to the sidewall (132) of the mesa (130).

15. The first sublayer (136 １ 15. The optoelectronic semiconductor device (10) of claim 14, wherein the bandgap of said first gate electrode (12) is greater than the bandgap of said active zone.

16. The second sublayer (136 ２ 16. An optoelectronic semiconductor device (10) according to claim 14 or 15, wherein the bandgap of said first gate electrode (Gd) is greater than the bandgap of said active zone.

17. 11. The array (15) of optoelectronic semiconductor devices (10) of claim 10, wherein adjacent optoelectronic semiconductor devices (10) are separated from one another by isolation trenches (140) in the cover layer (135), the isolation trenches (140) extending between the hard masks (123) of the adjacent optoelectronic semiconductor devices (10).

18. a semiconductor layer stack (105) including an active zone (115) for generating or receiving electromagnetic radiation, the semiconductor layer stack (105) being patterned to form a plurality of mesas (130) having a first laterally measured width w; a portion of a hard mask (123) including a dielectric layer (124), the portion of the hard mask (123) being disposed on the semiconductor layer stack (105) and having a width d measured in the first lateral direction, d>w, the hard mask (123) protruding from each of the mesas (130) at a first lateral end and a second lateral end of each of the mesas (130), the first lateral end and the second lateral end being disposed on opposite sides of the mesa (130) along the first lateral direction; a cover layer (135) disposed on a sidewall (132) of each of the mesas (130), the cover layer (135) comprising a semiconductor material; an array (15) of optoelectronic semiconductor devices (10), comprising: a plurality of isolation trenches (140) between adjacent optoelectronic semiconductor devices (10), the isolation trenches (140) extending between the portions of the hard mask (123) of adjacent optoelectronic semiconductor devices (10) and directly adjacent to the portions of the hard mask (123) of the adjacent optoelectronic semiconductor devices (10).

19. An optoelectronic apparatus (25) comprising an optoelectronic semiconductor device (10) according to claim 10 or an array (15) of optoelectronic semiconductor devices (10) according to claim 17.

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