Image Sensor

Abstract

To provide an image sensor and image-sensing method capable of operating in low noise and with low power even though a pixel is configured of three transistors.SOLUTION: An image sensor 1 includes: a plurality of pixels 10 two-dimensionally disposed in row direction and column direction; a vertical scan circuit 11 for selecting pixels on a specific row; a plurality of analog to digital converters 12 for performing analog to digital conversion in column parallel, on signals from a pixel 10 selected by the vertical scan circuit 11; and a control part 14 for controlling the above-mentioned components. The image sensor outputs, as an analog to digital converted value of a pixel signal, a difference value between a reference signal value and an accumulated signal value, the reference signal value being obtained by digital-converting, by the analog to digital converter 12, a difference between a first reset voltage taken out by a voltage buffer part in each pixel 10 of the selected row and a voltage at reset release, and the accumulated signal value being obtained by digital-converting, by the analog to digital converter 12, a difference between a voltage immediately before a second reset operation taken out by the voltage buffer part and a voltage at the second reset.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an image sensor Sa Regarding. [Background technology]

[0002] Image sensors generally consist of multiple pixels, each equipped with a photoelectric sensor that converts optical signals into electrical signals and a transistor that controls the electrical signals, arranged two-dimensionally in the row and column directions, a column A / D (analog-to-digital) converter that converts the electrical signals of each row and column into digital values, and a scanning circuit that controls each pixel. Furthermore, by using photoelectric films such as organic thin films, quantum dot thin films, and carbon-based thin films in the photoelectric sensors, it becomes possible to detect light in wavelength ranges such as infrared light, which could not be detected by silicon photodiodes that have been used until now. In addition, by combining multiple photoelectric films with different properties, it becomes possible to give image sensors various functions.

[0003] 16 is a circuit diagram showing the configuration of a pixel using a photoelectric film. The pixel 100 shown in 16 includes a reset transistor M0 that resets the photoelectric film 110 to a predetermined voltage, a capacitance C H 16 includes a transistor M1 that configures a source follower, and a transistor M2 that selects a pixel and selectively outputs a voltage proportional to the accumulated charge to a common signal line D via the source follower. A configuration having three transistors as shown in FIG. 16 is generally called a three-transistor configuration (see, for example, Patent Document 1 and Non-Patent Document 1).

[0004] Fig. 17 is a block diagram showing an example of the configuration of an image sensor using the pixels 100 shown in Fig. 16. In the image sensor shown in Fig. 17, the pixels 100 are arranged two-dimensionally in the row and column directions, and each pixel 100 is controlled row by row by a vertical scanning circuit 101, and signals are extracted sequentially. The signals of the pixels 100 in each selected row are then converted into digital values ​​by a plurality of A / D converters 102. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-165760 [Non-patent literature]

[0006] [Non-Patent Document 1] Takao Kuroda, "The Essence and Fundamentals of Image Sensors," Corona Publishing, December 21, 2012, pp. 96-110 Summary of the Invention [Problem to be solved by the invention]

[0007] However, the conventional three-transistor pixel described above has the problem that it is difficult to perform effective correlated double sampling and that noise is large.

[0008] FIG. 18 shows the capacitance C H Terminal voltage V G 18 is a waveform diagram showing the pixel signal readout period. The portion enclosed by the dashed line in FIG. 18 indicates the pixel signal readout period. As shown in FIG. 18, the reset signal RST first goes to "H", and the transistor M0 turns on the capacitor C H Terminal voltage V G is the reset voltage V RST(n-m) Here, n is the row number from which the signal is read out, and m is the exposure time expressed in number of rows. This reset voltage V RST(n-m) is the threshold voltage of transistor M0, V TH0 , power supply voltage V DD and is expressed by the following formula 1.

[0009]

number

[0010] Next, when the reset signal RST is set to "L" to turn off the transistor M0, the voltage V STD(n-m) is expressed by the following formula 2. Note that V n(n-m) is the capacitance C H is the noise voltage including the kT / C noise and the offset voltage due to switch feedthrough.

[0011]

number

[0012] When exposure begins, the terminal voltage V SIG(n) is the voltage V STD(n-m) Starting from the point, the current excited by light is I p , and the retention capacity is C H , one horizontal period is T H is expressed by the following Equation 3.

[0013]

number

[0014] Next, after reading out the signal, if the reset signal RST is set to "H", the terminal voltage V G Since this is the voltage shown in the above formula 1, it is expressed by the following formula 4.

[0015]

number

[0016] Therefore, the voltage V expressed by the above formula 3 SIG(n) Therefore, the voltage V expressed by the above formula 4 RST(n) The output voltage V is calculated by subtracting CDS(n) is expressed by the following Equation 5.

[0017]

number

[0018] The voltage V of the MOS transistor M0 shown in Equation 5 above TH Since the voltage of the signal line D is not affected by variations in the threshold voltage of the transistor, it can be prevented from appearing in the signal obtained by canceling out the voltage of the signal line D. Similarly, when the voltage of the signal line D is converted into a digital signal, it is read out via a source follower formed by the transistor M1, and the gate-source voltage is V GS1 Then, the read voltage is affected by this voltage, but the signal voltage V SIG(n) and signal voltage V RST(n) Since the difference in read time is short, the voltage V GS1 It is considered that there is almost no change in the voltage V GS1 is cancelled out by correlated double sampling (CDS), and the effect is almost invisible.

[0019] However, as shown in the above formula 5, in a conventional pixel with a three-transistor configuration, the noise V n(n-m) As a result, image sensors with conventional three-transistor pixel configurations have a significant problem of high noise, which reduces the signal-to-noise ratio (SNR) and causes image quality degradation, especially in low light conditions.

[0020] Therefore, the present invention provides an image sensor that operates with low noise and low power consumption even if the pixel has a three-transistor configuration. Sa The purpose is to provide. [Means for solving the problem]

[0021] In order to solve the above-mentioned problems, the present inventors have studied signal readout from CMOS image sensors and discovered that, rather than performing correlated double sampling by taking the voltage difference between the signal voltage of the storage capacitor after exposure and the reset voltage as in the conventional method, it is possible to perform correlated double sampling by taking the voltage difference between the reset signal before the start of exposure and the voltage of the storage capacitor immediately after the reset is released, and by obtaining the difference between these two correlated double sampled signals, it is possible to cancel the effects of noise and transistor threshold drift, leading to the present invention.

[0022] That is, the image sensor according to the present invention comprises a plurality of pixels arranged two-dimensionally in row and column directions, a vertical scanning circuit that selects pixels in a specific row, a plurality of analog-to-digital converters that perform analog-to-digital conversion in column-parallel on signals from each pixel in the row selected by the vertical scanning circuit, and a control unit that controls the pixels, the vertical scanning circuit, and the analog-to-digital converters, The pixel includes a photoelectric conversion element that converts an optical signal into a current, a capacitance that accumulates the current converted by the photoelectric conversion element and converts it into a signal voltage, a reset unit that resets the capacitance to a predetermined voltage, and a voltage buffer unit that receives the voltage of the capacitance as an input, The control unit controls the following operations: (1) a first reset operation in which the reset unit resets the capacitance to a predetermined voltage in each pixel of a specific row selected by the vertical scanning circuit, and then releases the reset; (2) an operation in which the analog-to-digital converter converts the difference between the first reset voltage extracted by the voltage buffer unit of each pixel of the specific row and the voltage at the time of the reset release into a digital value, and stores the value in memory as a reference signal value; (3) an operation in which, after a certain exposure time has elapsed since the reset release, the second reset operation is performed, and the analog-to-digital converter converts the difference between the voltage extracted by the voltage buffer unit just before the second reset operation and the voltage at the time of the second reset into a digital value, and uses the digital value as an accumulation signal value; and (4) an operation in which the difference value between the reference signal value stored in memory and the accumulation signal value is output as an analog-to-digital conversion value of the pixel signal.

[0023] Furthermore, an image sensing method according to the present invention is a method of performing image sensing using an image sensor having a plurality of pixels arranged two-dimensionally in row and column directions, a vertical scanning circuit that selects pixels in a specific row, a plurality of analog-to-digital converters that perform column-parallel analog-to-digital conversion of signals from each pixel in the row selected by the vertical scanning circuit, and a control unit that controls the pixels, the vertical scanning circuit, and the analog-to-digital converters, wherein the pixels each include a photoelectric conversion element that converts an optical signal into a current, a capacitor that accumulates the current converted by the photoelectric conversion element and converts it into a signal voltage, a reset unit that resets the capacitor to a predetermined voltage, and a voltage buffer unit that receives as input the voltage of the capacitor, a step of performing a first reset operation by the reset unit for pixels in a specific row selected by the vertical scanning circuit, resetting capacitances of the pixels to a predetermined voltage, and then releasing the set state; converting a difference between the first reset voltage extracted by the voltage buffer unit and the voltage at the time of reset release into a digital value by the analog-to-digital converter, and storing the digital value in a memory as a reference signal value; performing a second reset operation after a certain exposure time has elapsed since the reset release, converting a difference between the voltage immediately before the second reset operation extracted by the voltage buffer unit and the voltage at the time of the second reset into a digital value by the analog-to-digital converter, setting the value as an accumulation signal value, and setting a difference value between the reference signal value input to the memory and the accumulation signal value as an analog-to-digital converted value of the pixel signal; Do the following. [Effects of the Invention]

[0024] According to the present invention, even in a pixel having a three-transistor configuration, reset noise and drift of the threshold voltage of the transistors can be canceled, so that a high-quality image sensor with low noise can be obtained. Sa It can be achieved. [Brief explanation of the drawings]

[0025] [Figure 1]1 is a block diagram showing a configuration of an image sensor according to an embodiment of the present invention; [Figure 2] 2 is a waveform diagram showing a signal voltage in a pixel 10 of the image sensor 1 shown in FIG. [Figure 3] 10 is a diagram showing the output timing of a reset signal RST, a selection signal SEL, and an analog-to-digital conversion signal. FIG. [Figure 4] FIG. 10 is a diagram illustrating a correlated double sampling method using a memory 13. [Figure 5] FIG. 2 is a diagram showing the timing at which signals are output from the pixels 10 in each row. [Figure 6] 2 is a circuit diagram showing the configuration of a differential amplifier used in the A / D converter 12. FIG. [Figure 7] 7 is a block diagram showing the configuration of a time domain A / D converter using the differential amplifier 20 shown in FIG. 6 as a comparator. [Figure 8] 4A to 4D are circuit diagrams illustrating a first A / D conversion method. [Figure 9] 8A to 8F are circuit diagrams illustrating a second A / D conversion method. [Figure 10] 8A to 8F are circuit diagrams illustrating a third A / D conversion method. [Figure 11] 10A is a circuit diagram showing a third A / D conversion method, and FIG. 10B is a waveform diagram showing the relationship between the signal and the reference voltage VR2 during operation of FIG. [Figure 12] 10A to 10C are circuit diagrams illustrating a fourth A / D conversion method. [Figure 13] 10A to 10C are circuit diagrams illustrating a fourth A / D conversion method. [Figure 14] 10A to 10D are circuit diagrams illustrating a fifth A / D conversion method. [Figure 15] 10A to 10C are circuit diagrams illustrating a fifth A / D conversion method. [Figure 16] FIG. 1 is a circuit diagram showing the configuration of a pixel using a photoelectric film. [Figure 17] 17 is a block diagram showing an example of the configuration of an image sensor using the pixel 100 shown in FIG. 16. FIG. [Figure 18]10 is a waveform diagram showing a terminal voltage VG of a capacitor CH buffered by a source follower formed by a transistor M1 in the pixel 100. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0026] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below.

[0027] Fig. 1 is a block diagram showing the configuration of an image sensor according to an embodiment of the present invention. As shown in Fig. 1, the image sensor 1 according to this embodiment includes a plurality of pixels 10, a vertical scanning circuit 11 that selects pixels in a specific row, a plurality of A / D converters 12 that perform column-parallel analog-to-digital conversion of signals from each pixel 10 in the row selected by the vertical scanning circuit 11, a memory 13 that stores output signals from the A / D converters 12, and a control unit 14 that controls the pixels 10, the vertical scanning circuit 11, and the A / D converters 12.

[0028] The pixel 10 includes a photoelectric conversion element that converts an optical signal into a current, a capacitor that accumulates the current converted by the photoelectric conversion element and converts it into a signal voltage, a reset unit that resets the capacitor to a predetermined voltage, and a voltage buffer unit that receives the voltage of the capacitor as an input. The reset unit and the voltage buffer unit may be configured with, for example, MOS transistors. Note that either the reset unit or the voltage buffer unit may be configured with a MOS transistor, or both may be configured with MOS transistors.

[0029] In the image sensor 1 of this embodiment, a plurality of pixels 10 are arranged two-dimensionally in the row and column directions, and each pixel 10 is controlled row by row by a vertical scanning circuit 11, and signals are sequentially extracted. The signals of the pixels 10 in each selected row are then converted into digital values ​​by an A / D converter 12, and the output signal from the A / D converter 12 is temporarily stored in a memory 13, and a difference is calculated between this and the output signal of the A / D converter 12 at any timing, and the result is output as a converted output signal.

[0030] At this time, the control unit 14 controls the following operations (1) to (4). (1) A first reset operation in which, in each pixel 10 in a specific row selected by the vertical scanning circuit 11, the capacitance is reset to a predetermined voltage by the reset unit, and then the reset is released. (2) The difference between the first reset voltage extracted by the voltage buffer unit of each pixel 10 in a specific row and the voltage at the time of reset release is converted into a digital value by the A / D converter 12, and the value is stored in the memory 13 as a reference signal value. (3) After a certain exposure time has elapsed since the reset was released, a second reset operation is performed, and the difference between the voltage immediately before the second reset operation extracted by the voltage buffer unit and the voltage at the time of the second reset is converted into a digital value by the A / D converter 12, and this value is used as the accumulation signal value. (4) An operation of outputting the difference value between the reference signal value stored in the memory 13 and the aforementioned accumulated signal value as an analog-to-digital converted value of the pixel signal.

[0031] [Operation] 2 is a waveform diagram showing a signal voltage in the pixel 10 of the image sensor 1 shown in FIG. 2. In the pixel 10, the charge storage capacitance C H Terminal voltage V G The time range indicated by the dashed line is a voltage transmission period (pixel signal selection period) from the pixel 10 to the common signal line used to control the transistor M3.

[0032] As shown in FIG. 2, in the image sensor 1 of this embodiment, first, in the first reset for starting exposure, the reset pulse RST becomes “H”, and the terminal voltage V G is the reset voltage V RST(n-m) Here, n is the row number from which the signal is read out, and m is the exposure time expressed in number of rows. This reset voltage V RST(n-m) is the threshold voltage V of transistor M0 TH(n-m) , power supply voltage V DDTherefore, it is expressed by the following formula 6.

[0033]

number

[0034] Next, when the reset signal RST is set to "L" to turn off the transistor M0 and release the reset, the voltage V STD(n-m) is the offset voltage due to the feedthrough of the switch and the capacitance C H The noise voltage V is calculated by adding kT / C noise. n(n-m) This is expressed by the following Equation 7.

[0035]

number

[0036] In the image sensor 1 of this embodiment, these two signals are A / D converted. At this time, the gate-source voltage V GS Taking this effect into consideration, these voltages are expressed by the following formulas 8 and 9.

[0037]

number

[0038]

number

[0039] Then, as shown in the following Equation 10, when the difference between the two signals expressed by Equation 8 and Equation 9 is taken, the noise voltage V n(n-m) Only remains.

[0040]

number

[0041] In the image sensor 1 of this embodiment, this noise voltage V n(n-m) The A / D converted value representing the value is stored in the memory 13.

[0042] When the exposure time has elapsed, the terminal voltage V G After the specified exposure time has elapsed, the pixel selection signal SEL is set to “H” to turn on the transistor M2, and the terminal voltage V is applied to the common signal line D via the source follower. G At this time, the input voltage V of the A / D converter 12 is SIG(n)_ADC is the light-induced current I p , one horizontal period is T H , the gate-source voltage of the source follower is V GS(n) is expressed by the following Equation 11.

[0043]

number

[0044] Next, when the reset signal RST is set to "H" in the second reset to end the exposure, the input voltage V of the A / D converter 12 RST(n)_ADC is expressed by the following Equation 12.

[0045]

number

[0046] Then, the input voltage V expressed by the above formula 11 SIG(n)_ADC The input voltage V expressed by the above formula 12 is RST(n)_ADC The output voltage V SIG(n) _ CDS is expressed by the following formula 13.

[0047]

number

[0048] Here, the threshold voltage V THIt is considered that there is almost no fluctuation in the input voltage of the A / D converter 12, or if the threshold voltage is depleted, the threshold voltage causes almost no fluctuation in the input voltage of the A / D converter 12, so the above formula 13 can be expressed as the following formula 14.

[0049]

number

[0050] Then, the voltage V stored in memory 13 STD(n-m)_CDS The difference between them is read and the voltage is V SIG(n)_DCDS Then, as shown in the following formula 15, noise is cancelled and only the signal due to light can be extracted.

[0051]

number

[0052] 3 is a diagram showing the output timing of the reset signal RST, the selection signal SEL, and the analog-to-digital conversion signal. As shown in FIG. 3, in the image sensor 1 of this embodiment, the first reset signal RST(n-1-m) for row (n-1-m) first goes high, and then, a short time later, the selection signal SEL(n-1-m) for row (n-1-m) goes high. Even after the first reset signal RST(n-1-m) goes low, the signal after reset must be A / D converted, so it remains high for a while before going low. Then, after a short interval, the reset signal RST(nm) for row (nm) goes high, and then, a short time later, the selection signal SEL(nm) for row (nm) goes high. This process is repeated, shifting the rows sequentially.

[0053] When the exposure time indicated by row m has elapsed, the selection signal SEL(n-1) first becomes "H" and the signal voltage V SIG(n-1) After A / D conversion, the second reset signal RST(n-1) becomes "H". Then, the reset signal V RST(n-1)After being A / D converted, the selection signal SEL(n-1) goes to "L". Next, after a short interval, the selection signal SEL(n) for row n goes to "H", and after a short delay the reset signal RST(n) for row n goes to "H", shifting the rows sequentially. The A / D converted signal is the reference signal STD_ CDS and the correlated double sampled (CDS) pixel signal SIG_ CDS are generated alternately.

[0054] 4 is a diagram illustrating a correlated double sampling method using a memory 13. As shown in FIG. 4, a correlated double sampled (CDS) reference signal STD_ CDS is stored in the memory 13 and is a correlated double sampled (CDS) pixel signal SIG_ CDS The pixel signal SIG_ CDS and the reference signal STD_ CDS The difference is taken and a final correlated double sampling (CDS) is performed to remove noise and produce the final converted output.

[0055] 5 is a diagram showing the timing at which signals are output from the pixels 10 in each row. As shown in Fig. 5, in the image sensor 1 of this embodiment, a first reset voltage is output to the common line in the first 1 / 4 horizontal period of one horizontal period, and a reference voltage is output to the common line in the next 1 / 4 horizontal period.

[0056] Thereafter, an exposure period begins, and when the predetermined exposure period ends (set to two horizontal periods in FIG. 4), a signal voltage due to the photocurrent accumulated in the capacitor is output to the common line during the latter 1 / 4 horizontal period, and a second reset voltage is output to the common line during the 1 / 4 horizontal period. Thus, in the image sensor 1 of this embodiment, the first reset voltage, the reference voltage, the signal voltage due to the photocurrent, and the second reset voltage are output to the common line in units of 1 / 4 horizontal period in this order during one horizontal period so that the signals do not overlap each other.

[0057] [A / D converter 12] Next, the A / D converter 12 for realizing the above-mentioned operation will be described. Fig. 6 is a circuit diagram showing the configuration of a differential amplifier used in the A / D converter 12 shown in Fig. 1. In the differential amplifier 20 shown in Fig. 6, the transistor M 1a ,M 1b is a differential pair that converts a differential input voltage into a differential current, and transistor M 2a ,M 2b constitutes a current mirror that converts a differential current into an output voltage, and the differential input voltage is amplified and appears as the output voltage.

[0058] Transistor M0 provides the bias current for the differential pair and is connected to voltage V B is the bias voltage. A switch S1 is provided between the input and output terminals of the differential amplifier 20. a ,IN b and the output terminal of the differential amplifier 20, a pair of capacitances C s is provided.

[0059] Fig. 7 is a block diagram showing the configuration of a time domain A / D converter using the differential amplifier 20 shown in Fig. 6 as a comparator. As shown in Fig. 7, the differential amplifier 20 has a signal input terminal IN a ,IN b The differential voltage between the differential amplifier 20 and the counter 21 is amplified and an amplified signal is generated at the output terminal. The counter 21 counts the clock to update the time information, and the output signal of the differential amplifier 20 becomes the stop signal for the counter 21. The time information of the moment when the stop signal appears is stored in the counter 21.

[0060] In the image sensor 1 of this embodiment, time information may be obtained using a time-to-digital converter that inputs a time-varying code and latches the code at the moment a stop signal appears, in addition to the counter 21. The output of the counter 21 is often used as an A / D converted signal as is, but as shown in Fig. 7, a cumulative adder 22 may be used, in which multiple pieces of time information are input to the cumulative adder 22, which then accumulates and adds them, and the obtained average value is output as an A / D converted signal.

[0061] The time domain A / D converter shown in FIG. 7 controls each switch S1 of the differential amplifier 20 and the input terminal IN a ,IN b Depending on how the voltage is applied to the image sensor, it is possible to realize an image sensor with many features, as will be described below.

[0062] <First A / D conversion method> 8A to 8D are circuit diagrams showing a first A / D conversion method. In the first A / D conversion method, first, a voltage V RST1 Specifically, as shown in FIG. 8A, the first signal input terminal IN a The voltage V that appears on the common signal line when resetting RST1 is applied to the second signal input terminal IN b The reference voltage V R01 is applied and switch S1 is closed. At this time, the capacitance C sa ,C sb The voltage between the terminals of the differential amplifier 20 is V c is expressed by the following Equation 16.

[0063]

number

[0064] Next, the voltage V that appears on the common signal line after the reset is released STD and the voltage V that appears on the common signal line at reset RST1 Specifically, as shown in FIG. 8B, the switch S1 is opened and the first signal input terminal IN a The voltage V that appears on the common signal line after the reset is released STD is applied to the second signal input terminal IN b The reference voltage V changes proportionally to time. R1 is applied, and the voltage V appears at the two input terminals of the differential amplifier 20. a and voltage V b Compare the voltage V a and voltage V b is expressed by the following Equation 17 using Equation 16 above.

[0065]

number

[0066] The input voltage conditions under which the output voltage changes are expressed in the following formula 18, so the voltage V after reset is STD is the reset voltage V RST1と The difference between these two signals is taken, and the signal that has been subjected to correlated double sampling (CDS) is the converted signal. This correlated double sampled signal is then A / D converted into a digital value and stored in memory 13.

[0067]

number

[0068] Next, after a certain exposure time has elapsed, signal sampling is performed. Specifically, as shown in FIG. 8C, a The voltage V of the storage capacitance that appears on the common signal line through the source follower SIG is applied to the second signal input terminal IN b The reference voltage V R02 is applied and switch S1 is closed. At this time, the capacitance C sa ,C sb The voltage between the terminals of the differential amplifier 20 is V c is expressed by the following Equation 19.

[0069]

number

[0070] Next, the voltage V of the storage capacitance that appears on the common signal line through the source follower SIG and the voltage V that appears on the common signal line at the second reset RST2 Specifically, as shown in FIG. 8D, the switch S1 is opened and the first signal input terminal IN a The voltage V that appears on the common signal line at the second reset RST2is applied to the second signal input terminal IN b The reference voltage V changes proportionally to time. R2 is applied, and the voltage V appears at the two input terminals of the differential amplifier 20. a and voltage V b Compare the voltage V a and voltage V b is expressed by the following Equation 20 using Equation 19 above.

[0071]

number

[0072] The input voltage condition for the output voltage to change is expressed by the following formula 21, so the signal voltage V just before the second reset SIG is the second reset voltage V RST2 The difference between this and the signal is taken, and the signal that has been subjected to correlated double sampling (CDS) becomes the converted signal. This CDS-processed signal is then A / D converted to a digital value, and the data stored in memory 13 during the A / D conversion operation shown in FIG. 8B is read out, and the difference is taken to become the final A / D-converted value of the pixel signal.

[0073]

number

[0074] The first A / D conversion method described above performs correlated double sampling (CDS) using the analog voltage sampled in the capacitor, so only two A / D conversions are required. Furthermore, in the A / D conversion shown in Figure 8B, the difference between the first reset voltage and the voltage after reset release is considered to be extremely small, so the time required for A / D conversion can be shortened. Therefore, this method is effective in shortening the conversion time.

[0075] <Second A / D conversion method> 9A to 9F are circuit diagrams showing a second A / D conversion method. In the second A / D conversion method, first, a voltage V RST1Specifically, as shown in FIG. 9A, the first signal input terminal IN a The voltage V that appears on the common signal line when resetting RST1 is applied to the second signal input terminal IN b The reference voltage V R01 is applied and switch S1 is closed. At this time, the capacitance C sa ,C sb The voltage between the terminals of the differential amplifier 20 is V c This is expressed by the above-mentioned Equation 16.

[0076] Next, the offset and noise of the comparator 20 are converted. Specifically, as shown in FIG. 9B, the switch S1 is opened and the first signal input terminal IN a is the voltage V RST1 While continuing to apply the second signal input terminal IN b The reference voltage V changes proportionally to time. R1 is applied, and the voltage V appears at the two input terminals of the differential amplifier 20. a and voltage V b When switch S1 is opened, the offset voltage and capacitance C sa ,C sb Assuming that these non-ideal voltages appear at terminal a and denoting them as ΔV1, the voltage V a and voltage V b is expressed by the following formula 22.

[0077]

number

[0078] The input voltage condition under which the output voltage changes can be expressed by the following equation 23, so the non-ideal voltage ΔV1 can be A / D converted. Therefore, in the second A / D conversion method, this converted value is temporarily stored in a register or the like.

[0079]

number

[0080] Next, the voltage V that appears on the common signal line after the reset is released STD Specifically, as shown in FIG. 9C, the first signal input terminal IN a The voltage V that appears on the common signal line after the reset is released STD At this time, the voltage V a and voltage V b is expressed by the following Equation 24.

[0081]

number

[0082] The input voltage conditions under which the output voltage changes are expressed in the following formula 25, so the voltage V after reset is STD is the reset voltage V RST1 The difference between this and the non-ideal voltage ΔV1 is taken, and the correlated double sampled (CDS) signal is converted. However, in this case, a non-ideal voltage ΔV1 is applied to the voltage after the correlated double sampling (CDS). Therefore, in this conversion method, the A / D converted value of the non-ideal voltage ΔV1 temporarily stored in the register is read out and the difference is taken. This makes it possible to obtain correlated double sampling (CDS) with the non-ideal voltage ΔV1 canceled out. The value obtained by taking this difference is then input to memory 13.

[0083]

number

[0084] Next, the voltage V of the storage capacitance that appears on the common signal line through the source follower SIG Specifically, after a certain exposure time has elapsed, as shown in FIG. 9D, the first signal input terminal IN a The voltage V of the storage capacitance that appears on the common signal line via the source follower SIG is applied to the second signal input terminal IN b The reference voltage V R02 is applied and switch S1 is closed. At this time, the capacitance C sa ,Csb The voltage between the terminals of the differential amplifier 20 is V c This is expressed by the above-mentioned Equation 19.

[0085] Next, the offset and noise of the comparator 20 are converted. Specifically, as shown in FIG. 9E, the switch S1 is opened and the first signal input terminal IN a to voltage V SIG is continuously applied to the second signal input terminal IN b is a reference voltage V that changes proportionally with time. R2 At this time, the voltage V a and voltage V b is expressed by the following Equation 26, where ΔV2 is the non-ideal voltage.

[0086]

number

[0087] The input voltage condition under which the output voltage changes can be expressed by the following formula 27, so the non-ideal voltage ΔV2 can be A / D converted. Therefore, this converted value is temporarily stored in a register or the like.

[0088]

number

[0089] Next, the signal level and the second reset voltage V RST2 Specifically, as shown in FIG. 9F, a first signal input terminal IN a The voltage V that appears on the common signal line at the second reset RST2 At this time, the voltage V a and voltage V b is expressed by the following Equation 28.

[0090]

number

[0091] The input voltage condition for the output voltage to change is expressed by the following formula 29, so the signal voltage V just before the second reset is SIG is the second reset voltage V RST2 The difference between this and the non-ideal voltage ΔV2 is taken, and the correlated double sampled (CDS) signal is converted. However, in this case, a non-ideal voltage ΔV2 is applied to the correlated double sampled (CDS) voltage. Therefore, in this conversion method, the A / D converted value of the non-ideal voltage ΔV2 temporarily stored in the register is read out and the difference is taken. This makes it possible to obtain correlated double sampled (CDS) with the non-ideal voltage ΔV2 canceled out.

[0092]

number

[0093] This correlated double sampled (CDS) voltage is A / D converted to a digital value, and during the A / D conversion operation shown in Figure 9C, the data stored in memory 13 is read out, and the difference is taken to become the A / D converted value of the pixel signal.

[0094] This second conversion method requires a slightly longer conversion time than the first conversion method described above, but it can cancel the offset voltage due to the comparator's switch feedthrough and the kT / C noise of the comparator's capacitance, enabling very high-precision A / D conversion.

[0095] <Third A / D conversion method> 10A to 10F and FIG. 11A are circuit diagrams showing the third A / D conversion method, and FIG. 11B shows the relationship between the signal and the reference voltage V R2 In the third A / D conversion method, first, the voltage V that appears on the common signal line at the time of resetting is RST1 Specifically, as shown in FIG. 10A, the first signal input terminal IN a The voltage V that appears on the common signal line when resetting RST1 is applied to the second signal input terminal IN b The reference voltage V R01is applied and switch S1 is closed. At this time, the capacitance C sa ,C sb The voltage between the terminals of the differential amplifier 20 is V c This is expressed by the above-mentioned Equation 16.

[0096] Next, conversion (multi-conversion) of the offset and noise of the comparator 20 is performed. Specifically, as shown in FIG. 10B, the switch S1 is opened, and the first signal input terminal IN a to voltage V RST1 While continuing to apply the second signal input terminal IN b The reference voltage V changes proportionally to time. R1 is applied, and the voltage V appears at the two input terminals of the differential amplifier 20. a and voltage V b Compare.

[0097] When switch S1 is opened, the offset voltage and capacitance C sa ,C sb Assuming that these non-ideal voltages appear at terminal a and denoted as ΔV1, the non-ideal voltage ΔV1 can be A / D converted from the above-mentioned formulas 22 and 23. In the third A / D conversion method, the operation shown in Fig. 10A and the operation shown in Fig. 10B are repeated alternately multiple times, and the obtained multiple converted values ​​are averaged and temporarily stored in a register or the like.

[0098] However, to shorten the conversion time, the operation shown in FIG. 10A may be omitted, and the operation shown in FIG. 10B may be performed multiple times, and the average value of the resulting multiple conversion values ​​may be calculated and temporarily stored in a register or the like. By doing so, noise can be effectively reduced. Ideally, if the number of conversions is M, then the noise voltage V n decreases in proportion to the square root of M.

[0099]

number

[0100] Next, the voltage V that appears on the common signal line after reset is released is input to the first signal input terminal. STD Specifically, as shown in FIG. 10C, the first signal input terminal IN a The voltage V that appears on the common signal line after the reset is released STD From the above-mentioned formulas 24 and 25, the voltage V after reset is STD is the reset voltage V RST1 The difference is taken and the signal is converted using correlated double sampling (CDS).

[0101] In this conversion method, the reference voltage V R1 is swept multiple times and A / D converted, and the average of the multiple converted values ​​obtained is taken as the A / D converted value. Because the non-ideal voltage ΔV1 is applied to the voltage after correlated double sampling (CDS), a CDS that cancels the non-ideal voltage ΔV1 can be obtained by reading the A / D converted value of the non-ideal voltage ΔV1 temporarily stored in the register and taking the difference. This value is then input to memory 13.

[0102] Next, the voltage V of the storage capacitance that appears on the common signal line through the source follower SIG Specifically, after a certain exposure time has elapsed, as shown in FIG. 10D, the first signal input terminal IN a The voltage V of the storage capacitance that appears on the common signal line via the source follower SIG is applied to the second signal input terminal IN b The reference voltage V R02 is applied and switch S1 is closed. At this time, the capacitance C sa ,C sb The voltage between the terminals of the differential amplifier 20 is V c This is expressed by the above-mentioned Equation 19.

[0103] Next, the offset and noise of the comparator are converted (multi-conversion). Specifically, as shown in FIG. 10E, the switch S1 is opened, and the first signal input terminal IN a is the voltage V SIG is continuously applied to the second signal input terminal IN bThe reference voltage V changes proportionally to time. R2 At this time, the non-ideal voltage ΔV2 can be A / D converted from the above-mentioned formulas 26 and 27.

[0104] Furthermore, noise can be effectively reduced by alternately repeating the operation shown in Fig. 10D and the operation shown in Fig. 10E a plurality of times, averaging the obtained plurality of conversion values, and using the obtained value as the A / D conversion value. In this case as well, in order to shorten the conversion time, the operation shown in Fig. 10D may be omitted, and the operation shown in Fig. 10E may be performed a plurality of times, averaging the obtained plurality of conversion values, and using the obtained value as the A / D conversion value.

[0105] Next, as shown in FIG. 10F, the first signal input terminal IN a The voltage V that appears on the common signal line at the second reset RST2 is applied to the second signal input terminal IN b The threshold voltage V is used to determine whether the A / D conversion is working. TH At this time, the voltage V a and voltage V b is expressed by the following Equation 31.

[0106]

number

[0107] The input voltage condition for the output voltage to change is expressed by the following formula 32, so the signal voltage V just before the second reset is SIG is the second reset voltage V RST2 The difference between these is taken, and the magnitude is the threshold voltage V TH It is compared to.

[0108]

number

[0109] And V RST2 -V SIG is the threshold voltage V THIf the signal is weak and lower than the reference voltage V, the circuit shown in FIG. 11A performs multi-conversion. R2 is the threshold voltage V TH A / D conversion is performed multiple times within a voltage range slightly wider than V, and the average of the multiple conversion values ​​obtained is used as the A / D conversion value. This effectively reduces noise. RST2 -V SIG is the threshold voltage V TH If the signal is stronger than V, the circuit shown in Figure 11A switches to single conversion, and the reference voltage V is used as shown in Figure 11B. R2 sweeps the full-scale voltage range.

[0110] In this manner, in this conversion method, the signal V SIG and reset signal V RST2 The signal that has been subjected to correlated double sampling (CDS) is converted between the two. However, in this case, a non-ideal voltage ΔV2 is applied to the voltage after correlated double sampling (CDS). Therefore, in this conversion method, the A / D converted value of the non-ideal voltage ΔV2 temporarily stored in the register is read out and the difference is taken. This makes it possible to obtain correlated double sampling (CDS) with the non-ideal voltage ΔV2 canceled out.

[0111] This correlated double sampled (CDS) signal is A / D converted to a digital value, and during the A / D conversion operation shown in Figure 10C, the data stored in memory 13 is read out, and the difference is taken to become the A / D converted value of the pixel signal.

[0112] This third conversion method takes a little longer to convert than the second conversion method described above, but it not only cancels the offset voltage due to the switch feedthrough of the comparator and the kT / C noise of the comparator capacitance, but also takes the average of multiple A / D conversion values, thereby reducing noise in the entire circuit even more than the second A / D conversion method described above, enabling extremely low-noise A / D conversion.

[0113] <The fourth A / D conversion method> 12A to 12C and 13A to 13C are circuit diagrams showing a fourth A / D conversion method. In the fourth A / D conversion method, first, a voltage V RST1 Specifically, as shown in FIG. 12A, the first signal input terminal IN a The voltage V that appears on the common signal line when resetting RST1 is applied to the second signal input terminal IN b The reference voltage V R01 is applied and switch S1 is closed. This operation is the same as that of the first A / D conversion method shown in FIG. 8A.

[0114] Next, the voltage V that appears on the common signal line after the reset is released STD and the voltage V that appears on the common signal line at reset RST1 Specifically, as shown in FIG. 12B, the switch S1 is opened and the first signal input terminal IN a The voltage V that appears on the common signal line after the reset is released STD is applied to the second signal input terminal IN b The reference voltage V changes proportionally to time. R1 is applied, and the voltage V appears at the two input terminals of the differential amplifier 20. a and voltage V b This operation is also the same as the operation of the first A / D conversion method shown in FIG. 8B. Then, the voltage V after the reset is released STD is the reset voltage V RST1 The difference between this and the signal is taken, and the signal is converted by correlated double sampling (CDS). The correlated double sampled (CDS) signal is converted into a digital value by A / D conversion and input to memory 13.

[0115] Next, signal sampling is performed. Specifically, after a certain exposure time has elapsed, as shown in FIG. 12C, the voltage V of the storage capacitor appearing on the common signal line via the source follower is input to the first and second signal input terminals. SIG is applied and the switch S1 is closed. At this time, the capacitance C sa ,C sb The voltages between the terminals are equal, and the common input / output voltage of the differential amplifier 20 is Vc is expressed by the following Equation 33.

[0116]

number

[0117] Next, the voltage V SIG Specifically, as shown in FIG. 13A, the switch S1 is opened and the first signal input terminal IN a The voltage V SIG is applied to the second signal input terminal IN b The reference voltage V changes proportionally to time. R2 is applied, and the voltage V appears at the two input terminals of the differential amplifier 20. a and voltage V b Compare the voltage V a and voltage V b is expressed by the following Equation 34 using the above Equation 33.

[0118]

number

[0119] The input voltage condition for the output voltage to change is expressed by the following formula 35, so the voltage V SIG is A / D converted and the converted value is stored in a register.

[0120]

number

[0121] Next, the voltage V of the storage capacitance that appears on the common signal line through the source follower RST2 Specifically, as shown in FIG. 13B, the voltage V of the storage capacitance appearing on the common signal line via the source follower is sampled at the first and second signal input terminals. RST2 is applied and the switch S1 is closed. At this time, the capacitance C sa ,C sb The voltages between the terminals are equal, and the common input / output voltage of the differential amplifier 20 is Vc is expressed by the following Equation 36.

[0122]

number

[0123] Next, the voltage V RST2 Specifically, as shown in FIG. 13C, the switch S1 is opened and the first signal input terminal is continuously supplied with the voltage V RST2 is applied to the second signal input terminal, and a reference voltage V R2 is applied, and the voltage V appears at the two input terminals of the differential amplifier 20. a and voltage V b Compare the voltage V a and voltage V b is expressed by the following Equation 37 using Equation 36 above.

[0124]

number

[0125] The input voltage condition for the output voltage to change is expressed by the following formula 38, so the signal voltage V RST2 is converted to a digital value. Then, this converted value and the voltage V stored in the register are SIG The digital difference between the A / D converted values ​​is taken, resulting in a correlated double sampled (CDS) digital value. Finally, the data stored in memory 13 during the A / D conversion operation shown in FIG. 12B is read out, and the difference is taken to become the A / D converted value of the pixel signal.

number

[0126] The fourth A / D conversion method is to convert two voltages V a and voltage V b When comparing the voltages at the two inputs of the differential amplifier, the common voltage V cSince the input voltage range of the differential amplifier is close to the reference voltage, it is possible to reduce the operating voltage of the differential amplifier and reduce the power consumption of the A / D converter.

[0127] <The fifth A / D conversion method> 14A to 14D and 15A to 15C are circuit diagrams showing a fifth A / D conversion method. In the fifth A / D conversion method, first, a voltage V RST1 Specifically, as shown in FIG. 14A, the first signal input terminal IN a The voltage V that appears on the common signal line when resetting RST1 is applied to the second signal input terminal IN b The reference voltage V R01 is applied and switch S1 is closed. This operation is the same as the fourth A / D conversion method shown in FIG. 12A.

[0128] Next, the voltage V that appears on the common signal line after the reset is released STD and the voltage V that appears on the common signal line at reset RST1 Specifically, as shown in FIG. 14B, the switch S1 is opened and the first signal input terminal IN a The voltage V that appears on the common signal line after the reset is released STD is applied to the second signal input terminal IN b The reference voltage V changes proportionally to time. R1 is applied, and the voltage V appears at the two input terminals of the differential amplifier 20. a and voltage V b Compare.

[0129] and the reference voltage V R1 is swept multiple times within a limited voltage range and A / D converted, and the average of the multiple A / D converted values ​​obtained is taken and used as the A / D converted value. STD is the reset voltage V RST1と The difference between these two signals is taken and converted into a correlated double sampled (CDS) signal. This correlated double sampled (CDS) voltage is converted into a digital value by A / D conversion and input to memory 13.

[0130] Next, signal sampling is performed. Specifically, after a certain exposure time has elapsed, as shown in FIG. 14C, the voltage V of the storage capacitor appearing on the common signal line via the source follower is input to the first and second signal input terminals. SIG is applied and switch S1 is closed. This operation is the same as the operation in Fig. 12C in the fourth conversion method described above.

[0131] Next, the voltage V SIG Specifically, as shown in FIG. 14D, the switch S1 is opened and a voltage V is continuously applied to the first signal input terminal. SIG and at the same time, a threshold voltage V TH is applied, and the voltage V appears at the two input terminals of the differential amplifier 20. a and voltage V b Compare the voltage V SIG and threshold voltage V TH Determine the size of .

[0132] As a result of the judgment, the voltage V SIG is the threshold voltage V TH If the signal is weaker than V, the circuit shown in FIG. 15A performs multi-conversion, and the reference voltage V is used as shown in FIG. 11B. R2 is the threshold voltage V TH The voltage range is slightly wider than the reference voltage, and the average of the converted values ​​is taken as the A / D conversion value. This effectively reduces noise. SIG is the threshold voltage V TH If the signal is stronger than V, the circuit shown in FIG. 15A switches to single conversion, and the reference voltage V is used as shown in FIG. 11B. R2 sweeps the full-scale voltage range. In either operation, the voltage V SIG is A / D converted and the converted value is stored in a register.

[0133] Next, the voltage V of the storage capacitance that appears on the common signal line through the source follower RST2Specifically, as shown in FIG. 15B, the voltage V of the storage capacitance appearing on the common signal line via the source follower at the first and second signal input terminals is sampled. RST2 is applied and switch S1 is closed.

[0134] Next, the voltage V RST2 Specifically, as shown in FIG. 15C, the switch S1 is opened, and the first signal input terminal IN a Voltage V RST2 is applied to the second signal input terminal IN b is a reference voltage V that changes proportionally with time. R2 Then, the signal voltage V is applied. Then, multiple sweeps are performed within a limited voltage range, and the average of the multiple conversion values ​​obtained is taken as the A / D conversion value. This effectively reduces noise. RST2 is converted to A / D.

[0135] Next, this conversion value and the voltage V stored in the register are SIG The digital difference between the A / D converted values ​​is taken and a correlated double sampled (CDS) digital value is obtained. Finally, the data stored in memory 13 during the A / D conversion operation shown in FIG. 14B is read out, and the difference is taken to become the A / D converted value of the pixel signal.

[0136] The fifth A / D conversion method, like the fourth A / D conversion method described above, uses two voltages V a and voltage V b When comparing the voltages at the two inputs of the differential amplifier, the common voltage V c Since the input voltage range of the differential amplifier is close to the reference voltage, it is possible to suppress the input voltage range of the differential amplifier. As a result, the operating voltage of the differential amplifier can be lowered, and the power consumption of the A / D converter can be reduced. Furthermore, in the fifth A / D conversion method, A / D conversion is performed multiple times and the average value is taken, which also reduces read noise.

[0137] Incidentally, in order to rationally set the sweep range of the reference voltage and the threshold voltage, it is necessary to measure the first reset voltage, the second reset voltage, the voltage immediately after the first reset is released, and the signal voltage before the second reset, rather than the voltage obtained by correlated double sampling (CDS). For this reason, the image sensor of this embodiment stores the A / D converted value of the first reset voltage, the A / D converted value of the second reset voltage, the A / D converted value of the voltage after the first reset, and the A / D converted value before the second reset, and uses these to determine the voltage range of the reference voltage or the threshold voltage, thereby enabling higher precision and faster operation.

[0138] As described above in detail, the image sensor of this embodiment converts the difference between the first reset voltage extracted by the voltage buffer unit of each pixel in a specific row and the voltage at the time of first reset release into a digital value using an analog-to-digital converter, stores this value in memory as a reference signal value, performs a second reset operation after a certain exposure time has elapsed since reset release, converts the difference between the voltage extracted by the voltage buffer unit just before the second reset operation and the voltage at the time of the second reset into a digital value using an analog-to-digital converter, and sets this value as an accumulation signal value, and outputs the difference value between the reference signal value and the accumulation signal value stored in memory as the analog-to-digital converted value of the pixel signal.Therefore, even in pixels with a three-transistor configuration, reset noise and drift in the threshold voltage of the transistors can be canceled out, and high-quality images with little noise can be obtained. [Explanation of symbols]

[0139] 1 Image sensor 10, 100 pixels 11, 101 Vertical scanning circuit 12, 102 Analog-to-Digital (A / D) Converter 13. Memory 14 Control Unit 20 Differential Amplifier 21 Counter 22 Accumulator 110 Photoelectric film

Claims

1. A plurality of pixels arranged two-dimensionally in row and column directions; a vertical scanning circuit for selecting pixels in a specific row; a plurality of analog-to-digital converters that perform column-parallel analog-to-digital conversion of signals from pixels in rows selected by the vertical scanning circuit; a control unit that controls the pixels, the vertical scanning circuit, and an analog-to-digital converter; and The pixel is a photoelectric conversion element that converts an optical signal into an electric current; a capacitor that accumulates the current converted by the photoelectric conversion element and converts it into a signal voltage; a reset unit that resets the capacitor to a predetermined voltage; a voltage buffer unit that receives the voltage of the capacitor as an input; Equipped with The analog-to-digital converter a differential amplifier for amplifying a differential voltage between two input terminals and generating it at two output terminals; a first switch provided between the first input terminal and the first output terminal; a second switch provided between the second input terminal and the second output terminal; a first capacitance provided between a first signal input terminal and the first input end; a second capacitor provided between a second signal input terminal and the second input end; and converting time information at the first and second output terminals when a stop signal is generated into an analog-to-digital converted value, The control unit a first reset operation in which the reset unit resets the capacitance to a predetermined voltage in each pixel of a specific row selected by the vertical scanning circuit and then releases the reset; an operation of converting a difference between the first reset voltage extracted by the voltage buffer unit of each pixel in the specific row and the voltage at the time of reset release into a digital value by the analog-to-digital converter, and storing the digital value in a memory as a reference signal value; an operation of performing a second reset operation after a certain exposure time has elapsed since the reset release, converting a difference between the voltage immediately before the second reset operation, which is extracted by the voltage buffer unit, and the voltage at the time of the second reset operation into a digital value by the analog-to-digital converter, and setting the value as an accumulation signal value; and an operation of outputting a difference value between the reference signal value stored in the memory and the accumulated signal value as an analog-to-digital converted value of the pixel signal; Control the a first step of applying a voltage of the common signal line at the first reset time to the first signal input terminal, applying a first reference voltage to the second signal input terminal, and closing the first and second switches; a second step in which the first and second switches are released, the voltage of the common signal line after the first reset is released is applied to the first signal input terminal, a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal, and time information at the time of generation of a stop signal from the first and second output terminals is stored in a memory as a first analog-to-digital converted value; a third step of applying a voltage of the common signal line immediately before the second reset to the first signal input terminal, applying a second standard reference voltage to the second signal input terminal, and closing the first and second switches; a fourth step in which the first and second switches are released, a voltage of the common signal line at the second reset time is applied to the first signal input terminal, a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal, and time information at the time of generation of a stop signal from the first and second output terminals is converted into a second analog-to-digital converted value; and an image sensor that sets a difference value between the first analog-to-digital converted value and the second analog-to-digital converted value stored in the memory as an analog-to-digital converted value of a pixel signal;

2. A plurality of pixels arranged two-dimensionally in row and column directions; a vertical scanning circuit for selecting pixels in a specific row; a plurality of analog-to-digital converters that perform column-parallel analog-to-digital conversion of signals from pixels in rows selected by the vertical scanning circuit; a control unit that controls the pixels, the vertical scanning circuit, and an analog-to-digital converter; and The pixel is a photoelectric conversion element that converts an optical signal into an electric current; a capacitor that accumulates the current converted by the photoelectric conversion element and converts it into a signal voltage; a reset unit that resets the capacitor to a predetermined voltage; a voltage buffer unit that receives the voltage of the capacitor as an input; Equipped with The analog-to-digital converter a differential amplifier for amplifying a differential voltage between two input terminals and generating it at two output terminals; a first switch provided between the first input terminal and the first output terminal; a second switch provided between the second input terminal and the second output terminal; a first capacitance provided between a first signal input terminal and the first input end; a second capacitor provided between a second signal input terminal and the second input end; and converting time information at the first and second output terminals when a stop signal is generated into an analog-to-digital converted value, The control unit a first reset operation in which the reset unit resets the capacitance to a predetermined voltage in each pixel of a specific row selected by the vertical scanning circuit and then releases the reset; an operation of converting a difference between the first reset voltage extracted by the voltage buffer unit of each pixel in the specific row and the voltage at the time of reset release into a digital value by the analog-to-digital converter, and storing the digital value in a memory as a reference signal value; an operation of performing a second reset operation after a certain exposure time has elapsed since the reset release, converting a difference between the voltage immediately before the second reset operation, which is extracted by the voltage buffer unit, and the voltage at the time of the second reset operation into a digital value by the analog-to-digital converter, and setting the value as an accumulation signal value; and an operation of outputting a difference value between the reference signal value stored in the memory and the accumulated signal value as an analog-to-digital converted value of the pixel signal; Control the a first step of applying a voltage of the common signal line at the first reset time to the first signal input terminal, applying a first reference voltage to the second signal input terminal, and closing the first and second switches; a second step in which the first and second switches are released, the voltage of the common signal line at the first reset time is applied to the first signal input terminal, a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal, and time information at the time of generation of a stop signal from the first and second output terminals is temporarily stored in a register as a first analog-to-digital converted value; a third step of applying a voltage of the common signal line after the first reset is released to the first signal input terminal, applying a reference voltage whose voltage changes in proportion to time to the second signal input terminal, setting time information at the time of generation of a stop signal from the first and second output terminals as a second analog-digital converted value, and storing in memory a difference between the second analog-digital converted value and the first analog-digital converted value stored in the register in the second step as a third analog-digital converted value; a fourth step of applying a voltage of the common signal line immediately before the second reset to the first signal input terminal, applying a second standard reference signal to the second signal input terminal, and closing the first and second switches; a fifth step in which the first and second switches are released, a voltage of the common signal line immediately before the second reset is applied to the first signal input terminal, a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal, and time information at the time of generation of a stop signal from the output terminal is temporarily stored in a register as a fourth analog-to-digital converted value; a sixth step in which the voltage of the common signal line at the second reset time is applied to the first signal input terminal, a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal, time information at the time of generation of a stop signal from the first and second output terminals is set as a fifth analog-to-digital converted value, and a difference value between the fifth analog-to-digital converted value and the fourth analog-to-digital converted value stored in the register in the fourth step is set as a sixth analog-to-digital converted value; and an image sensor that sets a difference value between the third analog-to-digital converted value stored in the memory and the sixth analog-to-digital converted value as an analog-to-digital converted value of a pixel signal;

3. A plurality of pixels arranged two-dimensionally in row and column directions; a vertical scanning circuit for selecting pixels in a specific row; a plurality of analog-to-digital converters that perform column-parallel analog-to-digital conversion of signals from pixels in rows selected by the vertical scanning circuit; a control unit that controls the pixels, the vertical scanning circuit, and an analog-to-digital converter; and The pixel is a photoelectric conversion element that converts an optical signal into an electric current; a capacitor that accumulates the current converted by the photoelectric conversion element and converts it into a signal voltage; a reset unit that resets the capacitor to a predetermined voltage; a voltage buffer unit that receives the voltage of the capacitor as an input; Equipped with The analog-to-digital converter a differential amplifier for amplifying a differential voltage between two input terminals and generating it at two output terminals; a first switch provided between the first input terminal and the first output terminal; a second switch provided between the second input terminal and the second output terminal; a first capacitance provided between a first signal input terminal and the first input end; a second capacitor provided between a second signal input terminal and the second input end; and converting time information at the first and second output terminals when a stop signal is generated into an analog-to-digital converted value, The control unit a first reset operation in which the reset unit resets the capacitance to a predetermined voltage in each pixel of a specific row selected by the vertical scanning circuit and then releases the reset; an operation of converting a difference between the first reset voltage extracted by the voltage buffer unit of each pixel in the specific row and the voltage at the time of reset release into a digital value by the analog-to-digital converter, and storing the digital value in a memory as a reference signal value; an operation of performing a second reset operation after a certain exposure time has elapsed since the reset release, converting a difference between the voltage immediately before the second reset operation, which is extracted by the voltage buffer unit, and the voltage at the time of the second reset operation into a digital value by the analog-to-digital converter, and setting the value as an accumulation signal value; and an operation of outputting a difference value between the reference signal value stored in the memory and the accumulated signal value as an analog-to-digital converted value of the pixel signal; Control the a first step of applying a voltage of the common signal line at the first reset time to the first signal input terminal, applying a first reference voltage to the second signal input terminal, and closing the first and second switches; a second step of releasing the first and second switches, applying a voltage of the common signal line at the first reset time to the first signal input terminal, applying a reference voltage whose voltage changes in proportion to time to the second signal input terminal, and obtaining a first analog-to-digital converted value from time information at the time of generation of a stop signal at the first and second output terminals; a step of alternately repeating the first step and the second step a plurality of times, or of varying a reference voltage whose voltage varies in proportion to time a plurality of times in the second step, thereby obtaining a plurality of first analog-to-digital conversion values, and temporarily storing an average value of these values ​​in a register as a final first analog-to-digital conversion value; a third step in which the voltage of the common signal line after the first reset is released is applied to the first signal input terminal, a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal a plurality of times, a plurality of analog-to-digital converted values ​​obtained from time information when a stop signal is generated from the first and second output terminals are averaged to obtain a second analog-to-digital converted value, and a difference value between the averaged value and the first analog-to-digital converted value is stored in memory as a third analog-to-digital converted value; a fourth step of applying a voltage of the common signal line immediately before the second reset to the first signal input terminal, applying a second standard reference signal to the second signal input terminal, and closing the first and second switches; a fifth step in which the first and second switches are released, a voltage of the common signal line immediately before the second reset is applied to the first signal input terminal, a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal a plurality of times, and an average value of a plurality of analog-to-digital converted values ​​obtained from time information when a stop signal is generated from the first and second output terminals is temporarily stored in a register as a fourth analog-to-digital converted value; a sixth step of applying a voltage of the common signal line at the time of the second reset to the first signal input terminal, applying a threshold voltage to the second signal input terminal, and comparing the voltage of the common signal line immediately before the second reset with the output terminal signal; a seventh step in which, if the comparison signal obtained in the sixth step is small, a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal a plurality of times, and an average value of a plurality of analog-to-digital converted values ​​obtained from time information when stop signals are generated from the first and second output terminals is temporarily stored in a register as a fifth analog-to-digital converted value, or, if the comparison signal is large, a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal, and an analog-to-digital converted value obtained from time information when stop signals are generated from the first and second output terminals is temporarily stored in a register as a fifth analog-to-digital converted value; and an image sensor that sets a difference value between the third analog-to-digital converted value stored in the memory and the fifth analog-to-digital converted value as an analog-to-digital converted value of a pixel signal;

4. A plurality of pixels arranged two-dimensionally in row and column directions; a vertical scanning circuit for selecting pixels in a specific row; a plurality of analog-to-digital converters that perform column-parallel analog-to-digital conversion of signals from pixels in rows selected by the vertical scanning circuit; a control unit that controls the pixels, the vertical scanning circuit, and an analog-to-digital converter; and The pixel is a photoelectric conversion element that converts an optical signal into an electric current; a capacitor that accumulates the current converted by the photoelectric conversion element and converts it into a signal voltage; a reset unit that resets the capacitor to a predetermined voltage; a voltage buffer unit that receives the voltage of the capacitor as an input; Equipped with The analog-to-digital converter a differential amplifier for amplifying a differential voltage between two input terminals and generating it at two output terminals; a first switch provided between the first input terminal and the first output terminal; a second switch provided between the second input terminal and the second output terminal; a first capacitance provided between a first signal input terminal and the first input end; a second capacitor provided between a second signal input terminal and the second input end; and converting time information at the first and second output terminals when a stop signal is generated into an analog-to-digital converted value, The control unit a first reset operation in which the reset unit resets the capacitance to a predetermined voltage in each pixel of a specific row selected by the vertical scanning circuit and then releases the reset; an operation of converting a difference between the first reset voltage extracted by the voltage buffer unit of each pixel in the specific row and the voltage at the time of reset release into a digital value by the analog-to-digital converter, and storing the digital value in a memory as a reference signal value; an operation of performing a second reset operation after a certain exposure time has elapsed since the reset release, converting a difference between the voltage immediately before the second reset operation, which is extracted by the voltage buffer unit, and the voltage at the time of the second reset operation into a digital value by the analog-to-digital converter, and setting the value as an accumulation signal value; and an operation of outputting a difference value between the reference signal value stored in the memory and the accumulated signal value as an analog-to-digital converted value of the pixel signal; Control the a first step in which a voltage of the common signal line at the first reset time is applied to the first and second signal input terminals, and the first and second switches are closed; a second step in which the first and second switches are released, the voltage of the common signal line after the first reset is released is applied to the first signal input terminal, a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal, and time information at the time of generation of the stop signals at the first and second output terminals is stored in a memory as a first analog-to-digital converted value; a third step of applying a voltage of the common signal line immediately before the second reset to the first and second signal input terminals, and closing the first and second switches; a fourth step in which the first and second switches are released, a voltage of the common signal line immediately before reset is applied to the first signal input terminal, and a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal, and time information at the time of generation of the stop signal at the first and second output terminals is set as a second analog-to-digital converted value; a fifth step in which the voltage of the common signal line at the second reset time is applied to the first and second signal input terminals, and the first and second switches are closed; a sixth step in which the first and second switches are released, a voltage of the common signal line at the time of the second reset is applied to the first signal input terminal, and a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal, time information at the time of generation of the stop signals at the first and second output terminals is set as a third analog-digital converted value, and a difference value between the third analog-digital converted value and the second analog-digital converted value is set as a fourth analog-digital converted value; and an image sensor that sets a difference value between the first analog-to-digital converted value stored in the memory and the fourth analog-to-digital converted value as an analog-to-digital converted value of a pixel signal;

5. A plurality of pixels arranged two-dimensionally in row and column directions; a vertical scanning circuit for selecting pixels in a specific row; a plurality of analog-to-digital converters that perform column-parallel analog-to-digital conversion of signals from pixels in rows selected by the vertical scanning circuit; a control unit that controls the pixels, the vertical scanning circuit, and an analog-to-digital converter; and The pixel is a photoelectric conversion element that converts an optical signal into an electric current; a capacitor that accumulates the current converted by the photoelectric conversion element and converts it into a signal voltage; a reset unit that resets the capacitor to a predetermined voltage; a voltage buffer unit that receives the voltage of the capacitor as an input; Equipped with The analog-to-digital converter a differential amplifier for amplifying a differential voltage between two input terminals and generating it at two output terminals; a first switch provided between the first input terminal and the first output terminal; a second switch provided between the second input terminal and the second output terminal; a first capacitance provided between a first signal input terminal and the first input end; a second capacitor provided between a second signal input terminal and the second input end; and converting time information at the first and second output terminals when a stop signal is generated into an analog-to-digital converted value, The control unit a first reset operation in which the reset unit resets the capacitance to a predetermined voltage in each pixel of a specific row selected by the vertical scanning circuit and then releases the reset; an operation of converting a difference between the first reset voltage extracted by the voltage buffer unit of each pixel in the specific row and the voltage at the time of reset release into a digital value by the analog-to-digital converter, and storing the digital value in a memory as a reference signal value; an operation of performing a second reset operation after a certain exposure time has elapsed since the reset release, converting a difference between the voltage immediately before the second reset operation, which is extracted by the voltage buffer unit, and the voltage at the time of the second reset operation into a digital value by the analog-to-digital converter, and setting the value as an accumulation signal value; and an operation of outputting a difference value between the reference signal value stored in the memory and the accumulated signal value as an analog-to-digital converted value of the pixel signal; Control the a first step of applying a voltage of the common signal line at the first reset time to the first signal input terminal, applying a first reference voltage to the second signal input terminal, and closing the first and second switches; a second step in which the first and second switches are released, the voltage of the common signal line after the first reset is released is applied to the first signal input terminal, and a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal multiple times, and an average value of multiple analog-to-digital converted values ​​obtained from time information when stop signals are generated from the first and second output terminals is stored in memory as a first analog-to-digital converted value; a third step of applying a voltage of the common signal line immediately before the second reset to the first and second signal input terminals, and closing the first and second switches; a fourth step in which the first and second switches are opened, the voltage of the common signal line immediately before resetting is applied to the first signal input terminal, a threshold voltage is applied to the second signal input terminal, and the magnitude of the voltage of the common signal line immediately before resetting is determined based on the output voltage of the differential amplifier obtained; a fifth step in which, if the magnitude of the voltage of the common signal line immediately before the reset determined in the fourth step is equal to or less than a threshold value, a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal a plurality of times, and an average value of a plurality of analog-to-digital converted values ​​obtained from time information when a stop signal is generated at the output terminal is temporarily stored in a register as a second analog-to-digital converted value, or, if the magnitude of the voltage of the common signal line immediately before the reset exceeds a threshold value, a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal, and an analog-to-digital converted value obtained from time information when a stop signal is generated at the first and second output terminals is temporarily stored in a register as a second analog-to-digital converted value; a sixth step of applying the voltage of the common signal line at the second reset time to the first and second signal input terminals and closing the first and second switches; a seventh step in which the first and second switches are released, a voltage of the common signal line at reset is applied to the first signal input terminal, and a reference voltage whose voltage changes in proportion to time is applied to the second signal input terminal multiple times, the average value of multiple analog-to-digital converted values ​​obtained from time information when a stop signal is generated at the output terminal is set as a third analog-to-digital converted value, and the difference value between the third analog-to-digital converted value and the second analog-to-digital converted value is set as a fourth analog-to-digital converted value; and an image sensor that sets a difference value between the first analog-to-digital converted value stored in the memory and the fourth analog-to-digital converted value as an analog-to-digital converted value of a pixel signal;

6. 6. The image sensor according to claim 1, wherein at least one of the reset section and the voltage buffer section is configured with a MOS transistor.

7. 7. The image sensor according to claim 1, wherein the voltage range and / or threshold voltage of the reference voltage is determined based on one or more of an analog-to-digital conversion value of the first reset voltage, an analog-to-digital conversion value of the voltage after the first reset is released, an analog-to-digital conversion value of the second reset voltage, and an analog-to-digital conversion value before the second reset.

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