Imaging device

Abstract

To suppress a lateral band-like offset shift caused when a high-luminance object is present, without changing a horizontal period of an image sensor.SOLUTION: There is provided an imaging apparatus in which signals from a plurality of pixels are output to signal output lines during a predetermined reading period, and a first reading mode and a second reading mode where an AD conversion circuit performs AD conversion are included. The reading period includes a first period from when the signals from the pixels are output to the signal output lines to when the AD conversion is started a predetermined time later, and a second period where the AD conversion is performed on the signals from the pixels. The imaging apparatus is configured such that the reading period is equal between the first and second reading modes, and lengths of the first and second periods are different from each other.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to an imaging device. [Background technology]

[0002] Imaging devices such as digital cameras and video cameras use imaging elements 400 such as CMOS image sensors. CMOS image sensors are required to have faster pixel signal readout speeds in order to improve continuous shooting speeds and frame rates and to suppress rolling distortion. To achieve this, techniques have been developed to shorten the signal readout period per row in a pixel array or to simultaneously read signals from multiple rows of pixels.

[0003] Patent Document 1 discloses a technique for changing the signal readout period of an image sensor according to the ISO sensitivity. For example, it describes that when the ISO sensitivity is set to 100, the AD conversion period is made shorter than when the ISO sensitivity is set to 200 or higher, thereby realizing faster signal readout and reduced power consumption. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-54424 Summary of the Invention [Problem to be solved by the invention]

[0005] However, shortening the signal readout period to speed up signal readout can cause signal level offsets in the same row as a high-brightness subject in the captured image. Such signal level offsets occur when pixel potential fluctuations caused by a high-brightness subject propagate through the impedance of a common power supply line or GND to other columns in the same row that transfer signals at the same time as the high-brightness pixel.

[0006] The offset deviation of the signal level is visible as a horizontal band of color cast, particularly in dark areas of the image, and becomes more noticeable the higher the ISO sensitivity and the higher the gain applied to the pixel signal.To reduce this, it is expected that the signal readout period per row will be lengthened to ensure time for the potential fluctuations to settle.

[0007] However, extending the static period results in a longer period for reading out signals from the image sensor, which poses a problem that it is not possible to achieve high-speed signal reading. [Means for solving the problem]

[0008] The present invention has been made to achieve the above-mentioned object, and provides a digital signal processing device comprising: a pixel array in which a plurality of pixels are arranged in rows and columns; a plurality of column signal lines to which signals of the plurality of pixels are output for each column of the pixel array; a plurality of AD conversion circuits that perform AD conversion on the signals from the plurality of pixels output to the plurality of column signal lines for each column; an amplifier circuit that amplifies, with a digital gain, the digital signals AD converted by the plurality of AD conversion circuits; and control means that controls signals of the plurality of pixels arranged in the same row of the pixel array to be output for each column to the plurality of column signal lines and AD converted by the plurality of AD conversion circuits during a predetermined readout period, and controls to read out the signals of the plurality of pixels in a first signal readout mode when the digital signals are not amplified by the amplifier circuit, and to read out the signals of the plurality of pixels in a second signal readout mode when the digital signals are amplified by the amplifier circuit, wherein the predetermined readout period includes a first period from when the signals of the plurality of pixels are output to the plurality of column signal lines for each column until AD conversion is started by the plurality of AD conversion circuits, and a second period in which the signals from the plurality of pixels output to the plurality of column signal lines for each column are AD converted by the plurality of AD conversion circuits, signal Readout mode and the second signal In the read mode, the predetermined read periods are equal, and the second signal The first period in the read mode is the first signalThe first period in the read mode is longer than the second period signal The second period in the read mode is signal The period is shorter than the second period in the read mode. [Effects of the Invention]

[0009] According to the present invention, horizontal band-like offset deviations occurring when a high-brightness subject is present can be suppressed without changing the period for reading out signals from the image sensor. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 2 is a diagram showing the configuration of pixels and peripheral circuits of an image sensor according to an embodiment. [Figure 2] FIG. 2 is a diagram showing the configuration of a unit pixel in an image sensor according to an embodiment. [Figure 3] FIG. 2 is a schematic diagram showing a layered structure of an imaging element according to an embodiment. [Figure 4] FIG. 1 is a block diagram showing an example of the configuration of an imaging device including an imaging element according to an embodiment. [Figure 5] 10A and 10B are conceptual diagrams illustrating combinations of imaging modes, readout operations, and signal processing according to an embodiment. [Figure 6] 5 is a timing chart showing a first read operation according to the first embodiment. [Figure 7] 6 is a timing chart showing a second read operation according to the first embodiment. [Figure 8] 10 is a timing chart showing a third read operation according to the second embodiment. [Figure 9] 10 is a timing chart showing a fourth read operation according to the third embodiment. [Figure 10] FIG. 10 is a block diagram showing an example of the configuration of pixels and peripheral circuits of an image sensor according to a fourth embodiment. [Figure 11] 10 is a timing chart showing a fifth read operation according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0012] Example 1 Fig. 1 is a block diagram showing an example of the configuration of pixels and peripheral circuits of an image sensor 400 in Example 1. In Fig. 1, a plurality of pixels 102 are arranged in a matrix in a pixel array 101, and color filters with different spectral transmittances are formed on each of the pixels 102. In Fig. 1, the letters R, G, and B are attached to the pixels 102, indicating that color filters with red, green, and blue spectral transmittances are provided, respectively.

[0013] Signals from the pixels 102 are output to column signal lines for each column. In this embodiment, the description will be given assuming that each column has two column signal lines, but the number of column signal lines is not limited to this, and any number, such as four, twelve, or twenty, may be provided depending on the characteristics required of the image sensor 400.

[0014] The pixels 102A are connected to a column signal line 105A by a selection switch (not shown), and output signals from the pixels of each row are output to a column circuit 106A via the column signal line 105A. The pixels 102B are connected to a column signal line 105B by a selection switch (not shown), and output signals from the pixels of each row are output to the column circuit 106B via the column signal line 105B. The selection switch is used to selectively output pixel signals from a specific row based on a control signal supplied from the vertical scanning circuit 104 via a control signal line 103.

[0015] In this way, pixels 102A arranged in (2N-1) rows (N is a natural number) connected to column signal line 105A and pixels 102B arranged in 2N rows connected to column signal line 105B are periodically arranged in a matrix. The column signal line 105A and the column signal line 105B output pixel signals to the column circuits 106A and 106B, respectively, for each row. The column signal line 105A and the column signal line 105B may be collectively referred to as column signal line 105.

[0016] A timing generator (hereinafter referred to as TG) 110 generates pulse signals for controlling transistors in the pixels 102 via the vertical scanning circuit 104, and also controls a D / A converter 111 (hereinafter referred to as DAC). The DAC 111 generates a comparison reference signal to be supplied to the comparator 107 and a reference signal (slope signal or ramp signal) whose level changes over time. The comparison reference signal and the reference signal are input from the DAC 111 to one of the comparators 107 in the column circuits 106A and 106B under the control of the TG 110. As will be described later, the rate of change per time of the reference signal supplied from the DAC 111 to the comparator 107 can be changed, and by changing the rate of change per time of the reference signal, the analog gain during AD conversion can be changed.

[0017] Next, we will explain the configurations of the column circuits 106A and 106B. The column circuit 106A is connected to a column signal line 105A, and the column circuit 106B is connected to a column signal line 105B. Note that the column circuits 106A and 106B may be collectively referred to as the column circuits 106.

[0018] Each of the column circuits 106A and 106B is composed of a comparator 107, a counter 108, and a column memory 109. A reference signal generated by a DAC 111 is input to one input of the comparator 107, and an output signal of each pixel is input to the other input via a column signal line 105.

[0019] The comparator 107 compares the potential V, which changes in accordance with the output signal of the pixel on the column signal line 105, with a reference signal, and outputs either a low level or a high level as a binary value depending on the magnitude relationship. The counter 108 measures the time until the magnitude relationship is inverted based on a clock, and outputs the measured time as a digital signal. The column memory 109 holds the digital signal measured in the counter 108. In other words, the comparator 107, counter 108, and column memory 109 of the column circuit 106 constitute an AD conversion circuit. The AD conversion circuit of this embodiment is a slope-type AD conversion circuit that performs AD conversion on signals from multiple pixels using a reference signal whose level changes over time.

[0020] The horizontal scanning circuit 112 scans the column circuits 106 in the column direction and turns on the selection switches under the control of the TG 110. When the selection switches are turned on, digital signals for two rows of pixels 102A and 102B held in the column memory 109 of the column circuit 106 are simultaneously output via horizontal signal lines 113A and 113B commonly connected to each column.

[0021] 2 is a circuit diagram showing an example of the configuration of the pixel 102. Each pixel 102 has a plurality of photodiodes (hereinafter referred to as PD) 201A and 201B, which are photoelectric conversion units. That is, in this embodiment, a multi-pixel structure is used to acquire phase difference information of a subject through a photographing lens. Note that the pixel is not limited to the multi-pixel structure, and a single-pixel structure having one PD per pixel may also be used.

[0022] PD201A and PD201B share one microlens (not shown) for focus detection. In the following description, the signal based on photoelectric conversion by PD201A is referred to as signal A, and the signal based on photoelectric conversion by PD201B is referred to as signal B. Furthermore, the signals based on photoelectric conversion by both PD201A and PD201B are referred to as signal A+B.

[0023] PD 201A is connected via a transfer switch 202A, and PD 201B is connected via a transfer switch 202B to a common floating diffusion (hereinafter referred to as FD) 203. Here, transfer switch 202A is controlled by a transfer pulse PTXA supplied from a vertical scanning circuit 104, and transfer switch 202B is controlled by a transfer pulse PTXB supplied from the vertical scanning circuit 104.

[0024] The FD 203 temporarily stores the charges transferred from the PDs 201A and 201B and converts the charges into voltage. The reset switch 204 is controlled by a reset pulse PRES supplied from the vertical scanning circuit 104, and resets the FD 203 by supplying a reference potential VDD to the FD 203.

[0025] The pixel amplifier 205 is a source follower circuit made up of a MOS transistor and a constant current source. The selection switch 206 is controlled by a selection pulse PSEL supplied from the vertical scanning circuit 104, and outputs a potential fluctuation of the pixel amplifier 205 corresponding to the amount of charge stored in the FD 203 to the column signal line 105.

[0026] 3 is a schematic diagram showing the structure of an image sensor 400 of this embodiment. The image sensor 400 has a structure in which a first semiconductor substrate 301 on which the pixel section 101 and the like are formed is stacked on a second semiconductor substrate 302 on which the column circuit 106 and the like are formed. The first semiconductor substrate 301 and the second semiconductor substrate 302 are electrically connected by bumps or the like.

[0027] The second semiconductor substrate 302 is composed of the aforementioned column circuits 106, a data processing circuit 303, and a memory 304. The data processing circuit 303 performs various calculations and correction processes on the image signals output from the column circuits 106. The semiconductor substrate memory 304 is a volatile memory such as a DRAM, and is used for purposes such as temporarily storing image data and correction data when the image signals output from the column circuits 106 are processed by the data processing circuit 303. Note that other components of the image sensor 400 (not shown) may be located on either semiconductor substrate.

[0028] FIG. 4 is a block diagram showing the configuration of an image pickup device 411 of this embodiment.

[0029] 4, a photographing lens 401 is subjected to focus control and the like by a lens driving circuit 402, and an optical image of a subject is formed on an image sensor 400. The image sensor 400 converts incident light corresponding to the optical image of the subject into an image signal and outputs the image signal.

[0030] The shutter 403 is controlled by a mechanical drive circuit 404 to control the exposure amount of the image sensor 400. The signal processing circuit 405 (amplification circuit) performs various types of arithmetic processing such as amplification processing for amplifying the image signal output from the image sensor 400 with a digital gain, offset correction, and white balance correction.

[0031] The control circuit 406 controls the entire imaging device. That is, it performs various processes such as drive control of the image sensor 400, calculation processing for autofocus control that controls the focal position of the photographing lens 401 by the lens drive circuit 402, and control of the shutter 403 by the mechanical drive circuit 404. The signal processing circuit 405 may be incorporated into the control circuit 406.

[0032] The memory circuit 407 is a memory that stores image data and offset correction values, and is connected to the signal processing circuit 405. The memory circuit 407 may also be connected to the data processing circuit 303 of the image sensor 400, and may be configured to selectively communicate image data and correction data.

[0033] The recording circuit 408 records image data on a removable recording medium such as a semiconductor memory, typically an SD card. The operation circuit 409 accepts user input and operations using physical buttons, a touch panel, and various sensors. The display circuit 410 is composed of a rear LCD, an electronic viewfinder, etc., and displays various information from the imaging device 411.

[0034] Next, the relationship between the ISO sensitivity, which is the exposure index set in the image capture device 411 of this embodiment, and the readout mode, analog gain, and digital gain will be described using Fig. 5. Fig. 5 is a diagram illustrating the relationship between the ISO sensitivity, which is set in the image capture device 411 of this embodiment, and the readout mode, analog gain, and digital gain. Here, the analog gain is defined as the amplification factor of an analog signal applied before AD conversion by the AD conversion circuit, and the digital gain is defined as the amplification factor of a signal applied to a digital signal after AD conversion.

[0035] The image capture device 411 of this embodiment sets the readout mode and analog gain of the image capture element 400 according to the ISO sensitivity set by automatic exposure control or a user operation, and also sets the digital gain of the signal processing circuit 405. Details of the first readout mode and second readout mode set in the image capture element 411 will be described later.

[0036] First, when the ISO sensitivity is set between ISO100 and ISO3200, the imaging device 411 sets the image sensor 400 to a first readout mode. Furthermore, an analog gain of 1x to 32x is set in the image sensor 400 according to the set ISO sensitivity, and a digital gain of 1x is set in the signal processing circuit 405 regardless of the set ISO sensitivity. In other words, the signal processing circuit 405 does not amplify the digital signal by the digital gain. Then, the AD conversion by the AD conversion circuit is performed in 14 bits, and a 14-bit digital signal is output.

[0037] In this setting, the signal is amplified by analog gain only inside the image sensor 400, with ISO 3200 being the maximum amplification factor for analog gain inside the image sensor 400. For example, by changing the rate of change per time of the reference signal in the AD converter according to the set ISO sensitivity, it is possible to amplify the signal with an analog gain according to the ISO sensitivity during AD conversion.

[0038] Next, when the ISO sensitivity is set to ISO 6400, the imaging device 411 sets the second readout mode in the imaging element 400. Also, a 32x analog gain is set in the imaging element 400, and a 2x digital gain is set in the signal processing circuit 405. In this case, the AD conversion by the AD conversion circuit is performed in 13 bits, and a 14-bit digital signal is output by multiplying the signal by a 2x digital gain in the signal processing circuit 405.

[0039] Furthermore, when the ISO sensitivity is set to ISO12800, the imaging device 411 sets the second readout mode in the imaging element 400. Also, a 32x analog gain is set in the imaging element 400, and a 4x digital gain is set in the signal processing circuit 405. In this case, too, the AD conversion by the AD conversion circuit is performed at 13 bits, and a 15-bit digital signal is output by multiplying the 4x digital gain in the signal processing circuit 405.

[0040] It is also possible to configure the system so that when ISO12800 is set, 12-bit AD conversion is performed and a 14-bit digital signal is output by multiplying it by a 4x gain in the signal processing circuit 405. In this case, the AD conversion period can be further shortened, and the settling time of the dark area columns affected by the potential fluctuations of the high-brightness columns at high ISO sensitivity can be further extended, resulting in an effect of further reducing horizontal band-like offset deviations.

[0041] Furthermore, the configuration is not limited to applying digital gain in the signal processing circuit 405 provided outside the image sensor 400, but may be configured to apply digital gain to the signal after AD conversion in, for example, the data processing circuit 303 within the image sensor 400.

[0042] Next, we will explain how to handle signals after AD conversion. In this embodiment, as described above, 14-bit (0 to 16384 counts) AD conversion is performed between ISO100 and ISO3200, where the first readout mode is set. Also, 13-bit (0 to 8192 counts) AD conversion is performed between ISO6400 and ISO12800, where the second readout mode is set.

[0043] Consider the case where the AD conversion resolution required for the image capture device 411 is 14 bits and the recommended exposure index (ISO sensitivity) is ISO 6400. When ISO 6400 is set, the amplification factor before AD conversion (analog gain) is set to 32 times, and the amplification factor after AD conversion (digital gain) is set to 2 times, resulting in a total gain of 64 times.

[0044] If the required resolution of AD conversion is 14 bits, AD conversion is performed at 0 to 16,384 counts, which is equivalent to 14 bits, and multiplying by a double digital gain after AD conversion results in 0 to 32,768 counts, which is equivalent to 15 bits, with surplus counts of 16,385 to 32,768. Therefore, in this embodiment, AD conversion is performed at 0 to 8,192 counts, which is equivalent to 13 bits, and multiplying by a double digital gain after AD conversion makes it possible to generate a 14-bit wide digital signal of 0 to 16,384 counts.

[0045] In this way, when the digital signal after AD conversion is amplified by a digital gain of M times (M is a positive number), in order to maintain the same bit width of the digital signal, AD conversion can be performed at 1 / M times the rate of change of the reference signal without changing the rate of change per unit time. This control makes it possible to shorten the AD conversion period in the second readout mode.

[0046] As another example, the number of bits for AD conversion can be determined arbitrarily, such as performing AD conversion at 14.1 bits in the first read mode (0 to 17560 counts) and performing AD conversion at 14 bits in the second read mode (0 to 16384 counts).

[0047] Next, the first readout mode and the second readout mode set in the image sensor 411 will be described in detail.

[0048] Fig. 6 is a timing chart of the first readout mode in this embodiment. Fig. 6 shows the transition of pixel signals input to the comparator 107 for pixel columns where a high-brightness object is present (high-brightness columns), and the transition of pixel signals input to the comparator 107 for pixel columns where there is almost no incident light (dark columns). Here, it is assumed that pixels in each column in the same pixel row are driven in the same way.

[0049] By time t600, resetting of the pixel unit 101 by setting the reset pulse PRES to Hi and the transfer pulse PTX to Hi is completed, and charge accumulation is started by setting the transfer pulse PTX to Lo while the reset pulse PRES is Hi.

[0050] At time t601, the selection pulse PSEL goes high, and the pixels in the selected row are connected to the column signal line 105.

[0051] At time t602, the reset pulse PRES changes from Hi to Lo, releasing the reset, and a noise component signal (hereinafter referred to as N signal) corresponding to the potential according to the amount of charge in FD203 at that time is output to the column signal line 105 and input to the comparator 107.

[0052] Here, at time t602, a potential fluctuation occurs due to the reset pulse PRES, and this fluctuation is observed as an offset level common to the horizontal pixel column via the common reference potential VDD or GND and the signal line 103. This fluctuation converges to the reference level with a certain time constant, and in the first readout mode, the fluctuation in the input signal has converged by time t603.

[0053] At time t603, the DAC 111 starts outputting the reference signal VL that changes in a ramp manner, and at the same time that the DAC 111 starts outputting the ramp signal, the counter 108 starts counting.

[0054] At time t604, the magnitude relationship between the N signal and the reference signal input to the comparator 107 is reversed, causing the output of the comparator 107 to be inverted. The count value of the counter 108 at this time is stored in the column memory 109.

[0055] At time t605, after the reference signal has transitioned to reach a predetermined value, the horizontal scanning circuit 112 outputs the N signal held in the column memory 109 to the outside of the image sensor 400.

[0056] At time t606, the comparator 107 is reset. Also at time t606, the transfer pulses PTXA and PTXB become Hi, causing the photocharges generated in PD201A and PD201B to be transferred to FD203. Then, a light component signal (hereinafter referred to as an A+B signal), which is a potential according to the amount of charge transferred to FD203, is output to the column signal line 105 and input to the comparator 107.

[0057] At time t607, the transfer pulses PTXA and PTXB go to Lo, thereby completing the transfer of charges from PD201A and PD201B to FD203.

[0058] At time t608, the DAC 111 starts outputting the reference signal VL that changes in a ramp manner, and the counter 108 starts counting at the same time that the DAC 111 starts outputting the ramp signal.

[0059] At time t609, the magnitude relationship between the input signal of the dark column and the reference signal input to the comparator 107 is reversed, causing the output of the comparator 107 to be inverted, and the count value of the counter 108 at that time is stored in the column memory 109. Thereafter, the magnitude relationship between the input signal of the high-luminance column and the reference signal input to the comparator 107 is similarly reversed, causing the output of the comparator 107 to be inverted, and the value of the counter 108 at that time is stored in the column memory 109.

[0060] At time t610, after the reference signal has transitioned to reach a predetermined value, the horizontal scanning circuit 112 outputs the A+B signal held in the column memory 109 to the outside of the image sensor 400.

[0061] Thereafter, the signal processing circuit 405 subtracts the N signal from the A+B signal, thereby performing predetermined signal processing such as removing reset noise.

[0062] Here, potential fluctuations caused by high-brightness light in the high-brightness columns propagate to horizontal pixel columns via the common reference potential VDD, GND, and control signal line 103, and are therefore observed in the dark columns as an offset level of a signal superimposed on the potential corresponding to the A+B signal. The potential fluctuations occurring in the dark columns converge to the reference level with a certain time constant. However, in the first readout mode, the potential fluctuations of the input signal in the dark columns that began at time t607 have not converged by time t608, when the DAC 111 starts outputting the reference signal VL and the counter 108 starts counting.

[0063] 7 is a timing chart of the second read mode in this embodiment. Here, the operation from time t700 to time t706 when the N signal is output is the same as the operation from time t600 to time t606 in the first read mode described in FIG. 6, so a description thereof will be omitted.

[0064] At time t706, the comparator 107 is reset. Also at time t706, the transfer pulses PTXA and PTXB become Hi, causing the charges of PD201A and PD201B to be transferred to FD203. Then, a potential (A+B signal) according to the amount of charge transferred to FD203 is output to the column signal line 105 and input to the comparator 107.

[0065] At time t707, the transfer pulses PTXA and PTXB go low, thereby completing the transfer of charges from PD201A and PD201B to FD203.

[0066] At time t708, the DAC 111 starts outputting the reference signal VL that changes in a ramp shape, and the counter 108 starts counting at the same time that the DAC 111 starts outputting the reference signal.

[0067] At time t709, the magnitude relationship between the input signal of the dark column and the reference signal input to the comparator 107 is reversed, causing the output of the comparator 107 to be inverted, and the count value of the counter 108 at that time is held in the column memory 109. Note that the magnitude relationship between the input signal of the high-luminance column and the reference signal input to the comparator 107 does not invert, and the output of the comparator 107 does not invert, so the maximum count value of the counter 108 is held in the column memory 109.

[0068] At time t710, after the reference signal has transitioned to reach a predetermined value, the horizontal scanning circuit 112 outputs the A+B signal held in the column memory 109 to the outside of the image sensor 400.

[0069] Thereafter, the signal processing circuit 405 subtracts the N signal from the A+B signal, thereby performing predetermined signal processing such as removing reset noise.

[0070] Here, even in the second readout mode, potential fluctuations caused by high-brightness light in the high-brightness columns propagate to horizontal pixel columns via the common reference potentials VDD and GND and the control signal line 103. They are then observed in the dark columns as an offset level of a signal superimposed on a potential corresponding to the A+B signal. Potential fluctuations occurring in the dark columns converge to the reference level with a certain time constant. In the second readout mode, the potential fluctuations of the input signal in the dark columns that began at time t707 converge by time t708, when the DAC 111 starts outputting the reference signal VL and the counter 108 starts counting.

[0071] The differences between the first readout mode and the second readout mode will be explained below. Here, the period from when the reset pulse PRES or the transfer pulses PTXA and PTXB become Lo until the DAC 111 starts outputting the reference signal VL (the period until the AD conversion by the AD conversion circuit starts) is defined as the static period of potential fluctuations (first period). Also, the time from when the output of the reference signal VL starts until the reference signal VL reaches a predetermined value is defined as the AD conversion period (first period). Also, the entire period of a series of signal readouts (predetermined readout period) is generally called a horizontal period.

[0072] First, the entire period of the first readout mode (time t600 to t611) is equal to the entire period of the second readout mode (time t700 to t711). The first readout mode and the second readout mode differ in the lengths of the static period (first period) and AD conversion period (second period) of the A+B signal.

[0073] That is, the static period of the A+B signal in the second read mode (time t707 to t708) is controlled to be longer than the static period of the A+B signal in the first read mode (time t607 to t608).

[0074] Furthermore, the AD conversion period of the A+B signal in the second readout mode (time t708 to t710) is controlled to be shorter than the AD conversion period of the A+B signal in the first readout mode (time t608 to t610).

[0075] Thus, within the same horizontal period, the static period for the potential fluctuation of the A+B signal is longer and the AD conversion period for the A+B signal is shorter in the second readout mode than in the first readout mode. This is because, as described above, AD conversion is performed at 14 bits in the first readout mode, whereas AD conversion is performed at 13 bits in the second readout mode.

[0076] The rate of change of the reference signal per unit time when AD conversion is performed in each of the first and second readout modes is the same, and is set appropriately depending on the amplification factor of the analog gain during AD conversion inside the image sensor 400 and the resolution of the AD conversion.

[0077] Next, the output signal of the dark area sequence when the N signal is subtracted from the A+B signal in the signal processing circuit 405 will be described.

[0078] In the first readout mode, the N signal is AD converted at its original signal level (time t604), while the A+B signal is AD converted at a signal level shifted from its original signal level due to the influence of potential fluctuations in the high-brightness columns (time t609). Subtracting the N signal from the A+B signal removes the reset noise, but it cannot remove the offset level associated with the potential fluctuations. This occurs across each horizontal column, and is therefore visible as a horizontal band of offset shift.

[0079] In contrast, in the second readout mode, the static period of the A+B signal is extended, so that the A+B signal is also A / D converted at its original signal level without being affected by fluctuations in the potential of the high-brightness columns (time t709). Note that the N signal is also A / D converted at its original signal level (time t704), just like in the second readout mode. Furthermore, subtracting the N signal from the A+B signal removes the reset noise and eliminates horizontal offset shifts.

[0080] As a modification of this embodiment, the A signal for focus detection may be read between the N signal and the A+B signal. Furthermore, the B signal for focus detection can be obtained by subtracting the A signal from the A+B signal.

[0081] The offset deviation of the signal level occurring in the horizontal direction on the same row as a high-brightness subject in a photographed image becomes more noticeable as a horizontal band-like color cast in the image as the set ISO sensitivity increases and the signal amplification rate increases.

[0082] For example, if the first readout mode is applied when the ISO sensitivity is set to ISO 12800, the signals of the dark columns, which are affected by the potential fluctuations of the high-brightness columns, are AD converted at a potential before they settle. Furthermore, the signals are amplified four times by the digital gain, resulting in horizontal offset shifts. In contrast, if the second readout mode is applied when ISO 12800 is set, the signals of the dark columns, which are affected by the potential fluctuations of the high-brightness columns, are AD converted at a statically settled potential, thereby suppressing the horizontal offset shifts.

[0083] In addition, ISO sensitivity is generally set for each captured frame. If the readout period (horizontal period) for one line changes depending on the ISO sensitivity set for each captured frame, it becomes difficult to control the accumulation time when capturing moving images or continuous still image shooting (continuous shooting). Here, when capturing moving images, the image sensor 400 is driven using a rolling shutter, and when capturing still images continuously (continuous shooting), the image sensor 400 is driven using a slit rolling shutter.

[0084] By configuring as in this embodiment, the readout period (horizontal period) does not change even if the ISO sensitivity setting changes for each captured frame, so it is possible to change the ISO sensitivity and reduce horizontal band-like offset deviation at the same time.

[0085] As described above, it is possible to provide an imaging device that suppresses horizontal band-like offset deviation without changing the signal readout time (horizontal period) of the imaging element 400 depending on the imaging mode.

[0086] Example 2 In the second embodiment, an example will be described in which the image sensor 400 is driven in a third readout mode in addition to the first and second readout modes described in the first embodiment. Fig. 8 is a timing chart of the third readout mode in the second embodiment.

[0087] The difference from the second readout mode is that instead of lengthening the static period of the A+B signal, the static period of the N signal is controlled to be longer. Since the outline of the readout drive is the same as the second readout mode described above, this embodiment will be explained focusing on the differences from the first readout mode.

[0088] First, the overall period of the third readout mode (t800 to t811) is equal to the overall period of the first readout mode (t600 to t611). The third readout mode differs from the first readout mode in the length of the static period (first period) of the N signal and the AD conversion period (second period) of the A+B signal.

[0089] That is, the static period of the N signal in the third read mode (time t802 to t803) is controlled to be longer than the static period of the N signal in the first read mode (time t602 to t603).

[0090] Furthermore, the AD conversion period (time t808 to t810) of the A+B signal in the third readout mode is controlled to be shorter than the AD conversion period (time t608 to t610) of the A+B signal in the first readout mode.

[0091] As described above, within the same horizontal period, the third readout mode has a longer static period for the potential fluctuation of the N signal and a shorter AD conversion period for the A+B signal than the first readout mode. Horizontal band-like offset shifts can also occur due to potential fluctuations of the N signal. In this embodiment, shortening the AD conversion period for the A+B signal and using the resulting time for the static period for the potential fluctuation of the N signal can reduce the horizontal band-like offset shifts.

[0092] As described above, it is possible to provide an imaging device that suppresses horizontal band-like offset deviations caused by potential fluctuations of the N signal without changing the readout time (horizontal period) of the imaging element 400 depending on the imaging mode.

[0093] Example 3 In the third embodiment, an example will be described in which the image sensor 400 is driven in a fourth readout mode in addition to the first readout mode and the second readout mode described in the first embodiment and the third readout mode described in the second embodiment. Fig. 9 is a timing chart of the fourth readout mode in the third embodiment.

[0094] The difference from the second readout mode is that the same A+B signal is AD converted twice. Here, the operation from time t900 to time t910 is the same as the operation from time t700 to time t710 in the second readout mode described in Figure 6, so the description will be omitted.

[0095] At time t911, the reference signal VL is reset, and the DAC 111 starts outputting the reference signal VL that changes like a ramp again. At the same time that the DAC 111 starts outputting the reference signal, the comparator is reset and the counter 108 starts counting.

[0096] At time t912, the magnitude relationship between the input signal of the dark column and the reference signal input to the comparator 107 is reversed, causing the output of the comparator 107 to be inverted, and the count value of the counter 108 at that time is held in the column memory 109. Note that the magnitude relationship between the input signal of the high-luminance column and the reference signal input to the comparator 107 does not reverse, and the output of the comparator 107 does not invert, so the maximum value of the counter 108 is held in the column memory 109.

[0097] At time t913, after the reference signal has transitioned to reach a predetermined value, the horizontal scanning circuit 112 outputs the second A+B signal stored in the column memory to the outside of the image sensor 400. Thereafter, the two output A+B signals are subjected to averaging processing in the signal processing circuit 405. Note that the averaging processing may also be performed in the data processing circuit 303 before being output to the outside of the image sensor 400.

[0098] The difference between the fourth read mode and the first read mode will be explained below.

[0099] First, the overall period of the fourth readout mode (t900 to t914) is equal to the overall period of the first readout mode (t600 to t611). The fourth readout mode and the first readout mode differ in the lengths of the static period (first period) of the A+B signal and the AD conversion period (second period) of the A+B signal.

[0100] That is, the static period (time t907 to t908) of the A+B signal in the fourth read mode is controlled to be longer than the static period (time t607 to t608) of the A+B signal in the first read mode.

[0101] Furthermore, the AD conversion periods of the A+B signal in the fourth readout mode (time t908 to t910 and time t911 to t913) are controlled to be shorter than the AD conversion periods of the A+B signal in the first readout mode (time t708 to t710).

[0102] In this way, in the same horizontal period, the fourth readout mode has a longer static period for the potential fluctuation of the A+B signal than the first readout mode, a shorter AD conversion period for the A+B signal, and AD conversion is performed multiple times.

[0103] Generally, as the static period of potential fluctuations becomes longer, random noise (1 / f noise) increases. In consideration of this situation, this embodiment performs AD conversion of the same signal multiple times to reduce random noise that increases as the static period becomes longer. Note that, although the static period of pixel signal A+B is extended in the fourth readout mode, it may be the same length as in the first readout mode.

[0104] As described above, it is possible to provide an imaging device and a control method thereof that suppress horizontal band-like offset deviation without changing the length of the signal readout time (horizontal period) of the imaging element 400 depending on the imaging mode.

[0105] Example 4 In a fourth embodiment, a modified example of the configuration of pixels and peripheral circuits of the image sensor 400 will be described. FIG. 10 is a block diagram showing an example of the configuration of pixels and peripheral circuits of the image sensor 400 in the fourth embodiment. The difference from FIG. 1 is that a plurality of reference signals generated by the DAC 111 are output through separate wirings and input to one of the comparators 107 in the column circuits 106A and 106B, respectively. With this configuration, it is possible to supply a reference signal to each column circuit (each column of the pixel array) at a different timing.

[0106] 11 is a timing chart of the fifth read mode in Example 4. The outline of the read driving is the same as that of the second read mode described above, so in this example, the explanation will focus on the differences from the second read mode.

[0107] First, the entire period of the fifth read mode (t1000 to t1011) is equal to the entire period of the second read mode (t700 to t711). The fifth read mode and the second read mode differ in the timing at which the transfer pulses PTXA and PTXB become Hi.

[0108] That is, the timing (t1006) at which the transfer pulses PTXA and PTXB become Hi in the fifth readout mode is controlled to be later than the timing (t706) at which the transfer pulses PTXA and PTXB become Hi in the second readout mode.

[0109] The static period of the A+B signal in the fifth read mode (time t1007 to t1008) is shorter than the static period of the A+B signal in the second read mode (time t707 to t708).

[0110] Thus, in the same horizontal period, the fifth readout mode differs from the second readout mode in the timing at which the transfer pulses PTXA and PTXB become Hi, and the static period of the potential fluctuation of the A+B signal is shorter.

[0111] In the fourth embodiment, the column circuit 106A is controlled to read out signals in the second readout mode, and the column circuit 106B is controlled to read out signals in the fifth readout mode. That is, in the fourth embodiment, the signal readout timing is made different for each adjacent column circuit (each column of the pixel array).

[0112] The degree of the horizontal band-like offset deviation varies depending on the amount of potential fluctuations that occur simultaneously. In this embodiment, the horizontal band-like offset deviation can be reduced by dispersing the potential fluctuations that occur simultaneously in the column circuits 106A and 106B.

[0113] Alternatively, the column circuit 106A may read out signals in the first readout mode, and the column circuit 106B may read out signals in the fifth readout mode.

[0114] In yet another embodiment, the signal readout timing may be determined arbitrarily according to the arrangement of the column circuits, not limited to adjacent column circuits. For example, a configuration may be adopted in which the signal readout timing is varied for each partial position or region, such as the left side, right side, upper side, or lower side of the center of the image sensor 400.

[0115] As described above, it is possible to provide an imaging device that suppresses horizontal band-like offset deviation without changing the readout time (horizontal period) of the imaging element 400 depending on the imaging mode.

[0116] Although the preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications and changes are possible within the scope of the gist of the present invention.

[0117] (Other embodiments) The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program.The present invention can also be realized by a circuit (e.g., ASIC) that realizes one or more functions. [Explanation of symbols]

[0118] 101 pixel array 102 pixels 105 column signal line 106 column circuit 405 Signal Processing Circuit 406 Control Circuit

Claims

1. a pixel array in which a plurality of pixels are arranged in a matrix; a plurality of column signal lines to which signals of the plurality of pixels are output for each column of the pixel array; a plurality of AD conversion circuits that perform AD conversion on signals from the plurality of pixels that are output to the plurality of column signal lines for each column; an amplifier circuit that amplifies the digital signals AD-converted by the plurality of AD conversion circuits with a digital gain; a control means for controlling the output of signals from the plurality of pixels arranged in the same row of the pixel array to the plurality of column signal lines for each column during a predetermined readout period and for AD conversion by the plurality of AD conversion circuits, and for controlling the readout of signals from the plurality of pixels in a first signal readout mode when the digital signal is not amplified by the amplifier circuit, and the readout of signals from the plurality of pixels in a second signal readout mode when the digital signal is amplified by the amplifier circuit, the predetermined readout period includes a first period from when signals from the plurality of pixels are output to the plurality of column signal lines for each column until AD conversion is started by the plurality of AD conversion circuits, and a second period in which the signals from the plurality of pixels output to the plurality of column signal lines for each column are AD converted by the plurality of AD conversion circuits; an imaging device, characterized in that the predetermined readout period is equal in the first signal readout mode and the second signal readout mode, the first period in the second signal readout mode is longer than the first period in the first signal readout mode, and the second period in the second signal readout mode is shorter than the second period in the first signal readout mode.

2. 2. The imaging device according to claim 1, wherein the plurality of AD conversion circuits are slope-type AD conversion circuits that AD convert the signals of the plurality of pixels using a reference signal whose level changes over time.

3. 3. The imaging apparatus according to claim 2, wherein the rate of change of the reference signal per unit time is the same in the first signal readout mode and the second signal readout mode.

4. 4. The imaging device according to claim 1, wherein in the second signal readout mode, the plurality of AD conversion circuits perform AD conversion of the same signal a plurality of times.

5. 5. The imaging device according to claim 1, wherein the first signal readout mode and the second signal readout mode are assigned to each column of the pixel array.

Images