Semiconductor Devices

Abstract

To provide a semiconductor device which can be suppressed in voltage oscillation at recovery.SOLUTION: A semiconductor device includes first and second electrodes, and first to fifth semiconductor regions. The first semiconductor region is provided on and electrically connected to the first electrode and is of a first conductivity type. The second semiconductor region is provided on the first semiconductor region and is of the first conductivity type. The third semiconductor region is provided on a part of the second semiconductor region and is of the first conductivity type. The fourth semiconductor region is provided on the second semiconductor region and on the third semiconductor region and is of a second conductivity type. The fifth semiconductor region is provided on a part of the fourth semiconductor region and is of the second conductivity type. At least a part of the fifth semiconductor region is located above at least a part of the third semiconductor region. The second electrode is provided on and electrically connected to the fifth semiconductor region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art Semiconductor devices including diodes are used in applications such as power conversion, etc. During recovery, when the diode transitions from an on state to an off state, the voltage generated in the diode may oscillate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 10-93113 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device capable of suppressing voltage oscillation during recovery. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a fifth semiconductor region, and a second electrode. The first semiconductor region is of a first conductivity type and is provided on the first electrode and electrically connected to the first electrode. The second semiconductor region is of the first conductivity type and has a first conductivity type impurity concentration lower than the first conductivity type impurity concentration of the first semiconductor region. The third semiconductor region is provided on a portion of the second semiconductor region and is of the first conductivity type and has a first conductivity type impurity concentration higher than the first conductivity type impurity concentration of the second semiconductor region. The fourth semiconductor region is of a second conductivity type and provided on both the second semiconductor region and the third semiconductor region. The fifth semiconductor region is provided on a portion of the fourth semiconductor region and is of a second conductivity type and has a second conductivity type impurity concentration higher than the second conductivity type impurity concentration of the fourth semiconductor region. At least a portion of the fifth semiconductor region is located above at least a portion of the third semiconductor region. The second electrode is provided on the fifth semiconductor region and is electrically connected to the fifth semiconductor region. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic plan view illustrating a semiconductor device according to a first embodiment. [Figure 2] 1 is a schematic cross-sectional view illustrating a semiconductor device according to a first embodiment. [Figure 3] 1 is a schematic cross-sectional view illustrating a semiconductor device according to a first embodiment. [Figure 4] 1 is a schematic plan view illustrating a semiconductor device according to a first embodiment. [Figure 5] 1 is a schematic cross-sectional view illustrating a semiconductor device according to a first embodiment. [Figure 6] 1 is a schematic cross-sectional view illustrating a semiconductor device according to a first embodiment. [Figure 7] FIG. 10 is a graph illustrating the results of a simulation of the characteristics of a semiconductor device. [Figure 8] FIG. 10 is a graph illustrating the results of a simulation of the characteristics of a semiconductor device. [Figure 9] FIG. 10 is a schematic plan view illustrating a semiconductor device according to a second embodiment. [Figure 10] FIG. 10 is a schematic plan view illustrating a part of a semiconductor device according to a second embodiment. [Figure 11] FIG. 10 is a schematic cross-sectional view illustrating a semiconductor device according to a second embodiment. [Figure 12] FIG. 10 is a schematic cross-sectional view illustrating a semiconductor device according to a second embodiment. [Figure 13] FIG. 10 is a schematic cross-sectional view illustrating a semiconductor device according to a second embodiment. [Figure 14] FIG. 10 is a schematic plan view illustrating a part of a semiconductor device according to a second embodiment. [Figure 15] FIG. 10 is a schematic cross-sectional view illustrating a semiconductor device according to a second embodiment. [Figure 16] FIG. 10 is a schematic cross-sectional view illustrating a semiconductor device according to a second embodiment. [Figure 17] FIG. 10 is a schematic cross-sectional view illustrating a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In the present specification and the drawings, elements similar to those already explained are given the same reference numerals and detailed explanations will be omitted as appropriate.

[0008] In each of the embodiments described below, the p-type (an example of the second conductivity type) and n-type (an example of the first conductivity type) of each semiconductor region may be reversed to implement each embodiment.

[0009] (First embodiment) FIG. 1 is a schematic plan view showing a semiconductor device according to the first embodiment. FIG. 2 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. The semiconductor device 101 according to the embodiment shown in Figures 1 to 3 is, for example, a diode. Figure 2 corresponds to the cross section taken along line AA in Figure 1. Figure 3 corresponds to the cross section taken along line BB in Figure 1.

[0010] 2, the semiconductor device 101 includes a first electrode 11, a semiconductor layer 20, and a second electrode 12. The semiconductor layer 20 is, for example, a semiconductor substrate. The semiconductor layer 20 is provided between the first electrode 11 and the second electrode 12. The semiconductor layer 20 includes a first semiconductor region 21 (cathode region), a second semiconductor region 22 (drift region), a third semiconductor region 23, a fourth semiconductor region 24 (anode region), and a fifth semiconductor region 25 (contact region). Note that in FIG. 1, the second electrode 12 is not shown, and the position of the third semiconductor region 23 below the fourth semiconductor region 24 is indicated by a dashed line.

[0011] In the following description, the direction from the first electrode 11 toward the second electrode 12 is referred to as the Z direction. The Z direction is, for example, a direction perpendicular to the top surface of the first electrode 11. The Z direction corresponds to the direction from the first semiconductor region 21 toward the fourth semiconductor region 24. Two directions that are perpendicular to the Z direction and perpendicular to each other are referred to as the X direction and the Y direction. For the sake of explanation, the direction from the first electrode 11 toward the second electrode 12 is referred to as "up," and the opposite direction is referred to as "down." In other words, the second electrode 12 side is referred to as the upper side, and the first electrode 11 side is referred to as the lower side. These directions are based on the relative positional relationship between the first electrode 11 and the second electrode 12 and are unrelated to the direction of gravity.

[0012] The first electrode 11 is, for example, a back surface electrode provided on substantially the entire back surface (lower surface) of the semiconductor layer 20. The first semiconductor region 21 is provided on the first electrode 11 and is electrically connected to the first electrode 11. The first semiconductor region 21 is in contact with, for example, the upper surface of the first electrode 11. The first semiconductor region 21 is of a first conductivity type (for example, n-type).

[0013] The second semiconductor region 22 is provided on the first semiconductor region 21 and is electrically connected to the first semiconductor region 21. The second semiconductor region 22 is in contact with (continuous with) the first semiconductor region 21. The second semiconductor region 22 is of the first conductivity type. The impurity concentration of the first conductivity type in the second semiconductor region 22 is lower than the impurity concentration of the first conductivity type in the first semiconductor region 21.

[0014] 2, a semiconductor region 22b (buffer region) may be provided between the second semiconductor region 22 and the first semiconductor region 21. The semiconductor region 22b contacts the first semiconductor region 21 and the second semiconductor region 22, and electrically connects the first semiconductor region 21 and the second semiconductor region 22. The semiconductor region 22b is of the first conductivity type. The impurity concentration of the first conductivity type in the semiconductor region 22b is lower than the impurity concentration of the first conductivity type in the first semiconductor region 21 and higher than the impurity concentration of the first conductivity type in the second semiconductor region 22.

[0015] The third semiconductor region 23 is provided on a portion of the second semiconductor region 22 and is electrically connected to the second semiconductor region 22. As shown in FIG. 2, a bottom surface 23u and a side surface 23s of the third semiconductor region 23 are in contact with the second semiconductor region 22. The side surface 23s is a surface that intersects the X direction and extends in the Y direction. A top surface 23t of the third semiconductor region 23 is continuous with a top surface 22t of the second semiconductor region 22. The position of the top surface 23t in the Z direction may be the same as the position of the top surface 22t in the Z direction. The third semiconductor region 23 is of the first conductivity type. The impurity concentration of the first conductivity type in the third semiconductor region 23 is higher than the impurity concentration of the first conductivity type in the second semiconductor region 22. The impurity concentration of the first conductivity type in the third semiconductor region 23 may be lower than the impurity concentration of the first conductivity type in the first semiconductor region 21.

[0016] The impurity concentration of the first conductivity type in the third semiconductor region 23 is not particularly limited, but is, for example, 10 times or more and 500 times or less than the impurity concentration of the first conductivity type in the second semiconductor region 22. The impurity concentration of the first conductivity type in the third semiconductor region 23 is, for example, 1×10 15 atoms / cm 3 (atoms / cubic centimeter) or more than 5×10 16 atoms / cm3 The following is the result.

[0017] In this example, a plurality of third semiconductor regions 23 are provided. The plurality of third semiconductor regions 23 are periodically arranged along the X direction. Each third semiconductor region 23 extends in the Y direction.

[0018] The fourth semiconductor region 24 is provided on the second semiconductor region 22 and on the third semiconductor region 23. The fourth semiconductor region 24 is electrically connected to the second semiconductor region 22 and the third semiconductor region 23. As shown in Fig. 2, the fourth semiconductor region 24 is in contact with an upper surface 22t of the second semiconductor region 22 and an upper surface 23t of the third semiconductor region 23. The fourth semiconductor region 24 is of a second conductivity type (e.g., p-type).

[0019] The fifth semiconductor region 25 is provided on a portion of the fourth semiconductor region 24 and is electrically connected to the fourth semiconductor region 24. As shown in FIG. 2, a bottom surface 25u and a side surface 25s of the fifth semiconductor region 25 are in contact with the fourth semiconductor region 24. The side surface 25s is a surface that intersects the X direction and extends in the Y direction. An upper surface 25t of the fifth semiconductor region 25 is continuous with an upper surface 24t of the fourth semiconductor region 24. The position of the upper surface 25t in the Z direction may be the same as the position of the upper surface 24t in the Z direction. The fifth semiconductor region 25 is of the second conductivity type. The impurity concentration of the second conductivity type in the fifth semiconductor region 25 is higher than the impurity concentration of the second conductivity type in the fourth semiconductor region 24.

[0020] The impurity concentration of the second conductivity type in the fifth semiconductor region 25 is not particularly limited, but is, for example, 10 times or more and 200 times or less than the impurity concentration of the second conductivity type in the fourth semiconductor region 24. The impurity concentration of the second conductivity type in the fifth semiconductor region 25 is, for example, 1×10 17 atoms / cm 3 More than 1×10 19 atoms / cm 3 The following is the result.

[0021] At least a portion of the fifth semiconductor region 25 is located above at least a portion of the third semiconductor region 23. In other words, when viewed along the Z direction, at least a portion of the fifth semiconductor region 25 overlaps with at least a portion of the third semiconductor region 23.

[0022] In this example, a plurality of fifth semiconductor regions 25 are provided. The plurality of fifth semiconductor regions 25 are arranged periodically along the X direction. Each fifth semiconductor region 25 extends in the Y direction. The period at which the plurality of fifth semiconductor regions 25 are arranged in the X direction may be the same as the period at which the plurality of third semiconductor regions 23 are arranged in the X direction. In other words, the third semiconductor region 23 extends along the fifth semiconductor region 25. The length of the third semiconductor region 23 in the Y direction may be the same as the length of the fifth semiconductor region 25 in the Y direction.

[0023] At least a portion of each of the plurality of fifth semiconductor regions 25 is located above at least a portion of each of the plurality of third semiconductor regions 23. In other words, one third semiconductor region 23 is arranged above one fifth semiconductor region 25. As shown in FIG. 1 or FIG. 2, no third semiconductor region 23 is arranged below the center 20c of the region 20m between adjacent fifth semiconductor regions 25. In other words, the third semiconductor region 23 is not aligned (does not overlap) with the center 20c in the Z direction. For example, the third semiconductor region 23 is provided only below the fifth semiconductor region 25. When viewed from above as in FIG. 1, the center 20c is linear and extends in the Y direction, passing through the midpoint of the line segment connecting adjacent fifth semiconductor regions 25 at the shortest distance.

[0024] The second electrode 12 is provided on the fourth semiconductor region 24 and on the fifth semiconductor region 25, and is electrically connected to the fourth semiconductor region 24 and the fifth semiconductor region 25. As shown in Fig. 2, the lower surface of the second electrode 12 is in contact with the upper surface 24t of the fourth semiconductor region 24 and the upper surface 25t of the fifth semiconductor region 25. For example, the contact between the second electrode 12 and the fourth semiconductor region 24 is a Schottky contact, and the contact between the second electrode 12 and the fifth semiconductor region 25 is an ohmic contact.

[0025] An example of the material of each component of the semiconductor device 100 will be described. The first semiconductor region 21, the second semiconductor region 22, the third semiconductor region 23, the fourth semiconductor region 24, and the fifth semiconductor region 25 contain silicon, silicon carbide, gallium nitride, or gallium arsenide as the semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as the n-type impurity. Boron can be used as the p-type impurity. The third semiconductor region 23, the fourth semiconductor region 24, and the fifth semiconductor region 25 can be formed by, for example, ion implantation of impurities. The first electrode 11 and the second electrode 12 include a conductive material such as a metal. For example, the first electrode 11 and the second electrode 12 include at least one of aluminum, titanium, and tungsten. For example, the second electrode 12 includes aluminum and silicon. Alternatively, the second electrode 12 includes titanium or tungsten.

[0026] The operation of the semiconductor device 100 will now be described. When a positive voltage is applied to the second electrode 12 with respect to the first electrode 11, a forward voltage is applied to the pn junction between the second semiconductor region 22 and the fourth semiconductor region 24 and the pn junction between the third semiconductor region 23 and the fourth semiconductor region 24. Holes are injected from the fifth semiconductor region 25 into the second semiconductor region 22 (and the third semiconductor region 23) via the fourth semiconductor region 24, and electrons are injected from the first semiconductor region 21 into the second semiconductor region 22. A current flows from the second electrode 12 to the first electrode 11, and the semiconductor device 100 enters an on state. In the on state, holes and electrons are accumulated in the second semiconductor region 22, and the electrical resistance of the second semiconductor region 22 is significantly reduced.

[0027] Thereafter, when a positive voltage is applied to the first electrode 11 with respect to the second electrode 12, the current flowing from the second electrode 12 to the first electrode 11 is cut off, and the semiconductor device 100 enters an off state. The holes accumulated in the second semiconductor region 22 are discharged to the second electrode 12 through the fifth semiconductor region 25. The electrons accumulated in the second semiconductor region 22 are discharged to the first electrode 11 through the first semiconductor region 21. A depletion layer spreads from the pn junction surface between the second semiconductor region 22 and the fourth semiconductor region 24 toward the second semiconductor region 22 in response to the voltage. The depletion layer spreading into the second semiconductor region 22 maintains the breakdown voltage.

[0028] The effects of the embodiment will be described. As described above, in the semiconductor device 101 according to the embodiment, at least a portion of the fifth semiconductor region 25 is located above at least a portion of the third semiconductor region 23. In other words, at least a portion of the third semiconductor region 23 is located below the fifth semiconductor region 25. This suppresses oscillations in the voltage (recovery voltage) generated between the first electrode 11 and the second electrode 12 during recovery, which switches the semiconductor device 101 (diode) from an on state to an off state, thereby improving the recovery characteristics. This is thought to be because, for example, the provision of the third semiconductor region 23 suppresses the rate at which a depletion layer spreads from the pn junction surface toward the second semiconductor region 22 during recovery. For example, the provision of the third semiconductor region 23 lengthens the time it takes for the depletion layer to reach the first semiconductor region 21 (or the semiconductor region 22b). As a result, for example, it takes longer for carriers to be discharged from the second semiconductor region 22, suppressing abrupt changes in the potential difference between the first electrode 11 and the second electrode 12 during recovery, resulting in a soft recovery recovery characteristic.

[0029] On the other hand, providing the third semiconductor region 23 may affect the conduction characteristics in the on-state. Specifically, the on-resistance may increase. For example, a potential barrier may be formed between the third semiconductor region 23 and the fourth semiconductor region 24, reducing the on-state current. In contrast, in the semiconductor device 101, the third semiconductor region 23 is not disposed below the center 20c between the fifth semiconductor regions 25. In other words, the third semiconductor region 23 is disposed only below the fifth semiconductor region 25, which is the carrier injection location. In this case, the increase in on-resistance can be suppressed compared to when the third semiconductor region 23 is disposed below the center 20c. This is thought to be because, for example, the carrier concentration is relatively high directly below the fifth semiconductor region 25, which is the carrier injection location, thereby suppressing the effect of the potential barrier caused by the third semiconductor region 23. For example, when the carrier concentration is high, holes can cross the potential barrier relatively easily.

[0030] 1 and the like, the third semiconductor region 23 and the fifth semiconductor region 25 extend in the Y direction. That is, the third semiconductor region 23 is disposed so as to extend along the fifth semiconductor region 25. This makes it possible to suppress, for example, the influence of the third semiconductor region 23 on the conduction characteristics while suppressing the oscillation of the recovery voltage.

[0031] For example, as shown in FIG. 2, the length W23 of the third semiconductor region 23 along the X direction is equal to or greater than the length W25 of the fifth semiconductor region 25 along the X direction. This allows the third semiconductor region 23 to be provided over a relatively wide area below the fifth semiconductor region 25, for example, thereby further suppressing the oscillation of the recovery voltage. For example, it is considered that the rate at which the depletion layer extends downward during recovery can be further reduced. In this example, the length W23 is longer than the length W25, and both ends of one fifth semiconductor region 25 in the X direction are located above the third semiconductor region 23. For example, the entire fifth semiconductor region 25 overlaps with the third semiconductor region 23 in the Z direction. However, in an embodiment, the length W23 may be shorter than the length W25, and the third semiconductor region 23 may not be disposed below a portion of one fifth semiconductor region 25. The length W23 is not particularly limited, but is, for example, equal to or greater than 1 μm (micrometer) and equal to or less than 50 μm. The length W25 is not particularly limited, but is, for example, 5 μm or more and 50 μm or less.

[0032] Furthermore, for example, the length W23 of the third semiconductor region 23 along the X direction may be longer than the distance W23m between adjacent third semiconductor regions 23, or may be longer than the distance W25m between adjacent fifth semiconductor regions 25. When the length W23 is long, the third semiconductor region 23 is provided over a relatively wide range below the fifth semiconductor region 25, thereby making it possible to further suppress, for example, the oscillation of the recovery voltage. However, the embodiment is not limited to the above, and the length W23 of the third semiconductor region 23 along the X direction may be shorter than the distance W25m between adjacent fifth semiconductor regions 25, or may be longer than the distance W23m between adjacent third semiconductor regions 23. When the length W23 is short, it is easier to suppress the influence of the third semiconductor region 23 on the conduction characteristics.

[0033] For example, as shown in FIG. 2 , the length D23 of the third semiconductor region 23 along the Z direction is longer than the length D24 of the fourth semiconductor region 24 along the Z direction. Increasing the length D23 of the third semiconductor region 23 along the Z direction is believed to further suppress the expansion of the depletion layer during recovery. This can further suppress the oscillation of the recovery voltage. However, in the embodiment, the length D24 of the fourth semiconductor region 24 along the Z direction may be longer than the length D23 of the third semiconductor region 23 along the Z direction. If the length D24 of the fourth semiconductor region 24 along the Z direction is long, punch-through is less likely to occur at the surface of the fourth semiconductor region 24 when switching from the on state to the off state to interrupt current, improving the interruption capability. The length D23 is not particularly limited, but is, for example, 5 μm or more and 20 μm or less. The length D24 is not particularly limited, but is, for example, 2 μm or more and 10 μm or less.

[0034] (Variation) FIG. 4 is a schematic plan view illustrating the semiconductor device according to the first embodiment. FIG. 5 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. FIG. 6 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. Fig. 5 corresponds to the cross section taken along line CC in Fig. 4. Fig. 6 corresponds to the cross section taken along line DD in Fig. 4. As shown in Figs. 4 to 6, in the semiconductor device 102 according to the embodiment, the fourth semiconductor region 24 includes a first region 24a and a second region 24b. Apart from this, the same explanation as for the semiconductor device 101 can be applied to the semiconductor device 102.

[0035] 5, the first region 24a is aligned with the second region 24b in the X direction. The second region 24b is deeper than the first region 24a. That is, the position in the Z direction of the lower end 24bu of the second region 24b is lower than the position in the Z direction of the lower end 24au (lower surface) of the first region 24a. Note that the position in the Z direction of the upper end 24bt (upper surface) of the second region 24b may be the same as the position in the Z direction of the upper end 24at (upper surface) of the first region 24a.

[0036] At least a portion of the second region 24b is located between at least a portion of the third semiconductor region 23 and at least a portion of the fifth semiconductor region 25. For example, the length W24b in the X direction of the second region 24b is longer than the length W25 in the X direction of the fifth semiconductor region 25. For example, the entire fifth semiconductor region 25 is disposed on the second region 24b.

[0037] In this example, the length W23 in the X direction of the third semiconductor region 23 is longer than the length W24b in the X direction of the second region 24b. For example, as shown in FIG. 5, the third semiconductor region 23 may be in contact with side surfaces 24bq and 24br in the X direction of the second region 24b. The third semiconductor region 23 may be in contact with the lower end 24au of the first region 24a. However, in the embodiment, the length W23 may be shorter than the length W24b, and the third semiconductor region 23 may not be disposed below a part of the second region 24b.

[0038] A plurality of first regions 24a are provided. The plurality of first regions 24a are periodically arranged along the X direction. Each of the first regions 24a extends in the Y direction. A plurality of second regions 24b are provided. The plurality of second regions 24b are periodically arranged along the X direction. The first regions 24a and the second regions 24b are alternately arranged along the X direction. Each of the second regions 24b extends in the Y direction.

[0039] The concentration of the second conductivity type impurities in the second region 24b may be different from the concentration of the second conductivity type impurities in the first region 24a. For example, the concentration of the second conductivity type impurities in the second region 24b is higher than the concentration of the second conductivity type impurities in the first region 24a.

[0040] In this way, in the semiconductor device 102, a portion of the fourth semiconductor region 24 protrudes downward, making it less likely that punch-through will occur to the surface of the fourth semiconductor region 24 when the semiconductor device 102 is switched from the on state to the off state to interrupt the current, thereby improving the interruption tolerance.

[0041] In the semiconductor device 102, as in the semiconductor device 101, the oscillation of the recovery voltage can be suppressed.

[0042] FIG. 7 is a graph illustrating the results of a simulation of the characteristics of the semiconductor device. 7 shows the voltage and current during recovery of the semiconductor device 100 (not shown) according to the embodiment and semiconductor devices 190 and 191 (not shown) according to the reference examples. The semiconductor device 100 is a semiconductor device similar to the semiconductor device 102 described above. The semiconductor device 190 is configured such that the third semiconductor region 23 is omitted compared to the semiconductor device 100. The semiconductor device 191 is configured such that the position of the third semiconductor region 23 is shifted in the X direction compared to the semiconductor device 100. In the semiconductor device 191, the third semiconductor region 23 overlaps with the center 20c between the fifth semiconductor regions 25 in the Z direction, but does not overlap with the fifth semiconductor region 25 in the Z direction.

[0043] The horizontal axis of FIG. 7 represents time (seconds). The range of values ​​greater than 0 on the vertical axis of FIG. 7 represents the voltage V (volts) generated between the first electrode 11 and the second electrode 12. The range of values ​​less than 0 on the vertical axis of FIG. 7 represents the current I (amperes) flowing between the first electrode 11 and the second electrode 12. As shown in FIG. 7, oscillations occur in the voltage V190 and current I190 of the semiconductor device 190. In contrast, oscillations are suppressed in the voltage V100 and current I100 of the semiconductor device 100 compared to the semiconductor device 190. Furthermore, oscillations are suppressed in the voltage V191 and current I191 of the semiconductor device 191 compared to the semiconductor device 190. As such, in the embodiment, by providing the third semiconductor region 23, it is possible to suppress oscillations in voltage during recovery.

[0044] FIG. 8 is a graph illustrating the results of a simulation of the characteristics of the semiconductor device. Fig. 8 shows the characteristics in the on-state of semiconductor devices 100, 190, and 191. The vertical axis of Fig. 8 represents the current I (amperes) flowing between first electrode 11 and second electrode 12. The horizontal axis of Fig. 8 represents the voltage V (volts) generated between first electrode 11 and second electrode 12.

[0045] 8, the current IF191 in the semiconductor device 191 is significantly lower than the current IF190 in the semiconductor device 190. In contrast, the current IF100 in the semiconductor device 100 according to the embodiment is suppressed from decreasing from the current IF190. As such, in the embodiment, it is preferable that the third semiconductor region 23 is not disposed below the center 20c between the fifth semiconductor regions 25. This can suppress the effect on the conduction characteristics when the third semiconductor region 23 is provided.

[0046] (Second embodiment) FIG. 9 is a schematic plan view illustrating a semiconductor device according to the second embodiment. 9, the semiconductor device 103 according to the embodiment has a first region R1 and a second region R2. The first region R1 is, for example, a diode region in which a diode is provided. The second region R2 is, for example, an IGBT region in which an IGBT (Insulated Gate Bipolar Transistor) is provided. The semiconductor device 103 is, for example, an RC-IGBT (Reverse Conducting IGBT).

[0047] 9, there is one first region R1 and one second region R2. A plurality of first regions R1 and a plurality of second regions R2 may be provided. The first region R1 and the second region R2 are arranged side by side in the Y direction (or X direction).

[0048] A second electrode 12 and a third electrode 13 (for example, a gate pad) are provided on the upper surface of the semiconductor device 103. A termination insulating film 70 is provided on the edge of the upper surface of the semiconductor device 103.

[0049] FIG. 10 is a schematic plan view illustrating a part of the semiconductor device according to the second embodiment. 11 to 13 are schematic cross-sectional views showing a semiconductor device according to the second embodiment. Fig. 10 is an enlarged plan view of a portion RD of the first region R1 shown in Fig. 9. Note that the second electrode 12 is not shown in Fig. 10. Fig. 11 corresponds to the cross section taken along line EE shown in Fig. 10. Fig. 12 corresponds to the cross section taken along line FF shown in Fig. 10. Fig. 13 corresponds to the cross section taken along line GG shown in Fig. 10. The first region R1 of the semiconductor device 103 also includes a first electrode 11, a first semiconductor region 21, a second semiconductor region 22, a third semiconductor region 23, a fourth semiconductor region 24, a fifth semiconductor region 25, and a second electrode 12. The first region R1 of the semiconductor device 103 further includes a first conductive portion 31 and a first insulating film 51.

[0050] 11, for example, the first conductive portion 31 faces each of the side surface 22p of the second semiconductor region 22, the side surface 23p of the third semiconductor region 23, the side surface 24p of the fourth semiconductor region 24, and the side surface 25p of the fifth semiconductor region 25, via the first insulating film 51. That is, the first conductive portion 31 is aligned in the Y direction with each of the side surfaces 22p, 23p, 24p, and 25p. The first insulating film 51 is disposed between the first conductive portion 31 and each of the side surfaces (each of the side surfaces 22p, 23p, 24p, and 25p). The first insulating film 51 is in contact with the first conductive portion 31 and each of the side surfaces (each of the side surfaces 22p, 23p, 24p, and 25p). Note that each of the side surfaces 22p, 23p, 24p, and 25p intersects the Y direction and extends along the ZX plane.

[0051] The first conductive portion 31 is electrically connected to the second electrode 12 located above it. For example, the potential of the first conductive portion 31 is set to be the same as the potential of the second electrode 12.

[0052] A first trench T1 is provided in the semiconductor layer 20. The first trench T1 is a recess that extends downward from the surface of the semiconductor layer 20 (the upper surface 24t of the fourth semiconductor region 24 and the upper surface 25t of the fifth semiconductor region 25) and reaches the second semiconductor region 22. A first insulating film 51 is arranged on the inner side surface of the first trench T1, and a first conductive portion 31 is arranged inside the first insulating film 51.

[0053] There are provided a plurality of first trenches T1, a plurality of first insulating films 51, and a plurality of first conductive portions 31. The plurality of first trenches T1 are periodically arranged along the Y direction. Each first trench T1 extends in the X direction. The multiple first insulating films 51 are arranged periodically along the Y direction. Each first insulating film 51 is provided on the inner wall of each first trench T1 and extends in the X direction. The multiple first conductive portions 31 are arranged periodically along the Y direction. Each first conductive portion 31 is provided inside each first trench T1 and each first insulating film 51, and extends in the X direction.

[0054] 10, the fifth semiconductor region 25 extending in the Y direction is divided by the first trench T1 into a plurality of portions spaced apart in the Y direction. Similarly, the third semiconductor region 23 extending in the Y direction is divided by the first trench T1 into a plurality of portions spaced apart in the Y direction.

[0055] FIG. 14 is a schematic plan view illustrating a part of the semiconductor device according to the second embodiment. 15 to 17 are schematic cross-sectional views showing the semiconductor device according to the second embodiment. Fig. 14 is an enlarged plan view of a portion RI of the second region R2 shown in Fig. 9. Note that the second electrode 12 is not shown in Fig. 14. Fig. 15 corresponds to the cross section taken along line HH shown in Fig. 14. Fig. 16 corresponds to the cross section taken along line II shown in Fig. 14. Fig. 17 corresponds to the cross section taken along line JJ shown in Fig. 14. 15, the first electrode 11, the second electrode 12, and the second semiconductor region 22 are also provided in the second region R2. That is, the first electrode 11, the second electrode 12, and the second semiconductor region 22 are provided across the first region R1 and the second region R2, and are continuous from the first region R1 to the second region R2.

[0056] For example, the first electrode 11 functions as a cathode electrode in the first region R1 and functions as a collector electrode in the second region R2, and the second electrode 12 functions as an anode electrode in the first region R1 and functions as an emitter electrode in the second region R2.

[0057] 15, the second region R2 of the semiconductor device 103 further includes a sixth semiconductor region 26 (collector region), a seventh semiconductor region 27 (base region), an eighth semiconductor region 28 (emitter region), a semiconductor region 29 (barrier region), a second insulating film 52 (gate insulating film), and a second conductive portion 32 (gate electrode). For example, as shown in Fig. 16, the second region R2 of the semiconductor device 103 further includes a semiconductor region 40. Each semiconductor region is a part of the semiconductor layer 20 (semiconductor substrate).

[0058] The sixth semiconductor region 26 is provided between the first electrode 11 and the second semiconductor region 22, and is electrically connected to the second semiconductor region 22 and the first electrode 11. A semiconductor region 22b (buffer region) may be provided between the sixth semiconductor region 26 and the second semiconductor region 22. The sixth semiconductor region 26 is in contact with, for example, the second semiconductor region 22 (or the semiconductor region 22b) and the first electrode 11. The sixth semiconductor region 26 is of the second conductivity type.

[0059] The semiconductor region 29 is provided on the second semiconductor region 22 and is electrically connected to the second semiconductor region 22. The semiconductor region 29 is in contact with the second semiconductor region 22. The semiconductor region 29 is of a first conductivity type. The impurity concentration of the first conductivity type in the semiconductor region 29 is higher than the impurity concentration of the first conductivity type in the second semiconductor region 22.

[0060] The seventh semiconductor region 27 is provided on the semiconductor region 29 and is electrically connected to the semiconductor region 29. That is, the seventh semiconductor region 27 is provided on the second semiconductor region 22 above the sixth semiconductor region 26 and is electrically connected to the second semiconductor region 22. The seventh semiconductor region is of the second conductivity type.

[0061] The eighth semiconductor region 28 is provided on a portion of the seventh semiconductor region 27 and is electrically connected to the seventh semiconductor region 27. The eighth semiconductor region 28 is in contact with the seventh semiconductor region 27. The eighth semiconductor region 28 is of the first conductivity type. The impurity concentration of the first conductivity type in the eighth semiconductor region 28 is higher than the impurity concentration of the first conductivity type in the second semiconductor region 22 and higher than the impurity concentration of the semiconductor region 29.

[0062] 16, the semiconductor region 40 is provided on a portion of the seventh semiconductor region 27 and is electrically connected to the seventh semiconductor region 27. The semiconductor region 40 is in contact with the seventh semiconductor region 27. The semiconductor region 40 is of the second conductivity type. The impurity concentration of the second conductivity type in the semiconductor region 40 is higher than the impurity concentration of the second conductivity type in the seventh semiconductor region 27.

[0063] 15 and 16, the second electrode 12 is provided on the seventh semiconductor region 27, the eighth semiconductor region 28, and the semiconductor region 40, and is electrically connected to the seventh semiconductor region 27, the eighth semiconductor region 28, and the semiconductor region 40. The second electrode 12 is in contact with the seventh semiconductor region 27, the eighth semiconductor region 28, and the semiconductor region 40.

[0064] 15, for example, the second conductive unit 32 faces each of the side surface 22q of the second semiconductor region 22, the side surface 29q of the semiconductor region 29, the side surface 27q of the seventh semiconductor region 27, and the side surface 28q of the eighth semiconductor region 28, via the second insulating film 52. That is, the second conductive unit 32 is aligned in the Y direction with each of the side surfaces 22q, 29q, 27q, and 28q. The second insulating film 52 is disposed between the second conductive unit 32 and each of the side surfaces (each of the side surfaces 22q, 29q, 27q, and 28q). The first insulating film 51 is in contact with the second conductive unit 32 and each of the side surfaces (each of the side surfaces 22q, 29q, 27q, and 28q). Note that each of the side surfaces 22q, 29q, 27q, and 28q intersects the Y direction and extends along the ZX plane.

[0065] The second conductive part 32 is electrically connected to the third electrode 13 shown in FIG. 13. For example, the potential of the second conductive part 32 is set to be the same as the potential of the third electrode 13. A voltage can be applied to the second conductive part 32 via the third electrode 13. The second conductive part 32 is insulated from the second electrode 12.

[0066] A second trench T2 is provided in the semiconductor layer 20. The second trench T2 is a recess that extends downward from the surface of the semiconductor layer 20 (the upper surface of the seventh semiconductor region 27 and the upper surface of the eighth semiconductor region 28) in the second region R2 and reaches the second semiconductor region 22. A second insulating film 52 is arranged on the inner side surface of the second trench T2, and a second conductive portion 32 is arranged inside the second insulating film 52.

[0067] The eighth semiconductor region 28, the semiconductor region 40, the second trench T2, the second insulating film 52, and the second conductive portion 32 are each provided in plural numbers. The eighth semiconductor regions 28 are arranged periodically along the X direction. Each of the eighth semiconductor regions 28 extends in the Y direction. The semiconductor regions 40 are arranged periodically along the Y direction. Each semiconductor region 40 extends in the X direction. The multiple second trenches T2 are arranged periodically along the Y direction. Each second trench T2 extends in the X direction. When viewed from above, one semiconductor region 40 is disposed between two adjacent second trenches T2. In other words, the second trenches and the semiconductor regions 40 are arranged alternately in the Y direction. The multiple second insulating films 52 are arranged periodically along the Y direction. Each second insulating film 52 is provided on the inner wall of each second trench T2 and extends in the X direction. The multiple second conductive portions 32 are arranged periodically along the Y direction. Each second conductive portion 32 is provided inside each second trench T2 and each second insulating film 52, and extends in the X direction.

[0068] 14, the eighth semiconductor region 28 extending in the Y direction is divided by the second trench T2 into a plurality of portions spaced apart in the Y direction. The semiconductor region 40 extending in the X direction is divided by the eighth semiconductor region 28 into a plurality of portions spaced apart in the X direction.

[0069] The materials of the components of the semiconductor device 103 will be described. The sixth semiconductor region 26, the seventh semiconductor region 27, the eighth semiconductor region 28, the semiconductor region 29, and the semiconductor region 40 contain silicon, silicon carbide, gallium nitride, or gallium arsenide as the semiconductor material. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as the n-type impurity. Boron can be used as the p-type impurity. The first conductive portion 31 and the second conductive portion 32 include a conductive material such as a metal material or polysilicon, etc. Impurities may be added to the conductive material. The first insulating film 51 and the second insulating film 52 contain an insulating material such as silicon oxide or silicon nitride. The material of the third electrode 13 may be the same as the material of the second electrode 12 .

[0070] The operation of the semiconductor device 103 will now be described. The first region R1 operates as a diode, similar to the description of the semiconductor device 101. The second region R2 operates as an IGBT. Specifically, while a positive voltage relative to the second electrode 12 is applied to the first electrode 11, a voltage equal to or greater than the threshold is applied to the second conductive portion 32. This forms a channel in the seventh semiconductor region 27, turning the IGBT on. When electrons flow through the channel to the second semiconductor region 22, holes are injected from the sixth semiconductor region 26 into the second semiconductor region 22. The conductivity modulation occurring in the second semiconductor region 22 significantly reduces the electrical resistance of the semiconductor device 103. Thereafter, when the voltage applied to the second conductive portion 32 becomes lower than the threshold, the channel in the seventh semiconductor region 27 disappears, turning the IGBT off. By providing the semiconductor region 29, the potential barrier against holes becomes higher between the second semiconductor region 22 and the seventh semiconductor region 27. This suppresses the movement of holes to the seventh semiconductor region 27, and the density of electrons and holes in the second semiconductor region 22 increases when the IGBT is turned on, thereby reducing the on-resistance.

[0071] The effects of the semiconductor device 103 will be described. Also in the first region R1 of the semiconductor device 103, at least a part of the third semiconductor region 23 is provided below at least a part of the fifth semiconductor region 25. As a result, similar to the description of the semiconductor device 101, also in the semiconductor device 103, oscillations in the recovery voltage of the diode can be suppressed.

[0072] For example, when a reverse bias is applied in which a positive voltage is applied to the first electrode 11 with respect to the second electrode 12, the electric field of the pn junction between the third semiconductor region 23 and the fourth semiconductor region 24 is stronger than the electric field of the pn junction between the second semiconductor region 22 and the fourth semiconductor region 24. For example, when the third semiconductor region 23 is provided, punch-through to the surface of the fourth semiconductor region 24 may be more likely to occur when a reverse bias is applied. In other words, when the third semiconductor region 23 is provided, the breakdown voltage of the semiconductor device 103 may be reduced.

[0073] In contrast, by providing the first conductive portion 31 and the first insulating film 51, a depletion layer spreads from near the lower end of the first insulating film 51 to the second semiconductor region 22 during reverse bias. For example, the electric field near the lower end of the first insulating film 51 (the corner of the first trench T1) becomes stronger, and electric field concentration near the p-n junction can be suppressed. Therefore, by providing the first conductive portion 31 and the first insulating film 51 (first trench T1), a decrease in the breakdown voltage of the semiconductor device 103 can be suppressed. For example, as shown in FIG. 11, the position of the lower end T1u of the first trench T1 in the Z direction is preferably lower than the position of the lower end (bottom surface 23u) of the third semiconductor region 23 in the Z direction. In other words, the first trench T1 is deeper than the third semiconductor region 23. The depth of the first trench T1 may be substantially the same as the depth of the second trench T2.

[0074] The third semiconductor region 23 extends in the Y direction. On the other hand, as described with reference to FIG. 10, the first trench T1 extends in the X direction. That is, the first trench T1 is arranged so as to intersect (for example, perpendicular to) the third semiconductor region 23. This allows one first trench T1 to be in contact with multiple third semiconductor regions 23. Therefore, even when multiple third semiconductor regions 23 are provided, a decrease in the breakdown voltage of the semiconductor device 103 can be suppressed. Furthermore, the third semiconductor region 23 is in contact with multiple first trenches T1 aligned in the Y direction. Therefore, for example, a decrease in the breakdown voltage of the semiconductor device 103 along the Y direction can be suppressed.

[0075] In each of the embodiments described above, the relative level of the impurity concentration between each semiconductor region can be confirmed using, for example, a scanning capacitance microscope (SCM). Note that the carrier concentration in each semiconductor region can be considered to be equal to the concentration of activated impurities in each semiconductor region. Therefore, the relative level of the carrier concentration between each semiconductor region can also be confirmed using an SCM. Furthermore, the impurity concentration in each semiconductor region can be measured using, for example, SIMS (secondary ion mass spectrometry).

[0076] Although several embodiments of the present invention have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other. [Explanation of symbols]

[0077] 11 first electrode, 12 second electrode, 13 third electrode, 20 semiconductor layer, 20c center, 20m region, 21 first semiconductor region, 22 second semiconductor region, 22b semiconductor region, 22p, 22q side surface, 22t top surface, 23 third semiconductor region, 23p, 23s side surface, 23t top surface, 23u Bottom, 24 4th semiconductor region, 24a 1st region, 24at top, 24au bottom, 24b 2nd region, 24bq side, 24bt top, 24bu bottom, 24p side, 24t top, 25 5th semiconductor region, 25p, 25s side, 25t top, 25u bottom surface, 26 sixth semiconductor region, 27 7th semiconductor region, 27q side surface, 28 8th semiconductor region, 28q side surface, 29 semiconductor region, 29q side surface, 31 first conductive portion, 32 second conductive portion, 40 semiconductor region, 51 first insulating film, 52 second insulating film, 70 termination insulating film, 101-103 semiconductor device, D23, D24 length, I100, I190, I191, IF100, IF190, IF191 current, R1 first region, R2 second region, RD, RI part, T1 first trench, T1u bottom end, T2 second trench, V100, V190, V191 voltage, W23 length, W23m distance, W24b length, W25 length, W25m distance

Claims

1. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode; a second semiconductor region provided on the first semiconductor region, the second semiconductor region being of a first conductivity type and having an impurity concentration of the first conductivity type lower than an impurity concentration of the first conductivity type in the first semiconductor region; a third semiconductor region provided on a portion of the second semiconductor region, the third semiconductor region being of a first conductivity type and having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the second semiconductor region; a fourth semiconductor region of the second conductivity type provided on the second semiconductor region and on the third semiconductor region; a fifth semiconductor region provided on a portion of the fourth semiconductor region, the fifth semiconductor region being of the second conductivity type and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the fourth semiconductor region, at least a portion of which is located above at least a portion of the third semiconductor region; a second electrode provided on the fifth semiconductor region and electrically connected to the fifth semiconductor region; Equipped with the fourth semiconductor region includes a first region and a second region, a lower end of the second region is lower than a lower end of the first region, At least a portion of the second region is located between the fifth semiconductor region and the third semiconductor region.

2. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode; a second semiconductor region provided on the first semiconductor region, the second semiconductor region being of a first conductivity type and having an impurity concentration of the first conductivity type lower than an impurity concentration of the first conductivity type in the first semiconductor region; a third semiconductor region provided on a portion of the second semiconductor region, the third semiconductor region being of a first conductivity type and having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the second semiconductor region; a fourth semiconductor region of the second conductivity type provided on the second semiconductor region and on the third semiconductor region; a fifth semiconductor region provided on a portion of the fourth semiconductor region, the fifth semiconductor region being of the second conductivity type and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the fourth semiconductor region, at least a portion of which is located above at least a portion of the third semiconductor region; a second electrode provided on the fifth semiconductor region and electrically connected to the fifth semiconductor region; Equipped with the third semiconductor region and the fifth semiconductor region extend in a second direction perpendicular to a first direction from the first electrode to the second electrode, a length of the third semiconductor region along a third direction perpendicular to the first direction and the second direction is longer than a length of the fifth semiconductor region along the third direction; A semiconductor device, wherein a length of an upper portion of the third semiconductor region along the third direction is longer than a length of a lower portion of the third semiconductor region along the third direction.

3. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode; a second semiconductor region provided on the first semiconductor region, the second semiconductor region being of a first conductivity type and having an impurity concentration of the first conductivity type lower than an impurity concentration of the first conductivity type in the first semiconductor region; a third semiconductor region provided on a portion of the second semiconductor region, the third semiconductor region being of a first conductivity type and having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the second semiconductor region; a fourth semiconductor region of the second conductivity type provided on the second semiconductor region and on the third semiconductor region; a fifth semiconductor region provided on a portion of the fourth semiconductor region, the fifth semiconductor region being of the second conductivity type and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the fourth semiconductor region, at least a portion of which is located above at least a portion of the third semiconductor region; a second electrode provided on the fifth semiconductor region and electrically connected to the fifth semiconductor region; Equipped with the third semiconductor region and the fifth semiconductor region extend in a second direction perpendicular to a first direction from the first electrode to the second electrode, a length of the third semiconductor region along a third direction perpendicular to the first direction and the second direction is longer than a distance between the third semiconductor regions adjacent to each other; A semiconductor device, wherein a length of an upper portion of the third semiconductor region along the third direction is longer than a length of a lower portion of the third semiconductor region along the third direction.

4. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode; a second semiconductor region provided on the first semiconductor region, the second semiconductor region being of a first conductivity type and having an impurity concentration of the first conductivity type lower than an impurity concentration of the first conductivity type in the first semiconductor region; a third semiconductor region provided on a portion of the second semiconductor region, the third semiconductor region being of a first conductivity type and having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the second semiconductor region; a fourth semiconductor region of the second conductivity type provided on the second semiconductor region and on the third semiconductor region; a fifth semiconductor region provided on a portion of the fourth semiconductor region, the fifth semiconductor region being of the second conductivity type and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the fourth semiconductor region, at least a portion of which is located above at least a portion of the third semiconductor region; a second electrode provided on the fifth semiconductor region and electrically connected to the fifth semiconductor region; Equipped with the third semiconductor region and the fifth semiconductor region extend in a second direction perpendicular to a first direction from the first electrode to the second electrode, a length of the third semiconductor region along a third direction perpendicular to the first direction and the second direction is longer than a length of the fifth semiconductor region along the third direction; A semiconductor device, wherein the length of the third semiconductor region along the first direction is longer than the length of the fourth semiconductor region along the first direction.

5. A first electrode; a first semiconductor region of a first conductivity type provided on the first electrode and electrically connected to the first electrode; a second semiconductor region provided on the first semiconductor region, the second semiconductor region being of a first conductivity type and having an impurity concentration of the first conductivity type lower than an impurity concentration of the first conductivity type in the first semiconductor region; a third semiconductor region provided on a portion of the second semiconductor region, the third semiconductor region being of a first conductivity type and having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the second semiconductor region; a fourth semiconductor region of the second conductivity type provided on the second semiconductor region and on the third semiconductor region; a fifth semiconductor region provided on a portion of the fourth semiconductor region, the fifth semiconductor region being of the second conductivity type and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the fourth semiconductor region, at least a portion of which is located above at least a portion of the third semiconductor region; a second electrode provided on the fifth semiconductor region and electrically connected to the fifth semiconductor region; Equipped with the third semiconductor region and the fifth semiconductor region extend in a second direction perpendicular to a first direction from the first electrode to the second electrode, a length of the third semiconductor region along a third direction perpendicular to the first direction and the second direction is longer than a distance between the third semiconductor regions adjacent to each other; A semiconductor device, wherein the length of the third semiconductor region along the first direction is longer than the length of the fourth semiconductor region along the first direction.

6. a plurality of the third semiconductor regions are provided, The fifth semiconductor region is provided in plurality, 6. The semiconductor device according to claim 1, wherein the plurality of third semiconductor regions are not disposed below the center of a region between the adjacent fifth semiconductor regions.

7. The semiconductor device according to claim 1 , wherein the third semiconductor region and the fifth semiconductor region extend in a second direction perpendicular to a first direction extending from the first electrode to the second electrode.

8. further comprising a first conductive portion and a first insulating film; 8. The semiconductor device according to claim 1, wherein the first conductive portion faces a side surface of the third semiconductor region, a side surface of the fourth semiconductor region, and a side surface of the fifth semiconductor region via the first insulating film.

9. a sixth semiconductor region of the second conductivity type provided between the first electrode and the second semiconductor region and electrically connected to the first electrode; a seventh semiconductor region of the second conductivity type provided on the second semiconductor region above the sixth semiconductor region and electrically connected to the second semiconductor region; an eighth semiconductor region of the first conductivity type provided on a portion of the seventh semiconductor region and electrically connected to the second electrode; a second conductive portion facing a side surface of the second semiconductor region, a side surface of the seventh semiconductor region, and a side surface of the eighth semiconductor region via a second insulating film; The semiconductor device according to any one of claims 1 to 8, further comprising:

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