Semiconductor device and manufacturing method thereof

Abstract

This semiconductor device 1 includes: a p-type substrate 4; an n-type semiconductor layer 5 formed on the p-type substrate; and a transistor 40 having the n-type semiconductor layer as a drain, wherein the transistor includes a p-type well region 15 that is formed on a surface layer section of the n-type semiconductor layer and has an n-type source contact region on the surface layer section thereof, and an n-type drain contact region 14 that is formed on the surface layer section of the n-type semiconductor layer and disposed at a distance from the p-type well region 15, and a p-type embedded layer 10 is formed in the n-type semiconductor layer below the p-type well region.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including a transistor such as a DMOS (Diffused Metal Oxide Semiconductor) transistor, and a method for manufacturing the same. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a p-type silicon substrate, an n-type epitaxial layer formed on the p-type silicon substrate, an n-type buried layer formed at the boundary between the p-type silicon substrate and the n-type epitaxial layer, and a DMOS transistor with the n-type epitaxial layer as a drain.

[0003] In Patent Document 1, the DMOS transistor includes a P-type well region formed in a surface layer portion of an n-type epitaxial layer and having an n-type source contact region (n-type source region) in the surface layer portion, and an n-type well region formed in the surface layer portion of the n-type epitaxial layer at a distance from the P-type well region and having an n-type drain contact region (n-type drain region) in the surface layer portion. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2018-11089 Summary of the Invention [Problem to be solved by the invention]

[0005] In a semiconductor device having a DMOS transistor formed therein, such as the semiconductor device of Patent Document 1, when a drain voltage is applied, the potential distribution between the n-type source contact region and the n-type drain contact region (between the source and drain) becomes non-uniform, resulting in a problem of localized electric field concentration occurring between the source and drain.

[0006] An object of the present invention is to provide a semiconductor device capable of improving the breakdown voltage by making the potential distribution between the source and drain uniform, and a method for manufacturing the same. [Means for solving the problem]

[0007] One embodiment of the present invention provides a semiconductor device including a p-type substrate, an n-type semiconductor layer formed on the p-type substrate, and a transistor using the n-type semiconductor layer as a drain, the transistor including a p-type well region formed in a surface layer portion of the n-type semiconductor layer and having an n-type source contact region in the surface layer portion, and an n-type drain contact region formed in the surface layer portion of the n-type semiconductor layer and arranged at a distance from the p-type well region, and a p-type buried layer formed in the n-type semiconductor layer below the p-type well region.

[0008] In this configuration, the potential distribution between the source and drain is made uniform, and the breakdown voltage can be improved.

[0009] In one embodiment of the present invention, the semiconductor device further includes an n-type buried layer formed at the boundary between the p-type substrate and the n-type semiconductor layer and having a higher impurity concentration than the n-type semiconductor layer.

[0010] In one embodiment of the present invention, the width of the p-type buried layer is greater than the width of the p-type well region, and in a planar view, both sides of the p-type buried layer protrude outward from both sides of the p-type well region.

[0011] In one embodiment of the present invention, the p-type buried layer is disposed apart from the p-type well region.

[0012] In one embodiment of the present invention, the p-type buried layer is connected to the p-type well region.

[0013] In one embodiment of the present invention, the p-type buried layer includes a plurality of p-type buried layers spaced apart in the vertical direction.

[0014] In one embodiment of the present invention, the transistor includes: an n-type source region formed in a surface layer portion of the p-type well region and having an n-type impurity concentration higher than that of the n-type semiconductor layer; the n-type source contact region formed in a surface layer portion of the n-type source region and having an n-type impurity concentration higher than that of the n-type source region; an n-type drain region disposed at a distance from the p-type well region and having an n-type impurity concentration higher than that of the n-type semiconductor layer; and the n-type drain contact region formed in a surface layer portion of the n-type drain region and having an n-type impurity concentration higher than that of the n-type drain region.

[0015] In one embodiment of the present invention, the transistor further includes a gate insulating film formed to cover a channel region between the source contact region and the drain contact region, and a gate electrode formed on the gate insulating film and facing the channel region with the gate insulating film interposed therebetween.

[0016] In one embodiment of the present invention, the semiconductor device further includes a source wiring electrically connected to the n-type source contact region, and a drain wiring electrically connected to the n-type drain contact region.

[0017] In one embodiment of the present invention, the n-type drain region and the n-type drain contact region are formed endlessly so as to surround the p-type well region in plan view.

[0018] In one embodiment of the present invention, the p-type buried layer is disposed in a region surrounded by the n-type drain contact region in a plan view.

[0019] In one embodiment of the present invention, the p-type buried layer has a p-type impurity concentration of 1.0×10 16 cm -3 Over 1.0 x 10 18 cm -3 The following is the result.

[0020] In one embodiment of the present invention, a method for fabricating a semiconductor device includes the steps of selectively injecting n-type impurities into a surface of a p-type semiconductor substrate, and then forming a first n-type epitaxial layer on the surface of the p-type semiconductor substrate, thereby forming an n-type buried layer spanning the boundary between the p-type semiconductor substrate and the first n-type epitaxial layer; and selectively injecting p-type impurities into the surface of the first n-type epitaxial layer, and then forming a second n-type epitaxial layer on the surface of the first n-type epitaxial layer, thereby forming an n-type buried layer spanning the boundary between the first n-type epitaxial layer and the first n-type epitaxial layer. The method includes the steps of forming a p-type buried layer between the second n-type epitaxial layers, forming a p-type well layer in a surface portion of the second n-type epitaxial layer and disposed above the p-type buried layer, forming an n-type source contact region in the surface portion of the p-type well layer and having a higher impurity concentration than the second n-type epitaxial layer, and forming an n-type drain contact region in the surface portion of the second n-type epitaxial layer and having a higher impurity concentration than the second n-type epitaxial layer.

[0021] In one embodiment of the present invention, in the step of forming the p-type buried layer, the p-type buried layer is formed only in a surface layer portion of the first n-type epitaxial layer.

[0022] In one embodiment of the present invention, in the step of forming the p-type buried layer, the p-type buried layer is formed across the boundary between the first n-type epitaxial layer and the second n-type epitaxial layer.

[0023] In one embodiment of the present invention, the method further includes the steps of: forming a gate insulating film on a surface of the second n-type epitaxial layer so as to cover a channel region between the source contact region and the drain contact region; and forming a gate electrode on the gate insulating film so as to face the channel region with the gate insulating film interposed therebetween.

[0024] The above and other objects, features and advantages of the present invention will become apparent from the following description of the embodiments with reference to the accompanying drawings. [Brief explanation of the drawings]

[0025] [Figure 1] FIG. 1 is a schematic plan view for explaining the configuration of a semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. [Figure 3] FIG. 3 is a graph showing the calculation results of the Vd-Id characteristics for the comparative example and this embodiment. [Figure 4] FIG. 4 is an equipotential diagram showing the source-drain potential distribution of the comparative example when the drain voltage Vd is 100V. [Figure 5] FIG. 5 is an equipotential diagram showing the potential distribution between the source and drain in this embodiment when the drain voltage Vd is 150V. [Figure 6A] FIG. 6A is a cross-sectional view showing an example of a manufacturing process for the semiconductor device shown in FIGS. 1 and 2, and corresponds to the cross section of FIG. [Figure 6B] FIG. 6B is a cross-sectional view showing the next step of FIG. 6A. [Figure 6C] FIG. 6C is a cross-sectional view showing the step subsequent to FIG. 6B. [Figure 6D] FIG. 6D is a cross-sectional view showing the step subsequent to FIG. 6C. [Figure 6E] FIG. 6E is a cross-sectional view showing the step subsequent to FIG. 6D. [Figure 6F] FIG. 6F is a cross-sectional view showing the step subsequent to FIG. 6E. [Figure 6G] FIG. 6G is a cross-sectional view showing the step subsequent to FIG. 6F. [Figure 6H] FIG. 6H is a cross-sectional view showing the step subsequent to FIG. 6G. [Figure 6I] FIG. 6I is a cross-sectional view showing the step subsequent to FIG. 6H. [Figure 7] FIG. 7 is a schematic cross-sectional view for explaining the configuration of a semiconductor device according to a second embodiment of the present invention. [Figure 8A]8A is a cross-sectional view showing an example of a manufacturing process of the semiconductor device shown in FIG. 7, and is a cross-sectional view corresponding to the cross section of FIG. [Figure 8B] FIG. 8B is a cross-sectional view showing the next step of FIG. 8A. [Figure 8C] FIG. 8C is a cross-sectional view showing the step subsequent to FIG. 8B. [Figure 8D] FIG. 8D is a cross-sectional view showing the step subsequent to FIG. 8C. [Figure 8E] FIG. 8E is a cross-sectional view showing the step subsequent to FIG. 8D. [Figure 8F] FIG. 8F is a cross-sectional view showing the step subsequent to FIG. 8E. [Figure 8G] FIG. 8G is a cross-sectional view showing the step subsequent to FIG. 8F. [Figure 9] FIG. 9 is a schematic diagram for explaining an example of a preferable arrangement (lateral position and depth position) of the p-type buried layer relative to the arrangement of the p-type well region and the n+-type drain contact region. DETAILED DESCRIPTION OF THE INVENTION

[0026] Fig. 1 is a schematic plan view for explaining the configuration of a semiconductor device according to a first embodiment of the present invention. Fig. 2 is a schematic cross-sectional view taken along line II-II in Fig. 1. In Fig. 1, an interlayer insulating film 21, a drain wiring 25, and a source wiring 26 shown in Fig. 2 are omitted.

[0027] In the following description, the left-right direction on the plane of FIG. 1 will be referred to as the horizontal direction, and the up-down direction on the plane of FIG. 1 will be referred to as the vertical direction.

[0028] The semiconductor device 1 includes a base 3. The base 3 includes a p-type semiconductor substrate 4 and an n-type semiconductor layer formed on the p-type semiconductor substrate 4. - In this embodiment, the p-type semiconductor substrate is a silicon substrate. The p-type semiconductor substrate 4 is an example of the "p-type substrate" of the present invention, and includes an n-type epitaxial layer 5. - The n-type epitaxial layer 5 is an example of the "n-type semiconductor layer" of the present invention.

[0029] n - The thickness of the p-type epitaxial layer 5 is, for example, about 3.0 μm to 10 μm. A p-type element isolation region 7 that partitions the element region 2 is formed in the surface layer portion of the base 3. In this embodiment, the element region 2 has a rectangular shape that is elongated in the vertical direction in a plan view. The element region 2 has n - A DMOS transistor 40 is formed using the epitaxial layer 5 as a drain.

[0030] The p-type element isolation region 7 has an endless shape in plan view. In this embodiment, the p-type element isolation region 7 has a rectangular ring shape in plan view, but it may have an endless shape such as a circular ring or an elliptical ring. The p-type element isolation region 7 includes a lower isolation region 8 connected to the p-type semiconductor substrate and an upper isolation region 9 formed on the lower isolation region 8.

[0031] As a result, the base 3 has an n-type semiconductor substrate 4 surrounded by a p-type element isolation region 7. - An element region 2 made of a part of the p-type epitaxial layer 5 is defined in the p-type epitaxial layer 5. Although not shown, the p-type element isolation region 7 and the p-type semiconductor substrate 4 are grounded.

[0032] In the element region 2, a p-type semiconductor substrate 4 and an n - At the boundary of the p-type epitaxial layer 5, the p-type semiconductor substrate 4 and the n-type epitaxial layer 5 are - The n-type epitaxial layer 5 is formed across the n-type epitaxial layer 5. - The n-type epitaxial layer 5 has a higher impurity concentration than the n-type epitaxial layer 5. + A buried layer 6 is selectively formed. + The buried layer 6 is formed in a central region surrounded by the peripheral edge of the element region 2 in plan view. + The thickness of the mold-buried layer 6 is, for example, about 2.0 μm to 10.0 μm.

[0033] In addition, in the base 3, an element region (not shown) in which elements different from the DMOS transistor 40 in the element region 2 are formed is defined in the peripheral region of the element region 2.

[0034] A field insulating film 11 that is endless in plan view is formed on the surface of the p-type element isolation region 7. The field insulating film 11 is formed in a quadrangular ring shape in plan view so as to surround the region surrounded by the peripheral edge of the element region 2. The field insulating film 11 is wider than the p-type element isolation region 7 and is formed so as to completely cover the p-type element isolation region 7. The field insulating film 11 is, for example, - The LOCOS film is formed by selectively oxidizing the surface of the epitaxial layer 5 .

[0035] The DMOS transistor 40 is - The device region 2 includes an n-type drain region 13 and a p-type well region 15 formed at an interval from each other in a surface layer portion of the epitaxial layer 5. In this embodiment, the p-type well region 15 has a rectangular shape that is elongated in the vertical direction in a plan view, and is formed in the center of the device region 2 in the horizontal direction.

[0036] The n-type drain region 13 is - The n-type drain region 13 has a higher impurity concentration than the p-type epitaxial layer 5. The n-type drain region 13 is formed endlessly so as to surround the p-type well region 15 in plan view. In this embodiment, the n-type drain region 13 is formed in a square ring shape along the field insulating film 11 in plan view. The surface layer of the n-type drain region 13 has an n-type epitaxial layer 13 having a higher impurity concentration than the n-type drain region 13. + A type drain contact region 14 is formed.

[0037] The surface layer of the p-type well region 15 is - An n-type source region 16 having a higher impurity concentration than the n-type epitaxial layer 5 is formed in the surface layer of the n-type source region 16. + A source contact region 17 is formed.

[0038] The n-type source region 16 is formed to, for example, the same concentration and the same depth as the n-type drain region 13. +The outer periphery of the n-type source contact region 17 is spaced inward from the outer periphery of the p-type well region 15. + The source contact region 17 is, for example, an n + It is formed to the same concentration and depth as the type drain contact region 14 .

[0039] n - The epitaxial layer 5 has an n-type well region 15 below the p-type well region 15. + type source contact region 17 and n + A p-type buried layer 10 is formed to uniformize the electric field distribution between the n-type well region 15 and the n-type drain contact region 14 (hereinafter referred to as "potential distribution between the source and drain"). In this embodiment, the p-type buried layer 10 is formed below the p-type well region 15 and + The p-type buried layer 10 is disposed above the p-type buried layer 10. In this embodiment, the p-type buried layer 10 is disposed below the p-type well region 15 and spaced apart from the p-type well region 15.

[0040] In this embodiment, the p-type buried layer 10 has a rectangular shape that is long in the vertical direction in plan view. The width of the p-type buried layer 10 is larger than the width of the p-type well region 15, and both sides of the p-type buried layer protrude outward from both sides of the p-type well region 15 in plan view. In this embodiment, the p-type buried layer 10 has an n + The gate electrode 12 is disposed within a region surrounded by the drain contact region 14 .

[0041] The thickness of the p-type buried layer 10 is, for example, about 2.0 μm to 5.0 μm. The p-type impurity concentration of the p-type buried layer 10 is 1.0×10 16 cm -3 Over 1.0 x 10 18 cm -3 In this embodiment, the p-type impurity concentration of the p-type buried layer 10 is preferably 1.0×10 17 cm -3 That's about it.

[0042] n -The surface of the n-type epitaxial layer 5 + A field insulating film 12 having a rectangular ring shape in plan view is formed between the p-type drain contact region 14 and the p-type well region 15. The field insulating film 12 is a LOCOS film formed in the same process as the above-mentioned field insulating film 11. In FIG. 1, the inner peripheral edge of the field insulating film 12 is indicated by the reference symbol 12a.

[0043] The inner periphery 12a of the field insulating film 12 is spaced outward from the outer periphery of the p-type well region 15, and the outer periphery of the field insulating film 12 is + The n-type drain contact region 14 is disposed on the inner periphery thereof. + The type drain contact region 14 is formed in a region sandwiched between the outer periphery of the field insulating film 12 and the inner periphery of the field insulating film 11 .

[0044] Also, n - The surface of the n-type epitaxial layer 5 - A gate insulating film 18 is formed across the n-type epitaxial layer 5 and the p-type well region 15. The gate insulating film 18 has a thickness of 100 nm in plan view. + The gate insulating film 18 is formed in a rectangular ring shape so as to surround the n-type source contact region 17. A gate electrode 19 is formed on the gate insulating film 18. The gate electrode 19 is formed in a rectangular ring shape so as to surround the n-type source region 16 in a plan view. The gate electrode 19 is formed so as to selectively cover a part of the gate insulating film 18 and a part of the field insulating film 12.

[0045] The gate electrode 19 is made of, for example, polysilicon. The gate insulating film 18 is made of, for example, n - The silicon oxide film is formed by oxidizing the surface of the silicon epitaxial layer 5.

[0046] The region where the gate electrode 19 faces the p-type well region 15 via the gate insulating film 18 is the channel region 20 of the DMOS transistor 40. The formation of the channel in the channel region 20 is controlled by the gate electrode 19.

[0047] An interlayer insulating film 21 is formed so as to cover the entire element region 2. The interlayer insulating film 21 is formed of an insulating film such as an oxide film or a nitride film.

[0048] A drain contact plug 22, a source contact plug 23, and a gate contact plug 24 are buried in the interlayer insulating film 21. The lower end of the drain contact plug 22 is + The lower end of the source contact plug 23 is electrically connected to the n-type drain contact region 14. + The gate contact plug is electrically connected to the source contact region 17. The gate contact plug is electrically connected to the gate electrode 19.

[0049] A drain wiring 25, a source wiring 26, and a gate wiring (not shown) are formed on the interlayer insulating film 21. The drain wiring 25 is connected to n-type MOS transistors 21 via a plurality of drain contact plugs 22. + The source wiring 26 is electrically connected to the n-type drain contact region 14 via a plurality of source contact plugs 23. + The gate wiring is electrically connected to the gate electrode 19 via a plurality of gate contact plugs 24.

[0050] Although not shown in FIG. 1, the source wiring 26 has a rectangular shape that is long in the vertical direction in plan view, and covers the intermediate portion of the length between both ends of the gate electrode 19. A plurality of points in the widthwise center of the source wiring 26 are connected to the n-type semiconductor layer 14 via a plurality of source contact plugs 23. + The gate electrode 19 is electrically connected to the source contact region 17. The gate wiring is electrically connected to both ends of the gate electrode 19 via a plurality of gate contact plugs 24.

[0051] The drain wiring 25 is formed in a rectangular ring shape in plan view so as to surround the field insulating film 12. The drain wiring 25 is +The gate electrode 12 is disposed so as to cover the drain contact region 14 .

[0052] In this embodiment, n - In the epitaxial layer 5, the p-type buried layer 10 is formed below the p-type well region 15, so that the potential distribution between the source and the drain can be made uniform, thereby improving the breakdown voltage of the DMOS transistor 40.

[0053] The semiconductor device 1 in FIGS. 1 and 2 will be referred to as "this embodiment," and a configuration in which the p-type buried layer 10 is not formed in the semiconductor device 1 in FIGS. 1 and 2 will be referred to as "comparative example."

[0054] For each of the comparative example and this embodiment, the drain current Id and the source-drain electric field distribution were calculated by simulation when the gate potential, source potential, and substrate potential were set to 0 V and the drain voltage Vd was gradually increased.

[0055] 3 is a graph showing the Vd-Id characteristic calculation results for the comparative example and this embodiment. In FIG. 3, the dashed line shows the Vd-Id characteristic calculation results for the comparative example, and the solid line shows the Vd-Id characteristic calculation results for this embodiment.

[0056] From FIG. 3, it can be seen that the breakdown voltage is about 100 V in the comparative example, whereas it is about 150 V in this embodiment, and that the breakdown voltage is improved in this embodiment compared to the comparative example.

[0057] Fig. 4 is an equipotential diagram showing the potential distribution between the source and drain of the comparative example when the drain voltage Vd is 100 V. Fig. 5 is an equipotential diagram showing the potential distribution between the source and drain of the present embodiment when the drain voltage Vd is 150 V.

[0058] In the comparative example, as shown in FIG. - The equipotential lines extend obliquely to the surface of the n-type epitaxial layer 5. -The electric field distribution between the source and the drain is non-uniform in the surface layer portion of the n-type epitaxial layer 5. + type source contact region 17 and n + In the region between the n-type drain contact region 14 + The spacing between the equipotential lines is narrower in the region on the n-type source contact region 17 side. + A large electric field concentration occurs in the region on the side of the source contact region 17 .

[0059] In contrast, in this embodiment, since the p-type buried layer 10 is formed, the equipotential lines are arranged in a direction parallel to the n + Type source contact region 17 to n + The equipotential lines are expanded toward the n-type drain contact region 14. - In the surface layer portion of the n-type epitaxial layer 5, - The n-type epitaxial layer 5 extends in a direction substantially perpendicular to the surface thereof. - The electric field distribution between the source and the drain becomes more uniform in the surface layer portion of the type epitaxial layer 5. This is thought to result in a significantly higher breakdown voltage in this embodiment than in the comparative example.

[0060] 6A to 6I, a description will be given of a manufacturing process of the semiconductor device 1. Figures 6A to 6I are cross-sectional views for explaining an example of a manufacturing process of the semiconductor device 1, and are cross-sectional views corresponding to the cross section of Figure 2.

[0061] To manufacture the semiconductor device 1, a p-type semiconductor substrate 4 is prepared as shown in Fig. 6A. Next, an n + An n-type impurity for forming the buried layer 6 and a p-type impurity for forming the lower isolation region 8 are selectively implanted. Then, silicon is epitaxially grown on the p-type semiconductor substrate 4 while adding the n-type impurity under a heated condition of, for example, 1100° C. or higher. As a result, as shown in FIG. 6B, an n-type impurity is formed on the p-type semiconductor substrate 4. -A lower layer portion of the n-type epitaxial layer 5 (hereinafter referred to as "epitaxial lower layer portion 5A") is formed. The epitaxial lower layer portion 5A is an example of the "first n-type epitaxial layer" of the present invention.

[0062] During epitaxial growth, the n-type impurities and p-type impurities implanted into the p-type semiconductor substrate 4 diffuse in the growth direction of the epitaxial lower layer 5A. + A p-type buried layer 6 and a p-type lower isolation region 8 are formed. Examples of p-type impurities include B (boron) and Al (aluminum), and examples of n-type impurities include P (phosphorus) and As (arsenic).

[0063] 6C, p-type impurities are selectively implanted into the surface of the epitaxial lower layer 5A to form a p-type buried layer 10. Examples of p-type impurities include boron (B) and aluminum (Al). This forms the p-type buried layer 10 in the epitaxial lower layer 5A.

[0064] Then, for example, under a heated condition of 1100° C. or higher, silicon of the epitaxial lower layer 5A is epitaxially grown while adding n-type impurities. As a result, as shown in FIG. 6D, n-type impurities are formed on the epitaxial lower layer 5A. - The upper layer portion of the epitaxial layer 5 (hereinafter referred to as "epitaxial upper layer portion 5B") is formed. As a result, an n-type epitaxial layer consisting of the epitaxial lower layer portion 5A and the epitaxial upper layer portion 5B is formed. - The p-type epitaxial layer 5 is formed on the p-type semiconductor substrate 4 and the n-type epitaxial layer 5. - The substrate 3 is formed to include the epitaxial upper layer 5B and the n-type epitaxial layer 5. The epitaxial upper layer 5B is an example of the "second n-type epitaxial layer" of the present invention.

[0065] Next, as shown in FIG. 6E, an ion implantation mask (not shown) having selective openings in regions where p-type upper isolation regions 9 are to be formed is implanted into n-type silicon. -The p-type epitaxial layer 5 is then implanted with p-type impurities through the ion implantation mask. - The ions are implanted into the p-type epitaxial layer 5. As a result, the p-type element isolation region 7 is formed, which has a two-layer structure consisting of a lower isolation region 8 and an upper isolation region 9. After this, the ion implantation mask is removed.

[0066] Next, a hard mask 51 having selective openings in regions where the field insulating films 11 and 12 are to be formed is formed on the n - The n-type epitaxial layer 5 is then formed on the n-type epitaxial layer 5 through a hard mask 51. - The surface of the type epitaxial layer 5 is subjected to thermal oxidation treatment to form field insulating films 11 and 12. Thereafter, the hard mask 51 is removed.

[0067] Next, as shown in Figure 6F, - The surface of the type epitaxial layer 5 is subjected to thermal oxidation treatment to form a gate insulating film 18. At this time, the gate insulating film 18 is formed so as to be continuous with the field insulating films 11 and 12. Next, polysilicon for a gate electrode 19 is formed in the n-type epitaxial layer 5. - A polysilicon layer 52 is deposited on the epitaxial layer 5 .

[0068] 6G, a resist mask (not shown) having selective openings in regions where gate electrodes 19 are to be formed is formed on polysilicon layer 52. Then, unnecessary portions of polysilicon layer 52 are removed by etching through the resist mask, thereby forming gate electrodes 19. Thereafter, the resist mask is removed.

[0069] Next, in order to remove unnecessary portions of the gate insulating film 18, a hard mask (not shown) having selective openings is formed on the n - The hard mask is formed on the first epitaxial layer 5. Then, unnecessary portions of the gate insulating film 18 are etched through the hard mask. This forms the desired gate insulating film 18. Thereafter, the hard mask is removed. Note that the step of selectively etching the gate insulating film 18 may be omitted.

[0070] Next, as shown in Figure 6H, - A p-type well region 15 is formed in the surface layer of the n-type epitaxial layer 5. To form the p-type well region 15, first, an ion implantation mask (not shown) having openings selectively in the region where the p-type well region 15 is to be formed is formed. Then, p-type impurities are implanted through the ion implantation mask. - The p-type impurities are then implanted into the p-type epitaxial layer 5. Thereafter, the p-type impurities are thermally diffused at a temperature of, for example, 900°C to 1100°C, thereby forming the p-type well region 15. Thereafter, the ion implantation mask is removed. By setting the thermal diffusion temperature to a relatively low value and / or by setting the thermal diffusion time to a relatively short value, it is possible to prevent the p-type well region 15 from spreading into the epitaxial upper layer portion 5B.

[0071] Before the gate insulating film 18 and the gate electrode 19 are formed (FIG. 6E), the p-type impurity is introduced into the n - The p-type well region 15 may be formed by selectively implanting the p-type epitaxial layer 5 .

[0072] Next, n - An n-type drain region 13 is formed in the surface layer portion of the p-type epitaxial layer 5, and at the same time, an n-type source region 16 is formed in the inner region (surface layer portion) of the p-type well region 15. To form the n-type drain region 13 and the n-type source region 16, first, an ion implantation mask (not shown) having openings selectively in the region where the n-type drain region 13 and the n-type source region 16 are to be formed is formed. Then, n-type impurities are implanted through the ion implantation mask to form n - The ions are implanted into the n-type epitaxial layer 5. This forms the n-type drain region 13 and the n-type source region 16. After this, the ion implantation mask is removed.

[0073] Next, the n-type drain region 13 and the n-type source region 16 are respectively provided with n + type drain contact region 14 and n +The n-type source contact regions 17 are selectively formed. + type drain contact region 14 and n + To form the n-type source contact region 17, first + type drain contact region 14 and n + An ion implantation mask (not shown) having selective openings in the regions where the n-type source contact regions 17 are to be formed is formed. Then, n-type impurities are implanted into the n-type drain region 13 and the n-type source region 16 through the ion implantation mask. + type drain contact region 14 and n + The source contact regions 17 are formed, after which the ion implantation mask is removed.

[0074] Next, as shown in FIG. 6I, an insulating material is deposited to cover the gate electrode 19, thereby forming an interlayer insulating film 21. Next, a drain contact plug 22, a source contact plug 23, and a gate contact plug 24 are formed so as to penetrate the interlayer insulating film 21. The drain contact plug 22, the source contact plug 23, and the gate contact plug 24 are each formed of n + n-type drain contact region 14 + The gate electrode 19 is electrically connected to the source contact region 17 .

[0075] Finally, drain wiring 25, source wiring 26, and gate wiring (not shown), which are electrically connected to drain contact plug 22, source contact plug 23, and gate contact plug 24, respectively, are selectively formed on interlayer insulating film 21. To form drain wiring 25, source wiring 26, and gate wiring, for example, a wiring material layer is formed on interlayer insulating film 21. Then, by selectively removing the wiring material layer by photolithography and etching, drain wiring 25, source wiring 26, and gate wiring are formed. Through the above steps, the semiconductor device 1 according to the first embodiment is manufactured.

[0076] Next, a semiconductor device 1A according to a second embodiment of the present invention will be described with reference to Fig. 7. Fig. 7 is a schematic cross-sectional view for explaining the configuration of a semiconductor device according to the second embodiment of the present invention, and is a cross-sectional view corresponding to the cut surface of Fig. 2. In Fig. 7, parts corresponding to parts in the above-described Fig. 2 are denoted by the same reference numerals as in Fig. 2.

[0077] The plan view of the semiconductor device 1A according to the second embodiment is similar to the plan view of the semiconductor device 1 according to the first embodiment (FIG. 1).

[0078] The semiconductor device 1A according to the second embodiment differs from the semiconductor device 1 according to the first embodiment in that the p-type buried layer 10 is connected to the p-type well region 15 below the p-type well region 15.

[0079] More specifically, the p-type buried layer 10 in the second embodiment is formed to be thicker than the p-type buried layer 10 in the first embodiment. The lower part of the p-type well region 15 in the second embodiment is connected to the upper part of the p-type buried layer 10.

[0080] The method for manufacturing the semiconductor device 1A according to the second embodiment is substantially the same as the method for manufacturing the semiconductor device 1A according to the first embodiment described with reference to Figures 6A to 6I. However, the steps from Figure 6E onwards, which are performed after the p-type impurities for forming the p-type buried layer 10 are selectively implanted into the surface of the epitaxial lower layer portion 5A in Figure 6C, are slightly different.

[0081] 6E to 6G, the p-type impurity implanted into the epitaxial lower layer 5A diffuses in the growth direction of the epitaxial upper layer 5B by increasing the temperature and time of the thermal diffusion performed in the steps of Figures 6E to 6G or by adding a new thermal diffusion. As a result, the p-type buried layer 10 is formed so as to straddle the boundary between the epitaxial lower layer 5A and the epitaxial upper layer 5B.

[0082] In the step of FIG. 6H, n -When the p-type well region 15 is formed in the surface layer portion of the p-type epitaxial layer 5, the lower portion of the p-type well region 15 is connected to the upper portion of the p-type buried layer .

[0083] The semiconductor device 1A according to the second embodiment can also be manufactured by another manufacturing method as shown in Figures 8A to 8H, which are cross-sectional views corresponding to the cross-section of Figure 2.

[0084] First, as shown in FIG. 8A, a p-type semiconductor substrate 4 is prepared. Next, n + An n-type impurity for forming the buried layer 6 and a p-type impurity for forming the lower isolation region 8 are selectively implanted.

[0085] Then, silicon is epitaxially grown on the p-type semiconductor substrate 4 while adding n-type impurities under a heated condition of, for example, 1100° C. or higher. As a result, the p-type semiconductor substrate 4 and the n-type semiconductor substrate 4 are separated as shown in FIG. - A substrate 3 is formed that includes a silicon-doped epitaxial layer 5 .

[0086] During the epitaxial growth of the p-type semiconductor substrate 4, the n-type impurities and p-type impurities implanted into the p-type semiconductor substrate 4 are n - The n-type epitaxial layer 5 is then diffused in the growth direction of the p-type semiconductor substrate 4. - The n-type epitaxial layer 5 straddles the boundary + A p-type buried layer 6 and a p-type lower isolation region 8 are formed. Examples of p-type impurities include B (boron) and Al (aluminum), and examples of n-type impurities include P (phosphorus) and As (arsenic).

[0087] Next, as shown in FIG. 8C, an ion implantation mask (not shown) having selective openings in regions where p-type upper isolation regions 9 are to be formed is implanted onto the n-type silicon substrate. - The p-type epitaxial layer 5 is then implanted with p-type impurities through the ion implantation mask. -The ions are implanted into the p-type epitaxial layer 5. As a result, the p-type element isolation region 7 is formed, which has a two-layer structure consisting of a lower isolation region 8 and an upper isolation region 9. After this, the ion implantation mask is removed.

[0088] Next, a hard mask 51 having selective openings in regions where the field insulating films 11 and 12 are to be formed is formed on the n - The n-type epitaxial layer 5 is then formed on the n-type epitaxial layer 5 through a hard mask 51. - The surface of the type epitaxial layer 5 is subjected to thermal oxidation treatment to form field insulating films 11 and 12. Thereafter, the hard mask 51 is removed.

[0089] Next, as shown in Figure 8D, - The surface of the type epitaxial layer 5 is subjected to thermal oxidation treatment to form a gate insulating film 18. At this time, the gate insulating film 18 is formed so as to be continuous with the field insulating films 11 and 12. Next, polysilicon for a gate electrode 19 is formed in the n-type epitaxial layer 5. - A polysilicon layer 52 is deposited on the epitaxial layer 5 .

[0090] 8E, a resist mask (not shown) having selective openings in regions where gate electrodes 19 are to be formed is formed on polysilicon layer 52. Then, unnecessary portions of polysilicon layer 52 are removed by etching through the resist mask, thereby forming gate electrodes 19. Thereafter, the resist mask is removed.

[0091] Next, in order to remove unnecessary portions of the gate insulating film 18, a hard mask (not shown) having selective openings is formed on the n - The hard mask is formed on the first epitaxial layer 5. Then, unnecessary portions of the gate insulating film 18 are etched through the hard mask. This forms the desired gate insulating film 18. Thereafter, the hard mask is removed. Note that the step of selectively etching the gate insulating film 18 may be omitted.

[0092] Next, as shown in Figure 8F, -A p-type buried layer 10 and a p-type well region 15 are formed in the n-type epitaxial layer 5. To form the p-type buried layer 10 and the p-type well region 15, first, an ion implantation mask (not shown) having openings selectively in the region where the p-type well region 15 is to be formed is formed. Then, p-type impurities are implanted through the ion implantation mask to form n-type well regions. - The n-type epitaxial layer 5 is then implanted by heat treatment. - A p-type well region 15 is formed in the surface layer portion of the p-type epitaxial layer 5, and a wide p-type buried layer 10 is formed below the p-type well region 15, extending outward from the p-type well region 15. After this, the ion implantation mask is removed.

[0093] Next, n - An n-type drain region 13 is formed in the surface layer portion of the p-type epitaxial layer 5, and at the same time, an n-type source region 16 is formed in the inner region (surface layer portion) of the p-type well region 15. To form the n-type drain region 13 and the n-type source region 16, first, an ion implantation mask (not shown) having openings selectively in the region where the n-type drain region 13 and the n-type source region 16 are to be formed is formed. Then, n-type impurities are implanted through the ion implantation mask to form n - The ions are implanted into the n-type epitaxial layer 5. This forms the n-type drain region 13 and the n-type source region 16. After this, the ion implantation mask is removed.

[0094] Next, the n-type drain region 13 and the n-type source region 16 are respectively provided with n + type drain contact region 14 and n + The n-type source contact regions 17 are selectively formed. + type drain contact region 14 and n + To form the n-type source contact region 17, first + type drain contact region 14 and n +An ion implantation mask (not shown) having selective openings in the regions where the n-type source contact regions 17 are to be formed is formed. Then, n-type impurities are implanted into the n-type drain region 13 and the n-type source region 16 through the ion implantation mask. + type drain contact region 14 and n + The source contact regions 17 are formed, after which the ion implantation mask is removed.

[0095] Next, as shown in FIG. 8G, an insulating material is deposited to cover the gate electrode 19, thereby forming an interlayer insulating film 21. Next, a drain contact plug 22, a source contact plug 23, and a gate contact plug 24 are formed so as to penetrate the interlayer insulating film 21. The drain contact plug 22, the source contact plug 23, and the gate contact plug 24 are each formed of n + n-type drain contact region 14 + The gate electrode 19 is electrically connected to the source contact region 17 and the gate electrode 19, respectively.

[0096] Finally, drain wiring 25, source wiring 26, and gate wiring (not shown), which are electrically connected to drain contact plug 22, source contact plug 23, and gate contact plug 24, respectively, are selectively formed on interlayer insulating film 21. To form drain wiring 25, source wiring 26, and gate wiring, for example, a wiring material layer is formed on interlayer insulating film 21. Then, by selectively removing the wiring material layer by photolithography and etching, drain wiring 25, source wiring 26, and gate wiring are formed. Through the above steps, semiconductor device 1A according to the second embodiment is manufactured.

[0097] FIG. 9 shows the p-type well region 15 and the n + 1 is a schematic diagram for explaining an example of a preferable arrangement (lateral position and depth position) of the p-type buried layer 10 relative to the arrangement of the p-type drain contact region 14. FIG.

[0098] As mentioned above, n - In the surface portion of the epitaxial layer 5, the equipotential lines between the source and drain are - When the direction is nearly perpendicular to the surface of the epitaxial layer 5, the electric field distribution between the source and drain tends to become uniform.

[0099] The equipotential line between the source and drain is n - In order to make the p-type buried layer 10 substantially perpendicular to the surface of the p-type epitaxial layer 5, it is preferable that both ends of the p-type buried layer 10 are located at the following positions: That is, referring to FIG. + The distance to the width center of the type drain contact region 14 is defined as r1.

[0100] As shown in FIG. 9, one side edge of the p-type buried layer corresponding to the one side edge of the p-type well region 15 is formed in a vertical cross section along the lateral direction, as shown in FIG. 9A or 9B. + It is preferable that the contact region 14 is disposed so as to be in contact with a circle having a radius r1 and centered at the width center of the contact region 14.

[0101] Although not shown, the same applies to the other side edge of the p-type buried layer 10. That is, the other side edge of the p-type well region 15 and the outer n + The distance to the width center of the p-type drain contact region 14 is r2. The other side edge of the p-type buried layer 10 is + It is preferable that the contact region 14 is disposed so as to be tangent to a circle of radius r2 centered on the width center of the contact region 14. Note that radius r1 is approximately equal to radius r2.

[0102] Although the first and second embodiments of the present invention have been described above, the present invention can also be embodied in other embodiments. - Only one p-type buried layer 10 is formed in the n-type epitaxial layer 5. - Two or more p-type buried layers 10 are formed in the n-type epitaxial layer 5.- The p-type buried layer 10A and the p-type buried layer 10B may be disposed at intervals in the thickness direction of the p-type epitaxial layer 5. In this case, for example, as shown in FIG. - The epitaxial layer 5 may be formed on the substrate.

[0103] Although the embodiments of the present invention have been described in detail, these are merely examples used to clarify the technical contents of the present invention, and the present invention should not be construed as being limited to these examples, and the scope of the present invention is limited only by the appended claims.

[0104] This application corresponds to Patent Application No. 2020-44369 filed with the Japan Patent Office on March 13, 2020, the entire disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0105] 1,1A Semiconductor Device 2. Element area 3 Base 4 p-type semiconductor substrate 5n - Type epitaxial layer 6n + Mold-embedding layer 7 p-type element isolation region 8 Lower separation area 9 Upper separation area 10 p-type buried layer 11 Field insulating film 12 Field insulating film 13 n-type drain region 14n + Type drain contact region 15 p-type well region 16 n-type source region 17n + Source contact region 18 Gate insulating film 19 Gate electrode 20 channel region 21 Interlayer insulating film 22 Drain contact plug 23 Source contact plug 24 Gate contact plug 25 Drain wiring 26 Source wiring 30 Device termination area 40 DMOS transistors 51 Hard Mask 52 Polysilicon layer

Claims

1. a p-type substrate; an n-type semiconductor layer formed on the p-type substrate; a transistor having the n-type semiconductor layer as a drain, the transistor is formed in a surface layer portion of the n-type semiconductor layer, has an n-type source contact region in the surface layer portion, and includes: a p-type well region extending in a first direction along the surface layer portion of the n-type semiconductor layer; and an n-type drain contact region formed in the surface layer portion of the n-type semiconductor layer and arranged at a distance from the p-type well region in a second direction that is a direction along the surface layer portion of the n-type semiconductor layer and perpendicular to the first direction; a p-type buried layer is formed in the n-type semiconductor layer below the p-type well region, a semiconductor device in which, when the second direction distance between the center of length in the second direction of the n-type drain contact region and a side edge of the p-type well region on the n-type drain contact region side is r1, a side edge of the p-type buried layer corresponding to the side edge of the p-type well region is arranged so as to be tangent to a circle of radius r1 centered on the center of length in the second direction of the n-type drain contact region in a vertical cross section along the second direction.

2. 2. The semiconductor device according to claim 1, further comprising an n-type buried layer formed at the boundary between said p-type substrate and said n-type semiconductor layer, said n-type buried layer having a higher impurity concentration than said n-type semiconductor layer.

3. The width of the p-type buried layer is larger than the width of the p-type well region, and in a plan view, 3. The semiconductor device according to claim 1, wherein both sides of said p-type buried layer protrude outward from both sides of said p-type well region.

4. 4. The semiconductor device according to claim 1, wherein the p-type buried layer is disposed apart from the p-type well region.

5. 4. The semiconductor device according to claim 1, wherein the p-type buried layer is connected to the p-type well region.

6. 4. The semiconductor device according to claim 1, wherein said p-type buried layer includes a plurality of p-type buried layers arranged at intervals in the vertical direction.

7. The transistor is an n-type source region formed in a surface layer portion of the p-type well region and having a higher n-type impurity concentration than the n-type semiconductor layer; the n-type source contact region is formed in a surface layer portion of the n-type source region and has a higher n-type impurity concentration than the n-type source region; an n-type drain region that is spaced apart from the p-type well region and has a higher n-type impurity concentration than the n-type semiconductor layer; 7. The semiconductor device according to claim 1, further comprising: an n-type drain contact region formed in a surface layer portion of said n-type drain region, said n-type drain contact region having a higher n-type impurity concentration than said n-type drain region.

8. The transistor is a gate insulating film formed to cover a channel region between the n-type source contact region and the n-type drain contact region; 8. The semiconductor device according to claim 7, further comprising a gate electrode formed on said gate insulating film and facing said channel region via said gate insulating film.

9. a source wiring electrically connected to the n-type source contact region; 9. The semiconductor device according to claim 8, further comprising: a drain wiring electrically connected to said n-type drain contact region.

10. 10. The semiconductor device according to claim 7, wherein the n-type drain region and the n-type drain contact region are formed endlessly so as to surround the p-type well region in a plan view.

11. The semiconductor device according to claim 10 , wherein the p-type buried layer is disposed in a region surrounded by the n-type drain contact region in a plan view.

12. The p-type impurity concentration of the p-type buried layer is 1.0×10 １６ cm －３ Above 1.0 x 10 １８ cm －３ The semiconductor device according to any one of claims 1 to 11, wherein:

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