Vertical bipolar transistor and manufacturing method thereof

Abstract

To provide a GaN vertical bipolar transistor.SOLUTION: A vertical bipolar transistor includes an n-type first GaN layer, a p-type second GaN layer disposed on the top face of the first GaN layer, an n-type third GaN layer disposed on the top face of the second GaN layer, and a p-type fourth GaN layer disposed on the top face of the third GaN layer. The vertical bipolar transistor includes a first electrode disposed on a lower side of the first GaN layer, a second electrode disposed on the top face of the third GaN layer, and a third electrode disposed on the top face of the fourth GaN layer. Light can be emitted from an interface between the third GaN layer and the fourth GaN layer by applying a voltage between the second electrode and the third electrode. In response to the interface emitting light, a current path can be formed between the first electrode and the second electrode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a vertical bipolar transistor and a manufacturing method thereof. [Background technology]

[0002] GaN (gallium nitride) has excellent properties such as high breakdown voltage, high mobility, and high saturated drift velocity. Therefore, it is expected to be a semiconductor for creating next-generation vertical power devices. Related technology is disclosed in Patent Document 1. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 4465890 specification Summary of the Invention [Problem to be solved by the invention]

[0004] A p-type electrode that contacts p-type GaN may be formed on the current path of a power device. In this case, a high-concentration p-type region must be formed at the contact interface between the p-type GaN and the electrode. However, the technology for forming a high-concentration p-type region by ion implantation has not yet been established. Furthermore, when a high-concentration p-type region is formed by regrowth, the interface resistance increases due to concentration limitations and the pile-up of donor impurities such as Si at the interface. This results in high contact resistance of the p-type electrode. This results in a high-resistance p-type electrode being present on the current path of a large current, making it difficult to fabricate a power device. [Means for solving the problem]

[0005] One embodiment of a vertical bipolar transistor disclosed herein includes a first n-type GaN layer. The vertical bipolar transistor includes a second p-type GaN layer disposed on an upper surface of the first GaN layer. The vertical bipolar transistor includes a third n-type GaN layer disposed on an upper surface of the second GaN layer. The vertical bipolar transistor includes a fourth p-type GaN layer disposed on an upper surface of the third GaN layer. The vertical bipolar transistor includes a first electrode disposed below the first GaN layer. The vertical bipolar transistor includes a second electrode disposed on an upper surface of the third GaN layer. The vertical bipolar transistor includes a third electrode disposed on an upper surface of the fourth GaN layer. The vertical bipolar transistor is configured to be capable of emitting light at the interface between the third GaN layer and the fourth GaN layer by applying a voltage between the second electrode and the third electrode. In response to the interface emitting light, a current path is formed between the first electrode and the second electrode.

[0006] By emitting light at the interface between the third GaN layer and the fourth GaN layer, light can be irradiated onto the pn junction between the second GaN layer and the third GaN layer. This allows a photocurrent to flow from the second GaN layer to the third GaN layer. This photocurrent functions as the base current of a bipolar transistor, forming a current path for the amplified current between the first electrode and the second electrode. Therefore, since the base current can be caused to flow by the photocurrent, a p-type electrode for passing the base current to the second GaN layer is not required. This makes it possible to realize a configuration in which a p-type electrode is not connected to the first to third GaN layers, which form the current path.

[0007] The vertical bipolar transistor may further include a light-absorbing layer having a ternary alloy of GaN disposed at the interface between the second GaN layer and the third GaN layer. The vertical bipolar transistor may further include a light-emitting layer having a ternary alloy of GaN disposed at the interface between the third GaN layer and the fourth GaN layer. Details of the effects will be described in the examples.

[0008] The peak wavelength of the light emitted from the light emitting layer may be a wavelength that is transmitted through the third GaN layer and absorbed by the light emitting layer. Details of the effects will be described in the examples.

[0009] The peak wavelength may be within the range of 365 to 380 nm. Details of the effects will be explained in the examples.

[0010] The impurity concentration of the third GaN layer may be higher on the lower side than on the upper side. Details of the effect will be described in the examples.

[0011] There may be no electrode in contact with the second GaN layer.

[0012] The vertical bipolar transistor may have a specific region on the top surface of the third GaN layer where the fourth GaN layer is not disposed, and a second electrode may be disposed on the top surface of the third GaN layer in the specific region.

[0013] One embodiment of a method for manufacturing a vertical bipolar transistor disclosed herein includes a first growth step of epitaxially growing a p-type second GaN layer on the top surface of an n-type first GaN layer. The manufacturing method includes a second growth step of epitaxially growing an n-type third GaN layer on the top surface of the second GaN layer. The manufacturing method includes a third growth step of epitaxially growing a p-type fourth GaN layer on the top surface of the third GaN layer. The manufacturing method includes a removal step of removing a portion of the fourth GaN layer to expose the third GaN layer. The manufacturing method includes a step of forming a first electrode below the first GaN layer. The manufacturing method includes a step of forming a second electrode on the top surface of the third GaN layer exposed by the removal step. The manufacturing method includes a step of forming a third electrode on the top surface of the fourth GaN layer. Details of the effects will be described in the examples.

[0014] The manufacturing method may further include a step of epitaxially growing a light absorbing layer having a ternary mixed crystal of GaN, which is performed between the first and second growth steps. The manufacturing method may further include a step of epitaxially growing a light emitting layer having a ternary mixed crystal of GaN, which is performed between the second and third growth steps. Details of the effects will be described in the examples.

[0015] In the second growth step, the third GaN layer may be epitaxially grown so that the impurity concentration is higher on the lower side than on the upper side. Details of the effects will be described in the examples. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device 1. FIG. [Figure 2] FIG. 2 is a top view of the semiconductor device 1. [Figure 3] 1 is a cross-sectional schematic diagram of a GaN npn bipolar transistor 100. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0017] (Structure of semiconductor device 1) FIG. 1 shows a schematic cross-sectional view of semiconductor device 1. FIG. 2 shows a top view of semiconductor device 1. FIG. 1 is a cross-sectional view taken along line II in FIG. 2. Semiconductor device 1 is a vertical npn bipolar transistor fabricated using a GaN substrate. It is also a power transistor capable of handling high voltages and large currents. Semiconductor device 1 includes a support substrate 10, a first GaN layer 11, a second GaN layer 12, a third GaN layer 13, a fourth GaN layer 14, a light absorption layer 21, a light emitting layer 22, a first electrode 31, a second electrode 32, and a third electrode 33.

[0018] The support substrate 10 is an n-type freestanding GaN substrate. An n-type first GaN layer 11 is disposed on the upper surface of the support substrate 10. The n-type impurity concentration of the first GaN layer 11 is 1×10 16 (cm -3) or less. This allows the breakdown voltage of the semiconductor device 1 to be about 1200 V. In this example, the thickness of the first GaN layer 11 is 10 μm, and the impurity concentration is 1 to 2×10 16 (cm -3 ) was decided.

[0019] A p-type second GaN layer 12 is disposed on the upper surface of the first GaN layer 11. In this example, the thickness of the second GaN layer 12 is set to 100 to 500 nm, and the impurity concentration is set to 1 to 5×10 17 (cm -3 ) was decided.

[0020] The upper surface of the second GaN layer 12 is provided with p-type In x Ga 1-x An N light absorbing layer 21 is disposed on the interface between the second GaN layer 12 and the third GaN layer 13. In this example, the thickness of the light absorbing layer 21 is set to 10 to 100 nm.

[0021] In, a ternary alloy of GaN x Ga 1-x By changing the composition x, N can obtain any optical absorption edge wavelength between 365 nm and 1900 nm. When the composition x is 0, the material becomes GaN, so the band gap is 3.4 eV and the optical absorption edge wavelength is 365 nm. As the composition x increases, the band gap can be narrowed and the optical absorption edge wavelength can be lengthened. In this example, the composition x was determined so that the optical absorption edge wavelength was within the range of 365 to 380 nm. For example, the composition x was adjusted within the range of 0.01 to 0.03.

[0022] An n-type third GaN layer 13 is disposed on the upper surface of the light absorbing layer 21. The third GaN layer 13 includes an upper layer 13U and a lower layer 13L. The lower layer 13L has a higher impurity concentration than the upper layer 13U. In this example, the impurity concentration of the lower layer 13L is 1×10 19 ~10 20 (cm -3 The impurity concentration of the upper layer 13U was set to an arbitrary value lower than the impurity concentration of the lower layer 13L.

[0023] The upper surface of the third GaN layer 13 is provided with a p-type In x Ga 1-x An N light emitting layer 22 is disposed on the interface between the third GaN layer 13 and the fourth GaN layer 14. The light absorbing layer 21 is a so-called InGaN quantum well. In this example, the thickness of the light emitting layer 22 was set to 10 to 100 nm.

[0024] In x Ga 1-x By changing the composition x, N can emit light at any peak wavelength between 365 nm and 1900 nm. When the composition x is 0, the material becomes GaN, so the band gap is 3.4 eV and the peak wavelength is 365 nm. The larger the composition x, the longer the peak wavelength can be. In this example, the composition x was determined so that the peak wavelength was in the range of 365 to 380 nm. For example, the composition x was adjusted in the range of 0.01 to 0.03.

[0025] A p-type fourth GaN layer 14 is disposed on the upper surface of the light emitting layer 22. In this example, the impurity concentration of the fourth GaN layer 14 is 1×10 20 (cm -3 ) was decided.

[0026] A first electrode 31 is disposed on the lower surface of the support substrate 10. A specific region SR is formed on the upper surface of the third GaN layer 13, where the fourth GaN layer 14 is not disposed. A lower layer 13L of the third GaN layer 13 is exposed in the specific region SR. A second electrode 32 is disposed on the upper surface of the exposed lower layer 13L. A third electrode 33 is disposed on the upper surface of the fourth GaN layer 14.

[0027] 2, the fourth GaN layer 14 is formed in a circular shape. A third electrode 33 is disposed on the entire surface of the fourth GaN layer 14. The second electrode 32 has a ring shape that surrounds the periphery of the fourth GaN layer 14.

[0028] (Functions of semiconductor device 1) The semiconductor device 1 has the functions of an integrated phototransistor PT and a light-emitting diode LED. A more detailed description follows. A vertical phototransistor PT is configured with a first electrode 31, a support substrate 10, a first GaN layer 11, a second GaN layer 12, a light-absorbing layer 21, a third GaN layer 13, and a second electrode 32. Specifically, the first GaN layer 11 functions as the collector, the second GaN layer 12 functions as the base, and the third GaN layer 13 functions as the emitter. The first electrode 31 functions as the collector electrode, and the second electrode 32 functions as the emitter electrode. Since no electrode is in contact with the second GaN layer 12, there is no base electrode.

[0029] Furthermore, a light-emitting diode LED is configured by the third GaN layer 13, the second electrode 32, the light-emitting layer 22, the fourth GaN layer 14, and the third electrode 33. Specifically, the third electrode 33 functions as an anode electrode, and the second electrode 32 functions as a cathode electrode.

[0030] (Operation of the semiconductor device 1) The second electrode 32, which functions as an emitter electrode and a cathode electrode, is grounded. A positive high voltage is applied to the first electrode 31, which functions as a collector electrode. A control signal is input from a control unit (not shown) to the third electrode 33, which functions as an anode electrode.

[0031] To turn on semiconductor device 1, a control signal having a positive voltage equal to or greater than the threshold voltage is applied to third electrode 33. Light-emitting layer 22 disposed at the interface between third GaN layer 13 and fourth GaN layer 14 emits light, and the light is absorbed by light-absorbing layer 21 (see arrow A1). As photocurrent flows from second GaN layer 12 to third GaN layer 13, a current path CP for the amplified current is formed from first electrode 31 to second electrode 32.

[0032] On the other hand, to turn off the semiconductor device 1, a control signal of 0 V is applied to the third electrode 33. Since the light-emitting layer 22 stops emitting light, the current path CP from the first electrode 31 to the second electrode 32 is cut off.

[0033] (effect) The following describes the challenges. There is a demand for power transistors using GaN that can handle high voltages and large currents. However, forming a p-type electrode in contact with p-type GaN is extremely difficult. This is because a highly concentrated p-type region must be formed at the interface between the p-type GaN and the electrode, but technology for forming such a region by ion implantation has not yet been established. Furthermore, forming a highly concentrated p-type region by regrowth is problematic due to concentration limitations and the accumulation of donor impurities such as Si at the interface, resulting in high interface resistance. For example, to operate the GaN npn bipolar transistor 100 shown in Figure 3, a base electrode (p-type electrode) is required to pass current from the base layer to the emitter layer. However, as mentioned above, it is difficult to form a low-resistance p-type electrode in GaN, making it difficult to realize the bipolar transistor 100 shown in Figure 3. Therefore, in the semiconductor device 1 (Figure 1) described herein, a configuration is adopted in which a phototransistor PT fabricated using GaN is used as a power transistor rather than as a photodetector. By making the light-emitting layer 22 emit light and irradiating the light-absorbing layer 21 with light, a photocurrent can flow from the second GaN layer 12 to the third GaN layer 13. This photocurrent functions as the base current of the bipolar transistor, forming a current path CP for an amplified current between the first electrode 31 and the second electrode 32, thereby turning on the semiconductor device 1. Because the base current can be caused by the photocurrent, a base electrode (p-type electrode) in contact with the second GaN layer 12 is not required. This makes it possible to realize a structure in which the first GaN layer 11 to the third GaN layer 13 constituting the phototransistor PT do not have a p-type electrode. Note that the third electrode 33 is a p-type electrode and has high resistance. However, since the third electrode 33 is an electrode provided in the light-emitting diode LED and does not carry a large current, this does not pose a functional problem.

[0034] In the semiconductor device 1 of this specification, the phototransistor PT and the light-emitting diode LED are integrated into one structure by sharing the third GaN layer 13 and the second electrode 32 between them. This allows for a smaller and less expensive device compared to a structure in which the two are fabricated separately and then combined.

[0035] In the semiconductor device 1 of this specification, the impurity concentration of the third GaN layer 13 is higher in the lower layer 13L than in the upper layer 13U. This allows a pn junction to be formed using the lower-concentration upper layer 13U in the light-emitting diode LED. The depletion layer can be expanded to increase the light-emitting efficiency. Furthermore, in the phototransistor PT, the second electrode 32 can be formed in the lower layer 13L with a higher concentration. This allows the contact resistance of the second electrode 32, which functions as an emitter electrode, to be reduced, thereby reducing the on-resistance of the phototransistor PT.

[0036] The semiconductor device 1 of this specification has a structure in which a third GaN layer 13 made of GaN is disposed between a light emitting layer 22 and a light absorbing layer 21 made of InGaN. InGaN has a narrower bandgap than GaN, and therefore can have a longer emission peak wavelength and light absorption edge wavelength than GaN. Therefore, light with a peak wavelength equal to or greater than the light absorption edge wavelength (365 nm) of the third GaN layer 13 can be emitted from the light emitting layer 22, transmitted through the third GaN layer 13, and absorbed by the light absorbing layer 21. Since the attenuation of photons emitted from the light emitting layer 22 in the third GaN layer 13 can be suppressed, the efficiency of light absorption in the light absorbing layer 21 can be increased.

[0037] The light emitting layer 22 and the light absorbing layer 21 are made of In. x Ga 1-xThe larger the composition x of N, the smaller the bandgap (the longer the wavelength). However, the larger the composition x, the greater the lattice mismatch with GaN, and the more crystal defects there are. As a result, the characteristics of the power transistor deteriorate. In the semiconductor device 1 of this specification, the emission peak wavelength of the light emitting layer 22 and the light absorption edge wavelength of the light absorbing layer 21 are set to the range of 365 to 380 nm. The composition x required to achieve this range is very small, about 0.01 to 0.03. This makes it possible to increase the efficiency of light absorption in the light absorbing layer 21 while suppressing crystal defects.

[0038] The semiconductor device 1 of this specification has a structure in which the light emitting layer 22 and the light absorbing layer 21 are sandwiched between the first electrode 31 and the third electrode 33. This allows light emitted upward from the light emitting layer 22 (in the +z direction) to be reflected by the third electrode 33 and absorbed by the light absorbing layer 21. Furthermore, light that passes downward through the light absorbing layer 21 (in the -z direction) can be reflected by the first electrode 31 and absorbed by the light absorbing layer 21. By confining light in the vertical direction, the light absorption efficiency can be increased, making it possible to turn on the semiconductor device 1 with a smaller amount of light.

[0039] (Method of manufacturing semiconductor device 1) First, a support substrate 10 is prepared. On the upper surface of the support substrate 10, an n-type first GaN layer 11, a p-type second GaN layer 12, and a p-type In x Ga 1-x an N light absorption layer 21; a lower layer 13L and an upper layer 13U of an n-type third GaN layer 13; x Ga 1-x The n-type light-emitting layer 22 and the p-type fourth GaN layer 14 are epitaxially grown in this order. Various methods can be used for epitaxial growth. In this example, the MOCVD method was used. The n-type first GaN layer 11 to the p-type fourth GaN layer 14 may be grown continuously. Alternatively, the p-type GaN layer may be removed from the growth apparatus and annealed midway to remove hydrogen from the p-type GaN layer.

[0040] Using known photolithography techniques, a mask with openings corresponding to the specific regions SR is formed on the surface of the fourth GaN layer 14. As shown in FIG. 2, the mask openings are formed in areas other than the circular fourth GaN layer 14. Using known dry etching techniques, the fourth GaN layer 14 and upper layer 13U in the specific regions SR are removed, thereby exposing the lower layer 13L of the third GaN layer 13.

[0041] A second electrode 32 is formed on the upper surface of the exposed lower layer 13L. A third electrode 33 is formed on the upper surface of the fourth GaN layer 14. A first electrode 31 is formed on the lower surface of the support substrate 10. The materials and structures of the first electrode 31 to the third electrode 33 are not particularly limited and may vary. In this way, the semiconductor device 1 shown in FIG. 1 is completed.

[0042] Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. Furthermore, the technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives itself has technical utility.

[0043] (Variation) The technology of this specification is applicable not only to GaN but also to various other semiconductors. For example, the semiconductor device 1 may be formed using SiC or Ga2O3.

[0044] Although the case where InGaN is used as the ternary mixed crystal of GaN has been described, the present invention is not limited to this. For example, the light absorption layer 21 and the light emission layer 22 may be formed using AlGaN.

[0045] Although the present invention has been described with reference to an integrated structure of a phototransistor and a light-emitting diode, the present invention is not limited to this. A separately manufactured light-emitting diode or laser element may be disposed on the upper surface of third GaN layer 13, which functions as an emitter. Alternatively, a separately manufactured light-emitting diode or laser element may be connected to third GaN layer 13 via an optical fiber or optical waveguide, and light may be emitted.

[0046] Although the light absorption layer 21 and the light emitting layer 22 are single layers in the above description, they are not limited to this configuration. A multiple quantum well (MQW) structure may also be used. This can increase the luminous intensity of the light emitting layer 22. In addition, distributed Bragg reflectors (DBRs) can be configured above and below the layers, thereby confining light and increasing the light absorption efficiency.

[0047] Although the light absorption layer 21 and the light emitting layer 22 are made of p-type InGaN in the above description, the present invention is not limited to this configuration. An n-type InGaN may also be further provided to form a pn junction with the p-type InGaN.

[0048] The side surfaces of the fourth GaN layer 14, the light emitting layer 22, and the upper layer 13U in the specific region SR may have various shapes. For example, they may have inclined side surfaces called a mesa shape. This allows light emitted laterally (in the xy plane direction) from the light emitting layer 22 to be reflected downward (in the -z direction) by the inclined side surfaces, thereby allowing it to be absorbed by the light absorption layer 21.

[0049] The impurity concentration of the third GaN layer 13 may have any concentration distribution as long as it is higher on the lower side than on the upper side, for example, it may have a concentration gradient in which the concentration gradually increases toward the bottom.

[0050] The second electrode 32 and the fourth GaN layer 14 may have various positions and shapes. For example, the second electrode 32 and the fourth GaN layer 14 may be formed in a comb shape and arranged so as to interdigitate with each other.

[0051] The emitter and collector in this embodiment can be interchanged, so that the first GaN layer 11 can be the emitter and the third GaN layer 13 can be the collector.

[0052] The technique of this embodiment is applicable not only to npn-type bipolar transistors but also to pnp-type bipolar transistors.

[0053] A base electrode may be disposed on the second GaN layer 12, which functions as a base. This base electrode may be grounded when the semiconductor device 1 is in use. [Explanation of symbols]

[0054] 1: Semiconductor device 11: First GaN layer 12: Second GaN layer 13: Third GaN layer 13L: Lower layer 13U: Upper layer 14: Fourth GaN layer 21: Light absorption layer 22: Light emitting layer 31: First electrode 32: Second electrode 33: Third electrode

Claims

1. an n-type first GaN layer; a p-type second GaN layer disposed on an upper surface of the first GaN layer; an n-type third GaN layer disposed on an upper surface of the second GaN layer; a p-type fourth GaN layer disposed on an upper surface of the third GaN layer; a first electrode disposed below the first GaN layer; a second electrode disposed on an upper surface of the third GaN layer; a third electrode disposed on an upper surface of the fourth GaN layer; A vertical bipolar transistor comprising: an interface between the third GaN layer and the fourth GaN layer can be made to emit light by applying a voltage between the second electrode and the third electrode; A vertical bipolar transistor configured to be able to form a current path between the first electrode and the second electrode in response to light emission from the interface.

2. a light absorbing layer having a ternary mixed crystal of GaN, the light absorbing layer being disposed at an interface between the second GaN layer and the third GaN layer; a light-emitting layer having a ternary mixed crystal of GaN, the light-emitting layer being disposed at an interface between the third GaN layer and the fourth GaN layer; 10. The vertical bipolar transistor of claim 1 further comprising:

3. 3. The vertical bipolar transistor according to claim 2, wherein the peak wavelength of the light emitted from said light emitting layer is a wavelength that is transmitted through said third GaN layer and absorbed by said light emitting layer.

4. 4. The vertical bipolar transistor according to claim 3, wherein the peak wavelength is in the range of 365 to 380 nm.

5. 5. The vertical bipolar transistor according to claim 1, wherein the third GaN layer has a higher impurity concentration on the lower side than on the upper side.

6. 6. The vertical bipolar transistor according to claim 1, wherein there is no electrode in contact with the second GaN layer.

7. the vertical bipolar transistor includes a specific region on an upper surface of the third GaN layer where the fourth GaN layer is not disposed; 7. The vertical bipolar transistor according to claim 1, wherein the second electrode is disposed on an upper surface of the third GaN layer in the specific region.

8. A method for manufacturing a vertical bipolar transistor, comprising the steps of: a first growth step of epitaxially growing a p-type second GaN layer on an upper surface of the n-type first GaN layer; a second growth step of epitaxially growing an n-type third GaN layer on an upper surface of the second GaN layer; a third growth step of epitaxially growing a p-type fourth GaN layer on an upper surface of the third GaN layer; a removing step of removing a portion of the fourth GaN layer to expose the third GaN layer; forming a first electrode below the first GaN layer; forming a second electrode on the upper surface of the third GaN layer exposed by the removing step; forming a third electrode on an upper surface of the fourth GaN layer; A method for manufacturing a vertical bipolar transistor comprising:

9. a step of epitaxially growing a light absorbing layer having a ternary mixed crystal of GaN, the step being carried out between the first growth step and the second growth step; a step of epitaxially growing a light-emitting layer having a ternary mixed crystal of GaN, the step being carried out between the second growth step and the third growth step; The method for fabricating a vertical bipolar transistor according to claim 8 , further comprising:

10. 10. The method for manufacturing a vertical bipolar transistor according to claim 8, wherein in the second growth step, the third GaN layer is epitaxially grown so that the impurity concentration is higher in a lower side than in an upper side.

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