Insulated gate bipolar transistor and gate driver circuit

Abstract

To provide a high-performance insulated gate bipolar transistor and a gate driver circuit by suppressing a junction voltage between a p-type base layer and a high-concentration n-type layer, improving noise immunity, and reducing conduction resistance.SOLUTION: In an IGBT 100, a p-type collector layer 103 electrically connected to a collector electrode C is arranged on one side of an n-type base layer 101 in the thickness direction, and a high-concentration n-type layer 104 is provided on the other side of the n-type base layer in the thickness direction, and a p-type base layer 105 and an n-type source layer 106 connected to an emitter electrode E are laminated, and a gate 109 is formed inside an insulating film 108 covering the inner surface of a trench 107 formed to a depth reaching the n-type base layer 101. The gate 109 includes a first gate 109a connected to the gate electrode G and a second gate 109b fixed to the potential of the emitter electrode E. The impurity concentration of the high-concentration n-type layer 104 increases in the depth direction from the lower end position of the first gate 109a.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an insulated gate bipolar transistor and a gate driver circuit for driving the same. [Background technology]

[0002] Insulated gate bipolar transistors (hereinafter sometimes referred to as IGBTs) in which the gate is divided into two in the depth direction are known as the IGBT described in Patent Document 1. Such an IGBT will be described with reference to FIGS. 8 and 9.

[0003] The IGBT 1 described in Patent Document 1 and shown in FIG. 8 includes a collector electrode 10, an emitter electrode 11, a p+ type collector layer 12, an n- type base layer 13, an n- type barrier layer 14, a p- type base layer 15, an n+ type emitter layer 16, a gate electrode 17, and a first field plate electrode 19. In this conventional IGBT 1, the first field plate electrode 19 is electrically connected to the emitter electrode in a region not shown, and has the same potential as the emitter electrode. The n-type barrier layer 14 is an n-type semiconductor layer and has a higher n-type impurity concentration than the n-type impurity concentration of the n-type base layer 13, and the total amount of impurities is 1×10 12 ~1×10 14 cm -2 That's about it. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2019-12813 [Non-patent literature]

[0005] [Non-Patent Document 1] Fuji Electric Co., Ltd., "Fuji IGBT Module Application Manual", [online], December 2020, Rev.f, p.7-5, [Retrieved June 29, 2021], Internet <URL:https: / / www.fujielectric.co.jp / products / semiconductor / model / igbt / application / box / doc / pdf / RH984e / RH984f_JP.pdf> Summary of the Invention [Problem to be solved by the invention]

[0006] In the IGBT 1 described in Patent Document 1, the first field plate electrode 19 functions as a shield for the gate electrode 17, and therefore a shielding effect that improves noise resistance is obtained. However, the IGBT 1 described in Patent Document 1 has a high impurity concentration in the n-type barrier layer 14 (high-concentration n-type layer), and if the impurity concentration in the p-type base layer 15 is also made high, the electric field at the pn junction between the p-type base layer 15 and the n-type barrier layer 14 will exceed the critical electric field and become a high electric field, which may result in breakdown.

[0007] This voltage peak can be derived from the electric field from the gate surface of one trench to the gate surface of the other trench, as shown in Figures 9(A) to 9(C). Note that the first field plate electrode is omitted in Figure 9(A). First, the mesa width W mesa V at the center position of center The voltage is the area Sx of the graph showing the electric field shown in FIG. 9(C), and can be calculated from equation (1). However, t ox is the oxide thickness, E ox is the electric field in the oxide film, E Si is the electric field near the interface between the silicon semiconductor layer (n-type barrier layer 14) and the oxide film.

[0008]

number

[0009] Here, the electric field in the oxide film E ox is calculated from the following equation (2). However, ε Si is the dielectric constant of the silicon semiconductor layer, ε ox is the dielectric constant of the insulating film.

[0010]

number

[0011] Therefore, the electric field E in the oxide film in the above formula (1) ox Substituting equation (2) into equation (3) gives

[0012]

number

[0013] Electric field E in the silicon semiconductor layer Si is calculated from the following equation (4). where q is the number of elementary charges, N D is the impurity concentration of the n-type barrier layer 14.

[0014]

number

[0015] Therefore, when equation (4) is substituted into equation (3), equation (5) is obtained.

[0016]

number

[0017] From this equation (5), it can be seen that the voltage is determined by the structure and concentration. Therefore, if the concentration of the n-type barrier layer is made high, the area Sx of the electric field will become large. As a result, D value and high V centerThe electric field E between the p-type base layer 15 and the n-type barrier layer 14 is expressed as in equation (6) by the effect of both values ​​of Si-j increases.

[0018]

number

[0019] Therefore, although the IGBT 1 described in Patent Document 1 has a low on-voltage and is intended to reduce switching loss, it also reduces the withstand voltage, resulting in a decrease in performance.

[0020] Therefore, an object of the present invention is to provide a high-performance insulated gate bipolar transistor and gate driver circuit by suppressing the voltage at the junction between the p-type base layer and the heavily doped n-type layer, thereby improving noise resistance and reducing conduction resistance. [Means for solving the problem]

[0021] An insulated gate bipolar transistor according to a first aspect of the present invention includes an n-type base layer, a p-type collector layer disposed on one surface of the n-type base layer in a thickness direction and conducting with a collector electrode, a heavily doped n-type layer stacked on the other surface of the n-type base layer in the thickness direction and having an average impurity concentration higher than that of the n-type base layer, a p-type base layer stacked on the heavily doped n-type layer, an n-type source layer stacked on the p-type base layer, an emitter electrode connected to the p-type base layer and the n-type source layer, and a deep electrode extending from the n-type source layer to the n-type base layer. and a gate formed inside the insulating film, the gate being connected to a gate electrode and including a first gate formed to a depth position from the n-type source layer to the high-concentration n-type layer, and a second gate formed at a position deeper in the trench than the first gate via an insulating film for isolation and fixed to the potential of the emitter electrode, the insulating film being formed to a substantially constant thickness at a position corresponding to the second gate, and the impurity concentration of the high-concentration n-type layer being The height increases in the depth direction from , under the second gate It peaks at the bottom of the high-concentration n-type layer and decreases toward the bottomIt is characterized by:

[0022] In the insulated gate bipolar transistor of the first invention, the thickness of the insulating film at the position corresponding to the second gate is formed to be almost constant, and the high-concentration n-type layer has a region where the impurity concentration is higher at the lower end of the second gate than at the lower end of the first gate. This results in an electric field between the trenches at the junction between the p-type base layer and the high-concentration n-type layer having a lower impurity concentration than the lower part of the high-concentration n-type layer. Therefore, -qN D The gradient of the electric field indicated by / ε becomes gentler, which reduces the voltage at the junction. Also, because the lower part of the high-concentration n-type layer is heavily doped, it can supply a sufficient amount of electrons and prevent the passage of holes. This reduces the conduction resistance. Furthermore, because the upper part of the high-concentration n-type layer is lightly doped, the parasitic capacitance between the first gate and the high-concentration n-type layer can be reduced, preventing malfunctions due to noise.

[0023] In the first invention, the insulating film may be formed such that the thickness of the upper insulating film at a position corresponding to the first gate portion is thinner than the thickness of the lower insulating film at a position corresponding to the second gate portion. By making the upper insulating portion thin, sufficient electron density in the inversion layer (a large amount of electrons in the electron layer) can be ensured even with a low gate voltage, reducing channel resistance and conduction loss.

[0024] An insulated gate bipolar transistor according to a second aspect of the present invention includes an n-type base layer, a p-type collector layer disposed on one surface of the n-type base layer in a thickness direction and conducting with a collector electrode, a heavily doped n-type layer stacked on the other surface of the n-type base layer in the thickness direction and having an average impurity concentration higher than that of the n-type base layer, a p-type base layer stacked on the heavily doped n-type layer, an n-type source layer stacked on the p-type base layer, an emitter electrode connected to the p-type base layer and the n-type source layer, an insulating film covering the inner surface of a trench formed in a depth direction from the n-type source layer to the n-type base layer, and a gate formed inside the insulating film. the gate comprises a first gate connected to a gate electrode and formed to a depth position from the n-type source layer to the high-concentration n-type layer, and a second gate formed at a position deeper in the trench than the first gate via an isolation insulating film and fixed to the potential of the emitter electrode, the insulating film being thinner on the p-type base layer side at a position corresponding to the second gate and thicker on a side away from the p-type base layer, the high-concentration n-type layer having a region with the highest impurity concentration from a lower end position of the first gate to a predetermined depth, and the impurity concentration on the lower end side of the second gate being lower than that in the region.

[0025] In the insulated gate bipolar transistor of the second invention, the insulating film is thin on the p-type base layer side at a position corresponding to the second gate and thick on the side away from the p-type base layer. Furthermore, the high-concentration n-type layer has a region with the highest impurity concentration extending from the lower end of the first gate to a predetermined depth. This results in a high concentration of the electric field across the trench at the junction between the p-type base layer and the high-concentration n-type layer on the p-type base layer side of the high-concentration n-type layer. However, because the insulating film is thin, the area of ​​the electric field in the insulating film can be narrowed, thereby preventing the junction from becoming high voltage. In addition, because the insulating film is thick on the n-type base layer side of the high-concentration n-type layer, leakage current to the second gate connected to the emitter electrode can be suppressed, thereby improving the reliability of the gate insulating film.

[0026] In a second aspect of the present invention, the trench has a constant width, and the second gate has an inclined surface that is separated from the inner wall surface of the trench in the depth direction, so that the insulating film is formed to have a thickness that increases in the depth direction. This allows the insulating film to be thin on the p-type base layer side at a position corresponding to the second gate and to have a thickness that increases in the depth direction, even if the trench has a constant width.

[0027] In the first or second invention, the distance between the trenches can be set to 0.6 μm or more and 1.2 μm or less. By setting the distance between the trenches to 1.2 μm or less, the voltage at the junction can be further reduced.

[0028] The gate driver circuit of the present invention is characterized by including a charge control circuit that controls the charge on the gate capacitance depending on whether the transistor is turned on or off when a PWM signal is output to the gate electrode of the insulated gate bipolar transistor of the present invention to control switching.

[0029] The gate driver circuit of the present invention controls the charge on the gate capacitance during switching by a PWM signal, thereby preventing changes in operating characteristics due to the rate at which the gate capacitance is charged and discharged, thereby suppressing surge voltages while reducing switching losses.

[0030] The charge control circuit may include a first charge pulse generating unit that adds charge to the gate electrode from any timing between the PWM signal indicating turn-on and the rising edge of the collector current until before the peak of the rising edge of the collector current, and a second charge pulse generating unit that draws charge from the gate electrode from any timing between the PWM signal indicating turn-off and the rising edge of the collector-emitter voltage until before the peak of the collector-emitter voltage. By setting the timing for adding charge at turn-on to any time between the PWM signal indicating turn-on and the rising edge of the collector current, and by setting the timing for extracting charge at turn-off to any time between the PWM signal indicating turn-off and the rising edge of the collector-emitter voltage, it is possible to achieve the effect of suppressing surge voltage while suppressing switching loss.

[0031] In particular, the first charge pulse generating unit adds charge to the gate electrode from the rising edge of the collector current until before the peak of the rising edge of the collector current, and the second charge pulse generating unit extracts charge from the gate electrode from the rising edge of the collector-emitter voltage until before the peak of the collector-emitter voltage, thereby more effectively suppressing switching loss and surge voltage.

[0032] The charge control circuit can also add charge to the gate capacitance when the tail voltage of the collector-emitter voltage remains at turn-on.

[0033] In addition, the charge control circuit can also be provided with a delay unit that delays the pulse indicating turn-on and the pulse indicating turn-off indicated by the PWM signal to a predetermined timing, thereby suppressing switching loss and surge voltage. [Effects of the Invention]

[0034] According to the present invention, by adjusting the impurity concentration of the high-concentration n-type layer or adjusting the thickness of the insulating film, it is possible to suppress the voltage at the junction between the p-type base layer and the high-concentration n-type layer, thereby improving noise resistance and reducing conduction resistance. [Brief explanation of the drawings]

[0035] [Figure 1] 1 is a diagram illustrating a configuration of an IGBT according to a first embodiment of the present invention. [Figure 2]2 is a diagram for explaining the impurity concentration (donor concentration) of a high-concentration n-type layer of the IGBT shown in FIG. [Figure 3] 3A and 3B are diagrams showing examples of impurity concentrations in the high-concentration n-type layer shown in FIG. 2, where (A) is a diagram showing the concentration distribution and mesa region when the oxide film is 0.2 μm thick, and (B) is a diagram showing the concentration distribution and mesa region when the oxide film is 0.1 μm thick. [Figure 4] 2A and 2B are diagrams for explaining the electric field at the junction between the p-type base layer and the high-concentration n-type layer in the IGBT shown in FIG. 1, where (A) shows the electric field in the low-concentration region of the high-concentration n-type layer, (B) shows the electric field when the upper insulating film is formed thin, and (C) shows the electric field when the distance between trenches is 1 μm. [Figure 5] FIG. 10 is a diagram for explaining the configuration of an IGBT according to a second embodiment of the present invention, and is a diagram for explaining the impurity concentration (donor concentration) of a high-concentration n-type layer. [Figure 6] 2A is a diagram for explaining the mesa region of the IGBT shown in FIG. 1, and FIG. 2B is a graph showing the relationship between the impurity concentration (donor concentration) of the high-concentration n-type layer, the electric field at the junction, and the mesa width. [Figure 7] 6A is a diagram for explaining the mesa region of the IGBT shown in FIG. 5, and FIG. 6B is a graph showing the relationship between the impurity concentration (donor concentration) of the high-concentration n-type layer, the electric field at the junction, and the mesa width. [Figure 8] FIG. 1 is a diagram showing the configuration of a conventional IGBT described in Patent Document 1. [Figure 9] 10A and 10B are diagrams for explaining the conventional IGBT shown in FIG. 9, in which (A) is a schematic diagram showing the gap between trenches, (B) is a diagram showing the potential between the trenches, and (C) is a diagram showing the electric field between the trenches. [Figure 10] FIG. 1A is a diagram illustrating a gate driver circuit described in Non-Patent Document 1, FIG. 1B is a diagram illustrating gate capacitance, and FIG. 1C is a graph showing the relationship between surge voltage and switching loss. [Figure 11] FIG. 10 is a diagram illustrating a gate driver circuit according to a third embodiment of the present invention. [Figure 12]12 is a diagram for explaining a circuit example of the gate driver circuit shown in FIG. 11. FIG. [Figure 13] FIG. 1A is a diagram showing the timing of a first pulse at turn-on, and FIG. 1B is a diagram showing the timing of a second pulse at turn-off. [Figure 14] 12A and 12B are diagrams for explaining the operation of the gate driver circuit shown in FIG. 11, in which (A) is a diagram showing the collector current when a 1-1 pulse is generated, (B) is a diagram showing the collector current when a 1-1 pulse and a 1-2 pulse are generated, and (C) is a diagram showing the collector current when a second pulse is generated. [Figure 15] (A) is a graph showing the relationship between the gate charge and the collector-emitter voltage at turn-on, and (B) is a graph showing the relationship between the gate charge and the collector-emitter voltage at turn-off. [Figure 16] FIG. 10 is a diagram showing a modified example of the second charge pulse generating section. DETAILED DESCRIPTION OF THE INVENTION

[0036] A high-voltage power semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. The high-voltage power semiconductor device according to the present embodiment will be described using an insulated gate bipolar transistor (hereinafter abbreviated as IGBT) as an example. In this specification, the depth direction of the semiconductor layer may be referred to as downward, and the opposite direction as upward.

[0037] (Embodiment 1) First, an IGBT 100 according to a first embodiment of the present invention will be described with reference to the drawings. The IGBT 100 shown in FIG. 1 includes an n-type base layer 101, an n-type buffer layer 102 formed on one surface of the n-type base layer 101, a p-type collector layer 103 stacked on the n-type buffer layer 102, and a collector electrode C. The IGBT 100 also includes a high-concentration n-type layer 104 formed on the other surface of the n-type base layer 101, a p-type base layer 105 stacked on the high-concentration n-type layer 104, an n-type source layer 106 stacked on the p-type base layer 105, and an emitter electrode E. Furthermore, the IGBT 100 includes an insulating film 108 that covers the entire inner surfaces of multiple trenches 107 formed in the depth direction F1 (thickness direction) of the n-type source layer 106, the p-type base layer 105, the high-concentration n-type layer 104, and the n-type base layer 101, and gates 109 (first gate 109a, second gate 109b) formed inside the insulating film 108. Naturally, it is most preferable to provide the insulating film 108 so as to insulate the entire inner surface of the trench 107. However, in some cases, depending on the device specifications and the relationship with other layers, it is also possible to configure the insulating film 108 so that it is not provided on the entire inner surface of the trench 107, but on a portion (more preferably, a very small portion) of the inner surface of the trench 107. Therefore, the insulating film 108 is formed so as to cover almost the entire inner surface of the trench 107.

[0038] The n-type base layer 101 is an n-layer formed from an N-type silicon substrate. The n-type base layer 101 can be formed from only a silicon substrate, but may also be formed by forming an epitaxial layer on a wafer that will become the silicon substrate. The impurity concentration of the n-type base layer 101 is, for example, 1×10 14 (atoms / cm 3 ) can be about.

[0039] The n-type buffer layer 102 is an n+ layer having a higher impurity concentration (donor concentration) than the n-type base layer 101. The p-type collector layer 103 is a high-concentration p+ layer uniformly formed on the surface of the n-type buffer layer 102.

[0040] The high-concentration n-type layer 104 is formed in a range in the depth direction F1 (thickness direction) that includes the gap between the first gate 109a and the second gate 109b. In this embodiment, the high-concentration n-type layer 104 is formed from the lower end of the first gate 109a to a position corresponding to the second gate 109b. The high-concentration n-type layer 104 is an n+ layer in which the average impurity concentration of the surface in the gap portion is higher than that of the n-type base layer 101 . The impurity concentration of the high-concentration n-type layer 104 has a region where it is higher on the lower end side of the second gate 109b than on the lower end side of the first gate 109a. In the first embodiment, the impurity concentration of the high-concentration n-type layer 104 is formed so as to increase from the lower end position of the first gate 109a toward the depth direction F1. Specifically, as shown in FIG. 2, the impurity concentration at the lower end of the first gate 109a is higher than that of the n-type base layer 101, and increases further in the depth direction, reaching a peak at the bottom of the second gate 109b, and then decreasing toward the lower end of the high-concentration n-type layer 104.

[0041] For example, as shown in FIG. 3A, the peak concentration of the high-concentration n-type layer 104 is at a thickness t ox When the mesa width is set to 0.2 μm and the mesa thickness is set to 0.25 μm, the upper region is 3×10 16 (atoms / cm 3 ) and gradually increases in the depth direction, and the lower region from a depth of 0.4 μm is 5 × 10 16 (atoms / cm 3 ) and is formed so that the density decreases at the bottom end. As shown in FIG. 3B, the concentration of the high-concentration n-type layer 104 is determined by the thickness t ox When the mesa width is 0.1 μm, the upper region is 7 × 10 16 (atoms / cm 3 ) and gradually increases in the depth direction, and the lower region from a depth of 0.2 μm is 1.1 × 10 17 (atoms / cm 3 ) and is formed so that the density decreases at the bottom end. In this way, the thickness t of the insulating film 108 located at the second gate 109b ox By setting the mesa width to 0.1 μm, the impurity concentration is 1×10 17 (atoms / cm 3 ) or more.

[0042] 2 is connected to the emitter electrode E, and is selectively formed between adjacent trenches 107. The p-type base layer 105 is formed so that the channel length, which is the thickness, is 0.5 μm or less. The n-type source layer 106 is a high-concentration n+ layer stacked on the surface of the selectively formed p-type base layer 105 . The trenches 107 are grooves formed in a depth direction F1. The trenches 107 can be formed by, for example, subjecting the trench regions to reactive ion etching (RIE) or other techniques. The spacing between the trenches 107 (the spacing between the centers of the trenches 107) can be set in accordance with the concentration of the high-concentration n-type layer 104, but in the first embodiment, the distance between the trenches 107 is set to 0.6 μm or more and 1.2 μm or less.

[0043] The insulating film 108 can be formed of, for example, a silicon oxide film. The insulating film 108 is formed such that the thickness of the upper insulating film 108a at a position corresponding to the first gate 109a is thinner than the thickness of the lower insulating film 108b at a position corresponding to the second gate 109b. For example, the thickness of the upper insulating film 108a can be 33 nm, and the thickness of the lower insulating film 108b can be 100 nm. The lower insulating film 108b is formed so that the thickness of the trench 107 along the depth direction F1 is approximately constant. The thickness of the upper insulating film 108a may vary slightly due to errors in the manufacturing process or intentionally. Here, "constant" means a thickness within ±10% of the average thickness of the lower insulating film 108b. Furthermore, "approximately constant" means that a thickness that locally exceeds ±10% of the average thickness is acceptable.

[0044] The gate 109 can be made of, for example, polysilicon doped with n-type impurities. To reduce the resistance of the electrode material, n-type polysilicon can be used. The gate 109 includes a first gate 109a connected to the gate electrode G, and a second gate 109b fixed at a predetermined potential and formed at a deeper position in the trench 107 than the first gate 109a via an isolation insulating film 108c.

[0045] The first gate 109a is connected to a gate electrode G and is applied with, for example, 0 V to 5 V. The second gate 109b is connected to, for example, an emitter electrode E by a connection not shown.

[0046] First gate 109a is formed to be wider than second gate 109b. Therefore, in insulating film 108 formed on the inner surface of trench 107 having a uniform groove width, upper insulating film 108a is formed to be thinner than lower insulating film 108b, as described above.

[0047] The collector electrode C is formed on the p-type collector layer 103 and functions as a first electrode. The emitter electrode E is connected to the p-type base layer 105 and the n-type source layer 106 . The gate electrode G is formed on the surface of the chip. The gate electrode G and the first gate 109a are connected to each other by a plug electrode (not shown) in contact with the first gate 109a and a wiring portion on the upper part of the plug electrode, which is drawn out in the longitudinal direction of the trench structure.

[0048] The operation of the IGBT 100 according to the first embodiment of the present invention configured as above will be described with reference to the drawings. 1, an inversion layer is formed in the p-type base layer 105. As a result, similar to an N-type MOSFET, the n-type source layer 106, the p-type base layer 105, and the n-type base layer 101 including the heavily doped n-type layer 104 are turned on. When the N-type MOS is turned on, the collector electrode C is at a positive potential, so holes are injected from the p-type collector layer 103 on the collector side into the n-type base layer 101 via the n-type buffer layer 102. These injected holes accelerate the injection of electrons from the emitter electrode E side. This increases the number of carriers, that is, the number of electrons and holes, in the n-type base layer 101, which was previously a high-resistance layer, thereby reducing the resistance value of the n-type base layer 101. At this time, the heavily doped n-type layer 104 injects sufficient electrons, which in turn injects sufficient holes from the p-type collector layer 103. The heavily doped n-type layer 104 also functions as a barrier layer that blocks the passage of holes. This reduces the voltage drop when the semiconductor is conductive, thereby reducing the conduction resistance.

[0049] During switching, a displacement current flows from the gate 109 to the gate electrode G due to feedback capacitance between the gate 109 and the collector electrode C. The voltage drop across the resistor connected between the gate electrode G and the control circuit increases the voltage at the gate electrode G, causing a malfunction. In the first embodiment, gate 109 is divided into first gate 109a and second gate 109b, and second gate 109b is connected to emitter electrode E. Therefore, the displacement current flows through second gate 109b and then to emitter electrode E, so that the influence of the displacement current on first gate 109a can be avoided.

[0050] 4A, the electric field between the trench 107 at the junction between the p-type base layer 105 and the high-concentration n-type layer 104 is smaller than that at the bottom of the high-concentration n-type layer 104, because the impurity concentration is lower than that at the bottom of the high-concentration n-type layer 104, as shown in FIG. D Since the slope of / ε is gentle, the electric field in the insulating film can also be suppressed. Therefore, the area S1 enclosed by the graph shown in FIG. 4(A) can be made smaller than the area Sx of the graph shown in FIG. 9(C), so that the voltage at the junction can be suppressed. Furthermore, because the lower portion of the high-concentration n-type layer 104 is highly doped, it can supply a sufficient amount of electrons and prevent holes from passing through. Therefore, it is possible to suppress the voltage at the junction between the p-type base layer 105 and the high-concentration n-type layer 104 while also reducing the conduction resistance. Furthermore, because the upper portion of the high-concentration n-type layer 104 is lightly doped, it is possible to reduce the parasitic capacitance between the first gate 109a and the high-concentration n-type layer 104, thereby preventing malfunctions due to noise.

[0051] The upper insulating film 108a is formed to be thinner than the lower insulating film 108b at a position corresponding to the second gate 109b. 4(B), the slope of the graph showing the electric field remains the same, but the area of ​​the electric field in the insulating film becomes narrower, thereby suppressing the voltage at the junction between the p-type base layer 105 and the high-concentration n-type layer 104. Furthermore, a low gate voltage can ensure sufficient electron density in the inversion layer (a large amount of electrons in the electron layer), reducing the channel resistance and conduction loss.

[0052] Furthermore, the distance between the trenches 107 is set to 0.6 μm or more and 1.2 μm or less. Therefore, as shown in FIG. 4C, the distance between the sloped portions of the graph showing the electric field is narrower than when the distance between the trenches 107 is greater than 1.2 μm, and the area S3 of the graph can be reduced. Therefore, narrowing the distance between the trenches 107 (the width of the mesa region) can also reduce the voltage at the junction between the p-type base layer 105 and the high-concentration n-type layer 104.

[0053] (Embodiment 2) A high-voltage power semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings. In Fig. 5, the same components as those in Fig. 1 are designated by the same reference numerals and will not be described again. 5, the thickness of the insulating film 118 at a position corresponding to the second gate 119b is thinner on the p-type base layer 105 side and thicker on the side away from the p-type base layer 105. The p-type base layer 105 in the second embodiment is formed to be thicker in the depth direction F1. Furthermore, high-concentration n-type layer 114 is formed so that a region with the highest impurity concentration is formed from the lower end position of first gate 109a to a predetermined depth, and the impurity concentration is lower than this region on the lower end side of second gate 109b. High-concentration n-type layer 114 in the second embodiment is formed so that a region with the highest impurity concentration is formed from the lower end position of first gate 109a to a predetermined depth. The high concentration region of this high concentration n-type layer 114 is 1×10 17 (atoms / cm 3 ) or more.

[0054] 5, the trench 107 has a constant width. The second gate 119b has an inclined surface 119c that is spaced apart from the inner wall surface of the trench 107 in the depth direction F1, so that the thickness of the insulating film 118 increases in the depth direction.

[0055] By forming the IGBT 110 in this manner, the upper part of the insulating film 118 (lower insulating film 118b) at a position corresponding to the second gate 119b is formed to have the thinnest thickness. Therefore, even if the high-concentration n-type layer 114 has a region with the highest impurity concentration from the lower end position of the first gate 109a, the voltage can be suppressed as shown in the graph of the electric field in Figure 4(B). Therefore, the IGBT 110 can improve its withstand voltage.

[0056] For example, in the IGBT 100 shown in FIG. 1, the thickness of the insulating film 108 located at the second gate 109b is constant as shown in FIG. 6(A). In this case, the thickness t OX 6B, according to the PN junction breakdown field at the junction between the p-type base layer 105 and the high-concentration n-type layer 104, the impurity concentration is 2.5×10 16 (atoms / cm 3 ) is the limit, and the mesa width W mesa The limit for miniaturization is 0.4 μm.

[0057] As shown in FIG. 7A, the thickness t OX The thickness of the insulating film 118 located on the n-type base layer side, which is the lower end, is set to 0.1 μm. OX is set to 0.2 μm. In such a case, as shown in FIG. 7B, the impurity concentration of the high-concentration n-type layer 114 is doubled (5×10 16 (atoms / cm 3 )) can be achieved. In this way, a high concentration can be achieved, which promotes electron injection and reduces conduction loss. Furthermore, even with the same conduction loss, the trench depth can be made shallower (if the product of the thickness of the ND and N layers is the same, the performance is roughly the same); for example, the trench 107 below the p-type base layer 105 can be made approximately 0.6-1.0 μm. Furthermore, leakage current to the second gate 119b connected to the emitter electrode E can be suppressed, and the reliability of the gate insulating film can be improved.

[0058] Furthermore, since the side surface of the second gate 119b is formed on an inclined surface 119c along the depth direction F1, even if the groove width of the trench 107 is constant, the thickness of the insulating film 118 at the position corresponding to the second gate 119b can be made thinner on the p-type base layer 105 side and thicker toward the depth direction F1.

[0059] In the first and second embodiments, a gate 109 connected to the gate electrode E is provided in the trench 107 to form a trench gate. However, a dummy gate having a structure similar to that of the gates (first gate and second gate) may be formed in the trench, and a dummy trench may be formed in which the dummy gate is connected to the emitter electrode. In the case of a high voltage IGBT of 1200V or more, providing a dummy gate connected to the emitter electrode E has the effect of increasing electron injection. This is because the emitter electrode E only partially contacts the p-type base layer 105, reducing the amount of holes injected from the p-type collector layer 103 that flow into the emitter electrode E via the p-type base layer 105. In addition, the reduction in hole current allows for an increase in the amount of electron injection.

[0060] (Embodiment 3) A gate driver circuit according to a third embodiment of the present invention will be described with reference to the drawings. The gate driver circuit according to the third embodiment is used when controlling the gate of an IGBT or a MOS FET by PWM. First, a conventional gate driver circuit will be described based on Non-Patent Document 1.

[0061] Non-Patent Document 1 illustrates a basic gate driver circuit as shown in Figure 10(A). The gate driver circuit has a gate resistor R connected in series to a totem-pole type output. G is connected, and the gate resistor R G is connected to the gate electrode of the IGBT.

[0062] In such gate driver circuits, switching loss is reduced during high-speed operation, but surge voltage increases, increasing the risk of breakdowns and malfunctions.On the other hand, surge voltage is reduced during low-speed operation, increasing switching loss, but decreasing power conversion efficiency. The same problem occurs even if the resistance value of the gate resistor is adjusted, so this cannot be solved by simply adjusting the resistance value. This is because the gate capacitance (C gc ,C ge This is because the operating characteristics change depending on the charging and discharging speed of the battery. Therefore, the gate resistance R G This is because the switching characteristics change due to the change, and as shown in FIG. 10(C), there is a trade-off between the loss during switching and the surge voltage.

[0063] Therefore, as shown in FIG. 11, a gate driver circuit 200 according to the third embodiment includes a PWM drive circuit 210 and a charge control circuit 220. The PWM drive circuit 210 is similar to a conventional gate driver circuit. The PWM drive circuit 210 includes a PWM amplifier circuit 211 that amplifies a PWM signal from a PWM control circuit (not shown), and a first resistor R connected in series to the output of the PWM amplifier circuit 221. g1 and the second resistor R g2 It is equipped with the following.

[0064] The charge control circuit 220 controls the charge to the gate capacitance depending on whether the IGBT 100 is turned on or off when a PWM signal is output to the gate electrode G of the IGBT 100 to control switching. The charge control circuit 220 includes a delay circuit 221 that delays the pulse indicating turn-on and the pulse indicating turn-off indicated by the PWM signal to a predetermined timing, and a charge pulse generation circuit 222 that draws charge from the gate electrode G when turned off and adds charge to the gate electrode G when turned on, at the timing of the pulse delayed by the delay circuit 221.

[0065] This charge pulse generating circuit 222 can be configured, for example, by a circuit as shown in FIG. In the charge control circuit 220 shown in FIG. 12, the delay circuit 221 includes a first delay section 221a for turn-on and a second delay section 221b for turn-off. Furthermore, in the charge control circuit 220, the charge pulse generating circuit 222 comprises a first charge pulse generating section 222a for turn-on and a second charge pulse generating section 222b for turn-off.

[0066] The first charge pulse generating unit 222a applies charge to the gate electrode G from any timing between the PWM signal indicating turn-on and the rising edge of the collector current Ic until before the rising edge of the collector current Ic. In the third embodiment, the first charge pulse generating unit 222a applies charge to the gate electrode G from after the rising edge of the collector current Ic until before the rising edge of the collector current Ic. The first charge pulse generating section 222a includes a transistor Tr1 having a base connected to the first delay section 221a, an emitter grounded, and a collector connected to a resistor R1, and a pair of transistors Tr21 and Tr22 that are connected to the transistor Tr1 via the resistor R1 and form a current mirror circuit that draws current from a power supply Vcc in accordance with the current flowing through the transistor Tr1 and generates a first pulse to be added to the gate electrode G as a charge.

[0067] In addition, the second charge pulse generating unit 222b converts the collector-emitter voltage V CE At any time during the rise of CE In the third embodiment, the charge is extracted from the gate electrode G before the peak of the collector-emitter voltage V CE After the rise of the collector-emitter voltage V CE The charge is extracted from the gate electrode before the peak. The second charge pulse generating unit 222b includes a transistor Tr3 whose base is connected to the second delay unit 221b, whose emitter is grounded, and whose collector is connected to a dividing resistor Rx, thereby functioning as a level shifter; a transistor Tr4 whose base is connected to the dividing resistor Rx and whose emitter is connected to a power supply Vcc; and a pair of transistors Tr51 and Tr52 which are connected to the collector of transistor Tr4 via resistor R2 and form a current mirror circuit that generates a second pulse by drawing, from the gate electrode G, a current corresponding to the flow from transistor Tr4 as charge.

[0068] Note that Vcc is generally the same as the gate drive voltage. For example, if the gate drive voltage is 0V-5V, Vcc is 5V and GND is 0V. If the gate threshold of the IGBT100 is high and a voltage difference up to 5V cannot be sufficiently secured, or if you want to increase the current value of the first pulse at turn-on and shorten the pulse width, you can select a Vcc higher than the gate drive voltage, such as 10V. Similarly, if the gate threshold is low or you want to increase the current drawn from the gate capacitance at turn-off and shorten the pulse width, GND can be a negative voltage, such as -5V. Note that the same function can also be achieved with a voltage-to-current conversion circuit.

[0069] The operation of the gate driver circuit 200 according to the third embodiment of the present invention configured as above will be described with reference to the drawings. First, the collector current I of the IGBT100 when it is turned on and off. C and collector-emitter voltage V CE The time for each change is measured, and the time for the delay circuit 221 is set based on the measured time.

[0070] For example, as shown in FIG. 13(A), the first delay unit 221a is set so that the time from the rising time of the PWM signal to the rising time of the collector current Ic at turn-on is set as the delay time. And the collector current I C From the rising edge of C The first delay unit 221a is set to generate a 1-1 pulse having a pulse width equal to an arbitrary time period before the peak of the signal enters the overshoot.

[0071] Also, from the rise time of the PWM signal, the collector current I C becomes constant, and the collector-emitter voltage V CE The first delay unit 221a is set so that the time during which the tail voltage remains after the fall of the signal falls is set as the delay time. And this collector-emitter voltage V CEThe first delay unit 221a is set so as to generate a 1-2 pulse having a pulse width of an arbitrary time while the tail voltage of the 1-2 pulse remains. In this case, when charge control is performed by the charge control circuit 220, the collector current I C and collector-emitter voltage V CE Since the waveform of the first pulse from the charge control circuit 220 to the IGBT 100 changes, the delay time and pulse width are adjusted taking into consideration the effect of the first pulse from the charge control circuit 220 to the IGBT 100.

[0072] As shown in Figure 13(B), at turn-off, the collector-emitter voltage V CE The second delay unit 221b is set so that the time it takes for the signal to rise is set as the delay time. Also, the collector-emitter voltage V CE From the rising edge, the collector-emitter voltage V CE The second delay unit 221b is set so as to generate a second pulse having a pulse width equal to an arbitrary time period before the peak of the signal enters the overshoot. The above-mentioned arbitrary time period that determines the pulse width may be adjusted from the minimum width to the maximum width by operating the gate driver circuit 200. In the case of turn-off, as in the case of turn-on, when charge control is performed by the charge control circuit 220, the collector current I C and collector-emitter voltage V CE Since the waveform of the second pulse from the charge control circuit 220 to the IGBT 100 changes, the delay time and pulse width are adjusted taking into consideration the effect of the second pulse from the charge control circuit 220 to the IGBT 100.

[0073] As shown in FIG. 12, the first delay unit 221a and the second delay unit 221b set in this manner detect turn-on or turn-off when a PWM signal is input. The first delay unit 221a that detects the turn-on generates a first pulse with a delay from the turn-on at which the PWM signal rises. When the first pulse is input, the first charge pulse generating unit 222a turns on transistor Tr1. When transistor Tr1 turns on, transistor Tr21 turns on via resistor R1. This turns on transistor Tr22, which forms a current mirror circuit, in response to the current flowing through transistor Tr21. That is, a current of the same value as the current flowing through resistor R1 flows into the gate circuit. At this time, the transistor Tr52 is off, so that a current flows from the transistor Tr22, and charge is added to the gate electrode G of the IGBT 100 during the period of the first pulse width (mirror period). This allows charge to be added quickly to the gate capacitance.

[0074] This charge is the charge ΔQ due to the 1-1 pulse shown in FIG. G , charge ΔQ due to the first and second pulses G is the pulse width × voltage Vcc / R1. Alternatively, two first pulses (pulse 1-1 and pulse 1-2) shown in FIG. 14(B) may be generated together. Also, the collector-emitter voltage V CE If there is any remaining pulse, the first and second pulses may be long or may be generated multiple times.

[0075] 13, there are cases where it is necessary to change the delay time or pulse width depending on the operating conditions of the IGBT. For example, when generating a 1-2 pulse together with a 1-1 pulse, if the width of the 1-1 pulse is long, the delay time to the 1-2 pulse changes. The gate charge Q shown in FIG. G and the gate-emitter voltage V GE From this graph, the pulse delay and pulse timing, which are the conditions for the generated pulse, can be determined. This graph is generally obtained under resistive load conditions, but it is more accurate if obtained under L-load double pulse test conditions. That is, the gate charge Q G Gate-emitter voltage V GEbecomes flat (constant) for a while, but the 1-1 pulse is within the range included in the flat portion, and by terminating the 1-1 pulse so as not to exceed the flat portion, as shown in FIG. 14(A), surge currents and vibrations can be prevented while the current rise period at turn-on is shortened, thereby reducing switching loss.

[0076] Gate-emitter voltage V GE The amount of charge up to the point where the voltage becomes flat varies depending on the current and DC voltage conditions, as indicated by arrows A and B in Figure 15(A). For this reason, when prioritizing loss reduction, particularly at large currents, the amount of charge is set as indicated by arrow B. In other words, the gate charge amount at the end of the 1-1 pulse (the area of ​​the hatched portion shown in Figure 14(A) up to the end of the pulse) is set to match arrow B (see Figure 15(A)). In this case, the switching period is shortened, reducing switching loss, and surge currents and noise in large current areas are suppressed. However, when the current is low or the DC voltage drops, noise occurs beyond the plateau at the end of the 1-1 pulse (loss and noise are reduced, but noise occurs during low current operation).

[0077] On the other hand, if the charge amount at the end of the 1-1 pulse is set as shown by arrow A, surges can be suppressed under all conditions, but the rate of reduction in switching loss at large currents decreases. ΔQ of the 1st pulse G When prioritizing loss reduction, the maximum charge amount can be determined by using a graph corresponding to the maximum current and maximum voltage. However, when using the graph shown in FIG. 15, arrow B can be used. Furthermore, when prioritizing noise suppression, the graph corresponding to the minimum current and minimum voltage can be used, but when using the graph shown in FIG. 15, the value of arrow A can be used. Then, the resistor R1 (see FIG. 12) and the pulse width in the current mirror circuit are determined. Also, as the delay time by the first delay unit 221a is increased, ΔQ G Reduce the resistor R g1 , R g2The ratio of the sum of the resistance values ​​of the resistors R1 and R2 is 5 times or more (R g1 +R g2 >R1×5). This is the resistance R g1 ,R g2 This is because a large value is desirable for noise suppression, and a small value is required for resistor R1 to reduce switching loss.

[0078] By adding charge in this way, the collector-emitter voltage V CE and the collector current I C At this time, the gate charge Q G and the gate-emitter voltage V GE The relationship is as shown in the graph in FIG. In the graph shown in Figure 15(A), under low voltage conditions, V GE The amount of charge that flows into the gate from when the gate circuit starts operating at 0V to the end of the Miller period is shown by arrow A. Also, under high voltage conditions, V GE The amount of charge flowing into the gate from when the gate circuit starts operating at 0V until the mirror period ends is indicated by arrow B.

[0079] As can be seen from this graph, the change in gate charge value of the IGBT100 depending on the operating conditions is small compared to the conventional IGBT, and the ΔQ G The amount and timing of This is because the displacement current caused by the rise and fall of the electric field above the n-type base layer 101 (see FIGS. 1 and 5) due to switching flows into the second gate 109b, but does not flow into the first gate 109a, which is located "behind" the second gates 109b and 119b as seen from the n-type base layer 101 (V center Since the voltage at this gate does not depend on the electric field in the n-type base layer 101, changes in the electric field in the n-type base layer 101 are not transmitted to the first gate 109a. As a result, the change in the gate charge amount due to the operating state is small.

[0080] Next, as shown in FIG. 13(B), when a turn-off is detected from the PWM signal, the second delay unit 221b (see FIG. 12) generates a second pulse with a delay from the turn-off at which the PWM signal falls. When the second charge pulse generating section 222b receives the second pulse, it turns on the transistor Tr3. When the transistor Tr3 turns on, the dividing resistor Rx turns on the transistor Tr4. By doing so, a current flows through transistor Tr52, which forms a current mirror circuit, in response to the current flowing through transistor Tr51 via resistor R2, and by drawing gate current Ig through resistor Rg, charge is drawn from gate electrode G of IGBT 100 during the period of the second pulse width (mirror period). This allows charge to be drawn quickly from the gate capacitance.

[0081] In the case of turn-off, the gate charge Q G and the gate-emitter voltage V GE From the graph, the pulse delay and pulse timing can be determined. The curve on the graph of FIG. 15(B) is also generally obtained under resistive load conditions, but it is more accurate if it is obtained under L-load double pulse test conditions. The amount of charge discharged from the gate at the end of the second pulse (I shown in Figure 14(C)) G The hatched area from the left edge of the glass to the end of the second pulse is shown in I G The area obtained by the time integral of Q G By using a value of 0.01V or 0.1V (the difference between the values ​​of 0.01V and 0.1V), it is possible to reduce turn-off loss (switching loss) over a wide range.

[0082] On the other hand, noise may occur when the voltage is low. Therefore, to enhance the noise suppression effect, the gate charge Q corresponding to the arrow A in Figure 15(B) G It is preferable to make the amount of charge equal to the area of ​​the hatched portion including the portion due to the second pulse shown in FIG. 14(C). In this way, in the case of a method in which the second pulse is generated in advance and the amount of charge is fixed, the delay in generating the second pulse and the pulse time can be determined in advance based on FIG. 15(B). However, if the optimum conditions change depending on the operating conditions, the effect will be limited. On the other hand, by determining the delay and pulse width in advance, there is no need for current sensors, voltage sensors, or temperature sensors, or means for changing the pulse delay or width based on their data, making gate control easier.

[0083] ΔQ of the second pulse G When prioritizing loss reduction, the maximum value of the charge amount can be represented by arrow B shown in FIG. 15(B), although a graph corresponding to the maximum current and maximum voltage can be used. Furthermore, when prioritizing noise suppression, the graph corresponding to the minimum current and minimum voltage can be used, but when using the graph shown in FIG. 15, the value of arrow A can be used. Then, the resistor R2 of the current mirror circuit and the pulse width are determined. As the delay time by the second delay unit 221b is increased, ΔQ G Also, reduce the resistor R g1 , R g2 The ratio of the sum of R2 to R2 is 5 times or more (R g1 +R g2 >R1×5) is desirable. This is because the resistance R g1 ,R g2 A large value is desirable for noise suppression, and a small value is required for resistor R2 to reduce switching loss.

[0084] 15(B), the amount of charge that flows out of the gate electrode before the current starts to decrease under high current and low voltage conditions is indicated by arrow A. Also, the amount of charge that flows out of the gate electrode before the current starts to decrease under low current and high voltage conditions is indicated by arrow B.

[0085] The change in the value of the gate charge is small depending on the operating conditions when the IGBT 100 according to this embodiment is used, and ΔQ G This allows the amount and timing of the

[0086] In this way, the gate driver circuit 200 can add charge to the gate capacitance, which has a significant impact on switching loss and surge voltage during switching, when turned on, and extract charge from it when turned off. Therefore, the gate driver circuit 200 can reduce the surge voltage while reducing the switching loss. Therefore, the gate driver circuit 200 does not require controls such as changing the delay time, pulse time, resistors R1 and R2, etc. in accordance with the operating state of the IGBT. Therefore, by combining this gate drive circuit with the proposed IGBT, it is possible to reduce losses at low cost without requiring the installation of sensors for current, voltage, temperature, etc., or means for signal transmission and signal processing.

[0087] In the third embodiment, the first charge pulse generating unit 222a applies charge to the gate electrode G from the rising edge of the collector current Ic, and the second charge pulse generating unit 222b applies charge to the gate electrode G from the rising edge of the collector-emitter voltage V CE The charge is extracted from the gate electrode G from the rising edge of the gate electrode G. However, the first charge pulse generating unit 222a starts the collector-emitter voltage V from any timing between the PWM signal indicating turn-on and the rising edge of the collector current Ic, and the second charge pulse generating unit 222b starts the collector-emitter voltage V from any timing between the PWM signal indicating turn-off and the rising edge of the collector current Ic. CE Alternatively, the charge may be controlled from any timing between the rising edge of the first voltage and the falling edge of the second voltage.

[0088] By doing this, it is possible to reduce switching losses and shorten the time from when the PWM signal changes to when switching ends, which makes it possible to obtain a more accurate output waveform and shorten the shortest switching pulse width, thereby increasing the modulation rate of inverters, etc. Also, the amount of charge to be extracted can be calculated directly from Figure 15, making charge control easier.

[0089] In the gate driver circuit 200 shown in Fig. 12, the second pulse from the second charge pulse generating unit 222b is determined by the pulse width from the second delay unit 221b, but in the second charge pulse generating unit 222c shown in Fig. 16, a capacitor C1 is connected between resistor R2 and the collector of transistor Tr51, and a resistor R3 is connected between resistor R2 and the bases of transistors Tr51 and Tr52. Resistor R3 has a large resistance value for discharging capacitor C2. By configuring the second charge pulse generating unit 222c in this manner, if a second pulse is generated as a trigger from the second delay unit 221b, it is possible to always generate a pulse of a constant amount of charge by discharging the charge accumulated in the capacitor C2 without controlling the pulse width.

[0090] Although the gate driver circuit 200 according to the third embodiment has been described using the IGBT according to the present invention as an example, the present invention can be applied to any insulated gate controlled element, including conventional IGBTs. [Industrial Applicability]

[0091] The IGBT of the present invention is suitable for a trench gate type IGBT, and the gate driver circuit of the present invention is suitable as a drive circuit for an element whose conduction is controlled by a gate electrode, and is optimal as a drive circuit for the IGBT of the present invention. [Explanation of symbols]

[0092] 100,110 IGBT 101 n-type base layer 102 n-type buffer layer 103 p-type collector layer 104,114 High concentration n-type layer 105 p-type base layer 106 n-type source layer 107 Trench 108,118 Insulating film 108a Upper insulating film 108b, 118b Lower insulating film 108c Isolation insulating film Gate 109 109a Gate 1 109b, 119b 2nd Gate 119c slope C Collector electrode G gate electrode E Emitter electrode F1 Depth direction S1,S2,S3,Sx area 200 Gate driver circuit 210 PWM drive circuit 211 PWM amplifier circuit 220 Charge control circuit 221 Delay Circuit 221a First Delay Section 221b Second Delay Section 222 Charge pulse generating circuit 222a First charge pulse generating unit 222b, 222c Second charge pulse generating unit R G Gate resistor R g1 1st resistance R g2 2nd resistor R1,R2 resistance Tr1, Tr21, Tr22, Tr3, Tr4, Tr51, Tr52 transistors Vcc power supply

Claims

1. an n-type base layer; a p-type collector layer disposed on one surface side of the n-type base layer in a thickness direction and electrically connected to a collector electrode; a high-concentration n-type layer stacked on the other surface of the n-type base layer in the thickness direction, the high-concentration n-type layer having an average impurity concentration higher than that of the n-type base layer; a p-type base layer stacked on the high-concentration n-type layer; an n-type source layer stacked on the p-type base layer; an emitter electrode connected to the p-type base layer and the n-type source layer; an insulating film covering an inner surface of a trench formed in a depth direction from the n-type source layer to the n-type base layer; a gate formed inside the insulating film, the gate comprises a first gate connected to the gate electrode and formed to a depth position from the n-type source layer to the high-concentration n-type layer, and a second gate formed at a position deeper in the trench than the first gate via an isolation insulating film and fixed to the potential of the emitter electrode; the insulating film is formed to have a substantially constant thickness at a position corresponding to the second gate; an impurity concentration of the high-concentration n-type layer increases from a lower end position of the first gate toward the depth direction, reaches a peak below the second gate, and decreases toward the lower end of the high-concentration n-type layer;

2. 2. The insulated gate bipolar transistor according to claim 1, wherein the insulating film is formed so that an upper insulating film at a position corresponding to the first gate portion is thinner than a lower insulating film at a position corresponding to the second gate portion.

3. 3. The insulated gate bipolar transistor according to claim 1, wherein the distance between the trenches is set to 0.6 [mu]m or more and 1.2 [mu]m or less.

4. 4. A gate driver circuit comprising: a charge control circuit that controls charge on a gate capacitance depending on whether the transistor is turned on or off when a PWM signal is output to the gate electrode of the insulated gate bipolar transistor according to claim 1 to 3, and when switching is controlled by the PWM signal.

5. 5. The gate driver circuit according to claim 4, wherein the charge control circuit comprises: a first charge pulse generating unit that adds charge to the gate electrode from any timing between a PWM signal indicating turn-on and a rising edge of the collector current, until before the peak of the rising edge of the collector current; and a second charge pulse generating unit that draws charge from the gate electrode from any timing between a PWM signal indicating turn-off and a rising edge of the collector-emitter voltage, until before the peak of the collector-emitter voltage.

6. the first charge pulse generating section applies charge to the gate electrode from the rising edge of the collector current to before the peak of the rising edge of the collector current; 6. The gate driver circuit according to claim 5, wherein the second charge pulse generating section draws charge from the gate electrode from the rising edge of the collector-emitter voltage until before the collector-emitter voltage reaches its peak.

7. 7. The gate driver circuit according to claim 4, wherein the charge control circuit adds charge to the gate capacitance when a tail voltage of the collector-emitter voltage remains at the time of turn-on.

8. 8. The gate driver circuit according to claim 5, wherein the charge control circuit includes a delay unit that delays a pulse indicating turn-on and a pulse indicating turn-off indicated by the PWM signal until a predetermined timing.

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