Three-dimensional memory device and manufacturing method thereof

Abstract

A memory device architecture and a method for manufacturing a three-dimensional device are provided. The memory device architecture may include a plurality of memory blocks arranged in an array, where a given memory block comprises a cell region, the cell region comprising a three-dimensional array of memory cells arranged in a plurality of n memory cell layers, and a staircase region disposed adjacent at least a first side of the cell region, the staircase region comprising a signal line assembly coupled to the three-dimensional array of memory cells.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Non-Provisional Patent Application No. 17 / 868,156, entitled "THREE DIMENSIONAL MEMORY DEVICE AND METHOD OF FABRICATION," filed July 19, 2022, which is a continuation of U.S. Provisional Patent Application No. 63 / 248,799, entitled "THREE DIMENSIONAL MEMORY DEVICE AND METHOD OF FABRICATION," filed September 27, 2021, and which is incorporated herein by reference in its entirety.

[0002] The present embodiments relate to semiconductor substrates, and more particularly to three-dimensional semiconductor device structures. [Background technology]

[0003]

[0003] A trend in the development of integrated circuit-based semiconductor technology is an increase in device density within a semiconductor die and an increase in device functionality. For memory devices, such as dynamic random access memory (DRAM), one factor in improving the memory size for a DRAM chip for a given die area is to reduce the cell size for individual memory cells. Reducing cell size is associated with several well-known problems.

[0004] One envisioned approach to increasing memory size within a given die area is to fabricate three-dimensional memories, such as three-dimensional (3D) DRAMs. In this case, multiple memory cells may be stacked layer by layer in a “vertical” direction, orthogonal to the major plane of the semiconductor die. A challenge with forming such devices is the ability to address all cells in the memory array. For example, DRAM memory may be organized into blocks or subarrays, and every word line for a given stack of layers in a 3D DRAM subarray has a contact for connecting the word line with a controlling circuit within the subarray. As a result, in a 3D DRAM memory stack with n layers, a total of n word line contacts are required for each row of word lines. Therefore, the area for configuring such a word line contact architecture, such as in the peripheral region adjacent to the subarray, may consume a large portion of the (two-dimensional, in-plane) device area of ​​a given memory subarray. Furthermore, the size of this peripheral word line area increases with the number of layers n in the 3D DRAM memory array or subarray. Thus, in a 3D DRAM, as the number of layers increases, the peripheral word line area tends to consume a significantly larger portion of the overall DRAM area.

[0005] It is with respect to these and other considerations that the present disclosure is provided. Summary of the Invention

[0006] In one embodiment, a memory device architecture is provided. The memory device architecture may include a plurality of memory blocks arranged in an array. A given memory block may include a cell region comprising a three-dimensional array of memory cells, the cell region being composed of a plurality of n memory cell layers, and a staircase region disposed adjacent to at least a first side of the cell region, the staircase region comprising a signal line assembly coupled to the three-dimensional array of memory cells.

[0007] In another embodiment, a method for fabricating a three-dimensional device may include providing a memory stack on a substrate, the memory stack comprising a plurality of n unit stacks, where a given unit stack comprises an isolation layer, a sacrificial layer, and an active layer. The method may also include patterning the memory stack to form a plurality of memory blocks arranged in an array. As such, the given memory block may include a cell region comprising a three-dimensional array of memory cells composed of a plurality of n memory cell layers, and a staircase region disposed adjacent to at least a first side of the cell region, the staircase region comprising a signal line assembly coupled to the three-dimensional array of memory cells.

[0008] In a further embodiment, a three-dimensional dynamic random access memory may include a plurality of memory blocks arranged in an array. A given memory block may include a cell region comprising a three-dimensional array of memory cells configured in a plurality of n memory cell layers. The cell region may further comprise a first plurality of bit lines extending along a first direction and a second plurality of word lines configured in the plurality of n memory cell layers and extending along a second direction different from the first direction. The given memory block may also include a staircase region disposed adjacent to at least a first side of the cell region, the staircase region comprising a word line assembly connected to the second plurality of word lines of the three-dimensional array of memory cells. [Brief explanation of the drawings]

[0009] [Figure 1A] FIG. 2 is a top view of a memory array according to an embodiment of the present disclosure. [Figure 1B] FIG. 2 is a top view of a portion of a memory block according to an embodiment of the present disclosure. [Figure 1C] FIG. 1C is an enlarged top view of a region of the memory block portion of FIG. 1B, according to one embodiment of the present disclosure. [Figure 1D]FIG. 1C is an enlarged top view of a region of the memory block portion of FIG. 1B according to another embodiment of the present disclosure. [Figure 1E] FIG. 1C is an enlarged top view of a region of the memory block portion of FIG. 1B according to another embodiment of the present disclosure. [Figure 1F] 10A-10C illustrate two enlarged top views of a memory block and respective regions along opposite sides of the memory block, according to additional embodiments of the present disclosure. [Figure 1G] 1F shows a variation of the staircase structure shown in FIG. 1F according to an embodiment of the present disclosure. [Figure 1H] 1F shows a variation of the staircase structure shown in FIG. 1F according to an embodiment of the present disclosure. [Figure 2A] 1A-1C are top views of memory blocks during various stages of fabrication according to one embodiment of the present disclosure. [Figure 2B] 2B is a cross-sectional view of the memory block of FIG. 2A taken along cross section A. FIG. [Figure 2C] 2B is a cross-sectional view of the memory block of FIG. 2A taken along cross section B. FIG. [Figure 3A] 2B is a top view of the memory block of FIG. 2A during a subsequent stage of fabrication. [Figure 3B] 3B is a cross-sectional view of the memory block of FIG. 3A taken along cross section A. FIG. [Figure 3C] 3B is a cross-sectional view of the memory block of FIG. 3A taken along cross section B. FIG. [Figure 3D] FIG. 3B is a cross-sectional view of the memory block of FIG. 3A taken along cross section B'. [Figure 4A] FIG. 3B is a top view of the memory block of FIG. 3A during a subsequent stage of fabrication. [Figure 4B] 4B is a cross-sectional view of the memory block of FIG. 4A taken along cross section A. FIG. [Figure 4C] 4B is a cross-sectional view of the memory block of FIG. 4A taken along section C. FIG. [Figure 4D] 4B is a cross-sectional view of the memory block of FIG. 4A taken along cross section B. FIG. [Figure 5A] FIG. 4B is a top view of the memory block of FIG. 4A during a subsequent stage of fabrication. [Figure 5B] 5B is a cross-sectional view of the memory block of FIG. 5A taken along cross section A. FIG. [Figure 5C] FIG. 5B is a cross-sectional view of the memory block of FIG. 5A taken along section C. [Figure 5D] 5B is a cross-sectional view of the memory block of FIG. 5A taken along cross section B. FIG. [Figure 6A] FIG. 5B is a top view of the memory block of FIG. 5A during a subsequent stage of fabrication. [Figure 6B] 6B is a cross-sectional view of the memory block of FIG. 6A taken along cross section A. FIG. [Figure 6C] FIG. 6B is a cross-sectional view of the memory block of FIG. 6A taken along cross section B. [Figure 7A] 6C is a cross-sectional view of the memory block of FIG. 6B along section A at a subsequent stage of fabrication. [Figure 7B] 7B is a cross-sectional view of the memory block of FIG. 7A taken along cross section B. FIG. [Figure 8A] 7B is a top view of the memory block of FIG. 7A during a subsequent stage of fabrication. [Figure 8B] 8B is a cross-sectional view of the memory block of FIG. 8A taken along cross section A. FIG. [Figure 8C] FIG. 8C shows an enlarged portion of FIG. 8B along cross section A. [Figure 8D] 8B is a cross-sectional view of the memory block of FIG. 8A taken along cross section B. FIG. [Figure 9A] 8B is a top view of the memory block of FIG. 8A during a subsequent stage of fabrication. [Figure 9B] 9B is a cross-sectional view of the memory block of FIG. 9A taken along cross section A. FIG. [Figure 9C] 9B is a cross-sectional view of the memory block of FIG. 9A taken along cross section B. FIG. [Figure 10A] 9B is a top view of the memory block of FIG. 9A during a subsequent stage of fabrication. [Figure 10B] 10B is a cross-sectional view of the memory block of FIG. 10A taken along cross section A. FIG. [Figure 10C] 10B is a cross-sectional view of the memory block of FIG. 10A taken along cross section B. FIG. [Figure 11A]FIG. 10B is a top view of the memory block of FIG. 10A during a subsequent stage of fabrication. [Figure 11B] 11B is a cross-sectional view of the memory block of FIG. 11A taken along cross section A. FIG. [Figure 12A] FIG. 11B is a top view of the memory block of FIG. 11A during a subsequent stage of fabrication. [Figure 12B] 12B is a cross-sectional view of the memory block of FIG. 12A taken along cross section A. FIG. [Figure 13A] FIG. 12B is a top view of the memory block of FIG. 12A during a subsequent stage of fabrication. [Figure 13B] 13B is a cross-sectional view of the memory block of FIG. 13A taken along cross section A. FIG. [Figure 13C] 13B is a cross-sectional view of the memory block of FIG. 13A taken along cross section B. FIG. [Figure 14A] 13B is a partial cross-sectional view of the memory block of FIG. 12B along section A at an intermediate stage subsequent to the stage of FIG. 12B and prior to the stage of FIG. 13B. [Figure 14B] 13B is a partial cross-sectional view of the structure of FIG. 14A along section A at an intermediate stage subsequent to the stage of FIG. 14A and prior to the stage of FIG. 13B. [Figure 14C] 13B is a partial cross-sectional view of the structure of FIG. 14B along section A at an intermediate stage subsequent to the stage of FIG. 14B and prior to the stage of FIG. 13B. [Figure 14D] FIG. 13C is a partial cross-sectional view of the memory block of FIG. 13B. [Figure 15A] FIG. 13B is a top view of the memory block of FIG. 13A during a subsequent stage of fabrication. [Figure 15B] 15B is a cross-sectional view of the memory block of FIG. 15A taken along cross section A. FIG. [Figure 15C] 15B is a cross-sectional view of the memory block of FIG. 15A taken along cross section B. FIG. [Figure 16A] FIG. 15B is a top view of the memory block of FIG. 15A during a subsequent stage of fabrication. [Figure 16B] 16B is a cross-sectional view of the memory block of FIG. 16A taken along cross section A. FIG. [Figure 16C] FIG. 16B is a cross-sectional view of the memory block of FIG. 16A taken along cross section B. [Figure 17] FIG. 1 presents an exemplary process flow according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] The present embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which several embodiments are shown. The subject matter of this disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the subject matter to those skilled in the art. Like numbers refer to like elements throughout.

[0011] The present embodiments provide novel architectures for devices formed from three-dimensional (3D) arrays of unit structures, such as in memory devices or other semiconductor devices. These techniques may be particularly applicable to the formation of DRAM devices, although other devices may also be formed in accordance with embodiments of the present disclosure. Various non-limiting embodiments are particularly useful for implementations in which the array is organized as multiple blocks or sub-arrays connected to controlling circuitry.

[0012] In various embodiments of the present disclosure, a novel staircase architecture is coupled to blocks of a three-dimensional array of memory cells in a device. The novel staircase architecture may further include a novel signal line configuration, as described in more detail below. For purposes of explanation, a word line assembly for a three-dimensional memory array is disclosed in detail as representative of a signal line configuration according to some embodiments. The word line assembly may include an array of word lines configured to contact memory cells in multiple layers of the three-dimensional array of memory cells, as well as a word line contact assembly for coupling to control circuitry. However, this embodiment may extend to other signal lines for other three-dimensional device types, including non-volatile memory based on charge trap storage media or phase change materials, or storage media based on resistance changes.

[0013] Referring now to FIG. 1A, a top view of a memory array 100 is shown in accordance with an embodiment of the present disclosure. The memory array 100 may represent a DRAM array, for example, formed from a three-dimensional array of memory cells or memory bits, as follows: As shown in FIG. 1A, a two-dimensional array of subarrays can be seen, organized in an XY plane of a Cartesian coordinate system as shown. For purposes of explanation, where the memory array 100 may represent a DRAM array, the memory array 100 is arranged in a rectangular grid of subarrays, referred to as memory blocks 102. As further shown in FIG. 1B, according to an embodiment of the present disclosure, a given memory block 102 may include a cell region 104 and a staircase region 106 disposed adjacent to one side of the cell region 104. In particular, the cell region 104 may be arranged as a three-dimensional array of memory bits or memory cells distributed across n layers. According to various embodiments of the present disclosure, the value of "n" may be any suitable number up to or greater than 100 layers. Similarly, in various embodiments of the present disclosure, the staircase region 106 may be arranged as a series of n steps, which may provide access for control circuitry to contact the cell area using word line contacts configured within the staircase region 106, as described in further detail below.

[0014] For illustrative purposes, in cell region 104, 1000 memory cells may be organized per word line along the Y direction. Therefore, the view in FIG. 1B shows only an edge portion of cell region 104 adjacent to staircase region 106. FIG. 1C shows an enlarged top view of the memory block portion of FIG. 1B in accordance with one embodiment of the present disclosure. Memory cells 110 are shown along the edge of cell region 104, including capacitors 112, gates 114, and bit lines 116. Word line region structures 108 extend in staircase region 106. For a 250 nm cell width and 1024 memory cells, cell region 104 may have a width of 256 mm, and staircase region 106A in FIG. 1C has a width of 75 mm for a 100-layer-thick 3D memory. Therefore, staircase region 106A utilizes approximately 29% of the area of ​​memory block 102. Note that in this embodiment, the step width along the X direction may be equivalent to the width of the word lines along the X direction. Note that in this embodiment, as well as in the following embodiments, the word lines may extend along a first direction and the bit lines extend along a second direction, such as perpendicular to the first direction.

[0015] In other embodiments, staircase region 106 may be arranged differently to improve the efficiency of the layout of word line connections to cell region 104. FIG. 1D illustrates an enlarged top view of a region of the memory block portion of FIG. 1B according to another embodiment of the present disclosure. FIG. 1E illustrates an enlarged top view of a region of the memory block portion of FIG. 1B according to another embodiment of the present disclosure. The embodiment of FIG. 1E may represent a variation of the embodiment of FIG. 1D. Referring specifically to FIG. 1D, in this embodiment, staircase region 106B is disposed along one side of cell region 104. For clarity of illustration, staircase region 106B is shown as including four steps: step 120, step 122, step 124, and step 126. However, in other embodiments, staircase region 106 may include many more steps. Wordline structures 118 are formed within staircase region 106B, and the formation of such wordline structures is described in detail below. As can be seen in the top view of FIG. 1D , word line structure 118 occupies most of the area of ​​staircase region 106B. In the example of FIG. 1D , the step width, as well as the word line structure width, along the X direction is equal to the sum of the width of capacitor 112 and the word line width (of the word line structure of FIG. 1C ). In other words, the word line structure width is approximately equivalent to the bit width of a given memory cell along the X direction. The same applies to the embodiment of FIG. 1E , which also has staircase region 106C including four steps: step 140, step 142, step 144, and step 146. The difference between the two embodiments is that in the embodiment of FIG. 1E , at least one replacement slit and bridge (which portion may serve as a connecting portion) is provided for one word line.

[0016] 1F shows an enlarged top view of a memory block and two respective regions along opposite sides of the memory block, according to an additional embodiment of the present disclosure. In particular, cell region 104 is flanked by staircase regions 106D and 106E, respectively, located on opposite sides. Note that in staircase region 106E, the top bit B1 is connected to the corresponding word line structure in staircase region 106E, and in staircase region 106D, the bottom bit B2 is connected to the corresponding word line structure in staircase region 106D. In this example, the staircase width along the X direction (as well as the word line structure width) may be expanded by twice the sum of the word line width and the capacitor width, or 2*(WL width + Cap width), or equivalently twice the memory cell width.

[0017] 1G and 1H, two variations of the staircase structure shown in FIG. 1F are shown. As shown in FIG. 1G, the 2i-th set of WLs (in the WL direction) is connected to the right side of the cell region 104, and the 2i+1-th set of WLs is connected to the left side of the cell region 104. Each set of WLs (2i+1 or 2i in the WL direction) has n WLs stacked in the z direction. On the right / left side of the array, each set of WLs (2i+1 or 2i in the WL direction) has a staircase with a height ranging from the first unit cell to the nth unit cell. In particular, FIG. 1G presents an embodiment in which one height exists in one unit step width, while in the embodiment of FIG. 1H, two heights exist in one unit step width. Therefore, the embodiment of FIG. 1H has a smaller staircase area than the embodiment of FIG. 1G.

[0018] 2A-16C below, various views of an embodiment of the memory cell architecture of FIG. 1C are shown at different stages of fabrication. While this fabrication sequence has particular application to 3D DRAM, in other embodiments of the present disclosure, the general staircase fabrication principles as illustrated herein below may be applied to any other device structure in which signal lines connect to stacked conductive layers in a 3D device.

[0019] FIG. 2A illustrates a top view of a memory block corresponding to the embodiment of FIG. 1D during a stage of fabrication, according to one embodiment of the present disclosure. In this example, the view is rotated 90 degrees relative to the view of FIG. 1D. FIG. 2B illustrates a cross-sectional view of the memory block of FIG. 2A along cross-section A, and FIG. 2C illustrates a cross-sectional view of the memory block of FIG. 2A along cross-section B. As shown in FIG. 2A, a portion of cell region 104 abuts staircase region 106B. As further illustrated in FIGS. 2B and 2C, a series of unit stacks 202 are shown that make up different layers of a 3D memory block. A given unit stack is formed, in turn, from multiple layers, including an active layer. In some embodiments, a unit stack 202 is formed from an insulating layer 204, such as SiO, a sacrificial layer 206, such as SiN, and an active layer 208, such as polysilicon. These layers may be deposited in a blanket manner over at least the region of the memory device that will form the memory block. According to some embodiments, the thickness range for the insulating layer 204, the sacrificial layer 206, and the active layer 208 may be within a range of 5 nm to 50 nm for any of these layers. In this embodiment, a total of four unit stacks 202 are deposited to form the layer stack 200, which corresponds to four different memory layers of the 3D memory device. As shown in Figures 2A and 2B, at this stage, both the cell region 104 and the staircase region 106B are unpatterned.

[0020] Figure 3A shows a top view of the memory block of Figure 2A during a subsequent stage of fabrication, in which patterning of staircase region 106B has occurred. Figure 3B shows a cross-sectional view of the memory block of Figure 3A along cross section A, showing that cell region 104 remains unpatterned.

[0021] FIG. 3C shows a cross-sectional view of the memory block of FIG. 3A along cross section B, which intersects steps 140 and 142 of staircase region 106B. FIG. 3D shows a cross-sectional view of the memory block of FIG. 3A along cross section B′, which intersects steps 144 and 146 of staircase region 106B. As shown, patterning has been performed to form the individual steps. Patterning can be performed using known techniques for selectively opening targeted areas of staircase region 106B. In one example, a first patterning process etches region 302, and a second patterning process etches region 304, as shown. After etching the individual steps, a dielectric 148, such as SiO , is deposited to fill the etched areas. Dielectric 148 can then be planarized using known processes, such as chemical-mechanical polishing.

[0022] As shown in FIG. 3C, the upper surface 222 of step 140 represents the top layer of layer stack 200, the upper surface of step 142 is recessed from upper surface 222 by one unit stack 202, the upper surface of step 144 is recessed from upper surface 222 by two unit stacks 202, and the upper surface of step 146 is recessed from upper surface 222 by three unit stacks 202.

[0023] FIG. 4A shows a top view of the memory block of FIG. 3A during a subsequent stage of fabrication. FIG. 4B shows a cross-sectional view of the memory block of FIG. 4A along cross section A, and FIG. 4C shows a cross-sectional view of the memory block of FIG. 4A along cross section C. FIG. 4D shows a cross-sectional view of the memory block of FIG. 4A along cross section B. As shown in FIGS. 4A-4B, isolation regions 212 are formed in cell region 104 and in staircase region 106B by etching throughout layer stack 200.

[0024] FIG. 5A shows a top view of the memory block of FIG. 4A during a subsequent stage of fabrication. FIG. 5B shows a cross-sectional view of the memory block of FIG. 5A along cross-section A, FIG. 5C shows a cross-sectional view of the memory block of FIG. 5A along cross-section C, and FIG. 5D shows a cross-sectional view of the memory block of FIG. 5A along cross-section B. At this stage, fill insulation (e.g., SiO) has been formed in isolation region 212, which creates filled isolation region 220. Planarization can then be performed to result in the structure shown in FIGS. 5B-5D.

[0025] FIG. 6A shows a top view of the memory block of FIG. 5A during a subsequent stage of fabrication, FIG. 6B shows a cross-sectional view of the memory block of FIG. 6A along cross-section A, and FIG. 6C shows a cross-sectional view of the memory block of FIG. 6A along cross-section B. At this stage, patterning has been performed to form replacement gate structures in transistors to be formed in memory cells of cell region 104. Patterning involves etching the entire layer stack 200 to form continuous slits 240 that extend into cell region 104 and into staircase region 106B, as specifically shown in FIG. 6A. Also shown in FIG. 6A, discontinuous slits 242 are formed in staircase region 106B, with bridge portions 245 separating different portions of discontinuous slits 242. Discontinuous slits 242 separate main portions 244 of staircase region 106B from each other.

[0026] 7A shows a cross-sectional view of the memory block of FIG. 6B along cross section A at a subsequent stage of fabrication, and FIG. 7B shows a cross-sectional view of the memory block of FIG. 7A along cross section B. At this stage of processing, a portion of the sacrificial layer 206 adjacent to the continuous slit 240 has been selectively etched to form a recess 243. Similarly, the sacrificial layer 206 can be etched in the staircase region 106B, which forms a recess 241. The selective etching can be performed, for example, by providing a selective etchant through the continuous slit 240 and along the discontinuous slit 242. When the sacrificial layer 206 is silicon nitride (SiN), the active layer 208 is silicon, and the insulating layer 204 is silicon oxide (SiO), hot phosphoric acid can be a suitable example of a selective etchant.

[0027] 8A shows a top view of the memory block of FIG. 7A during a subsequent stage of fabrication, FIG. 8B shows a cross-sectional view of the memory block of FIG. 8A along cross section A, and FIG. 8C shows an enlarged portion of FIG. 8B along cross section A. FIG. 8D shows a cross-sectional view of the memory block of FIG. 8A along cross section B. At this stage of fabrication, transistor formation has occurred by forming a gate oxide layer 247 over exposed portions of active layer 208 adjacent continuous slit 240. In various non-limiting embodiments, the gate oxide can be a suitable insulator, such as a 2 nm to 10 nm thick layer of silicon oxide.

[0028] Additionally, a word line assembly is formed, shown as word line portion 248 disposed in cell region 104 and word line structure 246 disposed in staircase region 106B. As shown in FIG. 8D , word line structure 246 forms in recess 241 previously formed in main portion 244 of staircase region 106B. In the view of FIG. 8A , word line structure 246 may correspond to two or more word lines. Thus, as a result of the structure of main portion 244, on a given step, the word line structure may have two or more main portions, such as first main portion 246A and second main portion 246B, as shown. According to some non-limiting embodiments, the word line structure may be formed using a metallurgy, such as a TiN liner layer 249A and a tungsten portion 249B. To form word line portion 248, such metallurgy may be deposited in recess 243 using any suitable process, including atomic layer deposition (ALD), to provide deposition species through continuous slit 240. Node isolation may then be performed by removing the TiN and W from continuous slit 240, which shows continuous slit 240 empty again, as shown in Figures 8B and 8C. Similarly, this metal may also be deposited in recess 241 in staircase region 106B through continuous slit 240 and discontinuous slit 242.

[0029] 9A shows a top view of the memory block of FIG. 8A during a subsequent stage of fabrication, FIG. 9B shows a cross-sectional view of the memory block of FIG. 9A along cross-section A, and FIG. 9C shows a cross-sectional view of the memory block of FIG. 9A along cross-section B. At this stage of processing, the continuous slits 240 and the discontinuous slits 242 have been filled with an insulator, which forms isolation structures 250. Isolation structures 250 are formed by a suitable deposition process, such as atomic layer deposition of silicon oxide, according to some non-limiting embodiments. Planarization can then be performed, resulting in structures such as those shown in FIGS. 9B and 9C, among others.

[0030] 10A shows a top view of the memory block of FIG. 9A during a subsequent stage of fabrication, FIG. 10B shows a cross-sectional view of the memory block of FIG. 10A along cross section A, and FIG. 10C shows a cross-sectional view of the memory block of FIG. 10A along cross section B. At this stage, the structure of staircase region 106B remains unchanged from the structure of FIG. 9C, as shown in FIG. 10C. In cell region 104, capacitor slits 260 are formed by etching all the way through layer stack 200.

[0031] FIG. 11A shows a top view of the memory block of FIG. 10A during a subsequent stage of fabrication, and FIG. 11B shows a cross-sectional view of the memory block of FIG. 11A along cross section A. At this stage, the structure of staircase region 106B (not shown) has not changed from the structure of FIG. 10C. In cell region 104, specifically as shown in FIG. 11B, a capacitor recess 262 has been formed by etching a portion of active layer 208. This etching may be performed in a selective manner to selectively remove polysilicon relative to silicon nitride and silicon oxide, for example, if active layer 208 is silicon or polysilicon.

[0032] FIG. 12A shows a top view of the memory block of FIG. 11A during a subsequent stage of fabrication, and FIG. 12B shows a cross-sectional view of the memory block of FIG. 12A along cross section A. At this stage, the structure of staircase region 106B (not shown) remains unchanged from that of FIG. 10C. In cell region 104, as particularly shown in FIG. 12B, an enlarged capacitor recess 264 is formed by etching a portion of insulating layer 204, a portion of sacrificial layer 206, and a greater portion of active layer 208. This etching may be performed by one or more etch processes, and a given etch process may be performed in a selective manner according to some embodiments. For example, if active layer 208 is silicon or polycrystalline silicon, one etch process may be performed in a selective manner to selectively remove polycrystalline silicon relative to silicon nitride and silicon oxide. For example, multiple selective etch processes may be performed sequentially in a given process chamber or bath, or may be performed in different chambers.

[0033] 13A shows a top view of the memory block of FIG. 12A during a subsequent stage of fabrication, FIG. 13B shows a cross-sectional view of the memory block of FIG. 13A along cross section A, and FIG. 13C shows a cross-sectional view of the memory block of FIG. 13A along cross section B. At this stage, the structure of staircase region 106B (not shown) has not changed from the structure of FIG. 10C. As shown in FIGS. 13A and 13B, a capacitor 280 has been formed in cell region 104. Details of the formation of capacitor 280 according to some non-limiting embodiments of the present disclosure are described below.

[0034] In particular, Figure 14A shows a partial cross-sectional view of the memory block of Figure 12B along cross section A at an intermediate stage subsequent to the stage of Figure 12B and prior to the stage of Figure 13B. Similarly, Figure 14B shows a partial cross-sectional view of the structure of Figure 14A along cross section A at an intermediate stage subsequent to the stage of Figure 14A and prior to the stage of Figure 13B. Similarly, Figure 14C shows a partial cross-sectional view of the structure of Figure 14B along cross section A at an intermediate stage subsequent to the stage of Figure 14B and prior to the stage of Figure 13B. Figure 14D shows a partial cross-sectional view of the memory block of Figure 13B.

[0035] Referring now to FIG. 14A, the structure is shown after deposition of a bottom electrode layer 266, such as a TiN layer or other suitable electrode material layer. In FIG. 14B, the structure is shown after formation of a capacitor storage layer 268, which may be a suitable high-k layer. A non-limiting example of a suitable high-k layer is HfZrO. In FIG. 14C, the structure is shown after formation of a top electrode 270, such as a TiN layer or other suitable electrode material layer. In FIG. 14D, the structure is shown after formation of a second top electrode 272, such as a SiGe material. It should be noted that the materials shown in FIGS. 14A-14D are examples only, and other suitable capacitor materials as known in the art may be used in accordance with additional embodiments of the present disclosure.

[0036] Figure 15A shows a top view of the memory block of Figure 13A during a subsequent stage of fabrication, Figure 15B shows a cross-sectional view of the memory block of Figure 15A along cross section A, and Figure 15C shows a cross-sectional view of the memory block of Figure 15A along cross section B. At this stage of processing, contact patterns 284 have been defined on the top surface of the memory block structure in cell region 104 as well as in staircase region 106B. Contact patterns 284 define areas for forming bit line and word line contacts.

[0037] FIG. 16A shows a top view of the memory block of FIG. 15A during a subsequent stage of fabrication, FIG. 16B shows a cross-sectional view of the memory block of FIG. 16A along cross section A, and FIG. 16C shows a cross-sectional view of the memory block of FIG. 16A along cross section B. At this stage of processing, bit lines 288 are shown, including bit line contacts; a combination of TiN and W may be used for this process. Additionally, a word line contact assembly made up of multiple word line contacts 286 has been formed in staircase region 106B. The cross section of FIG. 16C shows two word line contacts, one at step 140 and the other at step 142.

[0038] Although the process flow highlighted in the above figures shows a four-step staircase embodiment, three-dimensional device embodiments having many more memory cell layers can include staircase embodiments having the same number of steps, i.e., unit stacks, as the number of memory cell layers. In staircase embodiments having tens of steps, or even more than 100 steps, the corresponding word line contact assembly can include word line contacts on the top word line structure of each given step.

[0039] 17 shows an exemplary process flow 400 according to an embodiment of the present disclosure. In block 402, a memory stack is deposited on a substrate, such as a silicon substrate or other semiconductor substrate. The memory block may include a plurality of n unit stacks, with a given unit stack including an insulating layer, a sacrificial layer, and an active layer. The value of n may range from a few layers to 100 or more layers according to various non-limiting embodiments. In some embodiments, the isolation layer includes silicon oxide, the sacrificial layer includes, in part, silicon nitride, and the active layer includes polycrystalline silicon.

[0040] In block 404, the memory stack is patterned to form a cell area including a three-dimensional array of memory cells made up of a plurality of n memory cell layers, with a given memory cell layer corresponding to a given unit stack of the plurality of n unit stacks.

[0041] At block 406, the memory stack is further patterned to form a staircase region in an area adjacent to the cell region, the staircase region including word line assemblies coupled to the three-dimensional array of memory cells. In some embodiments, the staircase region may comprise multiple staircase regions configured on multiple sides of the memory array. In some embodiments, the patterning to form the staircase region may be performed in a series of processes, and in at least one process, the patterning to form the staircase region coincides with the patterning to form the cell region.

[0042] The present embodiments offer various advantages over known processes for forming devices, such as arrays of semiconductor structures, for forming DRAM transistors. One advantage is that device structures, such as 3D DRAM arrays, can be formed such that word line assemblies are efficiently located in the peripheral staircase region without consuming excessive area of ​​a given DRAM sub-array. A further advantage provided by the present embodiments is increased word line width in the staircase region, which allows for wider process margins for easier word line contact formation. For example, word line widths can be extended from a range of 50 nm to 200 nm in the cell region to widths equal to or exceeding the width of an entire memory cell.

[0043] The present disclosure should not be limited in scope by the specific embodiments described herein. Indeed, various other embodiments and modifications of the present disclosure, in addition to those described herein, will be apparent to those skilled in the art from the foregoing description and the accompanying drawings. Accordingly, such other embodiments and modifications are likely to fall within the scope of the present disclosure. Moreover, while the present disclosure has been described herein in the context of particular implementations in particular environments for particular purposes, those skilled in the art will recognize that its usefulness is not limited thereto, and that the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be construed in light of the full breadth and spirit of the present disclosure as described herein.

Claims

1. Multiple memory blocks arranged in an array 1. A memory device architecture, wherein a given memory block comprises: a cell region, the cell region comprising a three-dimensional array of memory cells arranged in a plurality of n memory cell layers; a staircase region disposed adjacent to at least a first side of the cell region, the staircase region comprising: a signal line assembly including a word line assembly coupled to the three-dimensional array of memory cells; a plurality of n stages, a given stage of the plurality of n stages including a topmost word line structure of the word line assembly; a word line contact assembly, wherein a given word line contact of the word line contact assembly is connected to the topmost word line structure of the given stage; a staircase region comprising: Equipped with a given memory cell of the plurality of memory cells includes a memory cell width along a first direction, and at a given step of the staircase region, the top word line structure has a word line width along the first direction that is at least equivalent to the memory cell width; Memory device architecture.

2. 2. The memory device architecture of claim 1, wherein said top word line structure is connected to a given row of memory cells of a given memory cell layer of said cell region.

3. Within a given stage, the word line structure: a first main portion disposed on the first part of the given stage; a second main portion disposed on the second part of the given stage; and a connecting portion disposed to electrically connect the first main portion to the second main portion; 10. The memory device architecture of claim 1, comprising:

4. a given memory cell layer of the plurality of memory cell layers, an insulating layer; a sacrificial layer disposed below the insulating layer; an active layer disposed below the sacrificial layer; 10. The memory device architecture of claim 1, comprising:

5. The memory device architecture of claim 4 , wherein said signal line assembly extends from said staircase region into said cell region within said sacrificial layer.

6. the insulating layer comprises silicon oxide; the sacrificial layer comprises, in part, silicon nitride; the active layer comprises polycrystalline silicon; The memory device architecture of claim 4.

7. The staircase region is a first staircase region disposed adjacent the first side of the cell region; a second staircase region disposed adjacent to a second side of the cell region opposite the first side of the cell region; and 10. The memory device architecture of claim 1, comprising:

8. 8. The memory device architecture of claim 7, wherein the signal line assembly comprises a word line assembly, a given memory cell comprises a memory cell width along a first direction, and at a given step of the staircase region, the word line assembly has a word line width along the first direction that is twice the memory cell width.

9. 1. A method for manufacturing a three-dimensional device, comprising: providing a memory stack on a substrate, the memory stack including a plurality of n unit stacks, each unit stack including an insulating layer, a sacrificial layer, and an active layer; patterning the memory stack to form a plurality of memory blocks arranged in an array; and a given memory block includes: a cell region, the cell region including a three-dimensional array of memory cells arranged in a plurality of n memory cell layers; a staircase region disposed adjacent to at least a first side of the cell region, the staircase region including a signal line assembly coupled to the three-dimensional array of memory cells; A method comprising:

10. 10. The method of claim 9, wherein the staircase region is formed by etching the memory stack to form a plurality of n steps.

11. said patterning said memory stack further comprising: etching a continuous slit extending from the cell region into the staircase region; etching a plurality of discontinuous slits in the step region; Including, the continuous slit and the plurality of discontinuous slits extend through the plurality of n unit stacks of the memory stack; 10. The method of claim 9.

12. The patterning of the memory stack comprises: Selectively etching the sacrificial layer through the continuous slit and through the plurality of discontinuous slits, wherein a plurality of first recesses are formed in the cell region and a plurality of second recesses are formed in the staircase region. The method of claim 11 further comprising:

13. The patterning of the memory stack comprises: depositing metal into the plurality of first recesses and into the plurality of second recesses to form the signal line assembly; The method of claim 12 further comprising:

14. the signal line assembly includes a word line assembly, and the staircase region includes: a plurality of n stages, wherein a given stage of the plurality of n stages includes a top word line structure of the word line assembly; and said method further comprises: forming a word line contact assembly, a given word line contact of the word line contact assembly being connected to the top word line structure of the given stage; 10. The method of claim 9, further comprising:

15. a given memory cell of the three dimensional array of memory cells includes a capacitor, the method comprising: forming the cell area by etching a plurality of capacitor slits, a given capacitor slit of the plurality of capacitor slits extending entirely through the memory stack; selectively etching the active layers of the plurality of n memory cell layers through the plurality of capacitor slits, whereby a plurality of capacitor recesses are formed; 10. The method of claim 9, further comprising:

16. Multiple memory blocks arranged in an array 1. A three-dimensional dynamic random access memory comprising: a cell region comprising a three-dimensional array of memory cells arranged in a plurality of n memory cell layers, the cell region further including: a first plurality of bit lines extending along a first direction; and a second plurality of word lines arranged in the plurality of n memory cell layers and extending along a second direction different from the first direction; a staircase region disposed adjacent to at least a first side of the cell region, the staircase region comprising: a word line assembly connected to the second plurality of word lines of the three-dimensional array of memory cells; a plurality of n stages, a given stage of the plurality of n stages including a topmost word line structure of the word line assembly; a word line contact assembly, wherein a given word line contact of the word line contact assembly is connected to the top word line structure of the given stage; The staircase area includes Including, a given memory cell of the plurality of memory cells includes a memory cell width along a first direction, and at a given step of the staircase region, the top word line structure has a word line width along the first direction that is at least equivalent to the memory cell width.

17. 17. The three dimensional dynamic random access memory of claim 16, wherein a top word line structure is connected to a given row of memory cells of a given memory cell layer of said plurality of n memory cell layers.

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