Semiconductor Devices

Abstract

To favorably connect between a source electrode and a peripheral electrode without segmenting a gate wiring line.SOLUTION: A semiconductor device comprises: a field insulation film that contacts with an upper surface of a semiconductor substrate in a range between a source electrode and a peripheral electrode; a gate wiring line that is arranged on a top part of the field insulation film and connects between a gate electrode and a gate pad; an interlayer insulation film that covers the gate wiring line; and a bridge wiring line that passes on the top part of the interlayer insulation film to extend from the source electrode to the peripheral electrode. A p-type body layer that comprises an extension part which extends from a position contacting with the source electrode to a position contacting with the peripheral electrode is provided in the semiconductor substrate. A distance L1 between the source electrode and the peripheral electrode in a first direction crossing the gate wiring line and a width L2 of the bridge wiring line in the first direction satisfy a relation of L2<L1 at any position in a range of the bridge wiring line.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a semiconductor device.

[0002] The semiconductor substrate of the semiconductor device disclosed in Patent Document 1 has an element region in which a gated switching element is provided. A source electrode is provided on the upper surface of the semiconductor substrate within the element region. A peripheral electrode is provided at a position spaced from the source electrode. The upper surface of the semiconductor substrate is covered with a field insulating film in the area between the source electrode and the peripheral electrode. A gate wiring is provided on top of the field insulating film. The gate wiring is a wiring connecting a gate electrode and a gate pad. The gate wiring is covered with an interlayer insulating film. The gate wiring extends along the outer periphery of the source electrode. A dividing region where the gate wiring is divided is provided around the source electrode. A bridge wiring (in other words, a short-circuit electrode) connecting the source electrode and the peripheral electrode is disposed in the dividing region. The gated switching element has a p-type body layer and an n-type drift layer within the semiconductor substrate. The body layer has an extension extending from a position contacting the source electrode to a position contacting the peripheral electrode. The drift layer is in contact with the body layer from below.

[0003] Avalanche breakdown may occur in the drift layer outside the device region. When avalanche breakdown occurs in the drift layer outside the device region, avalanche current flows to the source electrode via the body layer (i.e., the extension) above the drift layer. When the avalanche current flows, the potential of the extension increases, increasing the potential difference between the extension and the gate wiring, and a high voltage is applied to the field insulating film. This high voltage may damage the field insulating film. In contrast, in the semiconductor device of Patent Document 1, the extension contacts not only the source electrode but also the peripheral electrode. That is, the extension contacts the source electrode and the peripheral electrode, which are arranged on both sides of the field insulating film. The peripheral electrode is connected to the source electrode via a bridge wiring. Therefore, the avalanche current flows in a distributed manner between the source electrode and the peripheral electrode via the extension. This distributed flow of the avalanche current suppresses the increase in the potential of the extension and suppresses damage to the field insulating film. In this way, in the semiconductor device of Patent Document 1, damage to the field insulating film is suppressed when avalanche breakdown occurs. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-044274 Summary of the Invention [Problem to be solved by the invention]

[0005] In the semiconductor device of Patent Document 1, the gate wiring is divided in the dividing region. Therefore, it is necessary to provide gate electrodes and other wiring so that the divided gate wirings are electrically connected to each other. This imposes restrictions on the layout and may result in a reduction in the area of ​​the element region. This specification proposes a technology for suitably connecting the source electrode and peripheral electrode without dividing the gate wiring. [Means for solving the problem]

[0006] The semiconductor device disclosed in this specification includes a semiconductor substrate having an element region provided with a gate-type switching element, a source electrode contacting the upper surface of the semiconductor substrate within the element region, a gate pad disposed above the semiconductor substrate, a peripheral electrode contacting the upper surface of the semiconductor substrate at a position spaced apart from the source electrode, a field insulating film contacting the upper surface of the semiconductor substrate within the range between the source electrode and the peripheral electrode, a gate wiring disposed above the field insulating film, extending along the outer peripheral edge of the source electrode, and connecting the gate electrode of the gate-type switching element and the gate pad, an interlayer insulating film covering the gate wiring, and a bridge wiring extending from the source electrode to the peripheral electrode through the upper portion of the interlayer insulating film and insulated from the gate wiring by the interlayer insulating film. The gate-type switching element is provided inside the semiconductor substrate and includes a p-type body layer having an extension portion extending from a position contacting the source electrode to a position contacting the peripheral electrode, and an n-type drift layer contacting the body layer from below. When the direction crossing the gate wiring when viewing the semiconductor substrate from above is defined as the first direction, the distance between the source electrode and the peripheral electrode in the first direction is defined as interval L1, and the width of the bridge wiring in the first direction is defined as width L2, the relationship L2 < L1 is satisfied at any position within the range of the bridge wiring.

[0007] In this semiconductor device, the bridge wiring extends from the source electrode to the peripheral electrode through the upper part of the interlayer insulating film covering the gate wiring. Therefore, the source electrode and the peripheral electrode can be connected by the bridge wiring without cutting the gate wiring. Also, in this structure, since the interlayer insulating film covers the gate wiring, the interlayer insulating film has a stepped portion along the shape of the gate wiring. Therefore, the bridge wiring covers the stepped portion of the interlayer insulating film. When the semiconductor device generates heat, a high thermal stress is applied to the stepped portion by the bridge wiring. If the thermal stress applied to the stepped portion becomes excessive, the interlayer insulating film and the gate wiring under the bridge wiring may be damaged. The thermal stress applied from the bridge wiring to the stepped portion increases as the width of the bridge wiring in the first direction crossing the gate wiring becomes wider. In the above semiconductor device, when the distance between the source electrode and the peripheral electrode in the first direction is defined as interval L1 and the width of the bridge wiring in the first direction is defined as width L2, the relationship L2 < L1 is satisfied at any position within the range of the bridge wiring. Since the width L2 is set small in this way, it is possible to prevent the thermal stress applied from the bridge wiring to the stepped portion from becoming excessive. Therefore, in this semiconductor device, damage to the interlayer insulating film and the gate wiring under the bridge wiring can be suppressed.

Brief Description of the Drawings

[0008] [Figure 1] Plan view of the semiconductor device of the embodiment. [Figure 2] Cross-sectional view taken along line II-II of FIG. 1. [Figure 3] Enlarged plan view of the bridge wiring. [Figure 4] Cross-sectional view taken along line IV-IV of FIG. 3. [Figure 5] Cross-sectional view taken along line V-V of FIG. 3. [Figure 6] Cross-sectional view of the bridge wiring of the comparative example. [Figure 7] Enlarged plan view of the bridge wiring of the modified example. [Figure 8] Enlarged plan view of the bridge wiring of the modified example.

Mode for Carrying Out the Invention

[0009] In the semiconductor device described above, the bridge wiring may be provided with a slit that extends along a direction intersecting the first direction when the semiconductor substrate is viewed from above.

[0010] According to this configuration, the relationship of L2 < L1 can be easily obtained.

[0011] In the semiconductor device described above, the body layer may include a contact p-layer and a low-concentration p-layer that has a lower p-type impurity concentration than the contact p-layer and contacts the contact p-layer from below. In the extension portion, the contact p-layer may extend from the position where it contacts the source electrode to the position where it contacts the peripheral electrode.

[0012] According to this configuration, an avalanche current can flow through the contact p-layer with low resistance, and the potential rise of the extension portion can be more effectively suppressed.

[0013] In the semiconductor device described above, the semiconductor substrate may be made of silicon carbide.

[0014] The semiconductor device 10 of the embodiment shown in FIG. 1 has a semiconductor substrate 12. The semiconductor substrate 12 is made of SiC (that is, silicon carbide). However, the semiconductor substrate 12 may be made of other semiconductors such as Si and GaN. The semiconductor substrate 12 has an element region 20 and a peripheral region 22. The element region 20 is a region where a MOSFET (metal-oxide-semiconductor field effect transistor) is provided. The element region 20 is arranged at the center of the semiconductor substrate 12. The peripheral region 22 is a region around the element region 20. The peripheral region 22 is arranged between the element region 20 and the outer peripheral surface 12c of the semiconductor substrate 12. Hereinafter, a direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x direction, and a direction parallel to the upper surface 12a and orthogonal to the x direction is referred to as the y direction.

[0015] 1 and 2, a source electrode 30 is provided on the upper surface 12a of the semiconductor substrate 12. The source electrode 30 is disposed in the element region 20. The source electrode 30 contacts the upper surface 12a of the semiconductor substrate 12 within the element region 20.

[0016] 2, a drain electrode 32 is provided on the lower surface 12b of the semiconductor substrate 12. The drain electrode 32 is distributed across the element region 20 and the peripheral region 22. The drain electrode 32 contacts the lower surface 12b of the semiconductor substrate 12 within the element region 20 and the peripheral region 22.

[0017] 2, a field insulating film 40 is provided on the upper surface 12a of the semiconductor substrate 12. The field insulating film 40 covers the upper surface 12a in the peripheral region 22.

[0018] As shown in FIG. 1, a gate pad 49 and a gate wiring 44 are provided on the upper surface 12a of the semiconductor substrate 12. In FIG. 1, the gate pad 49 and the gate wiring 44 are indicated by diagonal hatching. The gate wiring 44 extends along the outer periphery of the source electrode 30. The gate wiring 44 has a ring shape that surrounds the periphery of the source electrode 30 and is connected to the gate pad 49. The gate wiring 44 is insulated from the source electrode 30 and a peripheral electrode 42 (described later). Although not shown, the gate pad 49 is disposed on an insulating film and is insulated from the semiconductor substrate 12. As shown in FIG. 2, the gate wiring 44 is a wiring that connects the gate pad 49 and a gate electrode 38 (described later). The gate wiring 44 is disposed on a field insulating film 40. The gate wiring 44 is insulated from the semiconductor substrate 12 by the field insulating film 40. The gate wiring 44 has a lower layer 44a and an upper layer 44b. The lower layer 44a is made of polysilicon. The lower layer 44a is in contact with the upper surface of the field insulating film 40. The upper layer 44b is made of AlSi (that is, an alloy of aluminum and silicon). The upper layer 44b is in contact with the upper surface of the lower layer 44a.

[0019] As shown in FIG. 2, an interlayer insulating film 46 is provided on the upper surface 12a of the semiconductor substrate 12. The interlayer insulating film 46 covers the upper surface 12a and the surface of the field insulating film 40 in the peripheral region 22. The interlayer insulating film 46 also covers a portion of the surface of the lower layer 44a of the gate wiring 44. The interlayer insulating film 46 has step portions 46b-1 to 46b-4 on its upper surface. The step portions 46b-1 and 46b-4 are step portions formed on the ends of the field insulating film 40. The step portions 46b-2 and 46b-3 are step portions formed along the shape of the lower layer 44a. A contact hole 46a is provided in the interlayer insulating film 46 above the lower layer 44a. The upper layer 44b is provided on the interlayer insulating film 46 within a range including the contact hole 46a. The upper layer 44b is in contact with the upper surface of the lower layer 44a within the contact hole 46a.

[0020] The interlayer insulating film 46 is distributed across the peripheral region 22 and the element region 20. The interlayer insulating film 46 in the element region 20 is covered with the source electrode 30. A plurality of contact holes are formed in the interlayer insulating film 46 in the element region 20. The source electrode 30 contacts the upper surface 12a of the semiconductor substrate 12 in each contact hole. A contact hole 46c is formed in the interlayer insulating film 46 in the peripheral region 22. A peripheral electrode 42 is disposed on top of the interlayer insulating film 46 within an area including the contact hole 46c. The peripheral electrode 42 contacts the upper surface 12a of the semiconductor substrate 12 within the contact hole 46c. The peripheral electrode 42 is disposed at a position spaced apart from the source electrode 30. As shown in FIG. 1 , the peripheral electrode 42 has a ring shape that surrounds the source electrode 30. Although not shown, the contact hole 46c also has a ring shape that follows the peripheral electrode 42. Therefore, the peripheral electrode 42 is in contact with the upper surface 12a of the semiconductor substrate 12 in an area surrounding the source electrode 30. As shown in FIG. 2 , the field insulating film 40 is in contact with the upper surface 12a of the semiconductor substrate 12 in an area between the peripheral electrode 42 and the source electrode 30. Therefore, the gate wiring 44 is disposed between the peripheral electrode 42 and the source electrode 30.

[0021] 2, in the peripheral region 22, an insulating protective film 48 is provided on the semiconductor substrate 12. The insulating protective film 48 is made of polyimide. The insulating protective film 48 covers the outer periphery of the source electrode 30, the peripheral electrode 42, the interlayer insulating film 46, and the upper layer 44b of the gate wiring 44. Note that the insulating protective film 48 is not shown in FIG. 1.

[0022] As shown in FIGS. 1 and 2, a plurality of trenches 34 are provided on the upper surface 12a of the semiconductor substrate 12 in the element region 20. As shown in FIG. 1, each trench 34 extends elongately in the y direction on the upper surface 12a. The plurality of trenches 34 are spaced apart in the x direction on the upper surface 12a. As shown in FIG. 2, the inner surface of each trench 34 is covered with a gate insulating film 36. A gate electrode 38 is disposed in each trench 34. Each gate electrode 38 is insulated from the semiconductor substrate 12 by the gate insulating film 36. The upper surface of each gate electrode 38 is covered with an interlayer insulating film 46. Each gate electrode 38 is insulated from the source electrode 30 by the interlayer insulating film 46. As shown in FIG. 1, both ends of each trench 34 in the y direction are disposed below the gate wiring 44. Each gate electrode 38 is connected to the gate wiring 44 above it at both ends of the trench 34 in the y direction. Therefore, each gate electrode 38 is connected to a gate pad 49 via the gate wiring 44.

[0023] As shown in FIG. 2, the semiconductor substrate 12 has a plurality of source layers 60, a body layer 62, a drift layer 64, a buffer layer 66, a drain layer 68, and a plurality of field limiting rings (FLRs) 69.

[0024] The multiple source layers 60 are n-type layers and are arranged in the element region 20. Each source layer 60 contacts the gate insulating film 36 at the upper end of the side surface of the corresponding trench 34. Each source layer 60 is in ohmic contact with the source electrode 30.

[0025] The body layer 62 is a p-type layer. The body layer 62 has a main portion disposed within the element region 20 and an extension portion 62e extending from the element region 20 to the peripheral region 22. The body layer 62 has a contact p-layer 62a and a low-concentration p-layer 62b. The contact p-layer 62a has a higher p-type impurity concentration than the low-concentration p-layer 62b. The low-concentration p-layer 62b is in contact with the contact p-layer 62a from below. Within the element region 20, the contact p-layer 62a is disposed between the source layers 60. The contact p-layer 62a within the element region 20 is in ohmic contact with the source electrode 30. Within the element region 20, the low-concentration p-layer 62b is in contact with the contact p-layer 62a and the source layer 60 from below. The low-concentration p-layer 62b is in contact with the gate insulating film 36 below the source layer 60. The source layer 60 is separated from the drift layer 64 by a low-concentration p-layer 62b. The extension 62e of the body layer 62 extends from a position in contact with the source electrode 30 to a position in contact with the peripheral electrode 42. In the extension 62e, the contact p-layer 62a is distributed in an area including the upper surface 12a of the semiconductor substrate 12, and the low-concentration p-layer 62b is in contact with the contact p-layer 62a from below. The contact p-layer 62a of the extension 62e is in ohmic contact with the source electrode 30 and the peripheral electrode 42.

[0026] The drift layer 64 is an n-type layer having a lower n-type impurity concentration than the source layer 60. The drift layer 64 is distributed across the element region 20 and the peripheral region 22. The drift layer 64 is disposed below the low-concentration p-layer 62b of the body layer 62. The drift layer 64 contacts the low-concentration p-layer 62b from below in the element region 20 and the peripheral region 22. In the element region 20, the drift layer 64 contacts the gate insulating film 36 below the low-concentration p-layer 62b. Furthermore, the drift layer 64 is distributed up to the upper surface 12a of the semiconductor substrate 12 in an area closer to the outer circumferential surface 12c than the peripheral electrode 42.

[0027] The buffer layer 66 is an n-type layer having a higher n-type impurity concentration than the drift layer 64. The buffer layer 66 is distributed across the element region 20 and the peripheral region 22. The buffer layer 66 contacts the drift layer 64 from below within the element region 20 and the peripheral region 22.

[0028] The drain layer 68 is an n-type layer having a higher n-type impurity concentration than the buffer layer 66. The drain layer 68 is distributed across the element region 20 and the peripheral region 22. The drain layer 68 contacts the buffer layer 66 from below in the element region 20 and the peripheral region 22. The drain layer 68 is in ohmic contact with the drain electrode 32 in the element region 20 and the peripheral region 22.

[0029] Each FLR 69 is a p-type layer and is located closer to the outer peripheral surface 12c than the peripheral electrode 42. Each FLR 69 is distributed over an area including the top surface 12a. Although not shown, each FLR 69 has a ring shape that surrounds the element region 20 when the semiconductor substrate 12 is viewed from above. The periphery of each FLR 69 is surrounded by a drift layer 64.

[0030] As shown in FIG. 1, a bridge wiring 50 is provided on a portion of the upper part of the gate wiring 44. FIG. 3 shows an enlarged view of the bridge wiring 50. Note that in FIG. 3, for ease of viewing, the bridge wiring 50, the source electrode 30, and the peripheral electrode 42 are indicated by dotted hatching. Also, FIGS. 4 and 5 are cross-sectional views taken along lines IV-IV and VV in FIG. 3. As shown in FIGS. 4 and 5, within the area where the bridge wiring 50 is provided, the gate wiring 44 is composed only of the lower layer 44a. That is, within this area, the upper layer 44b is not provided on the upper part of the lower layer 44a. Furthermore, within this area, no contact hole 46a is provided in the interlayer insulating film 46, and the entire upper surface of the lower layer 44a is covered by the interlayer insulating film 46. As shown in FIGS. 3 to 5, the bridge wiring 50 extends from the source electrode 30 to the peripheral electrode 42, passing through the upper part of the interlayer insulating film 46 (i.e., above the gate wiring 44). Therefore, the bridge wiring 50 covers the step portions 46b-1 to 46b-4 of the interlayer insulating film 46. The bridge wiring 50 is insulated from the gate wiring 44 by the interlayer insulating film 46.

[0031] As shown in FIG. 3 , the bridge wiring 50 has two slits 52a and 52b extending in the y direction. The bridge wiring 50 is not provided on the interlayer insulating film 46 within the slits 52a and 52b. The slit 52a extends from one end of the bridge wiring 50 in the +y direction. The slit 52a extends along the boundary between the bridge wiring 50 and the source electrode 30. The slit 52b extends from the other end of the bridge wiring 50 in the -y direction. The slit 52b extends along the boundary between the bridge wiring 50 and the peripheral electrode 42. The tip of the slit 52a and the tip of the slit 52b are positioned in the same position in the y direction. Therefore, the bridge wiring 50 has a portion 50a connected to the source electrode 30 and a portion 50b connected to the peripheral electrode 42. The portions 50a and 50b are connected along the y direction.

[0032] In the range shown in FIG. 3, the x-direction is the direction that crosses the gate wiring 44 when viewing the semiconductor substrate 12 from above, and the y-direction is the direction in which the gate wiring 44 extends when viewing the semiconductor substrate 12 from above. In FIG. 3, the interval L1 indicates the interval between the source electrode 30 and the peripheral electrode 42 in the x-direction. In FIG. 3, the width L2a indicates the width of the portion 50a in the x-direction. Also, the width L2b indicates the width of the portion 50b in the x-direction. Further, hereinafter, the width of the gate wiring 44 in the x-direction at an arbitrary position in the y-direction is referred to as the width L2. Within the range of the portion 50a, L2 = L2a, and within the range of the portion 50b, L2 = L2b. As is clear from FIG. 3, L2a < L1 and L2b < L1. That is, the relationship L2 < L1 is satisfied at any position within the range in the y-direction where the bridge wiring 50 exists. <0000​​​​​When the MOSFET is turned off, the drift layer 64 is depleted, generating a high electric field within the drift layer 64. This high electric field can cause avalanche breakdown within the drift layer 64. Arrows 100 and 102 in FIG. 2 indicate the path of avalanche current when avalanche breakdown occurs within the drift layer 64 below the gate wiring 44. When avalanche breakdown occurs within the drift layer 64 below the gate wiring 44, the avalanche current flows through the extension 62e of the body layer 62 to the source electrode 30, as indicated by arrow 100. If the avalanche current flowing to the source electrode 30 is large, the potential of the extension 62e below the gate wiring 44 rises, and a high voltage is applied between the extension 62e and the gate wiring 44. This can damage the field insulating film 40 between the extension 62e and the gate wiring 44. In contrast, in this embodiment, the extension 62e is connected to the peripheral electrode 42, which is located on the opposite side of the gate wiring 44 from the source electrode 30. Because the peripheral electrode 42 is connected to the source electrode 30 via the bridge wiring 50, the peripheral electrode 42 has the same potential as the source electrode 30. Therefore, the avalanche current also flows to the peripheral electrode 42, as indicated by arrow 102. That is, in the extension 62e, the avalanche current flows in a dispersed manner, as indicated by arrows 100 and 102. This suppresses the potential rise in the extension 62e, and prevents damage to the field insulating film 40.

[0035] Furthermore, the semiconductor device 10 generates heat during use. Therefore, the semiconductor device 10 repeatedly undergoes thermal expansion and contraction during use. Therefore, due to the difference in the linear expansion coefficient between the bridge wiring 50 and the interlayer insulating film 46, thermal stress is repeatedly applied to the interlayer insulating film 46. In particular, high thermal stress is applied by the bridge wiring 50 to the step portions 46b-1 to 46b-4 of the interlayer insulating film 46. Repeated application of thermal stress to the step portions may damage the interlayer insulating film 46 or the gate wiring 44. FIG. 6 shows a cross-sectional view of the bridge wiring 50 of a semiconductor device according to a comparative example. In FIG. 6, the bridge wiring 50 does not have a slit, and the bridge wiring 50 extends in the x-direction from the source electrode 30 to the peripheral electrode 42. In other words, in FIG. 6, the width L2 of the bridge wiring 50 is equal to the distance L1 between the source electrode 30 and the peripheral electrode 42. If the bridge wiring 50 extends in the x direction from the source electrode 30 to the peripheral electrode 42 in this manner, extremely high thermal stress is applied from the bridge wiring 50 to the step portion. Therefore, in FIG. 6, the thermal stress applied to the step portions 46b-1 to 46b-4 is likely to damage the interlayer insulating film 46 and the gate wiring 44. In contrast, in this embodiment, as shown in FIG. 3, the slits 52a and 52b cause the width L2 of the bridge wiring 50 in the x direction to be smaller than the distance L1 between the source electrode 30 and the peripheral electrode 42 throughout the entire range of the bridge wiring 50. In other words, there is no location within the range of the bridge wiring 50 where the width L2 is equal to the distance L1. Therefore, the thermal stress applied from the bridge wiring 50 to the step portion is suppressed. Therefore, in this embodiment, damage to the interlayer insulating film 46 and the gate wiring 44 due to thermal stress can be suppressed.

[0036] Furthermore, in this embodiment, the bridge wiring 50 passes over the gate wiring 44 to connect the source electrode 30 and the peripheral electrode 42. Therefore, the gate wiring 44 is not divided at the location where the bridge wiring 50 is provided. This allows the layout of the gate wiring 44 with a relatively high degree of freedom, and as a result, the element region 20 can be provided widely.

[0037] Note that the shape of the bridge wiring 50 shown in FIG. 3 is an example. As long as the relationship L2 < L1 is satisfied throughout the range of the bridge wiring, various shapes can be adopted as the shape of the bridge wiring 50. For example, the bridge wiring 50 may have the shapes shown in FIGS. 7 and 8. In FIGS. 7 and 8, for the sake of clarity, the bridge wiring 50, the source electrode 30, and the peripheral electrode 42 are shown by dot hatching. Also in FIGS. 7 and 8, since the slit 52 is provided in the bridge wiring 50, the relationship L2 < L1 is satisfied at any position within the range of the bridge wiring 50.

[0038] Also, in the above-described embodiment, a gate-type switching element having a trench-type gate electrode is provided in the element region. However, a gate-type switching element having a planar-type gate electrode may be provided in the element region. Further, in the above-described embodiment, the switching element provided in the element region is a MOSFET, but other switching elements (for example, IGBT (insulated gate bipolar transistor), etc.) may be provided in the element region.

[0039] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples exemplified above. The technical elements described in this specification or the drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Also, the technology exemplified in this specification or the drawings achieves a plurality of purposes simultaneously, and has technical utility by achieving one of those purposes itself.

Explanation of Reference Numerals

[0040] 10: Semiconductor device, 30: Source electrode, 38: Gate electrode, 40: Field insulating film, 42: Peripheral electrode, 44: Gate wiring, 46: Interlayer insulating film, 49: Gate pad, 50: Bridge wiring, 62: Body layer, 62e: Extension

Claims

1. A semiconductor device, a semiconductor substrate (12) having an element region (20) in which a gate-type switching element is provided; a source electrode (30) in contact with the upper surface of the semiconductor substrate in the element region; a gate pad (49) disposed on top of the semiconductor substrate; a peripheral electrode (42) contacting the top surface of the semiconductor substrate at a position spaced from the source electrode; a field insulating film (40) contacting the upper surface of the semiconductor substrate in a range between the source electrode and the peripheral electrode; a gate wiring (44) disposed on the upper portion of the field insulating film, extending along the outer periphery of the source electrode, and connecting the gate electrode of the gate-type switching element and the gate pad; an interlayer insulating film (46) covering the gate wiring; a bridge wiring (50) extending from the source electrode to the peripheral electrode through the upper portion of the interlayer insulating film and insulated from the gate wiring by the interlayer insulating film; and The gate-type switching element is a p-type body layer (62) provided inside the semiconductor substrate and having an extension (62e) extending from a position in contact with the source electrode to a position in contact with the peripheral electrode; an n-type drift layer (64) in contact with the body layer from below; and When the direction crossing the gate wiring when the semiconductor substrate is viewed from above is defined as a first direction, the distance between the source electrode and the peripheral electrode in the first direction is defined as a distance L1, and the width of the bridge wiring in the first direction is defined as a width L2, the relationship L2<L1 is satisfied at any position within the range of the bridge wiring. Semiconductor device.

2. 2. The semiconductor device according to claim 1, wherein the bridge wiring is provided with a slit extending in a direction intersecting the first direction when the semiconductor substrate is viewed from above.

3. The body layer is a contact p layer; a low-concentration p-layer having a lower p-type impurity concentration than the contact p-layer and in contact with the contact p-layer from below; and In the extension portion, the contact p layer extends from a position where it contacts the source electrode to a position where it contacts the peripheral electrode.

3. The semiconductor device according to claim 1.

4. 3. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of silicon carbide.

Images