Power Semiconductor Devices

Abstract

In at least one embodiment, a power semiconductor device (1) comprises a semiconductor body (2), at least one source region (21) in the semiconductor body (2), a gate electrode (3) in the semiconductor body (2), a gate insulator (4, 41, 42) between the semiconductor body (2) and the gate electrode (3), and at least one well region (22) in the at least one source region (21) and in the gate insulator (4, 41, 42), the gate insulator (4, 41, 42) having a variable dielectric capacitance, the dielectric capacitance being in each case the quotient of the dielectric constant and the geometrical thickness of the gate insulator (4, 41, 42) at that particular location, the dielectric capacitance being greater in the at least one well region (22) than in the remaining regions of the gate insulator (4, 42).

Description

[Technical Field]

[0001] A power semiconductor device is provided. [Background technology]

[0002] The document WO2014 / 204491A1 refers to a low loss power SiC MOSFET.

[0003] The document US Pat. No. 8,436,367 (B1) mentions a SiC power vertical DMOS with an increased safe operating area.

[0004] U.S. Patent Application Publication No. 2016 / 0064550(A1) provides an insulated gate switching device including a first region having a first conductivity type, a body region having a second conductivity type and in contact with the first region, a second region having the first conductivity type and separated from the first region by the body region, an insulating film in contact with the first region, the body region, and the second region, and a gate electrode facing the body region via the insulating film. The body region includes a first body region and a second body region. The first body region has a theoretical threshold level Vth greater than that of the second body region.

[0005] The documents US Patent Application Publication Nos. 2016 / 0225905(A1) and 2020 / 0259012(A1) refer to semiconductor devices comprising a gate electrode. Summary of the Invention [Problem to be solved by the invention]

[0006] The problem to be solved is to provide a power semiconductor device with improved switching behavior. [Means for solving the problem]

[0007] Embodiments of the present disclosure relate to a power semiconductor device as defined in the independent patent claims. Exemplary further developments form the subject matter of the dependent patent claims.

[0008] The power semiconductor device may be based on a wide bandgap material and comprises a gate electrode and a gate insulator that may comprise a high-k material in whole or in part, the gate insulator having a variable dielectric capacitance in the central region that is greater than, for example, at the edges, the wide bandgap material being based on, for example, SiC.

[0009] Using such a gate insulator, lower on-state resistance of the device and equally short switching times can be maintained.

[0010] In at least one embodiment, the power semiconductor device comprises a semiconductor body having at least one source region. The power semiconductor device further comprises a gate electrode in the semiconductor body and a gate insulator between the semiconductor body and the gate electrode. At least one well region is located in the at least one source region and the gate insulator. The gate insulator has a variable dielectric capacitance, which in each case may be the quotient of the overall dielectric constant and the geometric thickness of the gate insulator at that particular location. The dielectric capacitance is greater in the at least one well region than in the remaining regions of the gate insulator. Optionally, in cross section, the gate insulator comprises two first gate insulator regions having a greater dielectric capacitance and a central second gate insulator region having a smaller dielectric capacitance, and the at least one well region is in direct contact only with the first gate insulator regions and not with the second gate insulator regions.

[0011] In other words, the dielectric capacitance is C dielectric = εε0 / t, where ε is the relative permittivity, ε0 ​​is the dielectric constant, and t is the geometric thickness of the gate insulator. dielectricis lower over the junction field effect transistor (JFET) region than over the channel region. The channel region may refer to the region where at least one well region is closest to the gate insulator, and the JFET region may refer to the central region of the gate electrode when viewed from a top view of the gate electrode.

[0012] The relative dielectric constant is sometimes referred to as the relative permittivity, abbreviated as ε or κ, or simply as k. The relative permittivity refers to, but is not limited to, a value measured at a temperature of 300 K and a frequency of 1 kHz.

[0013] Hereinafter, the term "gate insulator" may refer to the insulator below the gate electrode, i.e., between the gate electrode and the semiconductor body. Additional electrically insulating material, for example, on top of the gate electrode, i.e., on the side of the gate electrode away from the semiconductor body, may not be intended by the term "gate insulator", but only the insulating material that ensures immediate electrical insulation between the gate electrode and the semiconductor body.

[0014] The term "source region" can refer to both the source in a field effect transistor and the emitter in a bipolar transistor.

[0015] Thus, the power semiconductor device may be a silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) or a SiC metal-insulator-semiconductor field effect transistor (MISFET) with a variable dielectric region for improved switching behavior. For example, a power MOSFET based on silicon carbide material is described. The gate insulator is partially or entirely formed using at least one high-k material. Additionally, the gate insulator is divided into two sections: the first section overlaps the channel region, and the second section extends over the JFET region. The dielectric extending over the JFET region may be formed of a different material and / or a different layer thickness compared to the first section. The above-described gate structure allows for the utilization of the advantages of high-k dielectrics for conducting current without slowing down device switching.

[0016] Otherwise, using a high-k material may increase the capacitance seen by the gate terminal and reduce the switching speed. Using the above-mentioned two-zone gate insulator with different materials and / or thicknesses allows for a reduction in the gate capacitance.

[0017] Silicon carbide power semiconductor devices can replace silicon-based power semiconductor devices in low-voltage applications, for example, at voltages between 650 V and 1.2 kV. While the SiC market is largely driven by low-voltage devices, the use of SiC power MOSFETs at ≥3.3 kV for medium- and high-voltage systems, such as traction applications, has also attracted much attention. Despite the excellent material properties, several issues remain that must be addressed before SiC power devices can be widely used in various applications. For example, much of the effort has been focused on improving the quality of the gate dielectric / silicon carbide interface. In fact, it is known that several interface trap states and defects are created and present within the bandgap of SiC during the oxidation process to form gate insulators such as SiO2. These defects significantly degrade inversion channel mobility due to charge trapping and Coulomb scattering mechanisms.

[0018] The use of high-k materials for the gate insulator implies a higher number of carriers in the inversion channel for the same applied voltage and dielectric thickness. DS,ON In addition, high-k gate dielectrics have been shown to provide high threshold voltage stability and lower interface state density. However, one drawback of high-k materials is the increase in gate capacitance, e.g., the gate-source capacitance C GS and gate-drain Miller capacitance C GD has a higher value, which makes the switching speed slower.

[0019] Described herein is an improved gate insulator structure. Compared to gate dielectrics with a constant dielectric capacitance, the structures described herein are divided into different regions, with a first insulator gate region extending over the channel region and formed, for example, using at least one high-k material, and a second insulator gate region corresponding to the JFET region with a different configuration, which can have the same thickness as the channel region and be formed of SiO2, or can be thicker and be formed of either SiO2 or a high-k material, or a combination thereof. Thus, one design feature of the devices described herein is a lower dielectric capacitance of the gate insulator extending over the JFET region, thereby further reducing gate capacitance.

[0020] According to at least one embodiment, the semiconductor body is SiC, although the semiconductor body may alternatively comprise Si or a high bandgap compound semiconductor material such as GaO or GaN.

[0021] According to at least one embodiment, the power semiconductor device is a field effect transistor or an insulated gate bipolar transistor, IGBT for short. For example, the power semiconductor device described herein is or includes, for example, a MOS-based SiC trench device or planar device such as a MOSFET and an IGBT. Thus, the power semiconductor device may be or be, for example, a device including or selected from the group consisting of a metal oxide semiconductor field effect transistor (MOSFET), a metal-insulator-semiconductor field effect transistor (MISFET), and an insulated gate bipolar transistor (IGBT).

[0022] According to at least one embodiment, the gate insulator includes a first material and a second material. The second material has a higher dielectric constant than the first material, and as a result may be a high-k material. For example, the ratio between the dielectric constants of the second material and the first material varies between 1.2 and 5, e.g., by at least a factor of 1.2, or by at least a factor of 1.5, or by at least a factor of 2.5, and / or by up to a factor of 4.5. For example, the first material may be SiO2 and the second material may be selected from the group consisting of Si3N4, Al2O3, YO3, ZrO2, HfO2, La2O3, Ta2O5, and TiO2.

[0023] According to at least one embodiment, only the second material is present directly on the channel region, i.e., directly on the well region. The first low-k material can be applied only away from the well region, thereby confining the first material to the JFET region.

[0024] According to at least one embodiment, the second material is present as a continuous layer, which may extend completely between the gate electrode and the semiconductor body, thereby eliminating the need for a direct, linear connection between the gate electrode and the semiconductor body without extending through the second material, i.e., the high-k material.

[0025] According to at least one embodiment, the first material is located on a side of the second material that is remote from the semiconductor body. In this case, the second material can be in direct contact with the semiconductor body, and the first material can be remote from the semiconductor body and not in direct contact with the semiconductor body. For example, the second material can be first applied to the semiconductor body as a continuous layer, and then the first material can be applied in a structured manner, or vice versa.

[0026] According to at least one embodiment, the continuous layer of the second material has a constant geometric layer thickness. The term "constant geometric layer thickness" may allow for thickness variations of up to 10%, or up to 5%, of the maximum thickness of the layer. Thus, inadvertent thickness variations due to, for example, manufacturing tolerances, are not considered variable thickness in this context.

[0027] According to at least one embodiment, the second material is located on a side of the first material that is remote from the semiconductor body. In this case, both the first material and the second material can be in direct contact with the semiconductor body. For example, the first material can be applied to the semiconductor body in a structured manner, so that only a portion of the semiconductor body is covered with the first material in the region of the subsequent gate electrode, and then the first material can be applied as a continuous layer, which can also have a constant thickness, for example.

[0028] According to at least one embodiment, the gate insulator has a constant geometric thickness. In this case, the first material and the second material are located next to each other in a common plane. For example, both materials are applied directly onto the upper side of the semiconductor body having a constant thickness. For example, both materials are applied separately and non-overlappingly when viewed from a top view of the upper side. Thus, the first and second materials may be directly adjacent to each other without overlapping each other. In other cases, the first and second materials may overlap due to, for example, the manufacturing process.

[0029] According to at least one embodiment, the gate insulator consists of exactly one material and therefore has a non-variable dielectric constant and consequently a variable geometric thickness.

[0030] According to at least one embodiment, the geometric thickness of the gate insulator is greatest at a central portion of the gate insulator when viewed in cross section. The term "cross section" may refer to a plane perpendicular to the upper side of the semiconductor body and, when viewed from a top view of the upper side, perpendicular to the direction of the main extent of the gate electrode, for example, when the gate electrode is a strip electrode. The central portion of the gate insulator is that region of the gate insulator that is in direct contact with the drift layer.

[0031] According to at least one embodiment, the gate electrode has a planar configuration, i.e., the gate electrode is located on an upper side of the semiconductor body, the upper side being planar, and in this case neither the gate electrode nor the gate insulator penetrates through the semiconductor body.

[0032] According to at least one embodiment, the gate electrode has a trench configuration, where the gate electrode extends into a trench in the semiconductor body, e.g., a gate insulator covers the trench sidewalls and the trench bottom, and the gate electrode is embedded in the gate insulator within the trench.

[0033] According to at least one embodiment, the gate electrode extends deeper into the semiconductor body than the at least one well region and / or the at least one source region. As a result, the gate insulator also has a depth that is greater than the depth of the at least one well region and / or the at least one source region. "Depth" may refer to a direction extending away from and perpendicular to a top side of the semiconductor body.

[0034] According to at least one embodiment, at least one well region and / or at least one source region is directly adjacent to the trench, whereby the at least one well region and / or at least one source region can be in direct contact with the gate insulator at the sidewall of the trench.

[0035] According to at least one embodiment, the gate insulator comprises two or more first gate insulator regions with a larger dielectric capacitance and one or at least one central second gate insulator region with a smaller dielectric capacitance, for example, when viewed in a cross section perpendicular to the upper side of the semiconductor body through the gate electrode. In this cross section, the first gate insulator regions can be located at the edges of the gate electrode, and the second gate insulator region can be located in the middle of the gate electrode.

[0036] According to at least one embodiment, for example, when viewed in a cross section perpendicular to the top side of the semiconductor body through the gate electrode, the at least one well region is in direct contact only with at least one of the first gate insulator regions and not with the second gate insulator region, and thus the at least one well region can be limited to a respective first gate insulator region having a higher dielectric capacitance.

[0037] According to at least one embodiment, the semiconductor body further comprises a drift region. The drift region and the at least one source region can have a first conductivity type, for example, n-type conductivity, and thus can be n-doped. For example, the at least one source region and the at least one well region can be embedded in the drift region, such that the majority of the semiconductor body consists of the drift region. The drift region can have a homogeneous doping concentration.

[0038] According to at least one embodiment, the at least one well region has a second conductivity type different from the first conductivity type. For example, the at least one well region has p conductivity type and is therefore p-doped. Within the semiconductor body, the at least one well region can completely separate the respective source region from the drift region, such that there is no direct contact between the respective source region and the drift region.

[0039] According to at least one embodiment, for example, when viewed in a cross section perpendicular to the top side of the semiconductor body through the gate electrode, only the region of the semiconductor body contacted by the second gate insulator region is the drift region, which allows the second gate insulator region to be spaced from the at least one well region and form the at least one source region.

[0040] According to at least one embodiment, when viewed in a cross section perpendicular to the top side of the semiconductor body, e.g., through the gate electrode, the first gate insulator region is in contact with the at least one source region and / or the at least one well region, and the drift region, such that the first gate insulator region is in close proximity to all three regions of the semiconductor body, although the proportion of the first gate insulator region in contact with the drift region is, e.g., smaller than the proportion in contact with the at least one source region and / or the at least one well region.

[0041] According to at least one embodiment, the semiconductor further comprises a collector layer. The collector layer has the same conductivity type as the well region. The collector layer may be located on a lower side of the semiconductor body opposite the upper side. There may be one collector layer for all of the source regions. A collector electrode may be applied directly to the collector layer. When a collector layer is present, the power semiconductor device may be an IGBT.

[0042] According to at least one embodiment, the semiconductor further comprises at least one drain region. The drain region has the same conductivity type as the at least one source region. For example, the drain region is a layer in the lower portion. For example, the drift region is located between the upper portion and the drain region. There may be one common drain region for all of the source regions. The drain electrode may be in direct contact with the at least one drain region. If a drain region is present, the power semiconductor device may be a MOSFET or MISFET. The drain layer has a higher doping concentration than the drift layer.

[0043] According to at least one embodiment, the proportion of the second gate insulator area along the interface of the gate electrode facing the semiconductor body is at least 20%, or at least 30%, or at least 40%, and / or at most 80%, or at most 70%, or at most 60% of the total area of ​​the interface. The interface may be the contact surface between the gate insulator and the semiconductor body. The above values ​​apply, for example, when viewed in a cross section perpendicular to the upper side of the semiconductor body, for example along the shortest line through the gate electrode. If the gate electrode is planar, the interface may extend along a straight line, and if the gate electrode has a trench design, the interface may be U-shaped when viewed in cross section.

[0044] According to at least one embodiment, in a cross-sectional view, the first gate insulator region is located symmetrically around the second gate insulator region along the interface, such that in a cross-sectional view, there may be a line of mirror symmetry through the gate insulator with respect to the design of the first and second gate insulator regions.

[0045] According to at least one embodiment, the overall geometric thickness of the gate insulator is at least 5 nm, or at least 40 nm, or at least 100 nm. Alternatively or additionally, the geometric thickness is at most 1.5 μm, or at most 0.8 μm, or at most 0.5 μm.

[0046] According to at least one embodiment, the semiconductor body comprises at least one plug, e.g., the plug is in direct contact with a source electrode to achieve electrical contact with the at least one assigned well region. For example, the at least one plug and the at least one well region may have the same conductivity type, with the at least one plug being more heavily doped.

[0047] According to at least one embodiment, a power semiconductor device includes at least two of a source region and a source electrode. The source electrode is in electrical contact, for example, direct contact, with at least two of the source regions, such that the at least two source regions can be at the same potential. Optionally, the source electrode can also be in direct contact with at least one plug.

[0048] According to at least one embodiment, when viewed in a cross section perpendicular to the top side, a gate electrode is located between two of the at least two source regions, whereby two source regions can be assigned to one gate electrode, and the source regions can be arranged symmetrically adjacent to each gate electrode.

[0049] According to at least one embodiment, when viewed in cross section perpendicular to the top side, the source electrode partially or completely covers the gate electrode on the side remote from the semiconductor body. The source electrode and the gate electrode are electrically insulated by one or more layers of one or more insulating materials. Thereby, the source electrode can be a common electrode for at least two assigned source regions.

[0050] According to at least one embodiment, the power semiconductor device has a cell design. This can mean, for example, but not limited to, that the gate electrode has a square or approximately square shape when viewed from a top view. Alternatively, the power semiconductor device can be a stripe design, whereby the gate electrode is significantly longer than it is wide. In both the cell design and the stripe design, there can be multiple gate electrodes.

[0051] According to at least one embodiment, the power semiconductor device is a power device, for example, configured for a maximum current through the drain electrode or collector layer of at least 1 A, or at least 20 A. Alternatively or additionally, the power semiconductor device is configured for a maximum voltage of at least 0.1 kV, or at least 0.6 kV, or at least 1.2 kV.

[0052] The power semiconductor device is for example a power module in a vehicle that converts direct current from a battery into alternating current for an electric motor, for example in a hybrid or plug-in electric vehicle. Furthermore, the power semiconductor device can be a fuse in a vehicle such as an automobile. It is also possible for the power semiconductor device to be used in trains or rail networks, for example as a converter.

[0053] The power semiconductor device will now be described in more detail by way of exemplary embodiments with reference to the drawings, in which identical elements in the different drawings are designated by the same reference numerals, and the relationships between the elements are not shown to scale, but rather individual elements may be shown exaggeratedly large to aid understanding. [Brief explanation of the drawings]

[0054] [Figure 1] FIG. 1 is a schematic perspective view of an exemplary embodiment of a power semiconductor device as described herein, where a detailed view of the gate electrode region is also provided. [Figure 2] FIG. 1 is a schematic perspective view of an exemplary embodiment of a power semiconductor device as described herein, where a detailed view of the gate electrode region is also provided. [Figure 3] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device as described herein. [Figure 4] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device as described herein. [Figure 5] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device as described herein. [Figure 6] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device as described herein. [Figure 7] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device as described herein. [Figure 8] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device as described herein. [Figure 9] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device as described herein. [Figure 10] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device as described herein. [Figure 11] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device as described herein. [Figure 12] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device as described herein. [Figure 13] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device as described herein. [Figure 14] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device as described herein. [Figure 15] FIG. 1 is a schematic perspective view of a modified power semiconductor device. [Figure 16] FIG. 3 illustrates simulation data for the exemplary embodiment of FIGS. 1 and 2. [Figure 17] FIG. 3 illustrates simulation data for the exemplary embodiment of FIGS. 1 and 2. [Figure 18] FIG. 3 illustrates simulation data for the exemplary embodiment of FIGS. 1 and 2. [Figure 19] FIG. 3 illustrates simulation data for the exemplary embodiment of FIGS. 1 and 2. DETAILED DESCRIPTION OF THE INVENTION

[0055] 1, an exemplary embodiment of a power semiconductor device 1 is shown. The power semiconductor device 1 comprises a semiconductor body 2. The semiconductor body 2 comprises two source regions 21 on an upper side 20 of the semiconductor body 2 and two well regions 22 in the source regions 21. Furthermore, there is a drift region 23 in which the well regions 22 and the source regions 21 are embedded. The well region 22 separates the source regions 21 from the drift region 23. If the power semiconductor device 1 is a MISFET or MOSFET, there may be an optional drain region 24 on a lower side 29 of the semiconductor body 2 opposite the upper side 20. Optionally, a buffer layer (not shown) may be present between the drift region 23 and the drain region 24.

[0056] Optionally, there are two plugs 25 in the top side 20 that provide electrical contact with the well region 22. For example, the source region 21 and the well region 22 are electrically contacted by a source electrode 31. The drain region 24 may be electrically contacted by a drain electrode 32.

[0057] For example, the source region 21 and the drain region 24 are n + doped, and the drift region 23 is n - doped, the well region 22 is p-doped, and the optional plug 25 is p + Otherwise, the doping type can all be reversed.

[0058] For example, the maximum doping concentration of the source region 21, the drain region 24 and the plugs is at least 1×10 18 cm -3 , or at least 5 × 10 18 cm -3 , or at least 1 × 10 19 cm -3 , and / or up to 5 × 10 20 cm -3 , or up to 2 × 10 20 cm -3 , or up to 1×10 20 cm-3 Furthermore, the maximum doping concentration of the well region 22 is at least 5×10 16 cm -3 , or at least 1 × 10 17 cm -3 , and / or up to 5 × 10 19 cm -3 , or up to 5×10 18 cm -3 Depending on the voltage class of the power semiconductor device 1, the maximum doping concentration of the drift region 23 may be at least 1×10 14 cm -3 , or at least 5 × 10 14 cm -3 , or at least 1 × 10 15 cm -3 , and / or up to 1 × 10 17 cm -3 , or up to 5×10 16 cm -3 , or up to 1×10 16 cm -3 It could be.

[0059] The semiconductor body 2 may consist of a substrate and an epitaxially grown semiconductor section, or of only an epitaxially grown semiconductor section. Depending on the presence of a substrate, for example, the substrate may include a drain region 24, on top of which the drift region 23 is grown. The drift region thickness may be, for example, in the range of 3 μm to 0.2 mm, and / or the drain region thickness may be ≧1 μm and ≦0.5 mm.

[0060] Furthermore, the power semiconductor device 1 includes a gate electrode 3 at the top side 20 located between the well regions 22 of the drift region 23. For example, the gate electrode 3 is made of a metal or a highly conductive semiconductor material such as poly-Si.

[0061] Between the gate electrode 3 and the semiconductor body 2 is a gate insulator 4. The gate insulator 4 comprises two distinct zones: two first gate insulator regions 41 and one second gate insulator region 42. The second gate insulator region 42 has a smaller dielectric capacitance than the first gate insulator region 41. At each specific location of the gate insulator 4, the respective local dielectric capacitance refers to the quotient of the total dielectric constant and the local geometric thickness of the local material. In the case of the planar design of FIG. 1, the geometric thickness is measured perpendicular to the planar top side 20.

[0062] According to FIG. 1, the gate insulator 4 has a constant geometric thickness, and therefore the first and second gate insulator regions 41, 42 all have the same geometric thickness. To achieve different dielectric capacitances, the first gate insulator region 41 is made of a second material M2 having a higher dielectric constant than the first material M1 of the second gate insulator region 42. The second material M2 may be referred to as a high-k material. For example, the first material M1 may be SiO2, and the second material M2 may be Y2O3, ZrO2, HfO2, La2O3, Ta2O5, or TiO2. For example, the ratio of the dielectric capacitance of the first gate insulator region 41 to the dielectric capacitance of the second gate insulator region 42 may be at least 1.2 and / or at most 10.

[0063] The second gate insulator region 42 contacts the semiconductor body 2 only in the drift region 23, while the first gate insulator region 41 contacts the source region 21, the well region 22, and, e.g., to a lesser extent, the drift region 23. The first gate insulator region 41 is arranged in a mirror-symmetric manner adjacent to the second gate insulator region 42. The first gate insulator region 41 and the second gate insulator region 42 all lie directly on the top side 20 in a plane parallel to the top side 20.

[0064] Other than as shown in FIG. 1, the drain electrode 32 can be extended to the upper side 20 by a via, or can be located on the upper side 20 as well, for example, by locally exposing the drain layer 24 by a recess not shown.

[0065] The gate electrode 3, and thus the gate insulator 4, may have a strip shape, such that the length of the gate electrode 3 along the longitudinal direction G is greater than the width of the gate electrode 3. Alternatively, the power semiconductor device may have a cell design, whereby the gate electrode 3 has, but is not limited to, a square or approximately square shape. The lower cross section is perpendicular to the longitudinal direction G.

[0066] 2, the second gate insulator region 42 has a larger geometric thickness than the first gate insulator region 41. Therefore, the first gate insulator region 41 and the second gate insulator region 42 may have the same or different materials, since different dielectric capacitances can be obtained by the different geometric thicknesses. For example, the first gate insulator region 41 on the well region 22 may be made of a high-k material, i.e., the second material M2, and the second gate insulator region 42 may be made of a first material M1, such as SiO2.

[0067] The entire stack, consisting of both the gate insulator 4 and the gate electrode 3, may have a constant thickness, so that the gate electrode 3 has a U-shape when viewed in cross section.

[0068] Otherwise, FIG. 2 is similar to FIG. 3, the thickness of the second gate insulator region 42 corresponds to the thickness of the entire stack consisting of the gate insulator 4 and the gate electrode 3. The gate electrode 3 can thereby be confined to the first gate insulator region 41. In cross section, the gate electrode 3 can be divided into two equal parts by the second gate insulator region 42. For example, the second gate insulator region 42 can have a first material M1 with a low k, such as SiO2, or a second material M2 with a high k, and the first gate insulator region 41 can have the second material M2 with a high k.

[0069] Additionally, the power semiconductor device 1 may include an upper gate insulator region 6 located on a side of the gate electrode 3 away from the semiconductor body 2. The upper gate insulator region 6 may electrically isolate the source electrode 31 from the gate electrode 3. Such an upper gate insulator region 6 may also be present in the power semiconductor devices 1 of FIGS.

[0070] For example, the gate insulator 4 has a total width W of, for example, at least 1 μm and / or at most 20 μm. Along the top side 20, the second gate insulator regions 42 have a width W2 and each of the first gate insulator regions 41 has a width W1, so that W=W2+2×W1.

[0071] Otherwise, FIG. 3 is similar to FIG. According to Fig. 4, the gate insulator 4 comprises a continuous layer having a constant thickness directly on the upper side 20. For example, this layer comprises a second high-k material M2. On the side of this layer remote from the upper side 20 there is a coating, for example, comprising a first material M1. The coating of the first material M1 has a smaller width than the layer of the second material M2, and it is also possible that both the layer and the coating comprise the same material, for example the second material M2.

[0072] For example, in cross section, the film may have a trapezoidal shape, narrowing in the direction away from the top side 20. The entire stack, consisting of both the gate insulator 4 and the gate electrode 3, may have, for example, a constant thickness, as in FIG.

[0073] Otherwise, FIG. 4 is similar to FIGS. 1 to 3. 5 also comprises the above-described coatings and layers. Contrary to FIG. 4, the coating is applied directly onto the upper portion 20, and the layer completely covers the coating and part of the upper portion 20. Again, the layer may have a constant thickness.

[0074] Otherwise, FIG. 5 is similar to FIG. 6, the first gate insulator region 41 has a larger geometric thickness than the second gate insulator region 42, for example due to manufacturing issues. This can be compensated for by selecting a first material M1 for the second gate insulator region 42 and a second material M2 for the first gate insulator region 41 to obtain a desired dielectric capacitance. Thereby, the relative dielectric constants of the materials M1, M2 can compensate for the geometric thicknesses of the first and second gate insulator regions 41, 42.

[0075] Otherwise, FIG. 6 is similar to FIGS. 7, the power semiconductor device 1 has a trench design, so that in the semiconductor body 2 there is a trench 5 extending towards the underside 29. The gate electrode 3 and the gate insulator 4 are located mostly or completely within the trench 5. The trench 5 extends closer to the underside 29 than the well region 22 which is directly adjacent to the trench 5 and thus to the gate insulator 4. The gate electrode 3 can be covered by an upper gate insulator region 6 to separate the gate electrode 5 from the source electrode 31.

[0076] A first gate insulator region 41 is present on the sidewall 51 of the trench 5, and a second gate insulator region 42 is present on the trench bottom 52. Along the sidewall 51, the first gate insulator region 41 has a first length L1. The depth of the trench 5 corresponds to the sum of the first length L1 and the second length L2. The width of the trench 5 corresponds to a third length L3. For example, the length L2 is greater than the thickness of the first gate insulator region 41 in a direction perpendicular to the sidewall or channel.

[0077] That is, in cross section, the interface between the gate insulator 4 and the semiconductor body 2 has an overall length L=L1+L2+L3+L2+L1, while the second gate insulator region 42 consequently has a length L*=L2+L3+L2. At the trench bottom 52, the geometric thickness of the second gate insulator region 42 is L2.

[0078] The first and second gate insulator regions 41, 42 may have the same material, for example the second material M2.

[0079] Otherwise, FIG. 7 is similar to FIGS. 1 to 6. 8, there is a layer of constant thickness on all of the sidewalls 51 and trench bottom 52. On this layer, and on trench bottom 52, there is a film that defines second gate insulator region 42. For example, the film for second gate insulator region 42 has a first material M1, and the layer for mostly first gate insulator region 41 has a second material M2.

[0080] Otherwise, FIG. 8 is similar to FIG. 9, a coating is first applied to the trench bottom 52, and then a layer is applied to the coating and the remainder of the sidewalls 51. For example, the coating for the second gate insulator region 42 has a first material M1, and the layer for most of the first gate insulator region 41 has a second material M2.

[0081] Otherwise, FIG. 9 is similar to FIGS. 10, the coating has a variable thickness, for example to compensate for a curved trench bottom 52. In this context, it should be noted that in FIGS. 7-12, trench 5 is idealized and shown to have a rectangular cross-section, although due to the etching process, trench 5 may have a trapezoidal shape or a rectangular shape with rounded corners in cross-section.

[0082] Other than that, FIG. 10 is similar to FIGS. 11, the sidewalls 51 of the trench 5 are provided with, for example, a layer of a certain thickness of the second material M2, which defines the first gate isolation region 41. For the second gate isolation region 42, the first material M1 is applied at the trench bottom 52. Additionally or alternatively, each sidewall 51 and the trench bottom 52 can be covered essentially only by the second material M2.

[0083] Other than that, FIG. 11 is similar to FIGS. 12, the sidewalls 51 are again covered with the second material M2 and the trench bottom 52 is covered with the first material M1. Except in FIG. 11, the first material M1 also extends, for example, as a thin layer onto the other material on the sidewalls 51.

[0084] Other than that, FIG. 12 is similar to FIGS. 1 to 12, current flows essentially vertically from the source region 21 to the drain region 24, i.e., from the upper side 20 to the lower side 29. Conversely, in FIG. 13, both the drain region 24 and the source region 21 are located in the upper side 20.

[0085] Otherwise, Figure 13 is similar to Figures 1 to 6. For example, the different gate insulator designs of Figures 1 to 6 can be used with the source-drain design of Figure 13 as well.

[0086] 1 to 13, the power semiconductor device 1 is a MISFET or a MOSFET. The power semiconductor device 1 in FIG. 14 is an IGBT. Therefore, at the lower side 29, there is a collector layer 26 having the same conductivity type as the well layer 22, for example p-doped. A buffer layer (not shown) may be present between the drift region 23 and the collector layer 26. The same applies to the optional plug 25, for example, regarding the doping concentration of the collector layer 26. As a result, at the side of the collector layer 26 remote from the gate electrode 4, there is a collector electrode 33.

[0087] Although the IGBT of Figure 14 has a planar design, the trench designs of Figures 7 to 14 are also applicable to IGBTs such as Figure 14. Therefore, Figure 14 is otherwise similar to Figures 1 to 12.

[0088] In Figure 15, a modified semiconductor device 9 is shown. The modified semiconductor device 9 comprises a modified gate insulator 91 having a constant dielectric capacitance and therefore a constant effective thickness. Compared to the power semiconductor device 1 of Figures 1 to 14, the modified semiconductor device 9 of Figure 15 has reduced, i.e., slower, switching behavior.

[0089] To demonstrate the positive effect of the gate insulator design described herein, Figures 16-19 show simulation results using TCAD (Telecommunication-Aided Design) technology for a power semiconductor device 1 configured for a voltage of 1.2 kV. Figures 16 and 17 refer to the power semiconductor device 1 of Figure 1, while Figures 18 and 19 refer to the power semiconductor device 1 of Figure 2. The simulated circuit is a standard used for inductive load switching (ILS), i.e., a device under test having an inductor with an uncontrolled diode as a load. As an example, the supply voltage is set to 600 V and the load current is set to 50 A.

[0090] Curve C shows the respective gate insulator 4 described above in the context of Figures 1 and 2, where the first gate insulator region 41 comprises a high-k material and the second gate insulator region 42 comprises SiO2. Curve A shows a modified gate insulator 91 having the same shape as Figures 1 and 2 but using only high-k material, and thus curve B shows a modified gate insulator 91 using only SiO2. Figures 16 and 18 show the gate-source voltage Vgs as a function of time T during the turn-off phase, and Figures 17 and 19 show the gate-source voltage Vgs during the turn-on phase.

[0091] 16-19 show that the gate insulator structures described herein can at least provide faster switching times compared to full high-k gate insulator designs.

[0092] The invention described herein is not limited by the description given with reference to exemplary embodiments, but rather the invention encompasses any novel feature and any combination of features, including any specific combination of features in the claims, even if that feature or combination itself is not explicitly recited in the claims or exemplary embodiments.

[0093] This patent application claims priority from European Patent Application No. 21159962.6, the disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0094] List of reference numbers 1. Power semiconductor devices 2. Semiconductor body 20 Upper part 21 Source Region 22 well area 23 Drift Region 24 Drain region 25 plug 26 Collector layer 29 Lower part 3. Gate electrode 31 Source electrode 32 Drain electrode 33 Collector electrode 4 Gate insulator 41 first gate insulator region 42 second gate insulator region 5. Trench 51 Side wall 52 Trench bottom 6. Top gate insulator region 9. Modified Semiconductor Devices 91 Modified Gate Insulator A Simulation data for using only high-k materials B Simulation data for using SiO2 only C Simulation data for the use of first and second gate insulator regions G Gate electrode length direction L1: First length of the first gate insulator region L2 Second length L3 Third length Materials with a dielectric constant lower than M1 Materials with a higher dielectric constant than M2 T any unit of time Vgs Gate-source voltage in V W Overall gate insulator width W1 Width of the first gate insulator region W2 Width of the second gate insulator region

Claims

1. A power semiconductor device (1), a semiconductor body (2), at least one source region (21) in said semiconductor body (2), a gate electrode (3) in said semiconductor body (2), a gate insulator (4, 41, 42) between said semiconductor body (2) and said gate electrode (3); - at least one well region (22) in said at least one source region (21) and in said gate insulator (4, 41, 42), said gate insulator (4, 41, 42) has a variable dielectric capacitance which is in each case the quotient of the dielectric constant and the geometrical thickness of said gate insulator (4, 41, 42) at that particular location; - said variable dielectric capacitance is greater in said at least one well region (22) than in the remaining regions of said gate insulator (4, 42); - in cross section, said gate insulator (4, 41, 42) consists of two first gate insulator regions (41) with the larger said variable dielectric capacitance and a central second gate insulator region (42) with the smaller said variable dielectric capacitance, said at least one well region (22) being in direct contact only with said first gate insulator regions (41) and not with said second gate insulator region (42); the gate insulator (4, 41, 42) comprises a first material (M1) and a second material (M2), the second material (M2) having a higher dielectric constant than the first material (M1); said second material (M2) being a continuous layer extending completely between said gate electrode (3) and said semiconductor body (2); Power semiconductor device (1).

2. - said semiconductor body (2) consists of a wide bandgap material or silicon carbide; A power semiconductor device (1) according to claim 1.

3. The power semiconductor device (1) is a field effect transistor or an insulated gate bipolar transistor; A power semiconductor device (1) according to claim 2.

4. the first material (M1) is located on the side of the second material (M2) remote from the semiconductor body (2), said semiconductor body (2) being in direct contact with said second material (M2) but not with said first material (M1); the continuous layer of the second material (M2) has a constant geometric layer thickness; A power semiconductor device (1) according to any one of claims 1 to 3.

5. the second material (M2) is located on a side of the first material (M1) remote from the semiconductor body (2), whereby both the first material (M1) and the second material (M2) are in direct contact with the semiconductor body (2); A power semiconductor device (1) according to any one of claims 1 to 3.

6. the gate insulator (4, 41, 42) has a constant geometric thickness, the first material (M1) and the second material (M2) are located next to each other in a common plane, said first material (M1) and said second material (M2) are in direct contact with said semiconductor body (2), A power semiconductor device (1) according to any one of claims 1 to 3.

7. The power semiconductor device (1) according to any one of claims 1 to 6, wherein the gate electrode (3) has a planar configuration, whereby the gate electrode (3) is located on an upper side (20) of the semiconductor body (2), the upper side (20) being planar.

8. the gate electrode (3) has a trench configuration, whereby the gate electrode (3) extends into a trench (5) in the semiconductor body (2), the gate electrode (3) extends deeper into the semiconductor body (2) than the at least one well region (22), and the at least one well region (22) is directly adjacent to the trench (5); A power semiconductor device (1) according to any one of claims 1 to 6.

9. the semiconductor body further comprises a drift region (23); the drift region (23) and the at least one source region (21) have a first conductivity type, and the at least one well region (22) has a second conductivity type different from the first conductivity type; the only region of the semiconductor body (2) that is contacted by the second gate insulator region (42) is the drift region (23); In cross section, the first gate insulator region (41) is in contact with the at least one source region (21), the at least one well region (22), and the drift region (23). A power semiconductor device (1) according to any one of claims 1 to 8.

10. a proportion of the second gate insulator region (42) along the interface of the gate electrode (3) facing the semiconductor body (2) is between 20% and 80% of the total area of ​​the interface; In cross section, the first gate insulator region (41) is located symmetrically around the second gate insulator region (42) along the interface. A power semiconductor device (1) according to any one of claims 1 to 9.

11. the variable dielectric capacitance of the first gate insulator region (41) is at least 1.4 times and at most 6 times the variable dielectric capacitance of the second gate insulator region (42); A power semiconductor device (1) according to any one of claims 1 to 10.

12. The total geometric thickness of the gate insulator (4, 41, 42) is 10 nm or more and 1.5 μm or less. A power semiconductor device (1) according to any one of claims 1 to 11.

13. at least two source regions (21) and a source electrode (31) in electrical contact with at least two of the at least two source regions (21); Looking at the cross section, - said gate electrode (3) is located between two of said at least two source regions (21); - said source electrode (31) covers said gate electrode (3) on the side remote from said semiconductor body (2), whereby said source electrode (31) is a common electrode for said at least two source regions (21); A power semiconductor device (1) according to any one of claims 1 to 12.

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