Imaging device

Abstract

To provide an imaging device capable of realizing global shutter function while avoiding complication of a circuit in a pixel.SOLUTION: The imaging device includes: a photoelectric conversion layer for converting light into signal electric charge; a pixel electrode for collecting the signal electric charge; a first electric charge blocking layer between the photoelectric conversion layer and the pixel electrode; a counter electrode connected to the pixel electrode via the first electric charge blocking layer and the photoelectric conversion layer; and a voltage supply circuit for applying a bias voltage across the pixel electrode and the counter electrode. The amount of a light current, generated by the photoelectric conversion layer when light is received in a first state where a bias voltage within a first voltage range is applied across the pixel electrode and the counter electrode, is smaller than the amount of a light current, generated in a second state where the bias voltage within a second voltage range is applied across the pixel electrode and the counter electrode.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to an imaging device. [Background technology]

[0002] Conventionally, image sensors that utilize photoelectric conversion have been known. For example, CMOS (Complementary Metal Oxide Semiconductor) image sensors that have photodiodes have been widely used. CMOS image sensors are widely used. They have the advantages of low power consumption and the ability to access each pixel individually. CMOS image sensors generally use a so-called rolling shutter as a signal readout method, which sequentially exposes each row of the pixel array and reads out the signal charge.

[0003] In rolling shutter operation, the start and end of exposure are different for each row of the pixel array. As a result, when capturing an image of a fast-moving object, a distorted image of the object may be obtained, and when a flash is used, brightness differences may occur within the image. For these reasons, there is a demand for a so-called global shutter function, in which the start and end of exposure are the same for all pixels in the pixel array.

[0004] For example, Patent Document 1 below discloses a CMOS image sensor capable of global shutter operation. In the technology described in Patent Document 1, a transfer transistor and a charge storage unit (capacitor or diode) are provided for each of a plurality of pixels. In each pixel, the charge storage unit is connected to a photodiode via a transfer transistor. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] US Patent Application Publication No. 2007 / 0013798 Summary of the Invention [Problem to be solved by the invention]

[0006] An imaging device is provided that can achieve a global shutter function while suppressing the complexity of circuits within pixels. [Means for solving the problem]

[0007] According to certain non-limiting exemplary embodiments of the present disclosure, the following is provided:

[0008] an imaging device comprising: a plurality of unit pixel cells, each including a first electrode, a second electrode opposite the first electrode, a photoelectric conversion layer between the first electrode and the second electrode, a charge accumulation region electrically connected to the first electrode, and a signal detection circuit electrically connected to the charge accumulation region; and a voltage supply circuit electrically connected to the second electrode, the voltage supply circuit supplying a first voltage to the second electrode during an exposure period, which is a period for accumulating charges generated by photoelectric conversion in the charge accumulation region, and supplying a second voltage different from the first voltage to the second electrode during a non-exposure period, wherein the start and end of the exposure period are common to the plurality of unit pixel cells.

[0009] The generic or specific aspects may be realized as an element, a device, an apparatus, a system, an integrated circuit, a method, or a computer program, or may be realized as any combination of an element, a device, an apparatus, a system, an integrated circuit, a method, and a computer program.

[0010] Additional benefits and advantages of the disclosed embodiments will become apparent from the specification and drawings. The benefits and / or advantages are provided individually by the various embodiments or features disclosed in the specification and drawings, and not all are required to obtain one or more of them. [Effects of the Invention]

[0011] According to the embodiments of the present disclosure, it is possible to achieve a global shutter function while suppressing the complexity of the circuitry within the pixel. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a schematic diagram showing an exemplary circuit configuration of an imaging device according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a schematic cross-sectional view showing an exemplary device structure of the unit pixel cell 10. As shown in FIG. [Figure 3] FIG. 3 is a diagram showing an example of an absorption spectrum in a photoelectric conversion layer containing tin phthalocyanine. [Figure 4] FIG. 4 is a schematic cross-sectional view showing an example of the configuration of the photoelectric conversion layer 15. As shown in FIG. [Figure 5] FIG. 5 is a graph showing typical photocurrent characteristics of the photoelectric conversion layer 15. As shown in FIG. [Figure 6] FIG. 6 is a diagram for explaining an example of the operation of the imaging device according to the embodiment of the present disclosure. [Figure 7] FIG. 7 is a block diagram showing an example of an imaging system configured to be able to form a multiple exposure image. [Figure 8] FIG. 8 is a diagram for explaining an example of forming a multiple exposure image. [Figure 9] Figure 9 shows an exemplary multiple-exposure image acquired by the imaging system 100S shown in Figure 7, along with multiple images extracted in time series from the multiple-exposure image, each containing an image of a moving object. [Figure 10] FIG. 10 is a diagram showing an example of a multiple exposure image on which an image of an identifier indicating a change in the position of a moving object over time is superimposed. [Figure 11] FIG. 11 is a diagram showing another example of a multiple exposure image onto which an image of an identifier indicating a change in the position of a moving object over time is superimposed. [Figure 12] FIG. 12 is a diagram for explaining another example of forming a multiple exposure image. [Figure 13]FIG. 13 is a timing chart for explaining an exemplary operation of reset voltage source 34 during the reset period. [Figure 14] FIG. 14 is a timing chart for explaining an exemplary operation of reset voltage source 34 during the reset period. [Figure 15] FIG. 15 is a schematic diagram showing a modified example of the imaging device 100. In FIG. DETAILED DESCRIPTION OF THE INVENTION

[0013] An outline of one aspect of the present disclosure is as follows.

[0014] [Item 1] an imaging device comprising: a plurality of unit pixel cells, each including a first electrode, a second electrode opposite the first electrode, a photoelectric conversion layer between the first electrode and the second electrode, a charge accumulation region electrically connected to the first electrode, and a signal detection circuit electrically connected to the charge accumulation region; and a voltage supply circuit electrically connected to the second electrode, the voltage supply circuit supplying a first voltage to the second electrode during an exposure period, which is a period for accumulating charges generated by photoelectric conversion in the charge accumulation region, and supplying a second voltage different from the first voltage to the second electrode during a non-exposure period, wherein the start and end of the exposure period are common to the plurality of unit pixel cells.

[0015] [Item 2] An imaging device as described in item 1, wherein each of the plurality of unit pixel cells includes a reset transistor electrically connected to the charge accumulation region, which switches between supplying and blocking a reset voltage for initializing the charge accumulation region, and wherein the potential difference between the first electrode and the second electrode when the reset voltage is supplied is greater than the potential difference between the first electrode and the second electrode after the reset voltage is blocked.

[0016] [Item 3] 3. The imaging device according to item 2, wherein the reset transistor is an n-channel field effect transistor, and the reset voltage is greater than the second voltage.

[0017] [Item 4] The reset transistor is a p-channel field effect transistor, 3. The imaging device according to item 2, wherein the reset voltage is smaller than the second voltage.

[0018] [Item 5] 5. An imaging device according to any one of items 1 to 4, wherein the plurality of unit pixel cells are arranged two-dimensionally along rows and columns, and signals detected by the signal detection circuits of the plurality of unit pixel cells are read out at different times for each row.

[0019] [Item 6] 6. The imaging device according to any one of items 1 to 5, wherein one frame period includes a plurality of exposure periods.

[0020] [Item 7] 7. The imaging device according to item 6, wherein the voltage supply circuit supplies first voltages of different magnitudes to the second electrode during each of the multiple exposure periods.

[0021] [Item 8] Item 8. The imaging device according to item 6 or 7, further comprising an image forming circuit that acquires multiple image data based on outputs from the signal detection circuit for each of multiple exposure periods and forms a multiple exposure image by superimposing the multiple image data.

[0022] [Item 9] 8. The imaging device according to item 6 or 7, further comprising an image forming circuit that acquires a signal corresponding to the signal charge accumulated in the charge accumulation region during one frame period from the signal detection circuit and forms a multiple exposure image based on the signal.

[0023] [Item 10] 10. The imaging device according to any one of items 1 to 9, wherein the photoelectric conversion layer has photocurrent characteristics having a first voltage range in which the absolute value of the output current density increases as the reverse bias voltage increases, a second voltage range in which the output current density increases as the forward bias voltage increases, and a third voltage range between the first and second voltage ranges in which the absolute value of the rate of change of the output current density with respect to the bias voltage is smaller than those in the first and second voltage ranges, and the voltage supply circuit supplies a second voltage to the second electrode during a non-exposure period so that the bias voltage applied to the photoelectric conversion layer is within the third voltage range.

[0024] [Item 11] a plurality of unit pixel cells, each including a first electrode, a charge accumulation region electrically connected to the first electrode, and a signal detection circuit electrically connected to the charge accumulation region; a second electrode facing the first electrode; a photoelectric conversion layer disposed between the first electrode and the second electrode; a voltage supply circuit connected to the second electrode, the voltage supply circuit supplying different voltages to the second electrode between an exposure period and a non-exposure period; the photoelectric conversion layer has photocurrent characteristics in which the rate of change of the output current density with respect to the bias voltage is different from one another in a first voltage range in which the absolute value of the output current density increases as the reverse bias voltage increases, a second voltage range in which the output current density increases as the forward bias voltage increases, and a third voltage range between the first and second voltage ranges; the rate of change in the third voltage range is smaller than the rate of change in the first voltage range and the rate of change in the second voltage range; the start and end of the exposure period are common to the plurality of unit pixel cells; The imaging device, wherein the voltage supply circuit supplies a voltage to the second electrode during a non-exposure period that provides a potential difference in a third voltage range between the second electrode and the signal detection circuit.

[0025] According to the configuration of Item 11, a global shutter can be realized without providing a separate transfer transistor or the like in the unit pixel cell.

[0026] [Item 12] Item 12. The imaging device according to item 11, wherein one frame period includes multiple exposure periods.

[0027] [Item 13] Item 13. The imaging device according to item 12, wherein the voltage supply circuit supplies voltages of different magnitudes to the second electrode during each of the multiple exposure periods.

[0028] According to the configuration of item 13, it is possible to perform imaging with sensitivity changed for each of a plurality of exposure periods.

[0029] [Item 14] Item 14. The imaging device according to item 12 or 13, further comprising an image forming circuit that acquires multiple image data based on outputs from the signal detection circuit for each of multiple exposure periods and forms a multiple exposure image by superimposing the multiple image data.

[0030] According to the configuration of item 14, it is possible to know the trajectory of the image of an object that has been moving during one frame period from the multiple exposure images.

[0031] [Item 15] Item 14. The imaging device according to item 12 or 13, further comprising an image forming circuit that acquires a signal corresponding to the signal charge accumulated in the charge accumulation region during one frame period from the signal detection circuit and forms a multiple exposure image based on the signal.

[0032] According to the configuration of item 15, it is possible to know the trajectory of the image of an object that is moving during one frame period from the multiple exposure images.

[0033] [Item 16] Each of the plurality of unit pixel cells includes a reset transistor electrically connected to the charge accumulation region, the reset transistor switching between supplying and cutting off a reset voltage to the charge accumulation region; The reset transistor is an n-channel field-effect transistor, 16. The imaging device according to any one of items 11 to 15, wherein the reset voltage is greater than the voltage that the voltage supply circuit applies to the second electrode during the non-exposure period.

[0034] According to the configuration of Item 16, the parasitic sensitivity can be more effectively suppressed.

[0035] [Item 17] Each of the plurality of unit pixel cells includes a reset transistor electrically connected to the charge accumulation region, the reset transistor switching between supplying and cutting off a reset voltage to the charge accumulation region; The reset transistor is a p-channel field effect transistor, 16. The imaging device according to any one of items 11 to 15, wherein the reset voltage is smaller than the voltage applied to the second electrode by the voltage supply circuit in the second period.

[0036] According to the configuration of Item 17, parasitic sensitivity can be more effectively suppressed.

[0037] [Item 18] Item 18. The imaging device according to item 16 or 17, wherein the absolute value of the difference between the reset voltage and the voltage applied to the second electrode by the voltage supply circuit during the non-exposure period is smaller than the breakdown voltage of the photoelectric conversion layer.

[0038] According to the configuration of Item 18, damage to the photoelectric conversion layer caused by application of excessive voltage can be avoided.

[0039] [Item 19] Item 18. The imaging device according to item 16 or 17, wherein the absolute value of the difference between the reset voltage and the voltage applied to the second electrode by the voltage supply circuit during the non-exposure period is smaller than the input voltage to the signal detection circuit.

[0040] According to the configuration of Item 19, damage to the photoelectric conversion layer caused by application of excessive voltage can be avoided.

[0041] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component arrangements and connection forms, steps, and step orders shown in the following embodiments are merely examples and are not intended to limit the present disclosure. The various aspects described in this specification can be combined with each other as long as no contradiction occurs. Furthermore, among the components in the following embodiments, components that are not recited in independent claims that represent the highest concept will be described as optional components. In the following description, components having substantially the same functions will be designated by common reference symbols, and their description may be omitted.

[0042] (Embodiment of Imaging Device) Fig. 1 shows an exemplary circuit configuration of an imaging device according to an embodiment of the present disclosure. The imaging device 100 shown in Fig. 1 has a pixel array PA including a plurality of unit pixel cells 10 arranged two-dimensionally. Fig. 1 schematically shows an example in which the unit pixel cells 10 are arranged in a matrix of two rows and two columns. Needless to say, the number and arrangement of the unit pixel cells 10 in the imaging device 100 are not limited to the example shown in Fig. 1.

[0043] Each unit pixel cell 10 has a photoelectric conversion section 13 and a signal detection circuit 14. As will be described later with reference to the drawings, the photoelectric conversion section 13 has a photoelectric conversion layer sandwiched between two electrodes facing each other, and receives incident light to generate a signal. The entire photoelectric conversion section 13 does not need to be an independent element for each unit pixel cell 10, and for example, a portion of the photoelectric conversion section 13 may span multiple unit pixel cells 10. The signal detection circuit 14 is a circuit that detects a signal generated by the photoelectric conversion section 13. In this example, the signal detection circuit 14 includes a signal detection transistor 24 and an address transistor 26. The signal detection transistor 24 and the address transistor 26 are typically field effect transistors ( Here, the signal detection transistor 24 and the address transistor 26 are exemplified as N-channel MOS transistors.

[0044] 1, the control terminal (here, the gate) of the signal detection transistor 24 is electrically connected to the photoelectric conversion unit 13. Signal charges (holes or electrons) generated by the photoelectric conversion unit 13 are accumulated in a charge accumulation node (also called a "floating diffusion node") 41 between the gate of the signal detection transistor 24 and the photoelectric conversion unit 13. The structure of the photoelectric conversion unit 13 will be described in detail later.

[0045] The photoelectric conversion unit 13 of each unit pixel cell 10 is further connected to a sensitivity control line 42. In the configuration illustrated in FIG. 1 , the sensitivity control line 42 is connected to a sensitivity control voltage supply circuit 32 (hereinafter simply referred to as the “voltage supply circuit 32”). The voltage supply circuit 32 is a circuit configured to be able to supply at least two types of voltage. When the imaging device 100 is in operation, the voltage supply circuit 32 supplies a predetermined voltage to the photoelectric conversion unit 13 via the sensitivity control line 42. The voltage supply circuit 32 is not limited to a specific power supply circuit, and may be a circuit that generates a predetermined voltage or a circuit that converts a voltage supplied from another power source to the predetermined voltage. As will be described in detail later, the voltage supplied from the voltage supply circuit 32 to the photoelectric conversion unit 13 is switched between multiple different voltages, thereby controlling the start and end of accumulation of signal charge from the photoelectric conversion unit 13 to the charge accumulation node 41. In other words, in the embodiment of the present disclosure, an electronic shutter operation is performed by switching the voltage supplied from the voltage supply circuit 32 to the photoelectric conversion unit 13. An example of the operation of the imaging device 100 will be described later.

[0046] Each unit pixel cell 10 is connected to a power supply line 40 that supplies a power supply voltage VDD. As shown in the figure, an input terminal (typically a drain) of a signal detection transistor 24 is connected to the power supply line 40. The power supply line 40 functions as a source follower power supply, so that the signal detection transistor 24 amplifies and outputs a signal generated by the photoelectric conversion unit 13.

[0047] An input terminal (here, a drain) of the address transistor 26 is connected to an output terminal (here, a source) of the signal detection transistor 24. The output terminal (here, a source) of the address transistor 26 is connected to one of a plurality of vertical signal lines 47 arranged for each column of the pixel array PA. A control terminal (here, a gate) of the address transistor 26 is connected to an address control line 46, and by controlling the potential of the address control line 46, the output of the signal detection transistor 24 can be selectively read out to the corresponding vertical signal line 47.

[0048] In the illustrated example, the address control lines 46 are connected to a vertical scanning circuit (also called a "row scanning circuit") 36. The vertical scanning circuit 36 ​​applies a predetermined voltage to the address control lines 46 to select a plurality of unit pixel cells 10 arranged in each row on a row-by-row basis. This causes signals from the selected unit pixel cells 10 to be read out, and the pixel electrodes to be reset, as will be described later.

[0049] The vertical signal lines 47 are main signal lines that transmit pixel signals from the pixel array PA to peripheral circuits. Column signal processing circuits (also called "row signal accumulation circuits") 37 are connected to the vertical signal lines 47. The column signal processing circuits 37 perform noise suppression signal processing, such as correlated double sampling, and analog-to-digital conversion (AD conversion). As shown in the figure, a column signal processing circuit 37 is provided corresponding to each column of unit pixel cells 10 in the pixel array PA. Horizontal signal readout circuits (also called "column scanning circuits") 38 are connected to these column signal processing circuits 37. The horizontal signal readout circuits 38 sequentially read out signals from the multiple column signal processing circuits 37 to a horizontal common signal line 49.

[0050] In the configuration illustrated in FIG. 1 , the unit pixel cell 10 includes a reset transistor 28. The reset transistor 28 may be, for example, a field-effect transistor, similar to the signal detection transistor 24 and the address transistor 26. Below, unless otherwise noted, an example will be described in which an N-channel MOS is used as the reset transistor 28. As illustrated, the reset transistor 28 is connected between a reset voltage line 44 that supplies a reset voltage Vr and a charge storage node 41. A control terminal (here, the gate) of the reset transistor 28 is connected to a reset control line 48. By controlling the potential of the reset control line 48, the potential of the charge storage node 41 can be reset to the reset voltage Vr. In this example, the reset control line 48 is connected to a vertical scanning circuit 36. Therefore, by the vertical scanning circuit 36 ​​applying a predetermined voltage to the reset control line 48, it is possible to reset the plurality of unit pixel cells 10 arranged in each row, row by row.

[0051] In this example, a reset voltage line 44 that supplies a reset voltage Vr to the reset transistor 28 is connected to a reset voltage supply circuit 34 (hereinafter simply referred to as the "reset voltage source 34"). The reset voltage source 34 is not limited to a specific power supply circuit as long as it has a configuration that allows it to supply a predetermined reset voltage Vr to the reset voltage line 44 during operation of the imaging device 100, and similarly to the voltage supply circuit 32 described above, the reset voltage source 34 is not limited to a specific power supply circuit. The voltage supply circuit 32 and the reset voltage source 34 may each be part of a single voltage supply circuit or may be independent, separate voltage supply circuits. Note that one or both of the voltage supply circuit 32 and the reset voltage source 34 may be part of a vertical scanning circuit 36. Alternatively, the sensitivity control voltage from the voltage supply circuit 32 and / or the reset voltage Vr from the reset voltage source 34 may be supplied to each unit pixel cell 10 via the vertical scanning circuit 36.

[0052] It is also possible to use the power supply voltage VDD of the signal detection circuit 14 as the reset voltage Vr. In this case, a voltage supply circuit (not shown in FIG. 1) that supplies a power supply voltage to each unit pixel cell 10 and the reset voltage source 34 can be shared. Furthermore, since the power supply line 40 and the reset voltage line 44 can be shared, the wiring in the pixel array PA can be simplified. However, using different voltages for the reset voltage Vr and the power supply voltage VDD of the signal detection circuit 14 allows for more flexible control of the imaging device 100.

[0053] (Device structure of unit pixel cell) 2 schematically illustrates an exemplary device structure of a unit pixel cell 10. In the configuration illustrated in FIG. 2, the signal detection transistor 24, address transistor 26, and reset transistor 28 described above are formed on a semiconductor substrate 20. The semiconductor substrate 20 is not limited to a substrate made entirely of semiconductor. The semiconductor substrate 20 may be an insulating substrate having a semiconductor layer provided on the surface on which the photosensitive region is formed. Here, an example will be described in which a P-type silicon (Si) substrate is used as the semiconductor substrate 20.

[0054] The semiconductor substrate 20 has impurity regions (here, N-type regions) 26s, 24s, 24d, 28d, and 28s, and an element isolation region 20t for electrical isolation between the unit pixel cells 10. Here, the element isolation region 20t is also provided between the impurity region 24d and the impurity region 28d. The element isolation region 20t is formed, for example, by ion implantation of acceptors under predetermined implantation conditions.

[0055] The impurity regions 26s, 24s, 24d, 28d, and 28s are typically diffusion layers formed in the semiconductor substrate 20. As shown in FIG. 2, the signal detection transistor 24 includes impurity regions 24s and 24d and a gate electrode 24g (typically a polysilicon electrode). The impurity region 24s serves as, for example, a source region of the signal detection transistor 24. The impurity region 24d functions as, for example, a drain region of the signal detection transistor 24. A channel region of the signal detection transistor 24 is formed between the impurity regions 24s and 24d.

[0056] Similarly, the address transistor 26 includes impurity regions 26s and 24s and a gate electrode 26g (typically a polysilicon electrode) connected to an address control line 46 (see FIG. 1). In this example, the signal detection transistor 24 and the address transistor 26 are electrically connected to each other by sharing the impurity region 24s. The impurity region 26s functions as, for example, a source region of the address transistor 26. The impurity region 26s is connected to a vertical signal line 47 (see FIG. 1), not shown in FIG. 2.

[0057] The reset transistor 28 includes impurity regions 28d and 28s and a gate electrode 28g (typically a polysilicon electrode) connected to a reset control line 48 (see FIG. 1). The impurity region 28s functions as, for example, a source region of the reset transistor 28. The impurity region 28s is connected to a reset voltage line 44 (see FIG. 1), not shown in FIG. 2.

[0058] An interlayer insulating layer 50 (typically a silicon dioxide layer) is disposed on the semiconductor substrate 20 so as to cover the signal detection transistor 24, the address transistor 26, and the reset transistor 28. As shown in the figure, a wiring layer 56 may be disposed in the interlayer insulating layer 50. The wiring layer 56 is typically formed from a metal such as copper, and may include, for example, wiring such as the above-mentioned vertical signal line 47 as part thereof. The number of insulating layers in the interlayer insulating layer 50 and the number of layers included in the wiring layer 56 disposed in the interlayer insulating layer 50 can be set arbitrarily and are not limited to the example shown in FIG. 2 .

[0059] The above-described photoelectric conversion unit 13 is disposed on the interlayer insulating layer 50. In other words, in the embodiment of the present disclosure, a plurality of unit pixel cells 10 constituting a pixel array PA (see FIG. 1 ) are formed on a semiconductor substrate 20. The plurality of unit pixel cells 10 arranged two-dimensionally on the semiconductor substrate 20 form a photosensitive region (pixel region). The distance (pixel pitch) between two adjacent unit pixel cells 10 may be, for example, approximately 2 μm.

[0060] The photoelectric conversion unit 13 includes a pixel electrode 11, a counter electrode 12, and a photoelectric conversion layer 15 disposed therebetween. In this example, the counter electrode 12 and the photoelectric conversion layer 15 are formed across a plurality of unit pixel cells 10. On the other hand, the pixel electrode 11 is provided for each unit pixel cell 10, and is spatially separated from the pixel electrodes 11 of other adjacent unit pixel cells 10, thereby electrically separating the pixel electrodes 11 from the other unit pixel cells 10.

[0061] The counter electrode 12 is typically a transparent electrode made of a transparent conductive material. The counter electrode 12 is disposed on the side of the photoelectric conversion layer 15 where light is incident. Therefore, light transmitted through the counter electrode 12 is incident on the photoelectric conversion layer 15. Note that the light detected by the imaging device 100 is not limited to light within the wavelength range of visible light (e.g., 380 nm or more and 780 nm or less). In this specification, "transparent" means that at least a portion of the light within the wavelength range to be detected is transmitted, and it is not essential that light is transmitted over the entire wavelength range of visible light. In this specification, for convenience, electromagnetic waves in general, including infrared and ultraviolet rays, are referred to as "light." The counter electrode 12 may be made of, for example, ITO, IZO, AZO, FTO, SnO2, T Transparent Conducting Oxides (TCOs) such as iO2 and ZnO2 can be used.

[0062] The photoelectric conversion layer 15 receives incident light and generates hole-electron pairs. The photoelectric conversion layer 15 is typically made of an organic material. Specific examples of materials constituting the photoelectric conversion layer 15 will be described later. Describe.

[0063] As described with reference to FIG. 1 , the counter electrode 12 is connected to a sensitivity control line 42 that is connected to the voltage supply circuit 32. Here, the counter electrode 12 is formed across a plurality of unit pixel cells 10. Therefore, a sensitivity control voltage of a desired magnitude can be applied collectively to a plurality of unit pixel cells 10 from the voltage supply circuit 32 via the sensitivity control line 42. Note that, as long as a sensitivity control voltage of a desired magnitude can be applied from the voltage supply circuit 32, the counter electrode 12 may be provided separately for each unit pixel cell 10. Similarly, the photoelectric conversion layer 15 may be provided separately for each unit pixel cell 10.

[0064] As will be described in detail later, the voltage supply circuit 32 supplies different voltages to the counter electrode 12 during the exposure period and the non-exposure period. In this specification, the "exposure period" refers to a period during which one of positive and negative charges (signal charge) generated by photoelectric conversion is accumulated in the charge accumulation region, and may also be referred to as the "charge accumulation period." In addition, in this specification, a period other than the exposure period during operation of the imaging device is referred to as the "non-exposure period." Note that the "non-exposure period" is not limited to a period during which light is blocked from entering the photoelectric conversion unit 13, but may also include a period during which light is irradiated onto the photoelectric conversion unit 13. The "non-exposure period" also includes a period during which signal charge is unintentionally accumulated in the charge accumulation region due to the occurrence of parasitic sensitivity.

[0065] By controlling the potential of the counter electrode 12 relative to the potential of the pixel electrode 11, either the holes or the electrons of the hole-electron pairs generated in the photoelectric conversion layer 15 by photoelectric conversion can be collected by the pixel electrode 11. For example, when holes are used as signal charges, it is possible to selectively collect the holes by the pixel electrode 11 by setting the potential of the counter electrode 12 higher than that of the pixel electrode 11. The following describes an example in which holes are used as signal charges. Of course, electrons can also be used as signal charges.

[0066] The pixel electrode 11 facing the counter electrode 12 collects one of the positive and negative charges generated by photoelectric conversion in the photoelectric conversion layer 15 by applying an appropriate bias voltage between the counter electrode 12 and the pixel electrode 11. The pixel electrode 11 is made of a metal such as aluminum or copper, a metal nitride, or polysilicon that has been doped with impurities to make it conductive.

[0067] The pixel electrode 11 may be a light-shielding electrode. For example, forming a 100-nm-thick TaN electrode as the pixel electrode 11 can achieve sufficient light-shielding properties. By using the pixel electrode 11 as a light-shielding electrode, it is possible to suppress the incidence of light passing through the photoelectric conversion layer 15 into the channel regions or impurity regions of transistors (in this example, at least one of the signal detection transistor 24, address transistor 26, and reset transistor 28) formed on the semiconductor substrate 20. A light-shielding film may be formed in the interlayer insulating layer 50 using the above-mentioned wiring layer 56. By suppressing the incidence of light into the channel regions of the transistors formed on the semiconductor substrate 20, it is possible to suppress shifts in transistor characteristics (e.g., fluctuations in threshold voltage). Furthermore, by suppressing the incidence of light into the impurity regions formed on the semiconductor substrate 20, it is possible to suppress the introduction of noise due to unintended photoelectric conversion in the impurity regions. In this way, suppressing the incidence of light into the semiconductor substrate 20 contributes to improving the reliability of the imaging device 100.

[0068] As shown in FIG. 2, the pixel electrode 11 is connected to the gate electrode 24g of the signal detection transistor 24 via a plug 52, a wiring 53, and a contact plug 54. In other words, the gate of the signal detection transistor 24 is electrically connected to the pixel electrode 11. The plug 52 and the wiring 53 are made of a metal such as copper. The plug 52, the wiring 53, and the contact plug 54 constitute at least a part of the charge storage node 41 (see FIG. 1) between the signal detection transistor 24 and the photoelectric conversion unit 13. The wiring 53 is formed of a wiring layer 2, the gate electrode 24g of the signal detection transistor 24, the plug 52, the wiring 53, the contact plugs 54 and 55, and the impurity region 28d, which is one of the source region and drain region of the reset transistor 28, function as a charge accumulation region that accumulates the signal charge collected by the pixel electrode 11.

[0069] As signal charges are collected by the pixel electrode 11, a voltage corresponding to the amount of signal charges accumulated in the charge accumulation region is applied to the gate of the signal detection transistor 24. The signal detection transistor 24 amplifies this voltage. The voltage amplified by the signal detection transistor 24 is selectively read out as a signal voltage via the address transistor 26.

[0070] (Findings of the Inventors and Typical Examples of Photoelectric Conversion Layer Configurations) As described above, by irradiating the photoelectric conversion layer 15 with light and applying a bias voltage between the pixel electrode 11 and the counter electrode 12, one of the positive and negative charges generated by photoelectric conversion can be collected by the pixel electrode 11 and stored in the charge accumulation region. The inventors discovered that by using a photoelectric conversion layer 15 exhibiting the photocurrent characteristics described below in the photoelectric conversion unit 13 and reducing the potential difference between the pixel electrode 11 and the counter electrode 12 to a certain extent, signal charges already accumulated in the charge accumulation region can be prevented from migrating to the counter electrode 12 via the photoelectric conversion layer 15. Furthermore, the inventors discovered that further accumulation of signal charges in the charge accumulation region after reducing the potential difference can be prevented. In other words, by controlling the magnitude of the bias voltage applied to the photoelectric conversion layer 15, a global shutter function can be realized without providing separate elements such as transfer transistors for each of the multiple pixels, as in the technology described in Patent Document 1. A typical example of the operation of the imaging device 100 will be described later.

[0071] An example of the configuration of the photoelectric conversion layer 15 and the photocurrent characteristics of the photoelectric conversion layer 15 will be described below.

[0072] The photoelectric conversion layer 15 typically contains a semiconductor material. Here, an organic semiconductor material is used as the semiconductor material.

[0073] The photoelectric conversion layer 15 contains, for example, tin phthalocyanine represented by the following general formula (1) (hereinafter, may be simply referred to as "tin phthalocyanine").

[0074] [ka]

[0075] In general formula (1), R 1 ~R 24 are independently a hydrogen atom or a substituent. The substituent is not limited to a specific one. The substituent may be a deuterium atom, a halogen atom, an alkyl group (cyclohexyl), or the like. a cycloalkenyl group, a bicycloalkenyl group, a tricycloalkyl group, an alkenyl group (including a cycloalkenyl group and a bicycloalkenyl group), an alkynyl group, an aryl group, a heterocyclic group (which may also be called a heterocyclic group), a cyano group, a hydroxy group, a nitro group, a carboxy group, an alkoxy group, an aryloxy group, a silyloxy group, a heterocyclic oxy group, an acyloxy group, a carbamoyloxy group, an alkoxycarbonyloxy group, an aryloxycarbonyloxy group, an amino group (including an anilino group), an ammonio group, an acylamino group, an aminocarbonylamino group, an alkoxycarbonylamino group, an aryloxycarbonylamino group, a sulfonylamino group, an aryloxycarbon ... sulfamoylamino group, alkylsulfonylamino group, arylsulfonylamino group, mercapto group, alkylthio group, arylthio group, heterocyclic thio group, sulfamoyl group, sulfo group, alkylsulfinyl group, arylsulfinyl group, alkylsulfonyl group, arylsulfonyl group, acyl group, aryloxycarbonyl group, alkoxycarbonyl group, carbamoyl group, arylazo group, heterocyclic azo group, imido group, phosphino group, phosphinyl group, phosphinyloxy group, phosphinylamino group, phosphono group, silyl group, hydrazino group, ureido group, boronic acid group (-B(OH)2), phosphato group (-OPO(OH )2), a sulfato group (—OSO3H), or other known substituents.

[0076] As the tin phthalocyanine represented by the above general formula (1), commercially available products can be used. Alternatively, the tin phthalocyanine represented by the above general formula (1) can be synthesized using a naphthalene derivative represented by the following general formula (2) as a starting material, as shown in, for example, JP-A-2010-232410. R in general formula (2) 25 ~R 30 is R in general formula (1) 1 ~R 24 The substituents may be the same as those shown in the above.

[0077] [ka]

[0078] In the tin phthalocyanine represented by the above general formula (1), from the viewpoint of ease of control of the molecular aggregation state, R 1 ~R 24 Of these, 8 or more are hydrogen or deuterium atoms. Informative and R 1 ~R 24 It is more effective if 16 or more of them are hydrogen atoms or deuterium atoms. It is advantageous if all of the phthalocyanines are hydrogen atoms or deuterium atoms, and it is even more advantageous if all of the phthalocyanines are hydrogen atoms or deuterium atoms. Furthermore, tin phthalocyanine represented by the following formula (3) is advantageous in terms of ease of synthesis.

[0079] [ka]

[0080] The tin phthalocyanine represented by the general formula (1) has absorption in the wavelength band of approximately 200 nm or more and 1100 nm or less. For example, the tin phthalocyanine represented by the formula (3) has an absorption peak at a wavelength of approximately 870 nm, as shown in FIG. 3. FIG. 3 shows an example of the absorption spectrum of a photoelectric conversion layer containing the tin phthalocyanine represented by the formula (3). Note that the absorption spectrum was measured using a sample in which a photoelectric conversion layer (thickness: 30 nm) was laminated on a quartz substrate.

[0081] 3, a photoelectric conversion layer formed from a material containing tin phthalocyanine has absorption in the near-infrared region. That is, by selecting a material containing tin phthalocyanine as the material constituting the photoelectric conversion layer 15, it is possible to realize, for example, an optical sensor capable of detecting near-infrared light.

[0082] Fig. 4 shows a schematic diagram of an example of the configuration of the photoelectric conversion layer 15. In the configuration shown in Fig. 4, the photoelectric conversion layer 15 includes a hole-blocking layer 15h, a photoelectric conversion structure 15A formed using an organic semiconductor material containing tin phthalocyanine represented by the above-mentioned general formula (1), and an electron-blocking layer 15e. The hole-blocking layer 15h is disposed between the photoelectric conversion structure 15A and the counter electrode 12, and the electron-blocking layer 15e is disposed between the photoelectric conversion structure 15A and the pixel electrode 11.

[0083] The photoelectric conversion structure 15A shown in FIG. 4 includes at least one of a p-type semiconductor and an n-type semiconductor. In the configuration illustrated in FIG. 4, the photoelectric conversion structure 15A includes a p-type semiconductor layer 150p, an n-type semiconductor layer 150n, and a mixed layer 150m sandwiched between the p-type semiconductor layer 150p and the n-type semiconductor layer 150n. The p-type semiconductor layer 150p is disposed between the electron blocking layer 15e and the mixed layer 150m and has the functions of photoelectric conversion and / or hole transport. The n-type semiconductor layer 150n is disposed between the hole blocking layer 15h and the mixed layer 150m and has the functions of photoelectric conversion and / or electron transport. As described below, the mixed layer 150m may include at least one of a p-type semiconductor and an n-type semiconductor.

[0084] The p-type semiconductor layer 150p and the n-type semiconductor layer 150n contain an organic p-type semiconductor and an organic n-type semiconductor, respectively. That is, the photoelectric conversion structure 15A contains an organic photoelectric conversion material containing tin phthalocyanine represented by the above-mentioned general formula (1), and at least one of an organic p-type semiconductor and an organic n-type semiconductor.

[0085] An organic p-type semiconductor (compound) is a donor organic semiconductor (compound), mainly represented by a hole-transporting organic compound, which refers to an organic compound that has the property of readily donating electrons. More specifically, an organic p-type semiconductor (compound) refers to the organic compound with the smaller ionization potential when two organic materials are used in contact. Therefore, any organic compound with electron-donating properties can be used as a donor organic compound. For example, triarylamine compounds, benzidine compounds, pyrazoline compounds, styrylamine compounds, hydrazone compounds, triphenylmethane compounds, carbazole compounds, polysilane compounds, thiophene compounds, phthalocyanine compounds, cyanine compounds, merocyanine compounds, oxonol compounds, polyamine compounds, indole compounds, pyrrole compounds, pyrazole compounds, polyarylene compounds, fused aromatic carbocyclic compounds (naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, tetracene derivatives, pyrene derivatives, perylene derivatives, fluoranthene derivatives), and metal complexes having nitrogen-containing heterocyclic compounds as ligands can be used. The donor organic semiconductor is not limited to these, and as described above, any organic compound with a smaller ionization potential than the organic compound used as the n-type (acceptor) compound can be used as the donor organic semiconductor. The tin phthalocyanine described above is an example of an organic p-type semiconductor material.

[0086] An organic n-type semiconductor (compound) is an acceptor organic semiconductor (compound), and is mainly represented by an electron-transporting organic compound, which refers to an organic compound that has the property of readily accepting electrons. More specifically, an organic n-type semiconductor (compound) refers to the organic compound that has a larger electron affinity when two organic compounds are used in contact with each other. Therefore, any organic compound that has electron-accepting properties can be used as an acceptor organic compound. Examples of such organic compounds include fullerene, fullerene derivatives, fused aromatic carbocyclic compounds (naphthalene derivatives, anthracene derivatives, phenanthrene derivatives, tetracene derivatives, pyrene derivatives, perylene derivatives, and fluoranthene derivatives), 5- to 7-membered heterocyclic compounds containing nitrogen, oxygen, and sulfur atoms (e.g., pyridine, pyrazine, pyrimidine, pyridazine, triazine, quinoline, quinoxaline, quinazoline, phthalazine, cinnoline, isoquinoline, pteridine, acridine, phenazine, phenanthroline, tetrazole, pyrazole, and imidazoline). Examples of compounds that can be used include metal complexes having a ligand such as tetraazoindene, thiazole, oxazole, indazole, benzimidazole, benzotriazole, benzoxazole, benzothiazole, carbazole, purine, triazolopyridazine, triazolopyrimidine, tetrazaindene, oxadiazole, imidazopyridine, pyrazine, pyrrolopyridine, thiadiazolopyridine, dibenzazepine, tribenzazepine, etc.), polyarylene compounds, fluorene compounds, cyclopentadiene compounds, silyl compounds, and nitrogen-containing heterocyclic compounds. However, the organic semiconductor is not limited to these, and as described above, any organic compound having a larger electron affinity than the organic compound used as the p-type (donor) organic compound can be used as the acceptor organic semiconductor.

[0087] The mixed layer 150m may be, for example, a bulk heterojunction structure layer containing a p-type semiconductor and an n-type semiconductor. When the mixed layer 150m is formed as a layer having a bulk heterojunction structure, tin phthalocyanine represented by the above-mentioned general formula (1) may be used as the p-type semiconductor material. The n-type semiconductor material may be, for example, a fullerene and / or a fullerene derivative. It is advantageous if the material constituting the p-type semiconductor layer 150p is the same as the p-type semiconductor material contained in the mixed layer 150m. Similarly, it is advantageous if the material constituting the n-type semiconductor layer 150n is the same as the n-type semiconductor material contained in the mixed layer 150m. Bulk heterojunction structures are described in detail in Japanese Patent No. 5,553,727. The entire disclosure of Japanese Patent No. 5,553,727 is incorporated herein by reference.

[0088] By using an appropriate material depending on the wavelength range to be detected, an imaging device having sensitivity in the desired wavelength range can be realized. The photoelectric conversion layer 15 may contain an inorganic semiconductor material such as amorphous silicon. The photoelectric conversion layer 15 may contain a layer made of an organic material and a layer made of an inorganic material. In the following, tin phthalocyanine and C 60 An example in which a bulk heterojunction structure obtained by co-evaporating the above is applied to the photoelectric conversion layer 15 will be described.

[0089] (Photocurrent characteristics in the photoelectric conversion layer) Fig. 5 shows typical photocurrent characteristics of the photoelectric conversion layer 15. In Fig. 5, the thick solid line graph shows exemplary current-voltage characteristics (IV characteristics) of the photoelectric conversion layer 15 in a state where light is irradiated. Note that Fig. 5 also shows an example of the IV characteristics in a state where light is not irradiated by a thick dashed line.

[0090] Figure 5 shows the change in current density between the two principal surfaces of the photoelectric conversion layer 15 when the bias voltage applied between them is changed under a constant illuminance. In this specification, the forward and reverse directions of the bias voltage are defined as follows. When the photoelectric conversion layer 15 has a junction structure of a layered p-type semiconductor and a layered n-type semiconductor, a bias voltage that makes the potential of the p-type semiconductor layer higher than that of the n-type semiconductor layer is defined as a forward bias voltage. On the other hand, a bias voltage that makes the potential of the p-type semiconductor layer lower than that of the n-type semiconductor layer is defined as a reverse bias voltage. is defined as the reverse bias voltage. When an organic semiconductor material is used, the forward and reverse directions can be defined in the same way as when an inorganic semiconductor material is used. When the photoelectric conversion layer 15 has a bulk heterojunction structure, as shown in FIG. 1 of the aforementioned Japanese Patent Publication No. 5553727, one of the two main surfaces of the bulk heterojunction structure facing the electrode contains more p-type semiconductors than n-type semiconductors, and the other surface contains more n-type semiconductors than p-type semiconductors. Therefore, the bias voltage at which the potential on the main surface where more p-type semiconductors than n-type semiconductors are present is higher than the potential on the main surface where more n-type semiconductors than p-type semiconductors are present is defined as the forward bias voltage.

[0091] As shown in FIG. 5, the photocurrent characteristics of the photoelectric conversion layer 15 are roughly characterized by three voltage ranges, first to third. The first voltage range is a reverse bias voltage range, in which the absolute value of the output current density increases as the reverse bias voltage increases. The first voltage range can also be said to be a voltage range in which the photocurrent increases as the bias voltage applied between the principal surfaces of the photoelectric conversion layer 15 increases. The second voltage range is a forward bias voltage range, in which the output current density increases as the forward bias voltage increases. In other words, the second voltage range is a voltage range in which the forward current increases as the bias voltage applied between the principal surfaces of the photoelectric conversion layer 15 increases. The third voltage range is a voltage range between the first and second voltage ranges.

[0092] The first to third voltage ranges can be distinguished by the slope of the graph of the photocurrent characteristics when linear vertical and horizontal axes are used. For reference, in FIG. 5, the average slopes of the graphs in the first and second voltage ranges are indicated by dashed lines L1 and L2, respectively. As illustrated in FIG. 5, the first, second, and third voltage ranges have different rates of change in output current density with increasing bias voltage. The third voltage range is defined as a voltage range in which the rate of change in output current density with respect to bias voltage is smaller than the rates in the first and second voltage ranges. Alternatively, the third voltage range may be determined based on the position of a rising (falling) edge in the graph showing the IV characteristics. The third voltage range is typically greater than -1 V and less than +1 V. In the third voltage range, the current density between the principal surfaces of the photoelectric conversion layer 15 hardly changes even when the bias voltage is changed. As illustrated in FIG. 5, in the third voltage range, the absolute value of the current density is typically 100 μA / cm 2 The following is the result.

[0093] (Example of operation of imaging device 100) FIG. 6 is a diagram illustrating an example of the operation of an imaging device according to an embodiment of the present disclosure. FIG. 6 shows the timing of the falling (or rising) edges of the synchronization signal, the temporal change in the magnitude of the bias voltage applied to the photoelectric conversion layer 15, and the timing of reset and exposure for each row of the pixel array PA (see FIG. 1). More specifically, the top graph in FIG. 6 shows the timing of the falling (or rising) edges of the vertical synchronization signal Vss. The second graph from the top shows the timing of the falling (or rising) edges of the horizontal synchronization signal Hss. Below these graphs, an example of the temporal change in the voltage Vb applied to the counter electrode 12 from the voltage supply circuit 32 via the sensitivity control line 42 is shown. Below the graph of the temporal change in voltage Vb, the temporal change in the potential φ of the counter electrode 12 relative to the potential of the pixel electrode 11 is shown. The double-headed arrow G3 in the graph of the potential φ indicates the third voltage range described above. The chart below that diagram schematically illustrates the timing of reset and exposure for each row of the pixel array PA.

[0094] An example of the operation of the imaging device 100 will be described below with reference to Figures 1, 2, and 6. For simplicity, an example of the operation will be described here when the number of rows of pixels included in the pixel array PA is eight, from row R0 to row R7.

[0095] To acquire an image, first, the charge accumulation region of each unit pixel cell 10 in the pixel array PA is reset, and the pixel signals after the reset are read out. For example, as shown in FIG. 6, resetting of a plurality of pixels belonging to row R0 is started based on the vertical synchronization signal Vss (time t0). Note that the dotted rectangle in FIG. 6 schematically represents the signal readout period. This readout period may include a reset period for resetting the potential of the charge accumulation region of the unit pixel cell 10.

[0096] To reset the pixels in row R0, the address transistor 26, whose gate is connected to the address control line 46, is turned on by controlling the potential of the address control line 46 in row R0. Furthermore, the reset transistor 28, whose gate is connected to the reset control line 48, is turned on by controlling the potential of the reset control line 48 in row R0. This connects the charge storage node 41 to the reset voltage line 44, and a reset voltage Vr is supplied to the charge storage region. That is, the potentials of the gate electrode 24g of the signal detection transistor 24 and the pixel electrode 11 of the photoelectric conversion unit 13 are reset to the reset voltage Vr. Then, a post-reset pixel signal is read from the unit pixel cell 10 in row R0 via the vertical signal line 47. The pixel signal obtained at this time corresponds to the magnitude of the reset voltage Vr. After the pixel signal is read, the reset transistor 28 and address transistor 26 are turned off.

[0097] In this example, as shown in Figure 6, pixels in rows R0 to R7 are reset sequentially row by row in accordance with the horizontal synchronization signal Hss. Hereinafter, the interval between pulses of the horizontal synchronization signal Hss, in other words, the period from when a row is selected to when the next row is selected, may be referred to as a "1H period." In this example, the period from time t0 to time t1 corresponds to the 1H period.

[0098] 6, during the period from the start of image acquisition to the end of resetting all rows of the pixel array PA and reading out pixel signals (times t0 to t9), a voltage V3 that brings the potential difference between the pixel electrodes 11 and the counter electrode 12 into the above-mentioned third voltage range is applied from the voltage supply circuit 32 to the counter electrode 12. That is, during the period from the start of image acquisition to the start of the exposure period (time t9), a bias voltage in the third voltage range is applied to the photoelectric conversion layer 15 of the photoelectric conversion unit 13.

[0099] When a bias voltage in the third voltage range is applied to the photoelectric conversion layer 15, almost no signal charge is transferred from the photoelectric conversion layer 15 to the charge accumulation region. This is presumably because, when a bias voltage in the third voltage range is applied to the photoelectric conversion layer 15, most of the positive and negative charges generated by light irradiation quickly recombine and disappear before being collected by the pixel electrode 11. Therefore, when a bias voltage in the third voltage range is applied to the photoelectric conversion layer 15, almost no signal charge is accumulated in the charge accumulation region even when light is incident on the photoelectric conversion layer 15. This prevents unintended sensitivity (sometimes referred to as "parasitic sensitivity" in this specification) from occurring during periods other than the exposure period. Thus, the fact that sensitivity can be quickly reduced to zero by setting the bias voltage to the photoelectric conversion layer 15 in the third voltage range was discovered for the first time by the present inventors.

[0100] 6, when focusing on a certain row (for example, row R0), the periods indicated by the dotted rectangles and the hatched rectangles represent non-exposure periods. Note that the voltage V3 for applying the bias voltage in the third voltage range to the photoelectric conversion layer 15 is not limited to 0 V.

[0101] After resetting all rows of the pixel array PA and reading out pixel signals, an exposure period starts based on the horizontal synchronization signal Hss (time t9). In FIG. 6, the white rectangles schematically represent the exposure period for each row. During the exposure period, the voltage supply circuit 32 applies a voltage to the counter electrode 12. The change starts when the voltage applied to the pixel electrode 11 is switched to a voltage Ve different from the voltage V3. The voltage Ve is typically a voltage (for example, about 10 V) that causes the potential difference between the pixel electrode 11 and the counter electrode 12 to fall within the first voltage range described above. When the voltage Ve is applied to the counter electrode 12, the signal charges (holes in this example) in the photoelectric conversion layer 15 are collected by the pixel electrode 11 and stored in a charge storage region (which may also be called a charge storage node 41).

[0102] The voltage supply circuit 32 switches the voltage applied to the counter electrode 12 back to voltage V3, thereby ending the exposure period (time t13). As described above, in the embodiment of the present disclosure, the voltage applied to the counter electrode 12 is switched between voltage V3 and voltage Ve, thereby switching between an exposure period and a non-exposure period. As can be seen from FIG. 6, the start (time t9) and end (time t13) of the exposure period in this example are common to all pixels included in the pixel array PA. In other words, the operation described here is an example in which a global shutter is applied to the imaging device 100.

[0103] Next, signal charges are read out from pixels belonging to each row of the pixel array PA based on the horizontal synchronization signal Hss. In this example, starting from time t15, signal charges are read out from pixels belonging to rows R0 to R7, row by row, in sequence. Hereinafter, the period from when pixels belonging to a certain row are selected until pixels belonging to that row are selected again may be referred to as the "1V period." In this example, the period from time t0 to time t15 corresponds to the 1V period.

[0104] When reading out signal charges from pixels belonging to row R0 after the exposure period ends, the address transistor 26 of row R0 is turned ON. As a result, a pixel signal corresponding to the amount of charge accumulated in the charge accumulation region during the exposure period is output to the vertical signal line 47. Following the reading out of the pixel signal, the reset transistor 28 may be turned ON to reset the pixel. After the pixel signal is read out, the address transistor 26 (and reset transistor 28) are turned OFF. After the signal charges are read out from pixels belonging to each row of the pixel array PA, a signal from which fixed noise has been removed can be obtained by calculating the difference between the signal read out between time t0 and time t9.

[0105] During the non-exposure period, voltage V3 is applied to the counter electrode 12, and thus a bias voltage in the third voltage range is applied to the photoelectric conversion layer 15 of the photoelectric conversion unit 13. Therefore, even when light is incident on the photoelectric conversion layer 15, further accumulation of signal charge in the charge accumulation region hardly occurs. Therefore, the generation of noise due to unintended charge mixing is suppressed.

[0106] To prevent further accumulation of signal charge in the charge accumulation region, it is possible to terminate the exposure period by applying a voltage to the counter electrode 12 that is the opposite polarity of the voltage Ve. However, simply reversing the polarity of the voltage applied to the counter electrode 12 may cause the already accumulated signal charge to migrate to the counter electrode 12 via the photoelectric conversion layer 15. The migration of signal charge from the charge accumulation region to the counter electrode 12 via the photoelectric conversion layer 15 is observed as, for example, black dots in the captured image. In other words, the migration of signal charge from the charge accumulation region to the counter electrode 12 via the photoelectric conversion layer 15 may cause negative parasitic sensitivity.

[0107] In this example, after the exposure period ends, the voltage applied to the counter electrode 12 is changed back to voltage V3, so that the photoelectric conversion layer 15 after the accumulation of signal charges in the charge accumulation region is in a state in which a bias voltage in the third voltage range is applied. In a state in which a bias voltage in the third voltage range is applied, it is possible to suppress the movement of signal charges already accumulated in the charge accumulation region to the counter electrode 12 via the photoelectric conversion layer 15. In other words, the third bias voltage range is applied to the photoelectric conversion layer 15. By applying a bias voltage in this range, the signal charge accumulated during the exposure period can be retained in the charge storage region, which means that the occurrence of negative parasitic sensitivity due to loss of signal charge from the charge storage region can be suppressed.

[0108] As described above, in the embodiment of the present disclosure, the start and end of the exposure period are controlled by the voltage Vb applied to the counter electrode 12. That is, according to the embodiment of the present disclosure, a global shutter function can be realized without providing a transfer transistor or the like in each unit pixel cell 10. In the embodiment of the present disclosure, the electronic shutter is performed by controlling the voltage Vb without transferring signal charges via a transfer transistor, which enables faster operation. Furthermore, since there is no need to provide a separate transfer transistor or the like in each unit pixel cell 10, this is also advantageous for miniaturizing pixels.

[0109] (Application example) In the example of operation described with reference to FIG. 6, one exposure period is provided common to all pixels during a 1V period, and one image is acquired based on the signal charges accumulated during that exposure period. In such an operation, the total time required to acquire pixel signals necessary to form the final image, i.e., one frame of image, can be roughly equal to (1V period) + (number of rows in pixel array PA) × (signal readout period) ("×" means multiplication). In this specification, the total time required to acquire pixel signals necessary to form the final image is referred to as "one frame period." In the example shown in FIG. 6, the signal readout period for each row in pixel array PA is set equal to a 1H period, so one frame period can be said to be (1V + 8 × 1H).

[0110] In the example shown in FIG. 6, one exposure period is provided for all pixels during one frame period. However, multiple exposure periods may be provided for all pixels during one frame period. In other words, so-called multiple exposure may be performed to ultimately form one frame of image. Multiple exposure makes it possible to record the trajectory of an object that moves within one frame period (hereinafter, sometimes referred to as a "moving object") in one frame of image. Multiple exposure is useful for analyzing moving objects and high-speed phenomena. Hereinafter, an image formed based on pixel signals obtained by performing multiple exposure will be referred to as a "multiple-exposure image."

[0111] Fig. 7 schematically illustrates an example of an imaging system configured to form a multiple exposure image. The imaging system 100S illustrated in Fig. 7 generally includes a camera unit 80 and a display unit 90. The camera unit 80 and the display unit 90 may be two parts of a single device, or may be separate, independent devices. In the configuration illustrated in Fig. 7, the camera unit 80 includes an optical system 110, an imaging device 100, a system controller 120, and an image forming circuit 130, and the display unit 90 includes a signal processing circuit 150 and a display device 160.

[0112] The optical system 110 of the camera unit 80 includes an aperture, an image stabilization lens, a zoom lens, and a focus lens. The number of lenses included in the optical system 110 is determined appropriately depending on the required functions. The system controller 120 controls each component of the camera unit 80. The system controller 120 is typically a semiconductor integrated circuit such as a CPU, and sends control signals to, for example, a lens drive circuit in the optical system 110. In this example, the system controller 120 also controls the operation of the image capture device 100. For example, the system controller 120 controls the drive of the vertical scanning circuit 36. The voltage applied from the voltage supply circuit 32 to the sensitivity control line 42 may be switched based on the control of the system controller 120. The system controller 120 may include one or more memories. The image formation circuit 130 is configured to form a multiple exposure image based on the output of the image capture device 100. The image formation circuit 130 may include, for example, a DSP (Digital Signal Processor), an FPGA ( The image forming circuit 130 may include a memory. The operation of the image forming circuit 130 may be controlled by the system controller 120. An example of forming a multiple exposure image will be described later.

[0113] 7, the image forming circuit 130 has an output buffer 140. The image forming circuit 130 outputs data of the multiple exposure image to the display unit 90 via the output buffer 140. The data output from the image forming circuit 130 is typically RAW data, for example, a 12-bit signal. The data output from the image forming circuit 130 may be data compressed in accordance with the H.264 standard, for example.

[0114] The signal processing circuit 150 of the display unit 90 receives the output from the image forming circuit 130. The output from the image forming circuit 130 may be temporarily stored in an external recording medium (for example, a flash memory) that can be freely connected to and disconnected from the camera unit 80. In other words, the output from the image forming circuit 130 may be passed to the display unit 90 via the external recording medium.

[0115] The signal processing circuit 150 performs processes such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The signal processing circuit 150 is typically a DSP, an ISP (Image Signal Processor), or the like. The display device 160 of the display unit 90 is a liquid crystal display, an organic EL (electroluminescence) display, or the like. The display device 160 performs processes such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The display unit 90 displays an image based on an output signal from the processing circuit 150. The display unit 90 may be a personal computer, a smartphone, or the like.

[0116] An example of forming a multiple exposure image will be described below with reference to FIGS.

[0117] FIG. 8 is a diagram illustrating an example of forming a multiple-exposure image. Here, multiple exposures are performed to form one frame of a multiple-exposure image. As shown in FIG. 8, first, based on the vertical synchronization signal Vss, the pixels in rows R0 to R7 are reset and their pixel signals are read out sequentially row by row (time t00). At this time, the voltage supply circuit 32 (see FIG. 1) applies a voltage V3 to the counter electrode 12 so that the potential difference between the pixel electrode 11 and the counter electrode 12 falls within the third voltage range described above.

[0118] Next, the voltage applied to the counter electrode 12 is switched to voltage Ve1, thereby starting an exposure period common to all pixels in the pixel array PA. Voltage Ve1 is a voltage that causes the potential difference between the pixel electrode 11 and the counter electrode 12 to fall within, for example, the first voltage range described above. By applying voltage Ve1 to the counter electrode 12, one of the positive and negative charges (signal charge) generated by photoelectric conversion is accumulated in the charge accumulation region. The exposure period ends when the voltage supply circuit 32 switches the voltage applied to the counter electrode 12 back to voltage V3.

[0119] Next, based on the vertical synchronization signal Vss, pixel signals from pixels belonging to rows R0 to R7 are read out sequentially row by row (time t01). This results in image data corresponding to the exposure period between times t00 and t01. The image data obtained at this time is temporarily stored, for example, in the memory of the image forming circuit 130 (see FIG. 7). In this example, after the pixel signals are read out, resetting of the pixels belonging to rows R0 to R7 is again performed.

[0120] After the second reset is performed, the voltage applied to the counter electrode 12 is switched to voltage Ve2, thereby starting a second exposure period for all pixels in the pixel array PA. The voltage supply circuit 32 switches the voltage applied to the counter electrode 12 back to voltage V3, thereby ending the second exposure period. After the second exposure period ends, pixel signals from the pixels belonging to rows R0 to R7 are read out row by row (time t02). , image data corresponding to the second exposure period is obtained. The points of temporarily storing the image data obtained at this time, for example, in the memory of the image forming circuit 130, and re-executing the reset of the pixels belonging to each row from the R0th row to the R7th row after the pixel signal is read out are the same as those for obtaining the image data corresponding to the first exposure period.

[0121] After that, the same operation is repeated the desired number of times. As a result, a plurality of image data corresponding to each exposure period are obtained. The image forming circuit 130 forms a multiple-exposure image, for example, by superimposing these multiple image data.

[0122] As shown in FIG. 8, in obtaining a plurality of image data for forming a multiple-exposure image, voltages of different magnitudes may be supplied from the voltage supply circuit 32 to the counter electrode 12 for each exposure period. In the example shown in FIG. 8, the voltage supply circuit 32 applies voltages Ve1, Ve2, and Ve3 of different magnitudes to the counter electrode 12 during a plurality of exposure periods. Here, Ve1 < Ve2 < Ve3. In a multiple-exposure image, an image of a subject that moves during one frame period appears at different positions in the image. As in the example described here, by changing the bias voltage applied to the photoelectric conversion layer 15 for each exposure period, it is possible to impart a change in display attributes to each of the images of the moving object that appears in the multiple-exposure image. For example, the brightness can be changed between each of the images of the moving object that appears in the multiple-exposure image. In the image of the moving object, the display attributes that change due to the change in the bias voltage for each exposure period are typically at least one of brightness and color (hue or saturation).

[0123] FIG. 9 shows together an exemplary multiple-exposure image obtained by the imaging system 100S and a plurality of images taken out in time series from the multiple-exposure image, each containing one image of a moving object. FIG. 9 is an example when five exposure periods are included in one frame period.

[0124] As shown on the left side of FIG. 9, in a multiple-exposure image obtained by changing the bias voltage applied to the photoelectric conversion layer 15 for each exposure period, the display attributes of each image of a moving object are different. Therefore, as shown on the right side of FIG. 9, it is possible to construct a sequence of multiple images showing the movement of a moving object from the multiple-exposure image. In this way, by forming a multiple-exposure image by superimposing multiple pieces of image data obtained by changing the bias voltage during the exposure period, it is possible to include information showing the movement of an object (e.g., path, change in speed) during one frame period in the multiple-exposure image. This shooting method can reduce the increase in data volume compared to sending multiple pieces of image data corresponding to each exposure period. Note that the change in voltage supplied by the voltage supply circuit 32 during each exposure period may be a monotonically increasing change as shown in FIG. 8, a monotonically decreasing change, or a random change.

[0125] As illustrated in FIGS. 10 and 11, an identifier image indicating the change in the position of a moving object over time may be superimposed on a multiple exposure image. In the example illustrated in FIG. 10, arrows connecting the centers of multiple moving object images are superimposed as identifiers indicating the change in the position of the moving object over time. In the example illustrated in FIG. 11, numbers indicating the change in the position of the moving object over time are superimposed as identifiers. The moving object images included in the multiple exposure image exhibit display attributes corresponding to each exposure period. Therefore, it is possible to assign identifiers to the multiple exposure images after they are formed by analyzing the display attributes of the moving object images included in the multiple exposure image. Instead of numbers, letters, symbols, etc. may be used as identifiers. The superimposition of the identifier image may be performed by the image forming circuit 130.

[0126] 8, the signal charge accumulated in the charge accumulation region is read out in correspondence with each exposure period. However, a multiple exposure image may be formed by performing multiple exposures and reading out the signal charge accumulated in the charge accumulation region over the entire one frame period.

[0127] FIG. 12 is a diagram for explaining another example of forming a multiple-exposure image. In the example shown in FIG. 12, first, based on the vertical synchronization signal Vss, resetting of pixels belonging to each row from the R0th row to the R7th row and reading of pixel signals are sequentially executed in row units (time t00). Next, the first exposure is executed by applying a voltage Ve1 to the counter electrode 12. After the end of the first exposure period, without reading the pixel signals of the pixels, the second exposure is executed by applying a voltage Ve2 (where Ve2 > Ve1 here) to the counter electrode 12. Therefore, in the charge storage region, in addition to the signal charges already stored, signal charges corresponding to the second exposure period are further stored. Such accumulation of signal charges is executed a desired number of times while changing the magnitude of the applied voltage to the counter electrode 12 during the exposure period. In this example, the number of exposures is 5 times, and in the fifth exposure period, a voltage Ve5 (Ve1 < Ve2 <... < Ve5), different from both Ve1 and Ve2, is applied to the counter electrode 12.

[0128] After the end of the five exposure periods, based on the vertical synchronization signal Vss, reading of the pixel signals is executed (time t04). That is, in this example, reading of the total signal charges accumulated during the multiple exposure periods from the signal detection circuit is performed once during one frame period. Thus, the image forming circuit 130 may form a multiple-exposure image based on the finally obtained pixel signals instead of synthesizing a plurality of image data corresponding to each exposure period.

[0129] The image forming circuit 130 is not limited to a processing circuit specialized for forming a multiple-exposure image. The formation of a multiple-exposure image may be realized by a combination of a general-purpose processing circuit and a program in which processing for forming a multiple-exposure image is described. This program may be stored in a memory in the image forming circuit 130, a memory in the system controller 120, and the like.

[0130] (Other modified examples of the imaging device) Referring again to FIG. 2 , as already described, in the embodiment of the present disclosure, a global shutter is realized by applying different voltages to the counter electrode 12 during exposure and non-exposure periods. During the non-exposure period, the voltage supply circuit 32 (see FIG. 1 ) supplies a voltage to the counter electrode 12 via the sensitivity control line 42 such that the bias voltage applied to the photoelectric conversion layer 15 falls within the third voltage range described above. On the other hand, the potential of the pixel electrode 11 during the non-exposure period is determined by the reset voltage Vr supplied to the pixel electrode 11 and the charge accumulation region, which includes the impurity region 28d as a part thereof. As already described, the reset voltage Vr is supplied to the charge accumulation region via the reset transistor 28, which has the impurity region 28d as its drain region (or source region). The reset transistor 28 has the function of switching between supplying and blocking the reset voltage Vr to the charge accumulation region.

[0131] 2, the reset voltage Vr is supplied from a reset voltage source 34 (see FIG. 1) to an impurity region 28s, which is the source region (or drain region) of the reset transistor 28. The reset voltage source 34 and the voltage supply circuit 32 may be a common circuit. However, as will be described below, it is useful if the voltage supply circuit 32 and the reset voltage source 34 can independently supply voltages of different magnitudes.

[0132] FIG. 13 is a timing chart illustrating an exemplary operation of the reset voltage source 34 during the reset period. In FIG. 13, the top graph shows an example of the temporal change in the voltage Vb applied from the voltage supply circuit 32 to the counter electrode 12, and the second graph shows the change in the voltage level Vrst on the reset control line 48 connected to the gate of the reset transistor 28. The third graph from the top shows the temporal change in the potential φfd of the charge storage region. The temporal change in the potential φfd can be said to represent the temporal change in the potential of the pixel electrode 11. Below the graph of the temporal change in the potential φfd, the temporal change in the potential φ of the counter electrode 12 relative to the potential of the pixel electrode 11 is shown.

[0133] 13, the voltage Vc applied to the counter electrode 12 during the signal readout period, which includes the reset period as a part thereof, is typically constant. In this state, when the voltage of the reset control line 48 is set to high level, a reset voltage Vr is applied via the reset transistor 28, and the potential φfd of the charge storage region is reset to Vr. Therefore, at first glance, it is expected that if Vc=Vr, that is, if the reset voltage Vr is the same as the voltage Vc applied to the counter electrode 12, the potential difference between the pixel electrode 11 and the counter electrode 12 after resetting can be made zero.

[0134] However, in reality, when the voltage of the reset control line 48 is set to low level to turn off the reset transistor 28, the potential φfd of the charge storage region fluctuates due to coupling between the charge storage region and the reset transistor 28. In this example, turning off the reset transistor 28 causes the potential φfd of the charge storage region to drop by ΔV (ΔV>0). Therefore, simply setting the voltage Vc applied to the counter electrode 12 and the reset voltage Vr equal during the signal readout period may, in extreme cases, cause the potential difference between the pixel electrode 11 and the counter electrode 12 after reset to fall outside the third voltage range. If the potential difference between the pixel electrode 11 and the counter electrode 12 after reset falls outside the third voltage range, parasitic sensitivity occurs.

[0135] Therefore, the reset voltage Vr may be a voltage greater than the voltage Vc applied to the counter electrode 12 during the signal readout period. For example, taking into account the voltage drop in the charge accumulation region due to coupling, if a voltage obtained by adding ΔV to the voltage Vc applied to the counter electrode 12 is used as the reset voltage Vr, the potential difference between the pixel electrode 11 and the counter electrode 12 after resetting can be made close to 0, thereby canceling the sensitivity caused by electrical coupling.

[0136] The specific value of ΔV mainly depends on the characteristics of the reset transistor 28 (typically, the parasitic capacitance between the source and gate) and can be known in advance. For example, ΔV may be measured before shipping the product and the obtained ΔV may be written to a memory (e.g., a ROM) connected to the system controller 120 (see FIG. 7 ). The system controller 120 can correct the magnitude of the reset voltage Vr supplied from the reset voltage source 34 based on the value of ΔV by referring to the ΔV stored in the memory. Alternatively, the circuit configuration of the reset voltage source 34 may be adjusted in accordance with the value of ΔV so that the output voltage becomes a desired voltage. Instead of correcting the reset voltage Vr supplied from the reset voltage source 34, or in addition to correcting the reset voltage Vr, the voltage supplied from the voltage supply circuit 32 to the counter electrode 12 may be corrected. However, the correction of the reset voltage Vr is advantageous over the correction of the voltage supplied from the voltage supply circuit 32 to the counter electrode 12 in that it can be performed for each pixel. Such calibration of the reset voltage Vr (and / or the voltage supplied to the counter electrode 12) may be performed before shipping of the imaging device 100, or may be performed by the user of the imaging device 100.

[0137] If the reset transistor 28 is a P-channel transistor, the potential φfd of the charge storage region rises by ΔV when the reset transistor 28 is turned off, as shown in Fig. 14. Therefore, when a P-channel transistor is used as the reset transistor 28, a voltage smaller than the voltage Vc applied to the counter electrode 12 during the signal readout period should be used as the reset voltage Vr.

[0138] 13 and 14, in the period before the reset period, the potential φ of the counter electrode 12 is outside the third voltage range when the potential of the pixel electrode 11 is used as a reference. As in these examples, the voltage Vb applied to the counter electrode 12 from the voltage supply circuit 32 is within the third voltage range during the entire non-exposure period. The voltage does not need to be such that the potential difference between the pixel electrode 11 and the counter electrode 12 falls within the third voltage range over the entire period. Before the pixel is reset, the potential φ of the counter electrode 12 relative to the potential of the pixel electrode 11 may be outside the third voltage range.

[0139] Using the corrected voltage as the reset voltage Vr in this way can suppress the occurrence of parasitic sensitivity due to electrical coupling. If a correction value is too large, a large potential difference may occur between the pixel electrode 11 and the counter electrode 12 during reset, potentially causing charges in the charge storage region to flow into the counter electrode 12 through the photoelectric conversion layer 15. In other words, there is a risk of charges flowing back through the photoelectric conversion layer 15. Therefore, it is beneficial for the absolute value of the difference between the reset voltage Vr and the voltage Vc applied to the counter electrode 12 by the voltage supply circuit 32 to be smaller than the breakdown voltage of the photoelectric conversion layer 15. For example, if the reset transistor 28 is an N-channel transistor, it is beneficial for the reset voltage Vr not to exceed the voltage Vc. The breakdown voltage of the photoelectric conversion layer 15 can be defined as the voltage at which charges in the charge storage region flow from the pixel electrode 11 to the counter electrode 12 through the photoelectric conversion layer 15, causing the photoelectric conversion layer 15 to lose its function. Alternatively, it is beneficial that the absolute value of the difference between the reset voltage Vr and the voltage Vc applied to the counter electrode 12 by the voltage supply circuit 32 is smaller than the input voltage to the signal detection circuit 14 (typically VDD).

[0140] Fig. 15 shows a modified example of the imaging device 100. In the configuration shown in Fig. 15, the semiconductor substrate 20 is connected to a substrate voltage supply circuit 35 that supplies a predetermined substrate voltage Vs. The substrate voltage Vs applied from the substrate voltage supply circuit 35 is a voltage different from 0V.

[0141] If the reset voltage Vr is set to a voltage close to 0 V, the voltage Vc applied from the voltage supply circuit 32 to the counter electrode 12 can be set to 0 V, i.e., the counter electrode 12 can be grounded, which can further simplify the circuit configuration of the imaging device 100. However, if the reset voltage Vr is, for example, 0 V, the signal detection transistor 24 does not function as a source follower, and the signal voltage cannot be read out.

[0142] In the configuration illustrated in FIG. 15 , a substrate voltage Vs other than 0 V is applied to the semiconductor substrate 20. For example, a negative voltage is applied to the semiconductor substrate 20 as the substrate voltage Vs, thereby shifting the substrate potential. By shifting the substrate potential, it is possible to achieve both dark current suppression and linearity in the signal detection circuit 14, even when the reset voltage Vr and the voltage Vc applied from the voltage supply circuit 32 to the counter electrode 12 are set to 0 V. The substrate voltage supply circuit 35 may be shared with the voltage supply circuit 32 and / or the reset voltage source 34. Note that if the voltage Vc applied from the voltage supply circuit 32 to the counter electrode 12 is set to a positive voltage, it is possible to obtain the same effect as when the reset voltage Vr and the voltage Vc are set to 0 V, while avoiding the application of a negative voltage to the semiconductor substrate 20.

[0143] As described above, according to the embodiment of the present disclosure, it is possible to control the accumulation and retention of charges in the charge accumulation region by controlling the voltage applied to the counter electrode 12. Therefore, it is possible to achieve a global shutter function with a simpler device structure.

[0144] In addition to the above-described examples, various modifications are possible for the imaging device according to the embodiment of the present disclosure. For example, switching between global shutter driving and rolling shutter driving may be performed depending on the subject. In rolling shutter driving, the voltage applied to the counter electrode 12 by the voltage supply circuit 32 may be fixed at voltage Ve during both exposure and non-exposure periods. In this case, the exposure period can be determined by the time from the reset timing of the charge storage node 41 to the signal readout.

[0145] The signal detection transistor 24, address transistor 26 and reset transistor Each of the transistors 28 may be either an N-channel MOS or a P-channel MOS. It is not necessary that all of them be unified as either an N-channel MOS or a P-channel MOS. In addition to field effect transistors, bipolar transistors may also be used as the signal detection transistors 24 and / or the address transistors 26. [Industrial Applicability]

[0146] The imaging device of the present disclosure can be applied to, for example, an image sensor. The imaging device of the present disclosure can be used in medical cameras, robot cameras, security cameras, cameras mounted on vehicles, and the like. The vehicle-mounted camera can be used, for example, as an input to a control device to ensure safe vehicle driving. Alternatively, the camera can be used to assist an operator in ensuring safe vehicle driving. [Explanation of symbols]

[0147] 10 unit pixel cells 11 Pixel electrode 12 Counter electrode 13 Photoelectric conversion unit 14 Signal detection circuit 15 Photoelectric conversion layer 15A Photoelectric conversion structure 15e Electron Blocking Layer 15h hole blocking layer 20 Semiconductor substrate 20t isolation region 24d, 24s, 26s, 28d, 28s impurity region 24 Signal detection transistor 26 Address transistor 28 Reset transistor 24g, 26g, 28g gate electrodes 32 Voltage supply circuit (sensitivity control voltage supply circuit) 34 Reset voltage source (reset voltage supply circuit) 35 Substrate voltage supply circuit 36 Vertical scanning circuit 40 Power line 41 Charge storage node 42 Sensitivity control line 50 Interlayer insulation layer 44 Reset voltage line 46 Address Control Line 47 Vertical signal line 48 Reset control line 80 Camera Department 90 Display section 100 Imaging device 100S Imaging System 130 Image formation circuit PA pixel array

Claims

1. A plurality of pixels arranged in a matrix; a voltage supply circuit; Equipped with Each of the plurality of pixels is a photoelectric conversion layer that converts light into signal charges; a first electrode for collecting the signal charges; a charge accumulation region connected to the first electrode and configured to accumulate the signal charges; a second electrode facing the first electrode with the photoelectric conversion layer interposed therebetween; Including, the second electrodes are electrically connected to one another among the plurality of pixels, the plurality of pixels are switched between a global shutter drive and a rolling shutter drive in which exposure and reading of the signal charges are performed row by row; the voltage supply circuit supplies a first voltage to the second electrode during an exposure period when the plurality of pixels perform the global shutter drive, and supplies a second voltage different from the first voltage to the second electrode during a non-exposure period; a potential difference between the first electrode and the second electrode when the second voltage is supplied to the second electrode is smaller than a potential difference between the first electrode and the second electrode when the first voltage is supplied to the second electrode; Imaging device.

2. The global shutter drive and the rolling shutter drive are switched depending on the subject. The imaging device according to claim 1 .

3. the voltage supply circuit supplies a third voltage to the second electrode during both an exposure period and a non-exposure period when the plurality of pixels perform the rolling shutter drive.

3. The imaging device according to claim 1.

4. The voltage value of the third voltage is equal to the voltage value of the first voltage. The imaging device according to claim 3 .

5. the plurality of pixels perform the global shutter drive in a first frame, and perform the rolling shutter drive in a second frame different from the first frame; The imaging device according to claim 1 .

6. a first mode in which the plurality of pixels perform the global shutter drive and a second mode in which the plurality of pixels perform the rolling shutter drive; The imaging device according to claim 1 .

7. A plurality of pixels arranged in a matrix; a voltage supply circuit; Equipped with Each of the plurality of pixels is a photoelectric conversion layer that converts light into signal charges; a first electrode for collecting the signal charges; a charge accumulation region connected to the first electrode and configured to accumulate the signal charges; a second electrode facing the first electrode with the photoelectric conversion layer interposed therebetween; Including, the second electrodes are electrically connected to one another among the plurality of pixels, the voltage supply circuit supplies a first voltage to the second electrode during an exposure period, and supplies a second voltage different from the first voltage to the second electrode during a non-exposure period; a potential difference between the first electrode and the second electrode when the second voltage is supplied to the second electrode is smaller than a potential difference between the first electrode and the second electrode when the first voltage is supplied to the second electrode; Imaging device.

8. The potential difference between the first electrode and the second electrode when the second voltage is supplied to the second electrode is a potential difference that prevents the signal charge already accumulated in the charge accumulation region from moving to the second electrode through the photoelectric conversion layer, and also prevents the signal charge generated in the photoelectric conversion layer from moving to the charge accumulation region. The imaging device according to claim 1 .

9. The first electrode is connected to the charge storage region without a switch element. The imaging device according to claim 1 .

Images