semiconductor switching devices

Abstract

To provide aspects of the disclosure that can be implemented in any environment, apparatus or method for cooling a heat-generating module regardless of a function performed by the heat-generating module.SOLUTION: A semiconductor device cell includes a drift region having a first conductivity type, a well region having a second conductivity type disposed adjacently to the drift region, the well region defining a set of well region segments. A source region having the first conductivity type is disposed adjacently to the well region and surrounded by the well region. A channel region has the second conductivity type and defines a set of channel region segments, a periphery of the channel region segment being surrounded by the well region. The well region, source region and channel region cooperatively define a first axial length extending across the surface.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Patent Application No. 17 / 692,489, filed March 11, 2022, the entire contents of which are incorporated herein by reference. [Background technology]

[0002]

[0002] Semiconductor devices, such as silicon carbide (SiC) power devices, are widely used in conventional electrical systems to switch or convert power consumed by loads. Many electronic systems utilize a variety of semiconductor devices and components, such as thyristors, diodes, and various types of transistors (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), and other suitable transistors). For example, MOSFETs can be fabricated as individual transistor packages for high-power applications or as chips with millions of transistors. Thousands of these transistor "cells" can be combined into a single device to handle relatively high currents and voltages.

[0003]

[0003] Many conventional MOSFETs use a vertical structure with source and drain terminals on both sides of the chip. The vertical orientation eliminates congestion at the gate and provides a larger channel width. Generally, when a semiconductor device is conducting current, the on-state resistance of the device represents its conduction losses, which affects the efficiency of the device and its cost. That is, a conventional semiconductor device cell contains many internal components that can create resistance to the current flowing through the device. [Brief explanation of the drawings]

[0004] [Figure 1]

[0004]

[0005] FIG. 1 is a schematic diagram of a typical planar MOSFET device. [Figure 2]

[0006] FIG. 1 is a schematic diagram showing the resistance of various regions of a typical MOSFET device. [Figure 3]

[0007] 3 is a chart illustrating the relative resistive contributions of regions of the MOSFET device structure of FIG. 2; [Figure 4]

[0008] FIG. 1 is a top view of the surface of a SiC layer containing a typical MOSFET device structure with a striped cell layout. [Figure 5]

[0009] FIG. 1 is a top view of the surface of a SiC layer containing a typical MOSFET device structure with a striped cell layout. [Figure 6]

[0010] FIG. 1 is a top view of the surface of a SiC layer containing a typical MOSFET device structure with a cellular layout. [Figure 7]

[0011] FIG. 1 is a top view of a system including an array of semiconductor device cells in accordance with various aspects described herein. [Figure 8]

[0012] FIG. 1 is a top view of a system including an alternative array of semiconductor device cells in accordance with various aspects described herein. [Figure 9]

[0013] FIG. 9 is a cross-sectional view of the semiconductor device cell of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0005]

[0014] Aspects of the present disclosure may be implemented in any environment, apparatus, or method for cooling a heat-generating module, regardless of the function performed by the heat-generating module.

[0006]

[0015] As used herein, the term "set" or a "set" of elements may refer to any number of elements, including only one. When introducing elements of various embodiments of the present disclosure, the articles "a," "an," and "the" are intended to mean that there are one or more elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements. Furthermore, it should be understood that references to "one aspect" or "an aspect" of the present disclosure are not intended to exclude the existence of additional aspects that also incorporate the identified features. It should be understood that the shapes, positions, and alignments of the presently disclosed features are illustrated and described as relatively idealized (e.g., square, rectangular, and hexagonal cells and shielding regions with perfectly straight and aligned features) for simplicity. However, as will be understood by those skilled in the art, process variations and technological limitations may result in cellular designs with non-ideal shapes, or irregular features may still be in accordance with the present disclosure. Thus, the term "substantially" as used herein to describe the shape, position, or alignment of a feature is meant to encompass ideal or target shapes, positions, and alignments, as well as imperfectly implemented shapes, positions, and alignments that result from variability in semiconductor manufacturing processes, as can be understood by those skilled in the art.

[0007]

[0016] Additionally, semiconductor device cells are described herein as being disposed or fabricated "at," "in," "on," or "along" the surface of a semiconductor layer, and are intended to include semiconductor device cells having portions disposed within the bulk of the semiconductor layer, portions disposed proximate to the surface of the semiconductor layer, portions disposed with the surface of the semiconductor layer, and / or portions disposed on or atop the surface of the semiconductor layer.

[0008]

[0017] Although terms such as "voltage," "current," and "power" may be used herein, it will be apparent to those skilled in the art that these terms may be interrelated when describing aspects of electrical circuits or circuit operation.

[0009]

[0018] All directional references (e.g., radial, axial, top, bottom, upward, downward, left, right, lateral, front, rear, top, bottom, up, down, vertical, horizontal, clockwise, counterclockwise) are used for identification purposes only to aid the reader's understanding of this disclosure and do not imply any limitation as to their particular location, orientation, or use. Connection references (e.g., attached, coupled, connected, and joined) should be interpreted broadly and may include intermediate members between a collection of elements and relative movement between the elements, unless otherwise specified. Thus, connection references do not necessarily imply that two elements are directly connected and in a fixed relationship to each other. In non-limiting examples, connections or disconnections can be selectively configured to provide, enable, disable, etc., electrical connections between respective elements. The example figures are for illustrative purposes only, and the dimensions, positions, order, and relative magnitudes reflected in the figures attached hereto may vary.

[0010]

[0019] As used herein, a controllable switching element, or "switch," is an electrical device that may be controllable to toggle between a first mode of operation in which the switch is in a very low resistance state, "on" state, or otherwise in a conducting mode and is intended to transmit current from the switch input to the switch output, and a second mode of operation in which the switch is in a very high resistance state, off state, or otherwise in a non-conducting mode and is intended to prevent current from being transmitted between the switch input and the switch output. In a non-limiting example, connections or disconnections, such as connections enabled or disabled by a controllable switching element, may be selectively configured to provide, enable, disable, etc., electrical connections between the respective elements.

[0011]

[0020] Furthermore, for ease of explanation and understanding, various aspects may be described below with reference to SiC MOSFET devices, but it should be understood that the present approach is applicable to other types of MOSFETs, such as, but not limited to, SiC DMOSFETs, UMOSFETs, and VMOSFETs. It is contemplated that various material systems (e.g., silicon (Si), germanium (Ge), aluminum nitride (AlN), gallium nitride (GaN), gallium arsenide (GaAs), diamond (C), or any other suitable wide bandgap semiconductor) may be used. It is further contemplated that other types of device structures utilizing n-channel or p-channel designs (e.g., UMOSFETs, VMOSFETs, insulated gate bipolar transistors (IGBTs), insulated base MOS controlled thyristors (IBMCTs), or any other suitable FET and / or MOS devices) may be used in various non-limiting aspects.

[0012]

[0021] One of the most common solid-state semiconductor switching devices used in modern power electronics is the MOSFET device. While an ideal switch conducts current with zero electrical resistance when in its low-resistance "on" or conducting state, MOSFETs always exhibit finite electrical resistance. Therefore, it is generally desirable to reduce the total resistance (e.g., on-state resistance) to the smallest possible value. It is also desirable to minimize the on-state resistance of a MOSFET without reducing the off-state resistance, the device's switching speed, or both.

[0013]

[0022] A conventional MOSFET typically consists of a periodic array of unit cells. Each unit cell can have its own electrical resistance, and the on-state electrical resistance of the MOSFET can be defined by the sum of the resistances of the individual cells in a parallel electrical circuit. Furthermore, the resistance of each unit cell can be defined by the set of resistances of the structural components of the cells coupled in series. Therefore, the on-state resistance of a particular MOSFET can be defined at least in part based on the relative geometric configuration of the various functional components within each cell.

[0014]

[0023] When a MOSFET is in an on or conducting state, electrons flow through each individual cell from a "source metal" on the top surface of the SiC semiconductor body, through various structures defined within the SiC semiconductor body, to a "drain metal" on the back surface of the body. Each respective MOSFET unit cell surface can include four mutually exclusive, non-overlapping regions, referred to herein as a source contact region, an n+ / p-well region, and a channel / accumulation region (CHAN) and a JFET region. The four regions can be electrically coupled in series and can occupy substantially the entire area of ​​the respective cell.

[0015]

[0024] The resistive contributions of the source contact and CHAN regions to the on-state electrical resistance of a MOSFET are inversely proportional to their respective areas. The resistive contribution of the n+ / p-well region to the on-state electrical resistance of a MOSFET is approximately directly proportional to its area. Because the resistive contribution of the CHAN region is relatively larger than that of the n+ / p-well or source contact regions, the on-state electrical resistance of a MOSFET can be reduced by maximizing the relative area of ​​the CHAN region in a unit cell to the n+ / p-well or source contact regions. Therefore, conventional techniques typically use MOSFET structures that maximize the relative proportion of the CHAN region area by arranging the cell geometry to minimize the relative proportion of the n+ / p-well region area, the source contact region area, or both, to the CHAN region.

[0016]

[0025] However, for SiC MOSFETs, current manufacturing techniques can limit such optimization. For example, conventional techniques have focused on reducing the on-state resistance of MOSFETs using periodic cells created by surrounding a minimum-sized source contact region with a minimum-sized n+ region for the CHAN region. However, the minimum dimensions of the source contact region that can be fabricated (using conventional manufacturing techniques) may be larger than the calculated or determined optimized area. Furthermore, the CHAN region must be separated from the source contact region by a minimum width of the n+ / p-well region to avoid fabrication-related device failures. However, notably, the geometry of the n+ / p-well region is relatively unconstrained by such manufacturing concerns.

[0017]

[0026] Thus, as described in more detail herein, in non-limiting embodiments, cells can be arranged to minimize the relative proportion of n+ / p-well region area while minimizing source contact region area and CHAN region area. In this manner, embodiments described herein can arrange a larger net relative proportion of CHAN region area relative to source contact region or size n+ region, or both, compared to the prior art, thereby achieving improved (i.e., lower) on-state resistance for each cell than conventional devices.

[0018]

[0027] For example, non-limiting embodiments can use cellular structures including arrays of cells spaced further apart than conventional devices. The resulting increased space or area between adjacent cells can include alternating bands or segments of n+ / p-well and CHAN regions. In this novel configuration, the relative proportion of CHAN region to n+ / p-well, or source contact region, or both, can be advantageously increased beyond levels achievable using conventional techniques that increase the relative proportion of CHAN area by minimizing n+ / p-well, or source contact region, or a combination thereof. As described in more detail herein, undesirable increases in on-state resistance resulting from increased area of ​​n+ / p-well regions (e.g., in alternating bands) can be countered or overcome within a given dimension range due to the reduction in on-state resistance achieved by the corresponding increased area of ​​CHAN regions, thereby resulting in a net reduction in the on-state resistance of each cell compared to conventional designs.

[0019]

[0028] 1 illustrates an active cell of a conventional planar n-channel field effect transistor, such as a DMOSFET, hereinafter MOSFET device 10. It should be understood that certain commonly understood design elements (e.g., top metallization, passivation, edge termination, etc.) may be omitted to more clearly illustrate and describe certain components of MOSFET device 10, as well as other devices described below.

[0020]

[0029] The conventional MOSFET device 10 shown in FIG. 1 includes a semiconductor layer 2 (e.g., an epitaxial SiC semiconductor layer) having a first surface 4 and a second surface 6. The semiconductor layer 2 includes a drift region 16 having a first conductivity type (e.g., an n-type drift region 16) and a well region 18 having a second conductivity type (e.g., a p-type well region 18) adjacent to the drift region 16 and disposed near the first surface 4. The semiconductor layer 2 also includes a source region 20 of the first conductivity type (e.g., an n-type source region 20) adjacent to the well region 18 and disposed near the first surface 4. A dielectric layer 24 (also referred to as a gate insulating layer or gate dielectric layer) is disposed on a portion of the first surface 4 of the semiconductor layer 2, and a gate electrode 26 is disposed on the dielectric layer 24. The second surface 6 of the semiconductor layer 2 is a substrate layer 14 (e.g., a SiC substrate layer), and a drain contact 12 is disposed at the bottom of the MOSFET device 10 along the substrate layer 14. The source contact 22 is disposed on top of the semiconductor layer 2 and partially covers the source region 20 and the well region 18 .

[0021]

[0030] During on-state operation, an appropriate gate voltage (e.g., the threshold voltage (V TH ) or greater) causes an inversion layer to form in channel region 28 and carrier accumulation to enhance the conduction path in junction field effect transistor (JFET) region 29, allowing current to flow from drain contact 12 (i.e., drain electrode) to source contact 22 (i.e., source electrode). It should be understood that in the MOSFET devices described herein, channel region 28 can be generally defined as the upper portion of well region 18 disposed beneath gate electrode 26 and dielectric layer 24.

[0022]

[0031] FIG. 2 is a schematic cross-sectional view of the conventional MOSFET device 10 of FIG. 1. The source contact 22 of the MOSFET device 10 shown in FIG. 2 generally provides an ohmic connection to the source electrode and is disposed on both a portion of the source region 20 and a portion of the well region 18. The source contact 22 is generally a metal interface including one or more metal layers located between these semiconductor portions of the MOSFET device 10 and a metal source electrode. For clarity, the portion of the source region 20 (e.g., the n+ source region 20) of the MOSFET device 10 that is disposed below the source contact 22 may be referred to herein more specifically as the source contact region 42 of the MOSFET device 10. Similarly, the portion of the well region 18 (e.g., the p-well region 18) of the MOSFET device 10, which may be p+ doped at a higher level than the remainder of the well region 18, may be referred to herein more specifically as the body region 44 (e.g., the p+ body region 44) of the MOSFET device 10. For clarity, a portion of the body region 44 that is disposed below the source contact 22 (e.g., covered by, directly electrically connected to the source contact 22) may be referred to herein more specifically as the body contact region 44 (e.g., p+ body contact region 44) of the MOSFET device 10. For consistency, a portion of the source contact 22 may be designated herein based on the portion of the semiconductor device that is disposed below the source contact 22. For example, a portion of the source contact 22 that is disposed above the body contact region 44 may be referred to herein as the body contact portion of the source contact 22. Similarly, a portion of the source contact 22 that is disposed above the source contact region 42 of the MOSFET device 10 may be referred to herein as the source contact portion of the source contact 22.

[0023]

[0032] As shown schematically in FIG. 2, various regions of MOSFET device 10 may each have an associated resistance, and a total resistance (e.g., on-state resistance, Rds(on)) of MOSFET device 10 may be expressed as the sum of these respective resistances. For example, as shown in FIG. 2, the on-state resistance Rds(on) of MOSFET device 10 may be approximated as the sum of: resistance Rs 30 (e.g., the resistance of source region 20 and source contact 22); resistance Rch 32 (e.g., the inversion channel resistance of channel region 28 shown in FIG. 2); resistance Racc 34 (e.g., the resistance of the accumulation layer between dielectric layer 24 and the portion of drift region 16 located between well regions 18); resistance RJFET 36 (e.g., the resistance of the undepleted neck region between well regions 18); resistance Rdrift 38 (e.g., the resistance around drift region 16); and resistance Rsub 40 (e.g., the resistance around substrate layer 14). It should be noted that the resistances shown in FIG. 2 are not exhaustive and other resistances may be present in the MOSFET device 10 (eg, drain contact resistance, diffusion resistance, etc.).

[0024]

[0033] 2 may dominate the conduction losses of the MOSFET device 10, and addressing these factors may have a significant impact on Rds(on). For example, in devices where the drift resistance 38, substrate resistance 40, and contact resistance are negligible, such as low voltage devices or devices suffering from low inversion layer mobility (e.g., SiC devices), the channel resistance (Rch 32) may account for a significant portion of the conduction losses of the device.

[0025]

[0034] By way of further example, in medium and high voltage devices, the JFET region resistance (RJFET 36) can account for a significant portion of the total conduction losses. In some cases, the MOSFET channel and JFET can comprise approximately 55% of the on-state resistance of a typical semiconductor device.

[0026]

[0035] Referring to FIG. 3, a chart illustrating an example of the relative resistance contributions of various regions of the MOSFET device structure of FIG. 2 is shown. The relative resistance of each region is shown as a function of the respective region distance (e.g., path length). It can be seen that the inversion channel resistance Rch 32 of the channel region 28 can contribute most significantly to the on-state resistance Rds(on) of the MOSFET device 10, while the resistance Rs 30 (e.g., the resistance of the source region 20 and the resistance of the source contact 22) and the resistance Rsub 40 of the substrate or back contact region (e.g., the resistance around the substrate layer 14) contribute least significantly to the on-state resistance Rds(on) of the MOSFET device 10.

[0027] FIG. 4 illustrates a top view of a conventional semiconductor layer 2 including a MOSFET device structure 41 having a conventional striped cell layout (i.e., a non-cellular layout). The striped layout illustrated in FIG. 4 includes a channel region 28, a source region 20, a source contact region 42, a body contact region 44, and a JFET region 29. It will be appreciated that the set of source contact regions 42 and the set of body contact regions 44 may be formed as continuous stripes along the surface of the semiconductor for the striped layout illustrated in FIG. 4. Dimensionally, the conventional MOSFET device structure 41 may be described as having a particular channel length (Lch) 43, a distance from the channel region 28 to the ohmic region (Lch-to-ohm) 45, a width of the ohmic region (Wohm 47), and a width of the JFET region (WJFET) 49. Although the conventional striped cell layout shown in FIG. 4 provides good reliability (e.g., long-term and high-temperature performance), the relatively high channel resistance (Rch) 32 and JFET resistance (RJFET) 36 of the MOSFET device structure 41 result in a relatively high Rds(on), degrading the electrical performance of the device.

[0028] 5, which is a top or plan view of a striped ladder device layout 50 with segmented source / body contacts (i.e., a non-cellular layout). The illustrated striped ladder device layout 50 includes a channel region 28, a source region 20, a set of segmented source / body contacts 46 (including a body contact region 44 and a source contact region 42), and a JFET region 29. FIG. 5 further illustrates dimensions of the stripe ladder device layout 50, including the channel length (Lch) 43, the channel-to-ohmic region distance (Lch-to-ohm) 45, the width of the ohmic region (Wohm) 47, the width of the JFET region (WJFET) 49, the length of the source contact region segment (Ln) 51, the length of the body contact region segment (Lp) 52, a subset of the device area (Acell 53 represented by dashed rectangle 53), the JFET area within Acell 53 (ANET 54 represented by shaded area 54), and the width of the channel (Wch) 55 within Acell 54.

[0029] For further comparison, another example of a conventional device layout is shown in FIG. 6, which is a top or plan view of a square cellular device layout 60 that does not include segmented source / body contacts. The square cellular device layout 60 includes a channel region 28, a source region 20, a body contact region 44, a source contact 22, and a JFET region 29. FIG. 6 further shows dimensions of the square cellular device layout 60 for the cells of the illustrated square cellular device layout 60, including the channel length (Lch 62), the channel-to-ohmic region distance (Lch-to-ohm) 63, the ohmic region width (Wohm) 64, the JFET region width (WJFET) 65, the body contact region width (Wp) 67, the device cell area (Acell), represented by the dashed rectangle 68, and the JFET area per cell (AJFET), represented by the shaded area 69.

[0030] While the device layout shown in FIG. 6 may enable lower Rds(on) compared to a striped cell layout, as shown in FIG. 3, it is recognized that such a design may have a substantially higher electric field in the portion of the JFET region 29 between the corners of the well regions 18 of adjacent device cells under blocking conditions. For SiC MOS devices, the electric field in the dielectric layer 24 (e.g., SiO2) disposed above the JFET region 29 (shown in FIGS. 1 and 2) may be about 10 times higher compared to the electric field in a Si device when the device cell is operated under reverse bias. While SiC is generally robust to higher electric fields, the dielectric layer 24 may experience breakdown during long-term operation, resulting in reliability issues for the SiC device cell.

[0031] With the foregoing in mind, the present embodiments are directed to semiconductor device designs and layouts that enable improved semiconductor device performance. In particular, aspects described herein can advantageously reduce the resistance of MOSFET device components to reduce or minimize the device's on-state conduction losses (e.g., minimize Rds(on)). For example, non-limiting aspects can include cellular device designs and layouts that provide increased channel widths or increased channel densities over conventional designs to reduce channel resistance (Rch 32) and thereby reduce on-state conduction losses. It should be understood that the term "channel density," as used herein, can refer to the ratio of the channel perimeter of a particular device cell to the total area of ​​the device cell. Thus, in the aspects described and illustrated herein, channel density may be equal to the total channel perimeter of one device cell divided by the area of ​​the device cell. As described in more detail below, non-limiting aspects described herein enable a reduction in device pitch, thus increasing the channel perimeter per unit area or increasing the density of channel regions 28 in MOSFET devices.

[0032]

[0036] FIG. 7 shows a top or plan view illustrating a system 70 (e.g., a cellular semiconductor device such as a MOSFET) including an array of semiconductor device cells 72, according to a non-limiting embodiment. As described in more detail herein, the semiconductor device cells 72 can be configured to facilitate a reduction in the on-state resistance Rds(on) of the MOSFET device 10. Each semiconductor device cell 72 can be disposed on a first surface 4 of a semiconductor layer 2 (e.g., a silicon carbide (SiC) semiconductor layer). The semiconductor device cells 72 can define a vertical pitch or first axial length D1 extending across the extent of the first surface 4 of the semiconductor device cells 72, e.g., along the x-axis. The semiconductor device cells 72 can also define a horizontal pitch or second axial length D2 extending across the extent of the first surface 4 of the semiconductor device cells 72 orthogonal to the first axial length D1, e.g., along the y-axis. It will be appreciated that the area of ​​the semiconductor device cells 72 can be determined based on the product of the first axial length D1 and the second axial length D2.

[0033]

[0037] In a non-limiting embodiment, the body contact region 44 of the semiconductor device cell 72 may be surrounded by a source region 20 of a first conductivity type (e.g., n-type or p-type). The source region 20 may be surrounded by a well region 18 of a second conductivity type. It should be understood that a portion of the source region 20 disposed below the source contact 22 functions as part of the source contact region 42 of the semiconductor device cell 72. The semiconductor device cell 72 may include a drift region 16 having the first conductivity type.

[0034]

[0038] A well region 18 having a second conductivity type (e.g., p-type or n-type) can be disposed adjacent to the drift region 16. In certain embodiments, the well region 18 can include a set of elongated well region segments 17 spaced apart from one another. Each well region segment 17 can define a respective well region segment longitudinal axis 17a. For example, as shown, in some embodiments, each well region segment longitudinal axis 17a can extend across the first surface 4, e.g., along the x-axis. In non-limiting embodiments, the two or more well region segment longitudinal axes 17a can be substantially parallel to one another. In non-limiting embodiments, the longitudinal axes 17a of the well region segments can be substantially parallel to the first axial length D1. A source region 20 can be disposed directly adjacent to and surrounded by the well region 18.

[0035]

[0039] A channel region 28 having the second conductivity type can be disposed proximate the first surface 4. The channel region 28 can include a set of elongated channel region segments 28a spaced apart from one another. In non-limiting embodiments, the channel region segments 28a can define the periphery of the channel region 28. Each channel region segment 28a can define a respective channel region segment longitudinal axis 31. As shown, in some embodiments, each channel region segment longitudinal axis 31 can extend across the first surface 4, e.g., along the x-axis. In this sense, each channel region segment longitudinal axis 31 can be parallel to the first axial length D1. In non-limiting embodiments, the longitudinal axes 31 of two or more channel region segments can be substantially parallel to one another. Furthermore, in some embodiments, the two or more channel region segment longitudinal axes 31 can be substantially parallel to two or more well region segment longitudinal axes 17a. In a non-limiting embodiment, a pair of immediately adjacent channel region segments 28a can be spaced apart from one another along their respective longitudinal axes 31 to define a gap 33 therebetween. Each gap 33 can define a respective third axial length D3 that is orthogonal to the respective channel region segment longitudinal axis 31. In one embodiment, the third axial length D3 can be substantially orthogonal to the first axial length D1. In a non-limiting embodiment, each well region segment 17 can be disposed within the gap 33, and the longitudinal axis 17a of each well region segment can be parallel to the longitudinal axis 31 of the respective channel region segment.

[0036]

[0040] Furthermore, the channel region segments 28 a can be at least partially surrounded by the well regions 18. For example, in a non-limiting embodiment, the periphery of the channel region segments 28 a can be cooperatively surrounded by the respective well region segments 17 and drift region 16. As shown in FIG. 7 , the periphery of a set of channel region segments 28 a, a set of well region segments 17, and a portion of the field effect transistor (JFET) region 29 can be arranged to define a series of alternating, substantially parallel, elongated bands or stripes. Thus, a non-limiting embodiment can increase the density of conducting channel regions 28 per unit cell area over the prior art.

[0037]

[0041] In a non-limiting embodiment, a body contact region 44 having the second conductivity type can be disposed on a portion of well region 18. In a non-limiting embodiment, body contact region 44 can be disposed substantially in the center of the plane of source region 20 defined by first surface 4.

[0038]

[0042] In a non-limiting embodiment, the well region 18, the source region 20, and the channel region 28 can cooperatively or cumulatively define a first axial length D1 or pitch extending across the first surface 4 of the semiconductor device cell 72. In a non-limiting embodiment, the first axial length D1 can be substantially parallel to the channel region segment longitudinal axis 31 or the well region segment longitudinal axis 17a, or both. In an embodiment, the first axial length D1 can span substantially the entire length of the first surface 4 of the semiconductor device cell 72. In a non-limiting embodiment, each well region segment 17 can define a respective third axial length D3 or pitch extending across the surface 4, e.g., along the y-axis. In a non-limiting embodiment, the third axial length D3 can be disposed orthogonal to the first axial length D1.

[0039]

[0043] In non-limiting embodiments, the first axial length D1 can be within a range of 6 micrometers and 18 micrometers. In some non-limiting embodiments, the third axial length D3 can be within a range of 0.3 micrometers to 1.6 micrometers. In still other non-limiting embodiments, the relative dimensions of the first and third axial lengths D1, D3, and the third axial length D3 can be within a range of 5% to 20% of the first axial length D1. Other embodiments are not so limited, and the dimensions of the first axial length D1, or the third axial length D3, or both, can be varied as desired for various applications without departing from the scope of the present disclosure.

[0040]

[0044] Regardless of the dimensions of the first and third axial lengths D1, D3, or their relative dimensions to one another, or both, the particular dimensions of the first and third axial lengths D1, D3 are positioned or defined for the specific purpose of reducing the resistive contribution of the channel region 28 (i.e., the relatively high resistive contribution of the inversion channel resistance), even at the expense of a relatively small resulting increase in the resistive contribution of the well region 18.

[0041]

[0045] Figure 8 shows a top or plan view illustrating an array of systems 80 including semiconductor device cells 72 according to another non-limiting embodiment. The non-limiting embodiment of Figure 8 is similar to the embodiment shown in Figure 7, with one difference being that the semiconductor device cells 72 are arranged in a cellular layout. Reference is also made to Figure 9, which shows a cross-sectional view of the semiconductor device cell 72 of Figure 8 taken along line IX-IX.

[0042]

[0046] 8 and 9, the semiconductor device cells 72 are configured to facilitate a reduced on-state resistance Rds(on) of the system 80. Each semiconductor device cell 72 is disposed on a first surface 4 of a semiconductor layer 2 (e.g., a SiC semiconductor layer 2). The semiconductor device cells 72 may define a vertical pitch or first axial length D1 extending across the extent of the first surface 4 of the semiconductor device cell 72, for example, along the x-axis.

[0043]

[0047] A dielectric layer 24 (e.g., a gate insulating layer) is disposed on a portion of the first surface 4 of the semiconductor layer 2, and a gate electrode 26 is disposed on the dielectric layer 24. The body contact region 44 of the semiconductor device cell 72 is surrounded by a source region 20 of a first conductivity type (e.g., n-type or p-type). The source region 20 of the first conductivity type may be surrounded by a well region 18 of a second conductivity type. A portion of the source region 20 disposed below the source contact 22 functions as a part of the source contact region 42 of the semiconductor device cell 72. The semiconductor device cell 72 may include a drift region 16 having the first conductivity type.

[0044]

[0048] A well region 18 having a second conductivity can be disposed adjacent to the drift region 16. In one embodiment, the well region 18 can include a set of elongated well region segments 17 spaced apart from one another and defining respective well region segment longitudinal axes 17a. In a non-limiting embodiment, the longitudinal axes 17a of the well region segments can be substantially parallel to one another. In a non-limiting embodiment, the longitudinal axes 17a of the well region segments can be substantially parallel to the first axial length D1. The source region 20 is disposed directly adjacent to and surrounded by the well region 18.

[0045]

[0049] A channel region 28 having the second conductivity type can be disposed proximate the first surface 4. The channel region 28 includes a set of elongated channel region segments 28a spaced apart from one another and defining a longitudinal axis 31 of each channel region segment. In a non-limiting embodiment, the longitudinal axes 31 of each channel region segment can be substantially parallel to one another. In some embodiments, each channel region segment longitudinal axis 31 can extend across the first surface 4, e.g., along the x-axis. In this sense, each channel region segment longitudinal axis 31 can be parallel to the first axial length D1. Furthermore, in some embodiments, each channel region segment longitudinal axis 31 can be substantially parallel to the well region segment longitudinal axis 17a.

[0046]

[0050] In a non-limiting embodiment, one or more respective channel region segments 28a can be spaced apart from another immediately adjacent channel region segment 28a to define a gap 33 therebetween. Each gap 33 can define a respective third axial length D3 perpendicular to the respective channel region segment longitudinal axis 31. In certain embodiments, the third axial length D3 can be substantially perpendicular to the first axial length D1. In a non-limiting embodiment, each well region segment 17 can be disposed within the gap 33 such that the respective well region segment longitudinal axis 17a can be parallel to the respective channel region segment longitudinal axis 31. The periphery of the channel region segment 28a can be at least partially surrounded by the well region 18. For example, in a non-limiting embodiment, the channel region segment 28a can be cooperatively surrounded by the respective well region segment 17 and the drift region 16. 8, the set of channel region segments 28a, the set of well region segments 17, and a portion of the drift region 16 can be arranged to define a series of alternating substantially parallel bands or stripes. In this sense, as shown in FIG. 8, a semiconductor device cell 72 can be described as having well region segments 17 disposed on either side of a channel region segment 28a. Thus, non-limiting embodiments can minimize cell size and increase the density of conducting channel regions 28 per unit cell.

[0047]

[0051] In some non-limiting embodiments, a body contact region 44 having the second conductivity type can be disposed on a portion of well region 18. Body contact region 44 can be disposed substantially in the center of the plane of source region 20 defined by first surface 4.

[0048]

[0052] In a non-limiting embodiment, the well region 18, the source region 20, and the channel region 28 can cooperatively or cumulatively define a first axial length D1 or pitch extending across the first surface 4 of the semiconductor device cell 72. In a non-limiting embodiment, the first axial length D1 can be substantially parallel to the channel region segment longitudinal axis 31 or the well region segment longitudinal axis 17a, or both. In an embodiment, the first axial length D1 can span substantially the entire length of the first surface 4 of the semiconductor device cell 72. In a non-limiting embodiment, each well region segment 17 can define a respective third axial length D3 or pitch extending across the surface 4, e.g., along the y-axis. In a non-limiting embodiment, the third axial length D3 can be disposed orthogonal to the first axial length D1.

[0049]

[0053] In non-limiting embodiments, the first axial length D1 can be within a range of 6 micrometers and 18 micrometers. In some non-limiting embodiments, the third axial length D3 can be within a range of 0.3 micrometers to 1.6 micrometers. In still other non-limiting embodiments, the relative dimensions of the first and third axial lengths D1, D3, and the third axial length D3 can be within a range of 5% to 20% of the first axial length D1. Other embodiments are not so limited, and the dimensions of the first axial length D1, or the third axial length D3, or both, can be varied as desired for various applications without departing from the scope of the present disclosure.

[0050]

[0054] Regardless of the dimensions of the first and third axial lengths D1, D3, or their relative dimensions to one another, or both, the particular dimensions of the first and third axial lengths D1, D3 are positioned or defined for the specific purpose of reducing the resistive contribution of the channel region 28 (i.e., the relatively high resistive contribution of the inversion channel resistance), even at the expense of a relatively small resulting increase in the resistive contribution of the well region 18. Furthermore, the illustrated semiconductor device cell 72 can be described as having a portion of the well region 18 disposed on either side of the channel region segment 28a. Thus, non-limiting embodiments can minimize cell size and increase the density of conducting channel regions 28 per unit cell.

[0051]

[0055] Thus, the presently disclosed semiconductor device cell 72 minimizes cell size and increases the density of conductive regions (e.g., channels) per unit cell. In particular, embodiments of the present invention provide increased channel width and / or increased channel density to reduce channel resistance, thereby reducing conduction losses in the device (e.g., minimizing Rds(on)).

[0052]

[0056] To the extent not already described, different features and structures of various embodiments can be used in combination with each other as desired. The inability to illustrate a feature in all embodiments is not intended to imply that it is impossible, but is done for the sake of brevity of description. Thus, various features of different embodiments can be mixed and matched as desired to form new embodiments, regardless of whether the new embodiments are explicitly described. Any combination or variation of the features described herein is covered by this disclosure.

[0053]

[0057] This written description uses examples to disclose aspects of the disclosure, including the best mode, and also enables any person skilled in the art to practice aspects of the disclosure, including making and using any device or system, and practicing any incorporated methods. The patentable scope of the disclosure is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have elements that do not differ from the literal language of the claims, or if they contain equivalent elements that do not differ in material way from the literal language of the claims.

[0054]

[0058] The features disclosed in the foregoing description, the following claims and / or the accompanying drawings may, both separately and in any combination thereof, be material for realizing embodiments in diverse forms thereof.

[0055]

[0059] Various features, aspects, and advantages of the present disclosure may be embodied in any variation of the aspects of the present disclosure, including, but not limited to, the following technical solutions defined in the enumerated aspects.

[0056]

[0060] 1. A semiconductor device cell (72) comprising:

[0061] a semiconductor layer (2) including a drift region (16) of a first conductivity type; a well region (18) of a second conductivity type disposed adjacent to a surface (4) of the semiconductor layer (2), the well region (18) defining a set of well region segments (17); a source region (20) of the first conductivity type disposed adjacent to the well region (18), the source region (20) being surrounded by the well region (18); and a source region of the second conductivity type disposed adjacent to the well region (18), the source region (20) being surrounded by the well region (18). a channel region (28) proximate the surface (4) of the body layer (2), the channel region (28) defining a set of channel region segments (28a), the set of channel region segments (28a) being surrounded by the well region (18); and the well region (18), source region (20), and channel region (28) cooperatively defining a first axial length (D1) extending across the surface (4).

[0057]

[0062] 2. The semiconductor device cell (72) of any preceding paragraph, further comprising a JFET region, a portion of said JFET region being surrounded by said channel region.

[0058]

[0063] 3. A semiconductor device cell (72) according to any preceding paragraph, wherein pairs of immediately adjacent channel region segments (28a) are spaced apart from one another to define gaps (33) therebetween, said gaps (33) defining respective third axial lengths (D3) orthogonal to said first axial length (D1), and wherein each well region segment (17) is disposed within said gaps (33).

[0059]

[0064] 4. The semiconductor device cell (72) of any preceding paragraph, wherein the first axial length (D1) is in the range of 6 micrometers to 18 micrometers.

[0060]

[0065] 5. The semiconductor device cell (72) of any preceding paragraph, wherein the third axial length (D3) is in the range of 0.3 micrometers to 1.6 micrometers.

[0061]

[0066] 6. A semiconductor device cell (72) according to any preceding paragraph, wherein the third axial length (D3) is within a range of 8% to 15% of the first axial length (D1).

[0062]

[0067] 7. A semiconductor device cell (72) according to any preceding paragraph, wherein each respective channel region segment (28a) defines a respective first longitudinal axis (31) and each well region segment (17) defines a respective second longitudinal axis (17a), said first and second longitudinal axes (31), (17a) being parallel to one another.

[0063]

[0068] 8. The semiconductor device cell (72) of any preceding paragraph, further comprising a body contact region (44) having a second conductivity type disposed over a portion of the well region (18), the body contact region (44) being disposed substantially in the center of a plane of the source region (20) defined by the surface (4).

[0064]

[0069] 9. A semiconductor device cell (72) according to any preceding paragraph, wherein the set of channel region segments (28a), the set of well region segments (17), and a portion of the drift region (16) are arranged to define a series of alternating substantially parallel bands.

[0065]

[0070] 10. The semiconductor device cell (72) of any preceding paragraph, wherein the semiconductor device cell (72) is a MOSFET (70).

[0066]

[0071] 11. A system (70), (80) comprising: a set of semiconductor device cells (72) disposed on a surface (4) of a silicon carbide (SiC) semiconductor layer (2);

[0072] Each of the set of semiconductor device cells (72) comprises: a semiconductor layer (2) including a drift region (16) having a first conductivity type;

[0073] a well region (18) of a second conductivity type disposed proximate to a surface (4) of the semiconductor layer (2), the well region defining a set of well region segments (17); a source region (20) of the first conductivity type disposed adjacent to the well region (18), the source region (20) being surrounded by the well region (18) at its periphery; and a channel region (28) of the second conductivity type disposed proximate to the surface (4), the channel region (28) defining a set of channel region segments (28a), the set of channel region segments (28a) being surrounded by the well region (18); wherein the well region (18), source region (20), and channel region (28) cooperate to define a first axial length extending across the surface (4).

[0067]

[0074] 12. The system (70), (80) of any preceding paragraph, further comprising a JFET region, a portion of said JFET region being surrounded by said channel region.

[0068]

[0075] 13. The system (70), (80) of any preceding paragraph, wherein each respective channel region segment (28a) is spaced apart from another immediately adjacent channel region segment (28a) to define a gap (33) therebetween, said gaps (33) defining a respective third axial length (D3) orthogonal to said first axial length (D1), and each well region segment (16) is disposed within said gap (33).

[0069]

[0076] 14. The system (70), (80) of any preceding paragraph, wherein the first axial length (D1) is in the range of 6 micrometers to 18 micrometers.

[0070]

[0077] 15. The system (70), (80) of any preceding paragraph, wherein the third axial length (D3) is in the range of 0.3 micrometers to 1.6 micrometers.

[0071]

[0078] 16. The system (70), (80) of any preceding paragraph, wherein the third axial length (D3) is within the range of 5% to 20% of the first axial length (D1).

[0072]

[0079] 17. A system (70), (80) according to any preceding paragraph, wherein each respective channel region segment (28a) defines a respective first longitudinal axis (31), and each well region segment (17) defines a respective second longitudinal axis (17a), said first and second longitudinal axes (31), (17a) being parallel to one another.

[0073]

[0080] 18. The system (70), (80) of any preceding paragraph, further comprising a body contact region (44) having a second conductivity type disposed over a portion of the well region (18), the body contact region (44) being disposed substantially in the center of a plane of the source region (20) defined by the surface (4).

[0074]

[0081] 19. The system (70), (80) of any preceding paragraph, wherein the set of channel region segments (28a), the set of well region segments (17), and a portion of the drift region (16) are arranged to define a series of alternating substantially parallel bands.

[0075]

[0082] 20. The system (70), (80) of any preceding paragraph, wherein the set of semiconductor device cells (72) defines a MOSFET.

[0076]

[0083] Further aspects of the invention are provided by the subject matter of the following clauses.

[0077]

[0084] 1. A semiconductor device cell comprising: a semiconductor layer including a drift region having a first conductivity type; a well region having a second conductivity type disposed proximate a surface of the semiconductor layer, the well region defining a set of well region segments; a source region having the first conductivity type disposed adjacent to the well region, the source region being periphery-surrounded by the well region; and a channel region having the second conductivity type proximate the surface of the semiconductor layer, the channel region defining a set of channel region segments, the set of channel region segments being periphery-surrounded by the well region; wherein the well region, source region, and channel region cooperate to define a first axial length extending across the surface.

[0078]

[0085] 2. The semiconductor device cell of any preceding paragraph, further comprising a JFET region, a portion of said JFET region being surrounded by said channel region.

[0079]

[0086] 3. The semiconductor device cell of any preceding paragraph, wherein pairs of immediately adjacent channel region segments are spaced apart from one another to define gaps therebetween, said gaps defining respective third axial lengths orthogonal to said first axial length, and wherein each well region segment is disposed within said gaps.

[0080]

[0087] 4. The semiconductor device cell of any preceding paragraph, wherein the first axial length is in the range of 6 micrometers to 18 micrometers.

[0081]

[0088] 5. The semiconductor device cell of any preceding paragraph, wherein the third axial length is in the range of 0.3 micrometers to 1.6 micrometers.

[0082]

[0089] 6. The semiconductor device cell according to any preceding paragraph, wherein the third axial length is within a range of 8% to 15% of the first axial length.

[0083]

[0090] 7. The semiconductor device cell of any preceding paragraph, wherein each respective channel region segment defines a respective first longitudinal axis and each well region segment defines a respective second longitudinal axis, said first and second longitudinal axes being parallel to one another.

[0084]

[0091] 8. A semiconductor device cell according to any preceding paragraph, further comprising a body contact region having a second conductivity type disposed over a portion of the well region, the body contact region being disposed substantially in the center of a plane of the source region defined by the surface.

[0085]

[0092] 9. The semiconductor device cell of any preceding paragraph, wherein the set of channel region segments, the set of well region segments, and a portion of the drift region are arranged to define a series of alternating substantially parallel bands.

[0086]

[0093] 10. The semiconductor device cell of any preceding paragraph, wherein the semiconductor device cell is a MOSFET.

[0087]

[0094] 11. A system comprising: a set of semiconductor device cells disposed on a surface of a silicon carbide (SiC) semiconductor layer; each of the set of semiconductor device cells comprising: a semiconductor layer including a drift region having a first conductivity type; a well region having a second conductivity type disposed proximate to the surface of the semiconductor layer, the well region defining a set of well region segments; a source region having the first conductivity type disposed adjacent to the well region, the source region being peripheried by the well region; and a channel region having the second conductivity type proximate to the surface, the channel region defining a set of channel region segments, the set of channel region segments being peripheried by the well region; wherein the well region, source region, and channel region cooperate to define a first axial length extending across the surface.

[0088]

[0095] 12. The system of any preceding paragraph, further comprising a JFET region, a portion of said JFET region being surrounded by said channel region.

[0089]

[0096] 13. The system of any preceding paragraph, wherein each respective channel region segment is spaced from another immediately adjacent channel region segment to define a gap therebetween, said gaps defining a respective third axial length orthogonal to said first axial length, and wherein each well region segment is disposed within said gap.

[0090]

[0097] 14. The system of any preceding paragraph, wherein the first axial length is in the range of 6 micrometers to 18 micrometers.

[0091]

[0098] 15. The system of any preceding paragraph, wherein the third axial length is in the range of 0.3 micrometers to 1.6 micrometers.

[0092]

[0099] 16. The system of any preceding paragraph, wherein the third axial length is within the range of 5% to 20% of the first axial length.

[0093]

[0100] 17. The system of any preceding paragraph, wherein each respective channel region segment defines a respective first longitudinal axis and each well region segment defines a respective second longitudinal axis, said first and second longitudinal axes being parallel to one another.

[0094]

[0101] 18. The system of any preceding paragraph, further comprising a body contact region having a second conductivity type disposed over a portion of the well region, the body contact region being disposed substantially in the center of a plane of the source region defined by the surface.

[0095]

[0102] 19. The system of any preceding paragraph, wherein the set of channel region segments, the set of well region segments, and a portion of the drift region are arranged to define a series of alternating substantially parallel bands.

[0096]

[0103] 20. The system of any preceding paragraph, wherein the set of semiconductor device cells defines a MOSFET.

Claims

1. 1. A semiconductor device cell comprising: a semiconductor layer including a drift region having a first conductivity type; a well region having a second conductivity type disposed proximate a surface of the semiconductor layer, the well region defining a set of well region segments; a source region having the first conductivity type disposed adjacent to the well region, the source region being surrounded by the well region; a channel region having the second conductivity type proximate the surface of the semiconductor layer, the channel region defining a set of channel region segments, the set of channel region segments being surrounded by the well region; Equipped with the well region, the source region, and the channel region cooperate to define a first axial length extending across the surface; the pair of immediately adjacent channel region segments are spaced apart from one another to define a gap therebetween; Each well region segment is disposed within the gap; A semiconductor device cell, wherein a portion of the channel region extends the entire length of the periphery of the cell parallel to the first axial length.

2. The semiconductor device cell of claim 1 , further comprising a JFET region, a portion of said JFET region being surrounded by said channel region.

3. The semiconductor device cell of claim 1 , wherein the gaps define respective third axial lengths orthogonal to the first axial lengths.

4. The semiconductor device cell of claim 3 , wherein the first axial length is in the range of 6 micrometers to 18 micrometers.

5. The semiconductor device cell of claim 4 , wherein the third axial length is in the range of 0.3 micrometers to 1.6 micrometers.

6. The semiconductor device cell of claim 4 , wherein the third axial length is within a range of 8% to 15% of the first axial length.

7. 4. The semiconductor device cell of claim 3, wherein each respective channel region segment defines a respective first longitudinal axis and each well region segment defines a respective second longitudinal axis, said first and second longitudinal axes being parallel to one another.

8. 2. The semiconductor device cell of claim 1, further comprising a body contact region having a second conductivity type disposed over a portion of the well region, the body contact region being disposed substantially at a center of a plane of the source region defined by the surface.

9. The semiconductor device cell of claim 3 , wherein the set of channel region segments, the set of well region segments, and a portion of the drift region are arranged to define a series of alternating substantially parallel bands.

10. The semiconductor device cell of claim 1 , wherein the semiconductor device cell is a MOSFET.

11. 1. A system comprising: a set of semiconductor device cells disposed on a surface of a silicon carbide (SiC) semiconductor layer; The set of semiconductor device cells each include: a semiconductor layer including a drift region having a first conductivity type; a well region having a second conductivity type disposed proximate a surface of the semiconductor layer, the well region defining a set of well region segments; a source region having the first conductivity type disposed adjacent to the well region, the source region being surrounded by the well region; a channel region having the second conductivity type proximate the surface of the semiconductor layer, the channel region defining a set of channel region segments, the set of channel region segments being surrounded by the well region; Equipped with the well region, the source region, and the channel region cooperate to define a first axial length extending across the surface; each respective channel region segment is spaced from another immediately adjacent channel region segment to define a gap therebetween; Each well region segment is disposed within the gap; A system wherein a portion of the channel region extends the entire length of the periphery of the cell parallel to the first axial length.

12. The system of claim 11 , further comprising a JFET region, a portion of the JFET region being surrounded by the channel region.

13. The system of claim 11 , wherein the gaps define respective third axial lengths orthogonal to the first axial length.

14. The system of claim 11 , wherein the first axial length is in a range of 6 micrometers to 18 micrometers.

15. The system of claim 13 , wherein the third axial length is in the range of 0.3 micrometers to 1.6 micrometers.

16. The system of claim 13, wherein the third axial length is within a range of 5% to 20% of the first axial length.

17. 14. The system of claim 13, wherein each respective channel region segment defines a respective first longitudinal axis and each well region segment defines a respective second longitudinal axis, the first and second longitudinal axes being parallel to one another.

18. 12. The system of claim 11, further comprising a body contact region having the second conductivity type disposed over a portion of the well region, the body contact region disposed substantially in a center of a plane of the source region defined by the surface.

19. 14. The system of claim 13, wherein the set of channel region segments, the set of well region segments, and a portion of the drift region are arranged to define a series of alternating substantially parallel bands.

20. The system of claim 11 , wherein the set of semiconductor device cells defines a MOSFET.

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