Semiconductor device and manufacturing method thereof

Abstract

The semiconductor device (100) includes a semiconductor laminate structure (110) containing a two-dimensional electron gas, a p-type first semiconductor layer (120) provided on the semiconductor laminate structure (110), and a drain electrode (160) in contact with the first semiconductor layer (120). The first semiconductor layer (120) includes a thick film portion (122) and a thin film portion (124) that is thinner than the thick film portion (122). The semiconductor laminate structure (110) has a recess (112) in a first region (101) adjacent to the thin film portion (124) in a plan view, and the drain electrode (160) is in contact with a side surface (112b) of the recess (112) and a side surface (124b) of the thin film portion (124).

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Patent Document 1 discloses a high electron mobility transistor (HEMT) that includes a two-dimensional electron gas (2DEG) as a channel. In the HEMT disclosed in Patent Document 1, a p-type semiconductor layer is provided directly under the gate electrode to achieve normally-off operation. In addition, to mitigate current collapse, a p-type semiconductor layer that is thinner than the p-type semiconductor layer directly under the gate electrode is provided in contact with the drain electrode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-53585 Summary of the Invention [Problem to be solved by the invention]

[0004] However, the conventional HEMT has a problem in that it is difficult to achieve both normally-off operation and suppression of current collapse.

[0005] The p-type semiconductor layer in contact with the drain electrode, like the p-type semiconductor layer directly under the gate electrode, depletes the region where 2DEG occurs. Therefore, if the thickness of the p-type semiconductor layer in contact with the drain electrode becomes too thick, it becomes difficult to perform on-state operation. In other words, this can hinder the normally-off operation of the HEMT. On the other hand, if the thickness of the p-type semiconductor layer in contact with the drain electrode becomes too thin, the number of holes in the p-type semiconductor layer decreases, making it impossible to sufficiently suppress current collapse.

[0006] Therefore, the present disclosure provides a semiconductor device that can achieve both normally-off operation and suppression of current collapse, and a method for manufacturing the same. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment of the present disclosure comprises a semiconductor laminate structure containing a two-dimensional electron gas, a p-type first semiconductor layer provided on the semiconductor laminate structure, and a drain electrode in contact with the first semiconductor layer, wherein the first semiconductor layer includes a thick film portion and a thin film portion that is thinner than the thick film portion, and the semiconductor laminate structure has a recess in a region adjacent to the thin film portion in a planar view, and the drain electrode contacts a side surface of the recess and a side surface of the thin film portion.

[0008] A method for manufacturing a semiconductor device according to one embodiment of the present disclosure includes the steps of: forming a semiconductor laminate structure containing a two-dimensional electron gas; forming a p-type first semiconductor layer on the semiconductor laminate structure, the p-type first semiconductor layer having a thick film portion and a thin film portion thinner than the thick film portion; forming a recess in a first region of the semiconductor laminate structure adjacent to the thin film portion in a planar view; and forming a drain electrode in contact with a side surface of the recess and a side surface of the thin film portion of the first semiconductor layer. [Effects of the Invention]

[0009] According to the present disclosure, it is possible to achieve both normally-off operation and suppression of current collapse. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is an enlarged cross-sectional view showing the vicinity of the drain electrode of the semiconductor device according to the first embodiment. [Figure 3A] FIG. 3A is a cross-sectional view illustrating one step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3B] FIG. 3B is a cross-sectional view illustrating one step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3C] FIG. 3C is a cross-sectional view illustrating one step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3D] FIG. 3D is a cross-sectional view illustrating one step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3E] FIG. 3E is a cross-sectional view illustrating one step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3F] FIG. 3F is a cross-sectional view illustrating one step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3G] FIG. 3G is a cross-sectional view illustrating one step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3H] FIG. 3H is a cross-sectional view illustrating one step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3I] FIG. 3I is a cross-sectional view illustrating one step of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view of a semiconductor device according to a first modification of the first embodiment. [Figure 5] FIG. 5 is a cross-sectional view of a semiconductor device according to a second modification of the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view of a semiconductor device according to the second embodiment. [Figure 7] FIG. 7 is an enlarged cross-sectional view showing the vicinity of the drain electrode of the semiconductor device according to the second embodiment. [Figure 8] FIG. 8 is a plan view of a semiconductor device according to the second embodiment. [Figure 9A] FIG. 9A is a cross-sectional view illustrating one step of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 9B] FIG. 9B is a cross-sectional view illustrating one step of the method for manufacturing the semiconductor device according to the second embodiment. [Figure 9C] FIG. 9C is a cross-sectional view illustrating one step of the method for manufacturing the semiconductor device according to the second embodiment. [Figure 9D]FIG. 9D is a cross-sectional view illustrating one step of the method for manufacturing the semiconductor device according to the second embodiment. [Figure 9E] FIG. 9E is a cross-sectional view illustrating one step of the method for manufacturing the semiconductor device according to the second embodiment. [Figure 9F] FIG. 9F is a cross-sectional view illustrating one step of the method for manufacturing the semiconductor device according to the second embodiment. [Figure 9G] FIG. 9G is a cross-sectional view illustrating one step of the method for manufacturing the semiconductor device according to the second embodiment. [Figure 9H] FIG. 9H is a cross-sectional view illustrating one step of the method for manufacturing the semiconductor device according to the second embodiment. [Figure 9I] FIG. 9I is a cross-sectional view illustrating one step of the method for manufacturing the semiconductor device according to the second embodiment. [Figure 9J] FIG. 9J is a cross-sectional view illustrating one step of the method for manufacturing the semiconductor device according to the second embodiment. [Figure 9K] FIG. 9K is a cross-sectional view illustrating a step of the method for manufacturing the semiconductor device according to the second embodiment. [Figure 9L] FIG. 9L is a cross-sectional view illustrating one step of the method for manufacturing the semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] (Summary of the Disclosure) A semiconductor device according to a first aspect of the present disclosure comprises a semiconductor laminate structure containing a two-dimensional electron gas, a p-type first semiconductor layer provided on the semiconductor laminate structure, and a drain electrode in contact with the first semiconductor layer, wherein the first semiconductor layer includes a thick film portion and a thin film portion that is thinner than the thick film portion, and the semiconductor laminate structure has a recess in a region adjacent to the thin film portion in a planar view, and the drain electrode contacts a side surface of the recess and a side surface of the thin film portion.

[0012] This suppresses the expansion of the depletion layer into the semiconductor stack structure directly below the p-type first semiconductor layer, facilitating on-state operation. This is because the depletion layer formed directly below the thin-film portion is smaller than the depletion layer formed directly below the thick-film portion. Current collapse often occurs near the drain electrode, where the electric field is strongest during on-state operation (channel depletion due to electrons trapped in surface states). In contrast, in the semiconductor device according to this embodiment, the thin-film portion is provided in contact with the drain electrode, where current collapse is most likely to occur. Therefore, holes injected from the drain electrode into the thin-film portion can eliminate electrons trapped in surface states. This suppresses the expansion of the depletion layer and current collapse. Including the thick-film portion in the p-type first semiconductor layer increases the total number of holes in the p-type first semiconductor layer, thereby enhancing the suppression effect of current collapse. Thus, the semiconductor device according to this embodiment achieves both normally-off operation and reduced current collapse.

[0013] Furthermore, since the drain electrode is provided so as to contact the side surface of the recess, the drain electrode and the 2DEG can be brought into contact with each other or the distance therebetween can be shortened, thereby reducing the on-resistance.

[0014] A semiconductor device according to a second aspect of the present disclosure is the semiconductor device according to the first aspect, wherein a side surface of the recess and a side surface of the thin film portion are continuous.

[0015] This allows the patterning of the p-type first semiconductor layer and the formation of the recesses to be performed in the same process, and also allows the semiconductor device to be made smaller.

[0016] A semiconductor device according to a third aspect of the present disclosure is a semiconductor device according to the first or second aspect, further comprising a p-type second semiconductor layer provided apart from the first semiconductor layer, and a gate electrode provided above the second semiconductor layer, and the thickness of the second semiconductor layer is the same as the thickness of the thick film portion.

[0017] This allows the thin-film portion to be thinner than the p-type second semiconductor layer, so that when the drain electrode is low, the depletion layer formed directly below the thin-film portion can be made smaller, thereby reducing the on-resistance while suppressing the impact on normally-off operation.

[0018] A semiconductor device according to a fourth aspect of the present disclosure is a semiconductor device according to any one of the first to third aspects, further comprising an i-type third semiconductor layer provided on the thin film portion, and the drain electrode further contacts the upper surface of the thick film portion.

[0019] This allows the upper surface of the thick film portion to contact the drain electrode, so that even if the upper surface of the thin film portion does not contact the drain electrode, a sufficient number of holes can be injected from the drain electrode into the p-type semiconductor layer, thereby enhancing the effect of suppressing current collapse.

[0020] A semiconductor device according to a fifth aspect of the present disclosure is the semiconductor device according to the fourth aspect, wherein an upper surface of the thick film portion is flush with an upper surface of the third semiconductor layer.

[0021] This allows the third semiconductor layer to be easily formed by, for example, ion implantation, etc. For example, since it becomes easy to adjust the thickness of the third semiconductor layer, it also becomes easy to adjust the thickness of the thin film portion that is not ion-implanted.

[0022] A semiconductor device according to a sixth aspect of the present disclosure is a semiconductor device according to the fourth or fifth aspect, wherein, in a plan view, the third semiconductor layers are arranged side by side in the gate width direction, and the thick film portion includes a base portion extending in the gate width direction and a plurality of branch portions extending from the base portion between adjacent third semiconductor layers.

[0023] This allows holes to be efficiently injected from the drain electrode to the thin film portion via the plurality of branches, thereby enhancing the effect of suppressing current collapse.

[0024] A semiconductor device according to a seventh aspect of the present disclosure is the semiconductor device according to any one of the first to third aspects, wherein the drain electrode further contacts an upper surface of the thin film portion.

[0025] This allows holes to be efficiently injected from the drain electrode into the thin film portion, thereby enhancing the effect of suppressing current collapse.

[0026] A semiconductor device according to an eighth aspect of the present disclosure is the semiconductor device according to the seventh aspect, further comprising an i-type fourth semiconductor layer provided above the thick film portion.

[0027] This makes it difficult for holes to be injected from the drain electrode into the thick film portion, which prevents the depletion layer from spreading directly below the thick film portion and makes it difficult to inhibit on-state operation. This makes it easier to optimize normally-off operation and suppress current collapse.

[0028] A semiconductor device according to a ninth aspect of the present disclosure is a semiconductor device according to any one of the first to eighth aspects, further comprising an insulating layer provided above the thick film portion, and the drain electrode is provided above the insulating layer.

[0029] This allows the drain electrode to cover the insulating layer, thereby preventing the insulating layer from peeling off, thereby achieving a highly reliable semiconductor device.

[0030] A semiconductor device according to a tenth aspect of the present disclosure is a semiconductor device according to any one of the first to ninth aspects, wherein the length of the thin film portion along the gate length direction is longer than the length of the thick film portion along the gate length direction.

[0031] This makes it easier to achieve both normally-off operation and suppression of current collapse.

[0032] A method for manufacturing a semiconductor device according to an eleventh aspect of the present disclosure includes the steps of: forming a semiconductor laminate structure containing two-dimensional electron gas; forming a p-type first semiconductor layer on the semiconductor laminate structure, the p-type first semiconductor layer having a thick film portion and a thin film portion thinner than the thick film portion; forming a recess in a first region of the semiconductor laminate structure adjacent to the thin film portion in a planar view; and forming a drain electrode in contact with a side surface of the recess and a side surface of the thin film portion of the first semiconductor layer.

[0033] This makes it possible to manufacture a semiconductor device that can achieve both normally-off operation and reduced current collapse.

[0034] A twelfth aspect of the present disclosure relates to a method for manufacturing a semiconductor device according to the eleventh aspect, wherein the step of forming the first semiconductor layer includes a first step of depositing a p-type semiconductor film so as to cover at least the first region on the upper surface of the semiconductor laminated structure and a second region adjacent to the first region, a second step of removing the semiconductor film located in the first region, and a third step of removing at least a portion of the semiconductor film located only in the third region out of a third region and a fourth region included in the second region, and the step of forming the recess is performed simultaneously with the third step.

[0035] This allows the patterning of the p-type first semiconductor layer and the formation of the recesses to be performed in the same step.

[0036] A semiconductor device manufacturing method according to a thirteenth aspect of the present disclosure is a semiconductor device manufacturing method according to the twelfth aspect, wherein in the third step, the thin film portion is formed by removing a surface portion of the semiconductor film located in the third region, and the thick film portion is the semiconductor film remaining in the fourth region.

[0037] This allows the drain electrode to be formed in contact with the top surface of the thin film portion, which allows holes to be efficiently injected from the drain electrode into the thin film portion, thereby enhancing the effect of suppressing current collapse.

[0038] A semiconductor device manufacturing method according to a fourteenth aspect of the present disclosure is the semiconductor device manufacturing method according to the thirteenth aspect, wherein the step of forming the first semiconductor layer further includes, after the first step and before the third step, a fourth step of forming an i-type semiconductor film so as to cover at least the second region on the upper surface of the semiconductor film, and a fifth step of removing the i-type semiconductor film located in the third region, and the third step is performed consecutively from the fifth step.

[0039] This makes it difficult for holes to be injected from the drain electrode into the thick film portion by providing an i-type semiconductor layer, which suppresses the expansion of the depletion layer directly below the thick film portion and makes it difficult to inhibit on-state operation. This makes it easier to achieve optimal normally-off operation and suppression of current collapse.

[0040] A semiconductor device manufacturing method according to a fifteenth aspect of the present disclosure is the semiconductor device manufacturing method according to either the thirteenth or fourteenth aspect, in which the third step is performed using a plasma etching method.

[0041] This damages the upper surface of the thin film portion exposed to the plasma, thereby inactivating the p-type impurities contained near the upper surface of the thin film portion. By making the upper surface of the thin film portion i-type, the thickness that functions as a p-type semiconductor layer can be reduced.

[0042] A method for manufacturing a semiconductor device according to a sixteenth aspect of the present disclosure is a method for manufacturing a semiconductor device according to the twelfth aspect, wherein the step of forming the first semiconductor layer further includes, after the first step, a step of implanting ions into a surface layer portion of the semiconductor film located in the third region to make it i-type, thereby leaving a lower layer portion of the third region as the thin film portion.

[0043] This makes it easy to adjust the thickness of the thin film portion, since ion implantation has excellent controllability over the depth of the implanted region.

[0044] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0045] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0046] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0047] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel and perpendicular, terms indicating the shape of elements, such as rectangle and trapezoid, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0048] Furthermore, in this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "above" and "below" are applied not only to a case where two components are arranged with a gap between them and another component exists between them, but also to a case where two components are arranged closely together and the two components are in contact with each other.

[0049] In this specification and drawings, the x-axis, y-axis, and z-axis represent the three axes of a three-dimensional Cartesian coordinate system. Specifically, the x-axis is defined as an axis parallel to the gate length direction, and the y-axis is defined as an axis parallel to the gate width direction. The z-axis is defined as an axis perpendicular to the top surface of the semiconductor laminated structure. The z-axis direction is the stacking direction of each layer of the semiconductor laminated structure. In this specification, unless otherwise specified, "plan view" refers to a view from a direction perpendicular to the top surface of the semiconductor laminated structure, specifically, a view from the positive or negative side of the z-axis.

[0050] In this specification, n-type and p-type refer to the conductivity types of semiconductors, and are conductivity types of opposite polarity. + The n-type indicates a state in which a semiconductor is heavily doped with n-type dopants. - The term "type" refers to a state in which a semiconductor is doped with a low concentration of n-type dopants, a so-called light doping. + Type and n - Both types are examples of n-type, and may be referred to as n-type without distinction. + Type and p - The same is true for types.

[0051] The term "i-type" refers to a so-called undoped state in which no n-type or p-type dopants are added. Note that the i-type semiconductor layer may be doped with impurities other than n-type or p-type dopants.

[0052] In addition, in this specification, the term "major component" refers to the component with the highest content among all the components that make up a component. For example, a component with a content of 50% or more is a major component. A component may be a material, element, or compound. Furthermore, "component A is composed of component B" means that component A essentially contains only component B. However, component A may contain impurities other than component B that are unavoidable in the manufacturing process. The content of such unavoidable impurities is 1% or less.

[0053] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0054] (Embodiment 1) First, the semiconductor device according to the first embodiment will be described.

[0055] Fig. 1 is a cross-sectional view of a semiconductor device 100 according to the present embodiment. Fig. 2 is an enlarged cross-sectional view showing the vicinity of a drain electrode 160 of the semiconductor device 100 according to the present embodiment.

[0056] The semiconductor device 100 shown in FIGS. 1 and 2 is a nitride semiconductor device in which a semiconductor stacked structure 110 including a channel contains a nitride semiconductor as a main component. The nitride semiconductor is a group III nitride semiconductor containing one or more group III elements and nitrogen. Examples of group III elements include aluminum (Al), gallium (Ga), and indium (In). Examples of group III nitride semiconductors include GaN, AlN, InN, AlGaN, InGaN, and AlInGaN. Group III nitride semiconductors may contain one or more elements other than group III elements, such as silicon (Si) and phosphorus (P). In the following description, unless otherwise specified, the term "AlInGaN" means that the group III nitride semiconductor contains all of Al, In, Ga, and N. The same applies to other notations such as AlGaN and GaN.

[0057] 1 and 2 is a normally-off HEMT, and includes a semiconductor stack structure 110, p-type semiconductor layers 120 and 125, cap layers 130 and 135, a gate electrode 140, a source electrode 150, a drain electrode 160, and insulating layers 170 and 180.

[0058] The semiconductor laminated structure 110 includes a two-dimensional electron gas (2DEG). The semiconductor laminated structure 110 is a laminate of multiple nitride semiconductor layers. The semiconductor laminated structure 110 is supported on a substrate (not shown). For example, the substrate is a Si substrate, but it may also be an SOI (Silicon on Insulator) substrate. Alternatively, the substrate may be a substrate made of SiC, sapphire, diamond, GaN, AlN, or the like.

[0059] The semiconductor laminated structure 110 includes, for example, a channel layer and a barrier layer laminated on the channel layer. The channel layer has a smaller band gap than the barrier layer. The channel layer contains, for example, i-type GaN as a main component. The barrier layer contains, for example, i-type AlGaN as a main component. The barrier layer and the channel layer form an AlGaN / GaN heterojunction. channel A 2DEG is generated on the layer side.

[0060] The channel layer may be called an electron transit layer, and the barrier layer may be called an electron supply layer. A layer for suppressing alloy scattering, such as AlN, may be provided between the channel layer and the barrier layer. The semiconductor laminate structure 110 may also include at least one of a buffer layer for reducing lattice mismatch between the substrate and the channel layer and a back barrier layer provided between the buffer layer and the channel layer. The semiconductor laminate structure 110 may also include a cap layer covering the upper surface of the barrier layer. The buffer layer, the back barrier layer, and the barrier layer all contain a nitride semiconductor, such as GaN, AlGaN, or InGaN, as a main component.

[0061] The semiconductor laminated structure 110 has a recess 112 and a recess 114. The recess 112 is provided in a first region 101 of the semiconductor laminated structure 110. In a plan view, the first region 101 is a region adjacent to a second region 102 in which a p-type semiconductor layer 120 is provided. A drain electrode 160 is provided so as to cover a bottom surface 112a and a side surface 112b of the recess 112. A source electrode 150 is provided so as to cover a bottom surface 114a and a side surface 114b of the recess 114.

[0062] The p-type semiconductor layer 120 is an example of a p-type first semiconductor layer, and is provided on the semiconductor laminate structure 110. Specifically, the p-type semiconductor layer 120 is provided in contact with the upper surface 110a of the semiconductor laminate structure 110. The p-type semiconductor layer 120 contains, for example, p-type GaN as a main component. The concentration of the p-type dopant in the p-type semiconductor layer 120 is, for example, 10 18 atms / cm 3 Over 10 20 atms / cm 3 1, the p-type semiconductor layer 120 includes a thick portion 122 and a thin portion 124. The specific configuration of the p-type semiconductor layer 120 will be described later with reference to FIG.

[0063] The p-type semiconductor layer 125 is an example of a p-type second semiconductor layer, and is provided on the semiconductor laminate structure 110 at a distance from the p-type semiconductor layer 120. Specifically, the p-type semiconductor layer 125 is provided in contact with the upper surface 110a of the semiconductor laminate structure 110. The p-type semiconductor layer 125 contains, for example, p-type GaN as a main component. The concentration of the p-type dopant in the p-type semiconductor layer 120 is, for example, 10 18 atms / cm 3 Over 10 20 atms / cm 3 The following is the result.

[0064] Due to the provision of the p-type semiconductor layer 125, when 0 V or a negative voltage is applied to the gate electrode 140, a depletion layer expands in the semiconductor stack structure 110 directly below the p-type semiconductor layer 125, and the 2DEG disappears. As a result, the channel between the source electrode 150 and the drain electrode 160 is blocked, and the semiconductor device 100 is turned off (non-conductive state, blocked state). When a positive voltage equal to or greater than the threshold is applied to the gate electrode 140, the depletion layer directly below the p-type semiconductor layer 125 degenerates, and the 2DEG is generated. As a result, the channel between the source electrode 150 and the drain electrode 160 becomes conductive, and the semiconductor device 100 is turned on (conductive state).

[0065] The cap layer 130 is an example of an i-type fourth semiconductor layer, and is provided on the thick film portion 122 of the p-type semiconductor layer 120. Specifically, the cap layer 130 is provided in contact with the upper surface 122a of the thick film portion 122. The cap layer 130 contains, for example, i-type AlGaN as a main component.

[0066] The cap layer 135 is an example of an i-type fifth semiconductor layer, and is provided on the p-type semiconductor layer 125. Specifically, the cap layer 135 is provided in contact with the upper surface of the p-type semiconductor layer 125. The cap layer 135 contains, for example, i-type AlGaN as a main component. The provision of the cap layer 135 can reduce the current flowing from the gate electrode 140 to the 2DEG via the p-type semiconductor layer 125.

[0067] The gate electrode 140 is provided above the p-type semiconductor layer 125. Specifically, the gate electrode 140 is provided in contact with the upper surface of the cap layer 135. The gate electrode 140 contains, for example, TiN as a main component. Note that the gate electrode 140 only needs to be conductive, and may contain, as a main component, a conductive material such as a metal nitride other than TiN or a metal. The gate electrode 140 may also have a stacked structure of multiple metal films having different main components.

[0068] The source electrode 150 and the drain electrode 160 are provided to sandwich the gate electrode 140 therebetween. In the example shown in FIG. 1 , the distance between the source electrode 150 and the gate electrode 140 is shorter than the distance between the drain electrode 160 and the gate electrode 140, but this is not limited to this. The source electrode 150 contacts and covers a bottom surface 114a and a side surface 114b of a recess 114 provided in the semiconductor laminate structure 110. The drain electrode 160 contacts and covers a bottom surface 112a and a side surface 112b of a recess 112 provided in the semiconductor laminate structure 110. The drain electrode 160 is also in contact with the p-type semiconductor layer 120.

[0069] The source electrode 150 and the drain electrode 160 contain, as a main component, a conductive material that is in ohmic contact with the n-type nitride semiconductor. For example, the source electrode 150 and the drain electrode 160 contain, as a main component, a TiAl alloy. The source electrode 150 and the drain electrode 160 may contain, as a main component, a conductive material such as an elemental metal such as Ti or Al. The source electrode 150 and the drain electrode 160 may also have a stacked structure of multiple metal films with different main components. In this embodiment, the source electrode 150 and the drain electrode 160 contain the same material as a main component, but may also contain different materials as a main component.

[0070] The insulating layer 170 is a layer containing an insulating material as a main component. For example, the insulating layer 170 contains SiN as a main component. The insulating layer 170 may contain other insulating materials, such as SiO2 or SiON, as a main component. The insulating layer 170 may also have a stacked structure of multiple insulating films each containing a different main component.

[0071] The insulating layer 170 is provided on the semiconductor laminated structure 110. The insulating layer 170 is provided above the thick film portion 122 of the p-type semiconductor layer 120. The insulating layer 170 is also provided above the p-type semiconductor layer 125. Specifically, the insulating layer 170 contacts and covers the upper surface 110a of the semiconductor laminated structure 110, the side surfaces of the thick film portion 122 and the cap layer 130 facing the gate electrode 140, the upper surface 130a of the cap layer 130, the side surfaces of the p-type semiconductor layer 125, and the side surfaces and upper surface of the cap layer 135. Thus, the provision of the insulating layer 170 can suppress leakage current flowing through the upper surface 110a of the semiconductor laminated structure 110. The insulating layer 170 also functions as a protective film for the semiconductor laminated structure 110, the p-type semiconductor layers 120 and 125, and the cap layers 130 and 135.

[0072] The insulating layer 170 has an opening (gate opening) for exposing a portion of the upper surface of the cap layer 135. The gate electrode 140 is in contact with the upper surface of the cap layer 135 through the gate opening. The insulating layer 170 also has an opening (drain opening) for exposing the recess 112 and the thin film portion 124 of the p-type semiconductor layer 120, and an opening (source opening) for exposing the recess 114. The source electrode 150 is in contact with the bottom surface 114a and side surface 114b of the recess 114 of the semiconductor laminated structure 110 through the source opening. The drain electrode 160 is in contact with the top surface 124a and side surface 124b of the thin film portion 124 and also with the bottom surface 112a and side surface 112b of the recess 112 of the semiconductor laminated structure 110 through the drain opening.

[0073] The insulating layer 180 is a layer containing an insulating material as a main component. For example, the insulating layer 180 contains SiN as a main component. The insulating layer 180 may contain other insulating materials, such as SiO2 or SiON, as a main component. The insulating layer 180 may also have a stacked structure of multiple insulating films each containing a different main component. The insulating layer 180 contains the same insulating material as the insulating material contained as a main component of the insulating layer 170, but may also contain a different insulating material as a main component.

[0074] The insulating layer 180 is provided above the insulating layer 170. Specifically, the insulating layer 180 covers and comes into contact with the upper surface of the insulating layer 170. The insulating layer 180 also covers and comes into contact with a portion of the upper surface of the source electrode 150 and a portion of the upper surface of the drain electrode 160. This makes it possible to suppress leakage current between the gate electrode 140 and the source electrode 150, and between the gate electrode 140 and the drain electrode 160. The insulating layer 180 also functions as a protective film for the semiconductor stacked structure 110, the p-type semiconductor layers 120 and 125, and the cap layers 130 and 135.

[0075] The insulating layer 180 has openings for exposing a part of the upper surface of the source electrode 150 and a part of the upper surface of the drain electrode 160. Source wiring and drain wiring (not shown) are connected to the source electrode 150 and the drain electrode 160 through the openings.

[0076] [Characteristic composition] Next, the main characteristic configuration of the semiconductor device 100 according to this embodiment will be specifically described.

[0077] 2, the p-type semiconductor layer 120 includes a thick film portion 122 and a thin film portion 124. The thickness T1 of the thick film portion 122 is, for example, not less than 50 nm and not more than 200 nm, and is, for example, 180 nm. The thickness T2 of the thin film portion 124 is thinner than the thickness T1 of the thick film portion 122. For example, the thickness T2 of the thin film portion 124 is thinner than half the thickness T1 of the thick film portion 122. Furthermore, the thickness T2 of the thin film portion 124 is, for example, not less than 30 nm.

[0078] The thick film portion 122 and the thin film portion 124 each have a forward tapered cross-sectional shape. A forward tapered shape is a shape in which the width (length in the x-axis direction) narrows toward the top (positive direction of the z-axis), e.g., a trapezoid whose upper base is shorter than its lower base. The side surface 122b of the thick film portion 122 and the side surface 124b of the thin film portion 124 are each inclined with respect to the top surface 110a (xy plane) of the semiconductor laminate structure 110. This makes it less likely that steps will occur in the films (insulating layer 170, drain electrode 160, etc.) formed on the thick film portion 122 and the thin film portion 124, thereby realizing a highly reliable semiconductor device 100.

[0079] The side surfaces 122b and 124b may be perpendicular to the xy plane. This allows the lengths of the thick film portion 122 and the thin film portion 124 in the x-axis direction to be shortened, thereby achieving miniaturization of the semiconductor device 100. Alternatively, the thick film portion 122 and the thin film portion 124 may each have an inversely tapered cross-sectional shape. An inversely tapered shape is a shape that narrows downward (in the negative direction of the z-axis), such as a trapezoid whose upper base is longer than its lower base. The top surface 122a of the thick film portion 122 and the top surface 124a of the thin film portion 124 are parallel to the xy plane, but may be inclined at an angle. The top surfaces 122a and 124a and the side surfaces 122b and 124b are flat, but may also be curved, or may have fine irregularities within the surfaces.

[0080] Furthermore, the upper surface 124a of the thin film portion 124 may be provided with fine irregularities. This increases the contact area between the drain electrode 160 and the upper surface 124a, thereby improving the efficiency of hole injection from the drain electrode 160 to the thin film portion 124. The fine irregularities on the upper surface 124a can be formed by etching damage using plasma etching, for example. Furthermore, the side surface 124b of the thin film portion 124 and the side surface 122b of the thick film portion 122 may also be provided with fine irregularities. This can further increase the contact area between the p-type semiconductor layer 120 and the drain electrode 160, thereby further improving the efficiency of hole injection.

[0081] A depletion layer is formed in the semiconductor laminate structure 110 directly below the p-type semiconductor layer 120. The depth of the formed depletion layer depends on the thickness of the p-type semiconductor layer 120. Specifically, the thicker the p-type semiconductor layer 120, the deeper the depletion layer, and the thinner the p-type semiconductor layer 120, the shallower the depletion layer. In this embodiment, the p-type semiconductor layer 120 includes the thin film portion 124, which makes it possible to suppress the spread of the depletion layer into the semiconductor laminate structure 110 directly below the thin film portion 124. This makes it easier to turn on the semiconductor device 100.

[0082] In this embodiment, the thickness T1 of the thick film portion 122 is the same as the thickness of the p-type semiconductor layer 125 provided immediately below the gate electrode 140. That is, the thickness T2 of the thin film portion 124 is thinner than the thickness of the p-type semiconductor layer 125. Therefore, the depth of the depletion layer formed immediately below the thin film portion 124 is smaller than the depth of the depletion layer formed immediately below the p-type semiconductor layer 125. Therefore, the on-resistance can be reduced while suppressing the influence on the normally-off operation of the semiconductor device 100.

[0083] Current collapse often occurs near the drain electrode 160, where the electric field is strongest during on-state operation of the semiconductor device 100, causing channel depletion due to electrons trapped in the surface state. In contrast, in the semiconductor device 100 according to this embodiment, the thin-film portion 124 is provided so as to contact the drain electrode 160, where current collapse often occurs. Specifically, the drain electrode 160 is in contact with the side surface 124b of the thin-film portion 124. As a result, holes are injected from the drain electrode 160 into the thin-film portion 124. Note that in FIG. 2 , the injection of holes is schematically represented by an open arrow. As a result, electrons trapped in the surface state can be eliminated by the holes injected from the drain electrode 160. This suppresses the expansion of the depletion layer directly below the thin-film portion 124, thereby suppressing current collapse.

[0084] Furthermore, the drain electrode 160 is in contact with not only the side surface 124b of the thin film portion 124 but also the upper surface 124a. This allows holes to be efficiently injected from the drain electrode 160 into the thin film portion 124. This improves the effect of suppressing current collapse. Furthermore, in this embodiment, the drain electrode 160 is also in contact with the side surface 122b of the thick film portion 122. This allows holes to be injected from the drain electrode 160 into the thick film portion 122, and the total number of holes stored in the p-type semiconductor layer 120 can be increased. This further improves the effect of suppressing current collapse. Furthermore, the increase in the total number of holes also makes it possible to obtain good high-frequency characteristics.

[0085] In the semiconductor device 100 according to this embodiment, the p-type semiconductor layer 120 includes the thick film portion 122, which can increase the total number of holes in the p-type semiconductor layer 120. This can enhance the effect of suppressing current collapse. The thick film portion 122 is provided between the thin film portion 124 and the gate electrode 140. In other words, the thick film portion 122 and the thin film portion 124 are provided side by side in this order along the direction from the gate electrode 140 toward the drain electrode 160 (the positive direction of the x-axis).

[0086] The length L1 of the thick film portion 122 along the gate length direction (x-axis direction) is equal to or less than the length L2 of the thin film portion 124 along the gate length direction (x-axis direction). Each of the lengths L1 and L2 is, for example, 700 nm or less. The shorter the length L1 of the thick film portion 122, the more easily holes injected from the drain electrode 160 through the side surface 122b reach the end of the thick film portion 122 (the end on the negative side of the x-axis). For example, if the length L1 of the thick film portion 122 is 200 nm or less, sufficient hole injection is possible. Furthermore, by shortening the length L1 of the thick film portion 122, the depletion layer formed deep within the semiconductor stacked structure 110 becomes smaller. This makes it possible to suppress interference with normally-off operation.

[0087] The length L2 of the thin film portion 124 may be twice or more the length L1 of the thick film portion 122. This makes it easier to achieve both normally-off operation and suppression of current collapse. In terms of the cross-sectional area in the xz cross section, the cross-sectional area of ​​the thin film portion 124 may be, for example, 0.5 times or more the cross-sectional area of ​​the thick film portion 122. Alternatively, the cross-sectional area of ​​the thin film portion 124 may be equal to or greater than the cross-sectional area of ​​the thick film portion 122. This makes it easier to achieve both normally-off operation and suppression of current collapse.

[0088] The semiconductor laminated structure 110 has a recess 112 in the first region 101 adjacent to the thin film portion 124 in a plan view. The drain electrode 160 is in contact with a side surface 112b of the recess 112. The drain electrode 160 is also in contact with a bottom surface 112a of the recess 112. The cross-sectional shape of the recess 112 is inverted tapered, with the side surface 112b inclined relative to the bottom surface 112a, but is not limited to this. The side surface 112b may be perpendicular to the bottom surface 112a. Alternatively, the cross-sectional shape of the recess 112 may be forward tapered.

[0089] By providing the recess 112, the distance between the 2DEG and the drain electrode 160 can be shortened. For example, by forming the recess 112 deeper than the thickness of the barrier layer (AlGaN layer), the end of the 2DEG is exposed at the side surface 112b. This allows the 2DEG and the drain electrode 160 to contact each other at the side surface 112b. By bringing the 2DEG and the drain electrode 160 into contact with each other, the on-resistance can be reduced. Note that if the recess 112 is shallower than the thickness of the barrier layer, the 2DEG is not exposed at the side surface 112b. Even in this case, by providing the recess 112, the distance between the drain electrode 160 and the 2DEG becomes shorter. Therefore, the on-resistance can be reduced.

[0090] 1, the semiconductor stacked structure 110 also has a recess 114 on the source electrode 150 side. The source electrode 150 is in contact with bottom surfaces 114a and 114b of the recess 114. This allows the source electrode 150 to be in contact with the 2DEG or shortens the distance between them, thereby reducing the on-resistance.

[0091] 2, the side surface 112b of the recess 112 and the side surface 124b of the thin film portion 124 are continuous. That is, the upper end of the side surface 112b and the lower end of the side surface 124b are the same. In this embodiment, the inclination angle of the side surface 112b and the inclination angle of the side surface 124b are the same, and the side surface 112b and the side surface 124b are flush with each other. Note that the inclination angle of the side surface 112b and the inclination angle of the side surface 124b may be different.

[0092] In this way, by making the side surface 112b and the side surface 124b continuous, the length of the drain electrode 160 in the x-axis direction can be shortened. This makes it possible to reduce the size of the semiconductor device 100. Furthermore, by making the side surface 112b and the side surface 124b continuous, the patterning of the p-type semiconductor layer 120 and the formation of the recess 112 can be performed in the same process. A specific manufacturing method will be described later.

[0093] In this embodiment, a cap layer 130 is provided on the thick film portion 122. The cap layer 130 covers the entire upper surface 122a of the thick film portion 122. Therefore, the drain electrode 160 is not in contact with the upper surface 122a of the thick film portion 122. This prevents holes from being injected from the drain electrode 160 into the thick film portion 122 via the upper surface 122a. Since the amount of holes injected into the thick film portion 122 when the drain voltage is low can be limited, the depletion layer formed directly below the thick film portion 122 can be made shallower than the depletion layer formed directly below the gate electrode 140. This makes it possible to reduce the on-resistance while suppressing the effect on normally-off operation.

[0094] The band gap of the cap layer 130 is larger than the band gap of the p-type semiconductor layer 120. This allows a distribution (concentration gradient) of holes to be formed in the p-type semiconductor layer 120 (thick film portion 122), thereby enabling control of the on-resistance.

[0095] The thickness of the cap layer 130 is, for example, 5 nm to 30 nm, for example, 20 nm. The cap layer 130 can be formed in the same process as the cap layer 135 provided directly below the gate electrode 140. The cross-sectional shape of the cap layer 130 is forward tapered, but it may also be reverse tapered, and the side surface may be perpendicular to the xy plane.

[0096] An upper surface 130a of the cap layer 130 is covered with an insulating layer 170. Furthermore, a drain electrode 160 is provided above the cap layer 130. Specifically, the drain electrode 160 contacts and covers the upper surface and side surfaces of the insulating layer 170 above the cap layer 130. In this way, the drain electrode 160 covers the end portion of the insulating layer 170, making it difficult for the insulating layer 170 to peel off from the cap layer 130. This can improve the reliability of the semiconductor device 100.

[0097] [Manufacturing method] Next, a method for manufacturing semiconductor device 100 according to this embodiment will be described with reference to Figures 3A to 3I. Figures 3A to 3I are all cross-sectional views for explaining one step of the method for manufacturing semiconductor device 100 according to this embodiment.

[0098] The manufacturing method of the semiconductor device 100 includes the steps of forming a semiconductor laminated structure 110 containing a two-dimensional electron gas (Figure 3A), forming a p-type semiconductor layer 120 having a thick film portion 122 and a thin film portion 124 on the semiconductor laminated structure 110 (Figures 3A to 3E), forming a recess 112 in a first region 101 of the semiconductor laminated structure 110 adjacent to the thin film portion 124 in a planar view (Figure 3E), and forming a drain electrode 160 in contact with the side surface 112b of the recess 112 and the side surface 124b of the thin film portion 124 (Figure 3F).

[0099] The process of forming the p-type semiconductor layer 120 includes a first step (FIG. 3A) of forming a p-type semiconductor film 120A so as to cover at least the first region 101 and the adjacent second region 102; a second step (FIG. 3B) of removing the p-type semiconductor film 120A located in the first region 101; and a third step (FIG. 3E) of removing at least a portion of the p-type semiconductor film 120A located only in the third region 103 of the third region 103 and fourth region 104 included in the second region 102. In the third step, a surface layer portion of the p-type semiconductor film 120A located in the third region 103 is removed to form a thin film portion 124. At this time, the p-type semiconductor film 120A remaining in the fourth region 104 is a thick film portion 122. The third step is performed simultaneously with the step of forming the recess 112. The process of forming the p-type semiconductor layer 120 includes, after the first process and before the third process, a fourth process (FIG. 3A) of forming an i-type semiconductor film 130A so as to cover at least the second region 102 on the upper surface of the p-type semiconductor film 120A, and a fifth process (FIG. 3E) of removing the i-type semiconductor film 130A located in the third region 103. The third process is performed continuously from the fifth process.

[0100] Below, each step included in the method for manufacturing the semiconductor device 100 will be described in detail in the order of FIGS. 3A to 3I.

[0101] First, as shown in FIG. 3A , a semiconductor stacked structure 110, a p-type semiconductor film 120A, and an i-type semiconductor film 130A are formed in this order. Specifically, each semiconductor film is formed by epitaxially growing a nitride semiconductor on a substrate (not shown) using a method such as MOCVD (Metal-Organic Chemical Vapor Deposition). By adjusting the growth conditions (material, growth time, growth temperature, etc.) during the epitaxial growth, the channel layer and barrier layer included in the semiconductor stacked structure 110, the p-type semiconductor film 120A, and the i-type semiconductor film 130A are formed in this order. The p-type semiconductor film 120A is a film that serves as the base for the p-type semiconductor layers 120 and 125, and contains, for example, p-type GaN as a main component. The i-type semiconductor film 130A is a film that serves as the base for the cap layers 130 and 135, and contains, for example, i-type AlGaN as a main component.

[0102] 3A also shows a planned drain electrode portion 110d, a planned gate electrode portion 110g, and a planned source electrode portion 110s. The planned gate electrode portion 110g is a region for forming the gate electrode 140. The planned source electrode portion 110s is a region for forming the recess 114 for the source electrode 150. The planned drain electrode portion 110d is a region for forming the recess 112 for the drain electrode 160. The planned drain electrode portion 110d is an example of a first region, and is the same as the first region 101 shown in FIG.

[0103] Next, the i-type semiconductor film 130A and the p-type semiconductor film 120A are each patterned into a predetermined shape. Specifically, a mask is formed on the upper surface of the i-type semiconductor film 130A using a resist or the like, and the portions not covered by the mask are removed by etching. For example, the mask is formed to cover the gate electrode portion 110g and the second region 102 adjacent to the drain electrode portion 110d. The i-type semiconductor film 130A and the p-type semiconductor film 120A are removed in this order by etching, exposing the upper surface 110a of the semiconductor stacked structure 110. As a result, as shown in FIG. 3B, the cap layers 130 and 135 and the p-type semiconductor layers 120 and 125 are formed. The etching is dry etching, for example, using plasma etching. Alternatively, the etching may be wet etching. At this stage, the thickness of the p-type semiconductor layer 120 is substantially uniform. In other words, the thick portion 122 and the thin portion 124 have not yet been formed.

[0104] Next, as shown in FIG. 3C, an insulating layer 170 is formed. For example, the insulating layer 170 containing SiN as a main component is formed by plasma CVD (Chemical Vapor Deposition) using silane and ammonia. The insulating layer 170 is formed to cover the entire surface of the cap layers 130 and 135 and the upper surface 110a of the semiconductor laminate structure 110. Note that a SiN film formed by plasma CVD tends to have lower adhesion when the underlying layer is AlGaN than when the underlying layer is GaN. Therefore, as shown in FIGS. 1 and 2, peeling of the insulating layer 170 can be suppressed by covering the edge of the insulating layer 170 (SiN film) with the drain electrode 160.

[0105] Next, as shown in FIG. 3D, a portion of the insulating layer 170 is removed by etching. Specifically, portions of the insulating layer 170 located in the pre-source electrode portion 110s, the pre-drain electrode portion 110d (first region 101), and the third region 103 are removed. The etching is performed by dry etching using, for example, fluorine gas, but wet etching using hydrofluoric acid or hot phosphoric acid may also be used. The remaining portion of the insulating layer 170 is used as a mask for etching in a subsequent process.

[0106] Next, as shown in FIG. 3E, etching is performed using the insulating layer 170 as a mask. Specifically, recesses 112 and 114 are formed by removing the semiconductor laminate structure 110 located in the planned drain electrode portion 110d and the planned source electrode portion 110s. Furthermore, surface portions of the cap layer 130 and the p-type semiconductor layer 120 located in the third region 103 are removed. As a result, a thin film portion 124 is formed in the third region 103. Furthermore, the cap layer 130 and the p-type semiconductor layer 120 are not removed in the fourth region 104, and the remaining portion of the p-type semiconductor layer 120 is formed as a thick film portion 122.

[0107] In this way, the formation of the thin film portion 124 and the formation of the recess 112 can be performed in the same process. This makes the side surface 124b of the thin film portion 124 continuous with the side surface 112b of the recess 112. Note that by adjusting the film thickness of the cap layer 130, the film thickness of the thin film portion 124 and the depth of the recess 112 can be adjusted.

[0108] The etching is performed using a plasma etching method. Specifically, the etching is dry etching using a chlorine-based gas, a fluorine-based gas, or Ar gas. Dry etching forms fine irregularities on the upper surface 124a of the thin film portion 124. This increases the contact area between the upper surface 124a of the thin film portion 124 and the drain electrode 160, thereby improving the hole injection efficiency. Furthermore, physical damage caused by the plasma and bonding of Mg contained as a p-type impurity with chlorine or fluorine converts the region near the upper surface 124a of the thin film portion 124 to i-type. This further reduces the effective film thickness of the thin film portion 124. Note that after dry etching, wet etching using a sulfuric acid / hydrogen peroxide system may be performed. This removes dry etching residue.

[0109] Next, as shown in FIG. 3F, the source electrode 150 and the drain electrode 160 are formed. For example, a 20 nm Ti film and a 200 nm Al film are formed by sputtering or vapor deposition, and then heat treatment is performed to alloy the Ti and Al. The formed metal film is patterned by photolithography and etching to form the source electrode 150 and the drain electrode 160. Note that the patterning may be performed by a lift-off method.

[0110] 3G, the insulating layer 180 is formed. For example, the insulating layer 180 containing SiN as a main component is formed using the same method as that used to form the insulating layer 170.

[0111] Next, as shown in FIG. 3H, a portion of the insulating layer 180 is removed by etching to form an opening 181 for the gate electrode 140. Specifically, the opening 181 is formed at a position overlapping the p-type semiconductor layer 125 and the cap layer 135 in a plan view, thereby exposing the upper surface of the insulating layer 170. The etching is performed by dry etching using, for example, fluorine gas, but wet etching using hydrofluoric acid or hot phosphoric acid may also be used.

[0112] Next, as shown in FIG. 3I, the portion of the insulating layer 170 exposed in the opening 181 is removed by etching, thereby exposing the upper surface of the cap layer 135. The insulating layer 170 is etched by dry etching using, for example, fluorine gas, but may also be wet etching using hydrofluoric acid or hot phosphoric acid. The etching of the insulating layer 170 is performed consecutively to the step of forming the opening 181 in the insulating layer 180.

[0113] Next, the gate electrode 140 is formed so as to be in contact with the upper surface of the exposed cap layer 135. For example, a TiN film is formed by sputtering or the like, and then patterned by photolithography and etching to form the gate electrode 140. Note that the patterning may be performed by a lift-off method.

[0114] Through the above steps, the semiconductor device 100 shown in FIGS. 1 and 2 can be manufactured.

[0115] [Variations] Next, a description will be given of several modified examples of the semiconductor device 100 according to the first embodiment. The following description will focus on the differences from the first embodiment, and the description of the commonalities will be omitted or simplified.

[0116] <Variation 1> Fig. 4 is a cross-sectional view of a semiconductor device 100A according to Modification 1 of Embodiment 1. As shown in Fig. 4, the semiconductor device 100A is different from the semiconductor device 100 shown in Fig. 1 in the cross-sectional shapes of the recesses 112 and 114 and the cross-sectional shapes of the p-type semiconductor layer 120 and the cap layer 130. The semiconductor device 100A according to this modification can be manufactured when the etching selectivity is low in the etching step for forming the recesses 112 and 114 and the thin film portion 124 shown in Fig. 3E.

[0117] Specifically, the side surface 120b of the p-type semiconductor layer 120 and the side surface 130b of the cap layer 130 are each curved in a concave shape. In this modification, the area where the thickness of the p-type semiconductor layer 120 is substantially uniform is regarded as the thick film portion 122. In plan view, the area where the curved side surface 120b is provided is regarded as the thin film portion 124. The thickness of the thin film portion 124 is regarded as the average thickness of the thin film portion 124. The side surface 120b of the p-type semiconductor layer 120 is both the side surface and the top surface of the thin film portion 124.

[0118] In this modification, the inner surface of the recess 112 is also concavely curved. The inner surface of the recess 112 includes two different concavely curved surfaces. Specifically, as shown in Fig. 4, the recess 112 includes a first inner surface 112c and a second inner surface 112d.

[0119] First inner surface 112c is smoothly continuous with side surface 120b of p-type semiconductor layer 120. The lower end of side surface 120b of p-type semiconductor layer 120 coincides with the upper end of first inner surface 112c, and the inclination angle of side surface 120b and the inclination angle of first inner surface 112c at this coincidence point are the same.

[0120] The second inner surface 112d is continuous with the first inner surface 112c. The lower end of the first inner surface 112c coincides with the upper end of the second inner surface 112d, but the inclination angle of the first inner surface 112c and the inclination angle of the second inner surface 112d at this coincidence point are different. The inclination at the lower end of the first inner surface 112c is gentler than the inclination at the upper end of the second inner surface 112d.

[0121] By controlling the etching conditions, the first inner surface 112c may not be included in the inner surface of the recess 112. In this case, the side surface 120b of the p-type semiconductor layer 120 and the second inner surface 112d of the recess 112 are continuous.

[0122] The semiconductor device 100A according to this modification also has the same effects as those of the first embodiment, since the p-type semiconductor layer 120 includes the thick portion 122 and the thin portion 124. That is, the semiconductor device 100A can achieve both normally-off operation and suppression of current collapse.

[0123] <Variation 2> 5 is a cross-sectional view of a semiconductor device 100B according to Modification 2 of Embodiment 1. As shown in Fig. 5, the semiconductor device 100B differs from the semiconductor device 100 shown in Fig. 1 in the shape of the drain electrode 160.

[0124] Specifically, the drain electrode 160 extends beyond the p-type semiconductor layer 120 onto the gate electrode 140 side. That is, a part (extended part) of the drain electrode 160 is provided between the p-type semiconductor layer 120 and the p-type semiconductor layer 125 directly below the gate electrode 140 in a plan view. This allows the part of the drain electrode 160 to function as a field plate.

[0125] In this modification, the extension of the drain electrode 160 is provided on the insulating layer 180. That is, the drain electrode 160 covers both the insulating layers 170 and 180 above the cap layer 130. This makes it possible to prevent the insulating layers 170 and 180 from peeling off. In this case, the drain electrode 160 is formed after the insulating layer 180 is formed. In this modification, the drain electrode 160 and the source electrode 150 are formed in different processes. Note that, as in the first embodiment, the drain electrode 160 may be formed in the same process as the source electrode 150, before the insulating layer 180 is formed. In this case, the insulating layer 180 is provided so as to cover the extension of the drain electrode 160.

[0126] (Embodiment 2) Next, a description will be given of embodiment 2. In embodiment 2, a main difference from embodiment 1 is that an i-type semiconductor layer is provided on the top surface of a thin film portion of a p-type semiconductor layer that is in contact with a drain electrode. The following description will focus on the differences from embodiment 1, and description of commonalities will be omitted or simplified.

[0127] Fig. 6 is a cross-sectional view of the semiconductor device 200 according to this embodiment. Fig. 7 is an enlarged cross-sectional view showing the vicinity of the drain electrode 160 of the semiconductor device 200 according to this embodiment.

[0128] As shown in FIG. 6, the semiconductor device 200 differs from the semiconductor device 100 shown in FIG. 1 mainly in that it further includes an i-type semiconductor layer 220 and that it does not include the cap layers 130 and 135.

[0129] The i-type semiconductor layer 220 is an example of an i-type third semiconductor layer provided on the thin film portion 124. Specifically, the i-type semiconductor layer 220 is provided in contact with the upper surface 124a of the thin film portion 124 and the side surface 122b of the thick film portion 122. The i-type semiconductor layer 220 contains, for example, i-type GaN as a main component.

[0130] The i-type semiconductor layer 220 is formed, for example, by converting the surface layer of the p-type semiconductor layer into i-type before forming the thin film portion 124. Therefore, as shown in Fig. 7, the upper surface 220a of the i-type semiconductor layer 220 and the upper surface 122a of the thick film portion 122 are flush with each other. In addition, the side surface 220b of the i-type semiconductor layer 220 and the side surface 124b of the thin film portion 124 are flush with each other.

[0131] In this embodiment, since the i-type semiconductor layer 220 is provided, the drain electrode 160 does not contact the upper surface 124a of the thin film portion 124. Therefore, the only place where holes can be injected from the drain electrode 160 into the thin film portion 124 is the side surface 122b, which reduces the amount of injected holes and may result in an insufficient suppression effect of current collapse.

[0132] In contrast, in the present embodiment, the drain electrode 160 is in contact with the upper surface 122a of the thick film portion 122. As shown in FIG. 7, a portion of the upper surface 122a of the thick film portion 122 is covered with the insulating layer 170. Another portion of the upper surface 122a of the thick film portion 122 is not covered with the insulating layer 170 and is in contact with the drain electrode 160. This allows holes to be injected from the drain electrode 160 into the p-type semiconductor layer 120 via the upper surface 122a of the thick film portion 122. This makes it possible to prevent a shortage of the amount of injected holes and to enhance the effect of suppressing current collapse.

[0133] In order to increase the contact area between the thick film portion 122 and the drain electrode 160, the thick film portion 122 may be formed in a comb-like shape, as shown in Fig. 8. Fig. 8 is a plan view of a semiconductor device 200 according to this embodiment. Note that Fig. 8 does not illustrate the gate electrode 140, the source electrode 150, the drain electrode 160, and the insulating layers 170 and 180. The cross section taken along line VI-VI in Fig. 8 corresponds to the cross section shown in Fig. 6.

[0134] 8, the thick film portion 122 includes a base portion 122A extending in the gate width direction (y-axis direction) and a plurality of branch portions 122B extending from the base portion 122A. A plurality of i-type semiconductor layers 220 are provided side by side along the gate width direction. The branch portions 122B are provided between adjacent i-type semiconductor layers 220. Each of the plurality of branch portions 122B extends from the base portion 122A toward the positive side of the x-axis. This allows holes to be efficiently injected from the drain electrode 160 into the thin film portion 124 via the plurality of branch portions 122B, thereby enhancing the effect of suppressing current collapse.

[0135] Note that as the width (length in the y-axis direction) of the branch portion 122B increases, the area of ​​the thin film portion 124 decreases, which may hinder normally-off operation. Therefore, by narrowing the width of the branch portion 122B, it becomes easier to achieve both normally-off operation and suppression of current collapse. For example, the width of the branch portion 122B is 10% or less of the width of the i-type semiconductor layer 220. For example, the width of the branch portion 122B is 0.3 μm or more and 200 μm or less.

[0136] In this embodiment, the side surface 112b of the recess 112 is formed in a stepped shape. Specifically, as shown in Fig. 7, the side surface 112b includes an upper side surface 112e, a step surface 112f, and a lower side surface 112g.

[0137] The upper side surface 112e is smoothly continuous with the side surface 124b of the thin film portion 124. The lower end of the side surface 124b of the thin film portion 124 coincides with the upper end of the upper side surface 112e. In this embodiment, the upper side surface 112e, the side surface 124b of the thin film portion 124, and the side surface 220b of the i-type semiconductor layer 220 are flush with each other.

[0138] The step surface 112f is a surface located midway between the top surface 110a of the semiconductor laminate structure 110 and the bottom surface 112a of the recess 112. The step surface 112f connects the upper side surface 112e and the lower side surface 112g. The step surface 112f is parallel to the bottom surface 112a, but is not limited to this and may be inclined.

[0139] The lower side surface 112g is a surface that connects the step surface 112f and the bottom surface 112a of the recess 112. The inclination angle of the lower side surface 112g is the same as the inclination angle of the upper side surface 112e, but is not limited to this.

[0140] The upper side surface 112e, the step surface 112f, and the lower side surface 112g are all flat surfaces, but may be curved surfaces or may have fine irregularities. Furthermore, by reducing the area of ​​the step surface 112f, the semiconductor device 200 can be made smaller. The upper side surface 112e and the lower side surface 112g may be continuous without providing the step surface 112f. That is, the recess 112 provided in the semiconductor device 200 may be the same as the recess 112 provided in the semiconductor device 100 according to the first embodiment. Furthermore, in the semiconductor device 200 according to the present embodiment, the inner surface of the recess 112 may be curved in a concave shape, as in the first modification of the first embodiment. The side surfaces 220b and 122b may also be curved in a concave shape. The upper side surface 112e, the step surface 112f, and the lower side surface 112g may all be curved, or may be smoothly curved to the extent that they are indistinguishable from one another.

[0141] In the semiconductor device 200 according to the second embodiment, the drain electrode 160 may extend beyond the p-type semiconductor layer 120 toward the gate electrode 140, as in the semiconductor device 100B according to the second variant of the first embodiment.

[0142] [Manufacturing method] Next, a method for manufacturing semiconductor device 200 according to this embodiment will be described with reference to Figures 9A to 9L. Figures 9A to 9L are all cross-sectional views for explaining one step of the method for manufacturing semiconductor device 200 according to this embodiment.

[0143] The manufacturing method of the semiconductor device 200 includes the steps of forming a semiconductor laminated structure 110 containing a two-dimensional electron gas (Figure 9A), forming a p-type semiconductor layer 120 having a thick film portion 122 and a thin film portion 124 on the semiconductor laminated structure 110 (Figures 9A to 9E), forming a recess 112 in a first region 201 of the semiconductor laminated structure 110 adjacent to the thin film portion 124 in a planar view (Figure 9G), and forming a drain electrode 160 in contact with the side surface 112b of the recess 112 and the side surface 124b of the thin film portion 124 (Figure 9I).

[0144] The process of forming the p-type semiconductor layer 120 includes a first step (FIG. 9A) of forming a p-type semiconductor film 120A so as to cover at least the first region 201 and the adjacent second region 202, a second step (FIG. 9D) of removing the p-type semiconductor film 120A located in the first region 201, and a third step (FIG. 9G) of removing at least a portion of the p-type semiconductor film 120A located only in the third region 203 of the third region 203 and the fourth region 204 included in the second region 202. The process of forming the p-type semiconductor layer 120 further includes, after the first step, a step (FIG. 9B) of implanting ions into a surface portion of the p-type semiconductor film 120A located in the third region 203 to make it i-type, thereby leaving a lower portion of the third region 203 as a thin film portion 124.

[0145] Each step included in the method for manufacturing the semiconductor device 200 will be described in detail below in the order of FIGS. 9A to 9L.

[0146] First, as shown in FIG. 9A , the semiconductor stacked structure 110, the p-type semiconductor film 120A, and the resist 290 are formed in this order. Specifically, each semiconductor film is formed by growing a nitride semiconductor crystal on a substrate (not shown) by epitaxial growth such as MOCVD. By adjusting the growth conditions (material, growth time, growth temperature, etc.) for the epitaxial growth, the channel layer and barrier layer included in the semiconductor stacked structure 110 and the p-type semiconductor film 120A are formed in this order. Furthermore, the resist 290 is formed on the p-type semiconductor film 120A. The p-type semiconductor film 120A is a film that will become the base of the p-type semiconductor layers 120 and 125, and contains, for example, p-type GaN as its main component. The resist 290 serves as a mask in the subsequent ion implantation step.

[0147] Furthermore, an opening 291 is formed in the resist 290. The opening 291 is formed by photolithography, etching, or the like. The opening 291 is formed in the second region 202 adjacent to the pre-drain electrode portion 110d (first region 201). The size of the opening 291 is smaller than that of the second region 202. A part of the opening 291 may also be formed in the pre-drain electrode portion 110d. Note that the pre-gate electrode portion 110g and the pre-source electrode portion 110s shown in FIG. 9A are the same as those in the first embodiment. The combined region of the first region 201 and the third region 203 generally corresponds to the first region 101 shown in FIGS. 6 and 7. The fourth region 204 generally corresponds to the second region 102 shown in FIGS. 6 and 7.

[0148] Next, ion implantation is performed using resist 290 as a mask. Ions are implanted into the surface layer of the region of p-type semiconductor film 120A exposed through opening 291. The implanted ions are, for example, an n-type dopant such as Si. This makes the ion-implanted region i-type, and as shown in FIG. 9B, an i-type semiconductor layer 220 can be formed. After ion implantation, resist 290 is removed.

[0149] 9C, a resist 292 is formed to pattern the p-type semiconductor film 120A into a predetermined shape. The resist 292 covers the pre-gate electrode portion 110g and the second region 202. The resist 292 is formed so as not to cover any region other than the pre-gate electrode portion 110g and the second region 202.

[0150] Next, as shown in FIG. 9D, the p-type semiconductor film 120A in the area not covered with the resist 292 is removed by etching to expose the upper surface 110a of the semiconductor laminate structure 110. This forms the p-type semiconductor layers 120 and 125. The i-type semiconductor layer 220 is formed so as to be embedded in the p-type semiconductor layer 120. The etching is dry etching, and is performed using, for example, a plasma etching method. The etching may also be performed by wet etching.

[0151] Next, as shown in FIG. 9E, an insulating layer 170 is formed. For example, the insulating layer 170 containing SiN as a main component is formed by a plasma CVD method using silane and ammonia. The insulating layer 170 is formed to cover the entire surface of the p-type semiconductor layers 120 and 125, the i-type semiconductor layer 220, and the upper surface 110a of the semiconductor stacked structure 110. Note that a SiN film formed by a plasma CVD method tends to have lower adhesion when the underlying layer is AlGaN than when the underlying layer is GaN. Therefore, as shown in FIGS. 6 and 7, peeling of the insulating layer 170 can be suppressed by covering the end of the insulating layer 170 (SiN film) with the drain electrode 160.

[0152] Next, as shown in FIG. 9F, a portion of the insulating layer 170 is removed by etching. Specifically, the portions of the insulating layer 170 located in the pre-source electrode portion 110s and the pre-drain electrode portion 110d (first region 201) are removed. The etching is performed by dry etching using, for example, fluorine gas, but wet etching using hydrofluoric acid or hot phosphoric acid may also be used. The remaining portion of the insulating layer 170 is used as a mask for etching in a subsequent process. At this time, by exposing at least a portion of the i-type semiconductor layer 220, it is possible to prevent a thick film portion from being formed on the pre-drain electrode portion 110d side (the positive side of the x-axis) of the p-type semiconductor layer 120 relative to the thin film portion 124.

[0153] Next, as shown in FIG. 9G, etching is performed using the insulating layer 170 as a mask. Specifically, the semiconductor laminated structure 110 located in the planned drain electrode portion 110d (first region 201) and the planned source electrode portion 110s is removed to form recesses 112 and 114. The i-type semiconductor layer 220 and the p-type semiconductor layer 120 located in the third region 203 are also removed. This forms a side surface 220b of the i-type semiconductor layer 220 and a side surface 124b of the thin film portion 124. At this time, a portion of the semiconductor laminated structure 110 located in the third region 203 is also removed. Since the amount of the semiconductor laminated structure 110 removed differs between the first region 201 and the third region 203, a stepped recess 112 is formed.

[0154] The etching is performed using a plasma etching method. Specifically, the etching is dry etching using a chlorine-based gas, a fluorine-based gas, or Ar gas. After the dry etching, wet etching using a sulfuric acid / hydrogen peroxide system may be performed. This allows the removal of dry etching residues.

[0155] Next, as shown in FIG. 9H, a portion of the insulating layer 170 is removed by etching. Specifically, the portion of the insulating layer 170 is removed so as to expose the i-type semiconductor layer 220 and a portion of the thick film portion 122 of the p-type semiconductor layer 120. The etching is performed by dry etching using, for example, fluorine gas, but wet etching using hydrofluoric acid or hot phosphoric acid may also be used. The dry etching forms fine irregularities on the upper surface 122a of the thick film portion 122. This increases the contact area between the upper surface 122a of the thick film portion 122 and the drain electrode 160, thereby improving the hole injection efficiency. Note that after the dry etching, wet etching using a sulfuric acid / hydrogen peroxide solution may be performed. This removes dry etching residue.

[0156] Next, as shown in FIG. 9I, the source electrode 150 and the drain electrode 160 are formed. For example, a 20 nm Ti film and a 200 nm Al film are formed by sputtering or vapor deposition, and then heat treatment is performed to alloy the Ti and Al. The formed metal film is patterned by photolithography and etching to form the source electrode 150 and the drain electrode 160. Note that the patterning may be performed by a lift-off method.

[0157] 9J, an insulating layer 180 is formed. For example, the insulating layer 180 containing SiN as a main component is formed using the same method as that used to form the insulating layer 170.

[0158] 9K, a portion of the insulating layer 180 is removed by etching to form an opening 181 for the gate electrode 140. Specifically, the opening 181 is formed at a position overlapping the p-type semiconductor layer 125 in a plan view, exposing the upper surface of the insulating layer 170. The etching is performed by dry etching using, for example, fluorine gas, but may also be wet etching using hydrofluoric acid or hot phosphoric acid.

[0159] Next, as shown in FIG. 9L, the portion of insulating layer 170 exposed in opening 181 is removed by etching. This exposes the upper surface of p-type semiconductor layer 125. The etching of insulating layer 170 is performed by dry etching using fluorine gas, for example, but wet etching using hydrofluoric acid or hot phosphoric acid may also be used. The etching of insulating layer 170 is performed continuously from the step of forming opening 181 in insulating layer 180.

[0160] Next, the gate electrode 140 is formed so as to be in contact with the exposed upper surface of the p-type semiconductor layer 125. For example, a TiN film is formed by sputtering or the like, and then patterned by photolithography and etching to form the gate electrode 140. Note that the patterning may be performed by a lift-off method.

[0161] Through the above steps, the semiconductor device 200 shown in FIGS. 6 and 7 can be manufactured.

[0162] (Other embodiments) Although the semiconductor device and the manufacturing method thereof according to one or more aspects have been described based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and forms constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0163] For example, the components contained as main components in each semiconductor layer included in the semiconductor device 100 are not limited to the above examples. For example, InGaN may be contained as the main component instead of GaN, and GaN may be contained as the main component instead of AlGaN. Furthermore, each semiconductor layer may contain AlInGaN, InN, AlN, etc. as the main component.

[0164] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to the above-described embodiments within the scope of the claims or their equivalents. [Industrial Applicability]

[0165] The present disclosure can be used, for example, in a power amplifier for high-output or high-frequency applications, a wireless communication base station or terminal device in which the power amplifier is used, or a wireless power supply device that transmits power using microwaves. [Explanation of symbols]

[0166] 100, 100A, 100B, 200 Semiconductor device 101, 201 1st area 102, 202 2nd area 103, 203 Third area 104, 204 4th area 110 Semiconductor stacked structure 110a, 122a, 124a, 130a, 220a top 110d Drain electrode planned portion 110g Gate electrode area 110s Source electrode section 112, 114 recess 112a, 114a bottom 112b, 114b, 120b, 122b, 124b, 130b, 220b side 112c 1st inner surface 112d Second inner surface 112e Upper side 112f Step surface 112g Lower side 120, 125 p-type semiconductor layer 120A p-type semiconductor film 122 Thick film section 122A base 122B Branch 124 Thin Film Section 130, 135 cap layer 130A i-type semiconductor film 140 gate electrode 150 Source Electrode 160 drain electrode 170, 180 insulating layer 181, 291 openings 220 i-type semiconductor layer 290, 292 Resist

Claims

1. a semiconductor laminate structure including a two-dimensional electron gas; a p-type first semiconductor layer provided on the semiconductor laminated structure; a drain electrode in contact with the first semiconductor layer; the first semiconductor layer includes a thick film portion and a thin film portion that is thinner than the thick film portion, a recess is provided in the semiconductor laminated structure in a region adjacent to the thin film portion in a plan view; the drain electrode is in contact with a side surface of the recess and a side surface of the thin film portion. Semiconductor device.

2. The side surface of the recess and the side surface of the thin film portion are continuous. The semiconductor device according to claim 1 .

3. a p-type second semiconductor layer provided apart from the first semiconductor layer; a gate electrode provided above the second semiconductor layer, The thickness of the second semiconductor layer is the same as the thickness of the thick film portion. The semiconductor device according to claim 1 .

4. further comprising an i-type third semiconductor layer provided on the thin film portion; The drain electrode further contacts the upper surface of the thick film portion. The semiconductor device according to any one of claims 1 to 3.

5. an upper surface of the thick film portion is flush with an upper surface of the third semiconductor layer; The semiconductor device according to claim 4 .

6. In a plan view, the third semiconductor layer is provided in plurality and aligned in a gate width direction, the thick film portion includes a base portion extending in the gate width direction and a plurality of branch portions extending from the base portion between adjacent third semiconductor layers; The semiconductor device according to claim 4 .

7. the drain electrode further contacts the top surface of the thin film portion; The semiconductor device according to any one of claims 1 to 3.

8. further comprising an i-type fourth semiconductor layer provided above the thick film portion; The semiconductor device according to claim 7 .

9. further comprising an insulating layer provided above the thick film portion, the drain electrode is provided above the insulating layer. The semiconductor device according to any one of claims 1 to 3.

10. a length of the thin film portion along the gate length direction is longer than a length of the thick film portion along the gate length direction; The semiconductor device according to any one of claims 1 to 3.

11. forming a semiconductor laminate structure containing a two-dimensional electron gas; forming a p-type first semiconductor layer on the semiconductor laminate structure, the p-type first semiconductor layer having a thick film portion and a thin film portion thinner than the thick film portion; forming a recess in a first region of the semiconductor laminate structure adjacent to the thin film portion in a plan view; forming a drain electrode in contact with a side surface of the recess and a side surface of the thin film portion of the first semiconductor layer, A method for manufacturing a semiconductor device.

12. The step of forming the first semiconductor layer includes: a first step of depositing a p-type semiconductor film so as to cover at least the first region and a second region adjacent to the first region on the top surface of the semiconductor laminated structure; a second step of removing the semiconductor film located in the first region; a third step of removing at least a portion of the semiconductor film located only in the third region out of a third region and a fourth region included in the second region, The step of forming the recess is carried out simultaneously with the third step. The method for manufacturing a semiconductor device according to claim 11 .

13. In the third step, a surface layer portion of the semiconductor film located in the third region is removed to form the thin film portion; the thick film portion is the semiconductor film remaining in the fourth region. The method for manufacturing a semiconductor device according to claim 12.

14. The step of forming the first semiconductor layer further includes: a fourth step of forming an i-type semiconductor film so as to cover at least the second region on the upper surface of the semiconductor film after the first step and before the third step; a fifth step of removing the i-type semiconductor film located in the third region, The third step is carried out continuously from the fifth step. The method for manufacturing a semiconductor device according to claim 13.

15. The third step is performed using a plasma etching method. The method for manufacturing a semiconductor device according to claim 13 or 14.

16. The step of forming the first semiconductor layer further includes: a step of, after the first step, implanting ions into a surface layer portion of the semiconductor film located in the third region to make it i-type, thereby leaving a lower layer portion of the third region as the thin film portion. The method for manufacturing a semiconductor device according to claim 12.

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