Manufacturing method of power semiconductor device and power semiconductor device

Abstract

To control a threshold voltage of a semiconductor device.SOLUTION: There is provided a semiconductor device which includes: a plurality of trenches elongating on a front surface side of a semiconductor substrate in a previously determined elongation direction and reaching below a first semiconductor region; conductive sections charged inside of the plurality of trenches; an interlayer insulation film which covers the front surface of the semiconductor substrate with a prescribed pattern; and a first electrode provided above the interlayer insulation film, and contains: a first trench section having a prescribed distance from the surface of the semiconductor substrate to an upper end of the conductive section in a cross section perpendicular to the elongation direction; and a second trench section having a distance from the surface of the semiconductor substrate to the upper end of the conductive section being longer than the prescribed distance. The first trench section and the second trench section include, at upper ends, shoulder sections inclined toward a center side of a mesa region sandwiched between the first trench section and the second trench section, the shoulder sections inclined more than a side wall.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention provides Manufacturing method of power semiconductor device and power semiconductor device Regarding. [Background technology]

[0002] BACKGROUND ART Conventionally, a trench gate structure has been known in semiconductor devices such as IGBTs (see, for example, Patent Document 1). Patent Document 1 Japanese Patent Application Publication No. 08-255902 Summary of the Invention [Problem to be solved by the invention]

[0003] It is preferable that the manufacturing efficiency of the semiconductor device does not deteriorate. [Means for solving the problem]

[0004] In one embodiment of the present invention, The present invention provides a method for manufacturing a power semiconductor device, including the steps of: forming a trench having a shoulder in a front surface of a semiconductor substrate; forming an insulating film in the trench and forming a conductive portion in contact with the insulating film, the conductive portion having an upper end located deeper than the front surface of the semiconductor substrate; injecting N-type impurities from the front surface side of the semiconductor substrate to form a semiconductor region in which the lower end of a portion adjacent to the trench is located deeper than other portions; forming an interlayer insulating film on the front surface side of the semiconductor substrate; and forming an opening that penetrates the interlayer insulating film and reaches the inside of the semiconductor substrate, and providing a plug portion in the opening. In another aspect of the present invention, there is provided a power semiconductor device comprising: a trench having a shoulder provided on a front surface of a semiconductor substrate; a conductive portion provided in contact with an insulating film within the trench and having an upper end deeper than the front surface of the semiconductor substrate; an N-type semiconductor region having an impurity concentration higher than that of a drift region of the semiconductor substrate and having a lower end of a portion adjacent to the trench deeper than other portions; an interlayer insulating film provided in a predetermined pattern on the front surface side of the semiconductor substrate; an opening penetrating the interlayer insulating film and reaching an interior of the semiconductor substrate; an upper surface electrode provided on the upper side of the interlayer insulating film; and a plug portion provided in the opening and connecting the upper surface electrode to the interior of the semiconductor substrate.Another aspect of the present invention provides a method for manufacturing a semiconductor device, the method including the steps of etching a semiconductor substrate to form a first trench and etching the semiconductor substrate to form a second trench having a depth different from that of the first trench; forming a first insulating film on an inner wall of the first trench and forming a second insulating film on an inner wall of the second trench; and forming a first conductive portion inside the first trench and forming a second conductive portion inside the second trench, wherein the first trench and the second trench are arranged in a first direction, and the first conductive portion and the second conductive portion are formed so that, in any cross section parallel to both the first direction and a depth direction of the semiconductor substrate, the distance from a front surface of the semiconductor substrate to an upper end of the first conductive portion is different from the distance from the front surface to an upper end of the second conductive portion. In another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the method including the steps of: etching a semiconductor substrate to form a first trench and etching the semiconductor substrate to form a second trench having a depth different from that of the first trench; forming a first insulating film on an inner wall of the first trench and a second insulating film on an inner wall of the second trench; and forming a first conductive portion inside the first trench and a second conductive portion inside the second trench, wherein the first trench and the second trench are arranged in a first direction, and the first conductive portion and the second conductive portion are formed so that, in a cross section parallel to both the first direction and a depth direction of the semiconductor substrate, a distance from a front surface of the semiconductor substrate to a deepest portion of a surface of the first conductive portion is different from a distance from the front surface to a deepest portion of the surface of the second conductive portion. The semiconductor device according to another aspect of the present invention may include a first semiconductor region of a second conductivity type formed on a front surface side of a semiconductor substrate of a first conductivity type, and a second semiconductor region of the first conductivity type selectively formed in a portion of the front surface side of the first semiconductor region. The semiconductor device may include a plurality of trenches. The trenches may extend in a predetermined extension direction on the front surface side of the semiconductor substrate and reach below the first semiconductor region. The semiconductor device may include a conductive portion. The conductive portion may be filled inside the plurality of trenches. The semiconductor device may include an interlayer insulating film.The interlayer insulating film may cover the front surface of the semiconductor substrate in a predetermined pattern. The semiconductor device may include a first electrode. The first electrode may be connected to the semiconductor substrate via an exposed region exposed from the interlayer insulating film in a mesa region sandwiched between the trenches. The semiconductor device may include a first trench portion in a cross section perpendicular to the extension direction. The first trench portion has a predetermined distance from the surface of the semiconductor substrate to the deepest portion of the surface of the conductive portion. The semiconductor device may include a second trench portion in a cross section perpendicular to the extension direction. The second trench portion may have a distance from the surface of the semiconductor substrate to the deepest portion of the surface of the conductive portion that is longer than the predetermined distance. The first trench portion and the second trench portion may each have a shoulder at an upper end that is inclined toward the exposed region relative to the slope of the trench sidewall.

[0005] The first electrode may include an emitter electrode. The semiconductor device may include a first contact region of a second conductivity type. The first contact region may have a higher impurity concentration than the first semiconductor region. The first contact region may be selectively formed in a portion of the front surface side of the first semiconductor region. The first electrode may include an emitter electrode and a plug portion disposed between the semiconductor substrate and the emitter electrode. The semiconductor device may include a second contact region of the second conductivity type. The second contact region may have a higher impurity concentration than the first semiconductor region. The second contact region may be disposed below the plug portion. A lower end of the plug portion may be located deeper than a lower end of the second semiconductor region. The semiconductor device may include an accumulation region of the first conductivity type. The accumulation region may be disposed below the first semiconductor region. The accumulation region may have a higher impurity concentration than the semiconductor substrate.

[0006] The first semiconductor region may be a base region, and the second semiconductor region may be an emitter region.

[0007] The emitter region may be relatively longer on the side adjacent to the trench. In a cross section perpendicular to the extension direction, the emitter region is disposed in a mesa region sandwiched between the first trench portion and the second trench portion, but the emitter region does not have to be disposed symmetrically on the first trench portion side and the second trench portion side. The emitter region may have different depths on the first trench portion side and the second trench portion side.

[0008] In the first trench portion or the second trench portion, in a cross section perpendicular to the extension direction, the deepest portion of the surface of the conductive portion may be located at the center of the trench. In the first trench portion or the second trench portion, in a cross section perpendicular to the extension direction, the sidewall side of the surface of the conductive portion may be relatively close to the front surface of the semiconductor substrate. The cross section perpendicular to the extension direction may be a cross section passing through the second semiconductor region.

[0009] The conductive portion may be polysilicon. The semiconductor device may include an insulating film. The insulating film may cover an inner wall of the trench. The insulating film may ensure insulation between the semiconductor substrate and the conductive portion. A portion of the conductive portion may be connected to the gate electrode, and at least a portion of the other portion may be connected to the emitter electrode. The shoulder portion may have a larger average slope with respect to the depth direction of the semiconductor substrate than the sidewall. At least a portion of the shoulder portion may include a linear shape.

[0010] The shoulder portion may have a length D1 in the depth direction of the semiconductor substrate that is greater than a width W1 in the direction perpendicular to the extension direction. The width W1 of the shoulder portion may be 1 / 2 or less and 1 / 20 or more of the width of the trench at a position facing the upper end of the conductive portion. The width W1 of the shoulder portion may be 1 / 4 or less of the width of the trench at a position facing the upper end of the conductive portion. The width W1 of the shoulder portion may be 1 / 10 or more of the width of the trench at a position facing the upper end of the conductive portion.

[0011] At least a part of the shoulder may have an angle of 20 degrees or more with respect to the depth direction of the semiconductor substrate.

[0012] The upper ends of the conductive portions of the first trench portion and the second trench portion may be located deeper than the surface of the semiconductor substrate.

[0013] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a diagram showing a part of the surface of a semiconductor device 100 according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along the line AA′ in FIG. [Figure 3] 1A to 1C are diagrams illustrating a part of the manufacturing process of the gate trench portion 40 and the emitter region 12 of the semiconductor device 100. [Figure 4] 10A and 10B are diagrams illustrating the shape of a gate trench portion 40. FIG. [Figure 5] 2A and 2B are diagrams illustrating the shapes of the emitter region 12 and the gate conductive portion 44. FIG. [Figure 6A] 10A and 10B are diagrams showing modified shapes of the shoulder portion 33. FIG. [Figure 6B] 10A and 10B are diagrams showing modified shapes of the shoulder portion 33. FIG. [Figure 7] FIG. 2 is a diagram showing a cross section taken along the line BB′ in FIG. [Figure 8] 1 is a perspective view of a gate trench 41, a gate conductive portion 44, an emitter region 12, and a contact region 15. FIG. [Figure 9A] FIG. 9 is a view showing a cross section taken along the line CC′ in FIG. 8. [Figure 9B] FIG. 9 is a view showing a cross section taken along the line DD' in FIG. [Figure 10] 10A to 10C are diagrams illustrating an example of a manufacturing process for the gate conductive portion 44. [Figure 11] FIG. 2 is a cross-sectional view of a semiconductor device 100 according to a second embodiment. [Figure 12] 10A to 10C are diagrams showing an example of a process for forming a shoulder portion 33. [Figure 13] FIG. 10 is a diagram showing a part of the surface of a semiconductor device 100 according to a third embodiment. [Figure 14]FIG. 14 is a view showing a cross section taken along the line CC' in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0015] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0016] 1 is a diagram showing a portion of the surface of a semiconductor device 100 according to a first embodiment. The semiconductor device 100 of this example includes a plurality of gate trenches 40 extending in a predetermined extension direction on the surface of a semiconductor substrate. The plurality of gate trenches 40 are arranged at predetermined intervals along an arrangement direction perpendicular to the extension direction. The gate trenches 40 function as gates for power semiconductor elements such as IGBTs.

[0017] A P-type base region 14 is formed in the surface of the semiconductor substrate in a region sandwiched between the gate trench portions 40. A P+ type contact region 15 is formed on the surface of the base region 14. An N+ type emitter region 12 is selectively formed in a portion of the surface of the contact region 15. The emitter region 12 is an example of a first region. The contact region 15 is an example of a second region. The base region 14 is an example of a third region. Each region may have a conductivity type opposite to that described in this specification.

[0018] In this example, each of the contact region 15 and the emitter region 12 is formed from one adjacent gate trench portion 40 to the other adjacent gate trench portion 40. The contact region 15 and the emitter region 12 are formed so as to be alternately exposed along the extension direction of the gate trench portions 40 in the region sandwiched between the gate trench portions 40.

[0019] Alternatively, emitter regions 12 may be formed on both sides of each gate trench portion 40 along the extension direction, and contact regions 15 may be formed in regions sandwiched between the emitter regions 12. Note that an interlayer insulating film, an emitter electrode, and the like are formed on the surface of the semiconductor device 100, but are omitted in FIG.

[0020] 2 is a diagram showing the A-A' cross section in Fig. 1. The A-A' cross section is perpendicular to the surface of the semiconductor device 100 and perpendicular to the extension direction of the gate trench portion 40. In this cross section, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 26, an emitter electrode 52, and a collector electrode 24.

[0021] The interlayer insulating film 26 is formed in a predetermined pattern on the surface of the semiconductor substrate 10. The interlayer insulating film 26 covers the openings of the gate trench portions 40 and exposes at least a portion of the mesa region sandwiched between the gate trench portions 40. The interlayer insulating film 26 is, for example, a PSG film or a BPSG film. The emitter electrode 52 is formed on the upper side of the interlayer insulating film 26. The emitter electrode 52 is connected to the surface of the semiconductor substrate 10 that is not covered by the interlayer insulating film 26.

[0022] The collector electrode 24 is formed on the back surface of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a conductive material such as metal. In this specification, the surface of each component, such as a substrate, layer, or region, facing the emitter electrode 52 is referred to as the front surface or top surface, and the surface facing the collector electrode 24 is referred to as the back surface or bottom surface. The direction connecting the emitter electrode 52 and the collector electrode 24 is referred to as the depth direction. The direction from the collector electrode 24 toward the emitter electrode 52 is referred to as the top, and the direction from the emitter electrode 52 toward the collector electrode 24 is referred to as the bottom.

[0023] The semiconductor substrate 10 may be a silicon substrate, or may be a silicon carbide substrate, a nitride semiconductor substrate, etc. A P-type base region 14 is formed on the surface side of the semiconductor substrate 10. An N+ type emitter region 12 is selectively formed in a partial region on the surface side of the base region 14.

[0024] The semiconductor substrate 10 further includes an N-type drift region 18, an N-type buffer region 20, and a P+ type collector region 22. The drift region 18 is formed on the back surface side of the base region 14.

[0025] The buffer region 20 is formed on the back surface side of the drift region 18. The impurity concentration of the buffer region 20 is higher than the impurity concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the back surface side of the base region 14 from reaching the collector region 22. The collector region 22 is formed on the back surface side of the buffer region 20. In addition, a collector electrode 24 is provided on the back surface of the collector region 22.

[0026] One or more gate trench portions 40 are formed on the surface side of the semiconductor substrate 10. Each gate trench portion 40 extends from the surface of the semiconductor substrate 10, penetrating the base region 14, and reaches the drift region 18. In this cross section, the gate trench portion 40 extends from the surface of the semiconductor substrate 10, penetrating the emitter region 12 and the base region 14, and reaches the drift region 18.

[0027] The gate trench portion 40 has a gate trench 41, an insulating film 42, and a gate conductive portion 44 formed on the surface side of the semiconductor substrate 10. The insulating film 42 is formed to cover the inner wall of the gate trench 41. The insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench 41. The gate conductive portion 44 is formed inside the gate trench 41, further inside than the insulating film 42. In other words, the insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0028] An upper end 45 of the gate conductive portion 44 is provided at a position deeper than the surface of the semiconductor substrate 10. In other words, the upper end 45 of the gate conductive portion 44 is recessed into the gate trench 41. The upper end 45 of the gate conductive portion 44 refers to the uppermost end of the gate conductive portion 44.

[0029] An interlayer insulating film 26 is formed in a region inside the gate trench 41 where the gate conductive portion 44 and the insulating film 42 are not provided. This insulates the gate conductive portion 44 from the emitter electrode 52. However, the gate trench portion 40 is provided so as to extend to below the metal gate electrode in the semiconductor device 100. A contact hole is formed in the interlayer insulating film 26 below the gate electrode to electrically connect the gate conductive portion 44 and the gate electrode.

[0030] The gate conductive portion 44 includes at least a region facing the adjacent base region 14. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed in the surface layer of the interface of the base region 14 that contacts the gate trench 41.

[0031] The semiconductor device 100 may be provided with dummy trenches instead of some of the gate trenches 40. The dummy trenches have the same structure as the gate trenches 40. However, the conductive portions inside the dummy trenches are electrically connected to the emitter electrode 52. In this case, contact holes are provided in the interlayer insulating film 26 between the dummy trenches and the emitter electrode 52. By providing the dummy trenches, the carrier injection enhancement effect (IE effect) into the drift region can be improved, thereby reducing the on-voltage.

[0032] In a cross section of the semiconductor substrate 10 in the depth direction, the average slope of the sidewall of the gate trench 41 between the upper end 45 of the gate conductive portion 44 and the surface of the semiconductor substrate 10 is greater than the slope of the sidewall at a position opposite the upper end 45 of the gate conductive portion 44. Unless otherwise specified, the term "slope" in this specification refers to the slope relative to the depth direction of the semiconductor substrate 10 in the cross section. For example, the "slope" of the surface of the semiconductor substrate 10 is approximately 90 degrees, and the "slope" of a line parallel to the depth direction is 0 degrees. The average slope of the sidewall within a predetermined range of the gate trench 41 may be calculated by integrating the slope of the sidewall of the gate trench 41 in the cross section over a predetermined length of the sidewall of the gate trench 41 and dividing the integral value by the predetermined length.

[0033] The gate trench 41 of this example has a shoulder 33 in a region in contact with the surface of the semiconductor substrate 10. The shoulder 33 is formed on the sidewall of the gate trench 41 between the gate conductive portion 44 and the surface of the semiconductor substrate 10 (i.e., above the upper end 45 of the gate conductive portion 44). In this cross section, the average slope of the sidewall of the gate trench 41 at the shoulder 33 is smaller than the slope of the sidewall at a position facing the upper end 45 of the gate conductive portion 44. Note that the slope of the sidewall of the gate trench 41 between the shoulder 33 and the upper end 45 of the gate conductive portion 44 may be approximately equal to the slope of the sidewall of the gate trench 41 at a position facing the upper end 45 of the gate conductive portion 44.

[0034] In this way, by increasing the inclination of the sidewall of the gate trench 41 above the upper end 45 of the gate conductive portion 44, it becomes easier to control the depth of the emitter region 12 in the region that contacts the gate trench 41. By controlling the depth of the emitter region 12, it becomes possible to control the length of the remaining base region 14. The length of the base region 14 that contacts the gate trench 41 corresponds to the channel length. This makes it easier to control the threshold voltage of the semiconductor device 100.

[0035] 3 is a diagram illustrating a portion of the manufacturing process for the gate trench portion 40 and the emitter region 12 of the semiconductor device 100. First, in the gate trench formation step S300, a gate trench 41 is formed in the surface of the semiconductor substrate 10. The gate trench 41 has a shoulder 33 in the region that contacts the surface of the semiconductor substrate 10. For example, after forming a trench by etching the surface of the semiconductor substrate 10 using a first mask having a predetermined opening, the surface of the semiconductor substrate 10 may be wet-etched using a second mask having a larger opening than the first mask to form the gate trench 41 with the shoulder 33. The second mask may be formed by wet-etching the first mask to widen the opening area.

[0036] Next, in gate conductive portion formation step S302, an insulating film 42 and a gate conductive portion 44 are formed on the inner wall of the gate trench 41. The insulating film 42 may be formed by oxidizing the semiconductor substrate 10. The gate conductive portion 44 is formed so that an upper end 45 of the gate conductive portion 44 is located deeper than the surface 11 of the semiconductor substrate 10. In this example, the upper end 45 of the gate conductive portion 44 is located lower than the shoulder portion 33. The gate conductive portion 44 is formed of, for example, polysilicon doped with impurities.

[0037] After forming the gate conductive portion 44, a P-type impurity is implanted and diffused into the surface of the semiconductor substrate 10 to form the base region 14. The P-type impurity is, for example, boron. The diffusion temperature of the base region 14 is, for example, about 1100°C. Note that the gate trench portion 40 may be formed after the base region 14 is formed.

[0038] Next, in the emitter region formation step S304, N-type impurities are implanted and diffused into the semiconductor substrate 10. The N-type impurities are, for example, arsenic. P-type impurities such as boron are implanted and diffused into the contact region 15. The impurities in the emitter region 12 and the contact region 15 may be diffused in the same step. The temperature in this diffusion step may be lower than the diffusion temperature in the base region 14. The temperature in this diffusion step is, for example, 1000°C or lower.

[0039] This forms the emitter region 12. In S304, impurities are implanted not only into the surface of the semiconductor substrate 10 but also into the sidewalls of the gate trench 41 using the gate conductive portion 44 as a mask. By this method, the emitter region 12 is formed so that the portion in contact with the gate trench 41 is the deepest.

[0040] In S304, N-type impurities are diffused in the region adjacent to the gate trench 41 to a depth corresponding to the threshold voltage that the semiconductor device 100 should have. Diffusing the impurities to a deeper position requires heat treatment at a higher temperature or for a longer time. However, heat treatment over a long period of time degrades manufacturing efficiency, so heat treatment at a high temperature is preferable. However, when heat treatment is performed at a high temperature, the length of diffusion of the impurities per unit time increases, making it difficult to control the diffusion depth of the impurities.

[0041] In contrast, in the semiconductor device 100 and manufacturing method of the present example, the gate trench 41 has the shoulder 33, so that it is possible to reduce the length over which the impurities are diffused in the region in contact with the gate trench 41. That is, in the region where the shoulder 33 is provided, the impurities are implanted below the surface 11 of the semiconductor substrate 10. Therefore, when forming the emitter region 12 at a predetermined depth, it is possible to reduce the length over which the impurities must be diffused.

[0042] Therefore, even if the impurities are diffused at a lower temperature, the heat treatment time is not lengthened and the manufacturing efficiency is not deteriorated. Furthermore, since the impurities can be diffused at a low temperature, the depth of the emitter region 12 in the region adjacent to the gate trench 41 can be controlled with high precision.

[0043] Furthermore, since the gate trench 41 has the shoulder portion 33, it is possible to reduce the area of ​​the mesa region sandwiched between the gate trench portions 40. This makes it possible to obtain an electron injection enhancement effect (IE effect).

[0044] In step S304, the impurities may be implanted into the sidewalls of the gate trench 41 from a direction having a predetermined inclination θ1 with respect to the depth direction of the semiconductor substrate 10. This allows the impurities to be implanted efficiently. The inclination θ1 is, for example, 10 degrees or less.

[0045] Furthermore, since the emitter region 12 is formed in a self-aligned manner using the gate conductive portion 44 as a mask, the emitter region 12 can be easily brought into contact with the gate trench portion 40. On the other hand, if the emitter region 12 is formed using a mask that is separate from the gate trench portion 40, manufacturing variations in mask alignment, etc., may result in the emitter region 12 and the gate trench portion 40 not coming into contact, preventing the semiconductor device 100 from operating.

[0046] FIG. 4 is a diagram illustrating the shape of the gate trench portion 40. In this example, the inclination of the sidewall of the gate trench 41 at a position 31 facing the upper end 45 of the gate conductive portion 44 is defined as θ2. The width of a shoulder portion 33 in the radial direction of the opening of the gate trench 41 is defined as W1, and the length in the depth direction is defined as D1. The starting point of the shoulder portion 33 may be the end of the sidewall of the gate trench 41 at the surface 11 of the semiconductor substrate 10. The ending point of the shoulder portion 33 may be a position where, when tracing the sidewall of the gate trench 41 from the position 31 toward the surface 11 of the semiconductor substrate 10, the inclination of the sidewall of the gate trench 41 becomes larger than θ2 by a predetermined value or more. As an example, the predetermined value is 10 degrees. The predetermined value may be 0 degrees, 20 degrees, or 30 degrees.

[0047] The shoulder 33 may have a curved surface that is convex toward the inside of the semiconductor substrate 10. In other words, the inclination of the shoulder 33 increases as the distance from the surface of the semiconductor substrate 10 increases. This shape of the shoulder 33 allows impurities to be implanted more efficiently into a deeper position. This shortens the diffusion length of the impurities required to form the emitter region 12 at a predetermined depth.

[0048] Furthermore, the length D1 of the shoulder portion 33 may be greater than the width W1. This allows the opening area of ​​the gate trench 41 to be reduced for miniaturization, and also allows impurities to be implanted deep into the region adjacent to the gate trench 41. Furthermore, the length D1 may be equal to the width W1, or the length D1 may be smaller than the width W1.

[0049] The width W1 of the shoulder portion 33 may be equal to or less than half, or may be equal to or less than one-quarter, of the width of the gate trench 41 at the position 31. This makes it possible to prevent the area of ​​the gate trench 41 on the surface 11 of the semiconductor substrate 10 from increasing. Furthermore, the width W1 may be equal to or more than one-twentieth, or may be equal to or more than one-tenth, of the width of the gate trench 41 at the position 31. This allows the impurity to be efficiently implanted into a deep position.

[0050] Furthermore, the length D1 of the shoulder 33 may be equal to or less than half the distance R1 between the upper end 45 of the gate conductive portion 44 and the surface 11 of the semiconductor substrate 10. Alternatively, the length D1 may be greater than half the distance R1. Alternatively, the length D1 may be approximately equal to the distance R1. As an example, when the length D1 is 90% or more and 110% or less of the distance R1, the length D1 and the distance R1 are considered to be approximately equal.

[0051] Furthermore, the sidewall of the gate trench 41 has a portion with a slope of 20 degrees or more between the upper end 45 of the gate conductive portion 44 and the surface 11 of the semiconductor substrate 10. For example, the slope θ3 of at least a part of the shoulder portion 33 is 20 degrees or more. In this way, the slope of the sidewall of the gate trench 41 becomes larger above the upper end 45, which allows impurities to be efficiently implanted into a deep position and makes it easier to control the diffusion of impurities into the region adjacent to the gate trench 41.

[0052] 5 is a diagram illustrating the shapes of the emitter region 12 and the gate conductive portion 44. As described above, impurities are also implanted from the inner wall of the gate trench 41, so that the lower end 34 of the emitter region 12 adjacent to the gate trench 41 is located deeper than the other portions. This shape makes it possible to control the length of the base region 14 in the region adjacent to the gate trench 41, and thus the threshold voltage of the semiconductor device 100.

[0053] Furthermore, the length D2 in the depth direction of the portion of the emitter region 12 that is in contact with the gate trench 41 may be greater than the length of other portions of the emitter region 12. For example, the length D3 of the emitter region 12 in the mesa region where the gate trench 41 is not provided is smaller than the length D2.

[0054] Furthermore, of the end face of the gate conductive portion 44 on the surface 11 side of the semiconductor substrate 10, the portion adjacent to the sidewall of the gate trench 41 (upper end 45 in this example) is formed closest to the surface 11 of the semiconductor substrate 10. In this example, of the end face of the gate conductive portion 44 on the surface 11 side of the semiconductor substrate 10, the deepest portion 46 located in the center of the gate trench 41 is formed at a position farthest from the surface 11 of the semiconductor substrate 10.

[0055] As an example, the distance from the surface of the semiconductor substrate 10 to the end face of the gate conductive portion 44 gradually increases from the side wall of the gate trench 41 to the center of the gate trench 41. In other words, as the depth from the surface 11 of the semiconductor substrate 10 increases, the thickness of the gate conductive portion 44 adjacent to the side wall of the gate trench 41 gradually increases. As described above, when impurities are implanted obliquely using the gate conductive portion 44 as a mask, the impurities penetrate the gate conductive portion 44 and are implanted into the semiconductor substrate 10 in areas where the thickness of the gate conductive portion 44 is small. This makes it possible to easily implant and diffuse impurities into a deep position from the surface 11 of the semiconductor substrate 10 in the region adjacent to the gate trench 41.

[0056] 6A is a diagram showing a modified shape of shoulder portion 33. Shoulder portion 33 in this example has a curved surface that is convex toward the surface of semiconductor substrate 10. In other words, the inclination of shoulder portion 33 in this example decreases as the distance from the surface of semiconductor substrate 10 increases. Even with this shape, impurities can be easily diffused to a deep position as viewed from surface 11 of semiconductor substrate 10.

[0057] 6B is a diagram showing a modified shape of the shoulder portion 33. In this example, the shoulder portion 33 has at least a linear shape. The linear shape has an inclination that is greater than the inclination θ2 of the sidewall of the gate trench 41 at a position facing the upper end 45 of the gate conductive portion 44 by a predetermined value or more. The predetermined value may be 10 degrees, 20 degrees, or 30 degrees. Even with such a shape, impurities can be easily diffused deep into the surface 11 of the semiconductor substrate 10.

[0058] Fig. 7 is a view showing the cross section taken along line BB' in Fig. 1. In this cross section, the semiconductor device 100 has a contact region 15 instead of the emitter region 12 in the cross section shown in Fig. 2. The other structures are the same as those in the cross section shown in Fig. 2.

[0059] That is, the gate trench 41 has a shoulder 33 in both the region adjacent to the emitter region 12 and the region adjacent to the contact region 15. The shape of the shoulder 33 in the region adjacent to the emitter region 12 and the shape of the shoulder 33 in the region adjacent to the contact region 15 may be the same.

[0060] With this structure, the depth of the contact region 15 can also be controlled in the same way as the emitter region 12. That is, in the contact region 15 as well, the portion in contact with the gate trench 41 is formed to the deepest position.

[0061] 8 is a perspective view of the gate trench 41, the gate conductive portion 44, the emitter region 12, and the contact region 15. The shoulder portion 33 is formed to extend along the extension direction of the gate trench 41.

[0062] 9A is a view showing a CC' cross section in FIG. 8. This cross section is a cross section along the extension direction of the gate trench 41 in a region where the gate trench 41 is not provided (i.e., the mesa region). As described above, the emitter regions 12 and the contact regions 15 are alternately exposed on the surface 11 of the semiconductor substrate 10 along the extension direction of the gate trench 41. The contact regions 15 are formed to a position deeper than the emitter regions 12.

[0063] 9B is a diagram showing a cross section taken along line DD' in FIG. 8. This cross section is taken along the extension direction of the gate trench 41 in the region where the shoulder 33 is provided. The emitter region 12 in the shoulder 33 is formed to a position deeper than the emitter region 12 in the mesa region shown in FIG. 9A. Furthermore, the contact region 15 in the shoulder 33 is formed to a position deeper than the contact region 15 in the mesa region.

[0064] Furthermore, the depth D6 of the emitter region 12 at the shoulder 33 is greater than the length D3 of the emitter region 12 at the mesa region. The depth D8 of the contact region 15 at the shoulder 33 is greater than the length D5 of the contact region 15 at the mesa region. The difference D7 in length between the emitter region 12 and the contact region 15 at the shoulder 33 is greater than or equal to the difference D4 in length between the emitter region 12 and the contact region 15 at the mesa region.

[0065] 10 is a diagram showing an example of a manufacturing process for a gate conductive portion 44. First, a gate trench 41 having a shoulder portion 33 is formed in the surface 11 of the semiconductor substrate 10. Next, an insulating film 42 is formed on the surface of the gate trench 41 and the semiconductor substrate 10. Next, a conductive material 47 is deposited on the surface of the gate trench 41 and the semiconductor substrate 10. As the conductive material 47 is deposited, the thickness of the conductive material 47 deposited on the sidewall inside the gate trench 41 increases. Furthermore, the conductive material 47 increases in thickness while maintaining a shape that conforms to the shoulder portion 33.

[0066] When the conductive material 47 is filled up to the center of the gate trench 41, the conductive material 47 above the opening of the gate trench 41 has a downwardly convex shape, as shown in the lower part of FIG. 10. Then, the conductive material 47 is etched to a predetermined depth inside the gate trench 41, thereby forming the gate conductive portion 44 as shown in FIG. 5. In this way, since the gate trench 41 has a shoulder, it is easy to form the gate conductive portion 44 whose upper surface is convex downward. This makes it easy to implant impurities into the side surface of the gate trench 41.

[0067] 11 is a diagram showing a cross section of a semiconductor device 100 according to a second embodiment. The semiconductor device 100 of this example has a plurality of gate trenches 40 with different distances from the surface 11 of the semiconductor substrate 10 to the upper ends of the gate conductive portions 44. In other words, the semiconductor device 100 has a plurality of gate trenches 40 with different depths at the upper ends of the gate conductive portions 44. Each gate trench 40 penetrates a base region 14 whose lower end has a uniform depth. Furthermore, the cross section in which each gate trench 40 appears does not have to be a single plane.

[0068] When the depth of the upper end of the gate conductive portion 44 is different, the depth of the emitter region 12 in the region adjacent to the gate trench 41 is also different. Specifically, when the upper end of the gate conductive portion 44 is shallow, the emitter region 12 is also shallow, and when the upper end of the gate conductive portion 44 is deep, the emitter region 12 is also deep.

[0069] In this example, the distance between the upper end of the gate conductive portion 44 in the first gate trench portion 40-1 and the surface 11 of the semiconductor substrate 10 is defined as L1. The distance between the upper end of the gate conductive portion 44 in the second gate trench portion 40-2 and the surface 11 of the semiconductor substrate 10 is defined as L2. Distance L1 is smaller than distance L2.

[0070] As described above, the greater the distance between the upper end of the gate conductive portion 44 and the surface 11 of the semiconductor substrate 10, the deeper the emitter region 12 adjacent to the gate trench 41 and the shorter the channel length. Therefore, the channel length C1 of the first gate trench portion 40-1 is greater than the channel length C2 of the second gate trench portion 40-2. Therefore, the threshold voltage of the first gate trench portion 40-1 is greater than the threshold voltage of the second gate trench portion 40-2.

[0071] In this way, by controlling the depth of the upper end of the gate conductive portion 44, it is possible to control the threshold voltage of each gate trench portion 40. Therefore, it is possible to set an appropriate threshold voltage depending on the application or function of each gate trench portion 40.

[0072] The gate trenches 41 in the first gate trench portion 40-1 and the second gate trench portion 40-2 may have different depths from the surface 11 of the semiconductor substrate 10. Specifically, the gate trench 41 of the gate trench portion 40 for which a higher threshold voltage is desired is formed deeper. Then, gate conductive portions 44 of the same length are formed in each gate trench 41. As a result, the depth of the upper end of each gate conductive portion 44 differs depending on the depth of the gate trench 41. According to this example, the gate conductive portions 44 are formed simultaneously, making the manufacturing process more efficient, while also adjusting the threshold voltage of each gate trench portion 40.

[0073] Alternatively, a plurality of gate trenches 41 with different depths may be formed by etching the surface 11 of the semiconductor substrate 10 using a mask having a plurality of openings with different areas. If the opening area of ​​the mask is large, a deep gate trench 41 can be formed. This makes it possible to simultaneously form gate trenches 41 with different depths, improve the efficiency of the manufacturing process, and adjust the threshold voltage of each gate trench portion 40.

[0074] 12 is a diagram showing an example of a process for forming the shoulder portion 33. As described above, the gate trench 41 is formed by anisotropically etching the surface 11 of the semiconductor substrate 10 using a first mask 48. Next, the first mask 48 is wet-etched to form a second mask 49 with an enlarged mask opening. The opening of the second mask 49 exposes the region of the surface 11 where the shoulder portion 33 is to be formed. Then, the surface 11 of the semiconductor substrate 10 is wet-etched using the second mask 49. This allows the shoulder portion 33 to be formed with a slope that is gentler than the slope of the sidewall of the gate trench 41.

[0075] 13 is a diagram showing a portion of the surface of a semiconductor device 100 according to the third embodiment. The semiconductor device 100 of this example includes a plurality of gate trenches 40 extending in a predetermined extension direction on the surface of a semiconductor substrate. The gate trenches 40 are the same as the gate trenches 40 in any of the embodiments described with reference to FIGS. 1 to 12.

[0076] On the surface of the semiconductor substrate, an N+ type emitter region 12 is formed in a region sandwiched between the gate trench portions 40. The emitter region 12 is formed in a stripe shape in a region adjacent to the gate trench portion 40. In this example, the base region 14 is not exposed in the region sandwiched between the gate trench portions 40 on the surface of the semiconductor substrate.

[0077] In this example, the contact region 15 is formed inside the semiconductor substrate and is not exposed on the surface of the semiconductor substrate. The contact region 15 is formed in the semiconductor substrate in a stripe shape parallel to the gate trench portion 40. A contact opening exposing the contact region 15 is formed in the emitter region 12. A plug connecting the contact region 15 and the emitter electrode 52 is formed inside the contact opening.

[0078] FIG. 14 is a view showing a CC' cross section in FIG. 13. The CC' cross section is perpendicular to the surface of the semiconductor device 100 and perpendicular to the extension direction of the gate trench portions 40. In this example, in the region sandwiched between the two gate trench portions 40, an emitter region 12 is formed near the upper surface of the semiconductor substrate 10, and a base region 14 is formed below the emitter region 12. The semiconductor device 100 of this example also includes a plug portion 28. A contact region 15 is formed adjacent to the bottom of the plug portion 28. The other structures may be the same as those shown in FIG. 2.

[0079] The plug portion 28 is formed between the two gate trench portions 40, penetrating the interlayer insulating film 26 and the emitter region 12. The plug portion 28 may be disposed in the center of the region sandwiched between the two gate trench portions 40. The upper end of the plug portion 28 is connected to the emitter electrode 52, and the lower end is disposed inside the base region 14. The plug portion 28 may be formed of a material containing, for example, tungsten.

[0080] The contact region 15 is formed inside the base region 14. In this example, the contact region 15 is entirely surrounded by the base region 14. The contact region 15 is formed in contact with the lower end of the plug portion 28. This structure reduces the contact resistance between the emitter electrode 52 and the semiconductor region. In particular, as the semiconductor device 100 is miniaturized, the mesa width sandwiched between the gate trench portions 40 becomes smaller, resulting in a smaller contact area between the emitter electrode 52 and the semiconductor region. In contrast, in this example, by providing the plug portion 28, the contact resistance can be kept low even when the semiconductor device 100 is miniaturized.

[0081] The semiconductor device 100 may further include an N+ type accumulation region 16. The accumulation region 16 has a higher impurity concentration than the drift region 18. The accumulation region 16 is formed between the base region 14 and the drift region 18, between the two gate trench portions 40. This configuration enhances the carrier accumulation effect and improves the trade-off between the on-voltage and the turn-off loss. The accumulation region 16 may be applied to the semiconductor device 100 according to the first and second embodiments described with reference to FIGS. 1 to 12.

[0082] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0083] In the claims and the specification, "up" and "down" refer to opposite directions. However, the term "up" is not limited to a direction opposite to the direction of gravity. Also, the term "down" is not limited to a direction in the direction of gravity. [Explanation of symbols]

[0084] 10 semiconductor substrate, 11 surface, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 18 drift region, 20 buffer region, 22 collector region, 24 collector electrode, 26 interlayer insulating film, 28 plug portion, 33 shoulder portion, 34 bottom end, 40 gate trench portion, 41 gate trench, 42 insulating film, 44 gate conductive portion, 45 top end, 46 deepest portion, 47 conductive material, 48 first mask, 49 second mask, 52 emitter electrode, 100 semiconductor device

Claims

1. forming a trench having a shoulder in a front surface of a semiconductor substrate; forming an insulating film in the trench; forming a conductive portion in contact with the insulating film, the conductive portion having an upper end positioned deeper than the front surface of the semiconductor substrate; Injecting N-type impurities into the front surface of the semiconductor substrate to form a semiconductor region whose lower end is located adjacent to the trench and is deeper than other portions; forming an interlayer insulating film on the front surface side of the semiconductor substrate; forming an opening that penetrates the interlayer insulating film and reaches the inside of the semiconductor substrate at a position away from the shoulder portion; a plug portion is provided in the opening; The lower surface of the semiconductor region has an upwardly convex shape in at least a portion between the trench and the plug portion. A method for manufacturing a power semiconductor device.

2. Further, a P-type contact region is formed in contact with the bottom surface of the plug portion and spaced apart from the semiconductor region. The method for manufacturing a power semiconductor device according to claim 1 .

3. The opening is formed in the other portion. The method for manufacturing a power semiconductor device according to claim 1 or 2.

4. The portion of the semiconductor region adjacent to the trench is formed to a position deeper than the upper end of the conductive portion. The method for manufacturing a power semiconductor device according to claim 1 .

5. At least a portion of the plug portion is formed of a material containing tungsten. The method for manufacturing a power semiconductor device according to any one of claims 1 to 4.

6. The sidewall of the plug portion is in contact with the semiconductor region. The method for manufacturing a power semiconductor device according to any one of claims 1 to 5.

7. The semiconductor region is an emitter region. The method for manufacturing a power semiconductor device according to any one of claims 1 to 6.

8. The semiconductor region is formed in a stripe shape parallel to the trench. The method for manufacturing a power semiconductor device according to any one of claims 1 to 7.

9. The lower end of the plug portion contacts a P-type contact region formed in a stripe shape parallel to the trench. The method for manufacturing a power semiconductor device according to claim 1 .

10. The impurity concentration of the contact region is higher than that of a base region in which a channel is formed in a surface layer of the interface in contact with the trench. The method for manufacturing a power semiconductor device according to claim 2 or 9.

11. The inclination of the sidewall of the trench with respect to the depth direction of the semiconductor substrate is less than 10 degrees, The inclination of at least a part of the shoulder portion is 20 degrees or more with respect to the depth direction of the semiconductor substrate. The method for manufacturing a power semiconductor device according to any one of claims 1 to 10.

12. The length of the shoulder portion in the depth direction is 90% or more and 110% or less of the length from the front surface of the semiconductor substrate to the upper end of the conductive portion. The method for manufacturing a power semiconductor device according to any one of claims 1 to 11.

13. The semiconductor substrate is any one of a silicon substrate, a silicon carbide substrate, and a nitride semiconductor substrate. The method for manufacturing a power semiconductor device according to any one of claims 1 to 12.

14. a trench having a shoulder formed in a front surface of the semiconductor substrate; a conductive portion provided in contact with the insulating film in the trench and having an upper end deeper than the front surface of the semiconductor substrate; an N-type semiconductor region having a higher impurity concentration than the drift region of the semiconductor substrate, the lower end of the portion adjacent to the trench being located deeper than other portions; an interlayer insulating film provided in a predetermined pattern on the front surface side of the semiconductor substrate; an opening that penetrates the interlayer insulating film and reaches the inside of the semiconductor substrate; an upper electrode provided on the interlayer insulating film; a plug portion provided in the opening and connecting the upper surface electrode to the inside of the semiconductor substrate; Equipped with the opening is spaced apart from the shoulder; The lower surface of the N-type semiconductor region has an upwardly convex shape in at least a portion between the trench and the plug portion. Power semiconductor devices.

15. The semiconductor device further includes a P-type contact region provided in contact with a bottom surface of the plug portion and spaced apart from the N-type semiconductor region. The power semiconductor device according to claim 14.

16. The plug portion is formed of a material containing tungsten. The power semiconductor device according to claim 14 or 15.

17. a base region in which a channel is formed in a surface layer of an interface in contact with the trench; The impurity concentration of the contact region is higher than that of the base region. The power semiconductor device according to claim 15.

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