High-performance semiconductor devices

A reverse conducting IGBT with optimized pilot function-equipped standard cells and wide-gap semiconductors suppresses snapback and on-voltage degradation, addressing circuit disturbances and reliability issues, achieving high-performance and compact design.

JP7744035B2Active Publication Date: 2025-09-25菅原良孝
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Patent Information

Application Number
JP2023168710
Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
Filing Date
2023-09-28
Publication Date
2025-09-25
Estimated Expiration
2041-04-01

AI Technical Summary

Technical Problem

Existing silicon (Si) reverse-conducting IGBTs suffer from snapback phenomena causing abrupt voltage and current changes, leading to circuit disturbances, malfunctions, and potential destruction, especially at higher breakdown voltages, and SiC IGBTs face on-voltage degradation issues.

Method used

A reverse conducting IGBT structure composed solely of pilot function-equipped standard cells with optimized collector width and buffer layer configurations, using wide-gap semiconductors like SiC, suppresses snapback and on-voltage degradation by integrating unipolar and bipolar transistors in parallel, and applying the TEDEREC and Mach-TEDREC methods to manage current and voltage stresses.

Benefits of technology

The solution significantly reduces chip size, suppresses snapback and on-voltage degradation, enhances reliability, and minimizes switching losses, making it suitable for high-voltage applications.

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Abstract

To provide a high-performance reverse conduction semiconductor device having a smaller area and higher reliability, which can suppress the first-order snapback phenomenon and higher-order snapback phenomenon at turn-on to an acceptable range without impairing the performance of reverse conduction IGBT semiconductor devices, and also suppresses deterioration of the semiconductor body due to the snapback phenomenon.SOLUTION: A reverse conduction IGBT 100 is formed using a wide gap semiconductor, the active area is composed of a standard cell equipped with a pilot function, and high reliability is achieved by suppressing not only the first-order snapback phenomenon but also the higher-order snapback phenomenon. In addition, a buffer layer 104 of the standard cell, which is one of the main factors of the snapback phenomenon, is made into a double buffer layer, the reverse conduction IGBT chip is significantly downsized and the on-resistance is lowered, and a plurality of MOSFET surface areas within the standard cell is created to lower the on-resistance and reduce the chip area.SELECTED DRAWING: Figure 1
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Citation Information

Patent Citations

  • High-performance semiconductor device, and design method and operation method therefor

    JP2018098498A

  • Semiconductor device

    JP2019068096A

  • High performance semiconductor device

    JP2022158357A