Light-emitting diodes and light-emitting devices

Abstract

A light emitting diode according to one embodiment includes an n-type nitride semiconductor layer; an active layer located on the n-type nitride semiconductor layer; and a p-type nitride semiconductor layer located on the active layer, wherein the active layer has a single multiple quantum well structure in which a plurality of barrier layers and a plurality of well layers are stacked, and the active layer emits white light.

Description

[Technical Field]

[0001] The present disclosure relates to light emitting diodes, and more particularly to light emitting diodes that emit multi-band light at a single chip level. [Background technology]

[0002] Nitride semiconductors are used as light sources for display devices, traffic lights, lighting, and optical communication devices, and are mainly used in light emitting diodes (LEDs) that emit blue or green light and laser diodes. Nitride semiconductors can also be used in heterojunction bipolar transistors (HBTs) and high electron mobility transistors (HEMTs).

[0003] Generally, nitride semiconductor light-emitting diodes have a heterojunction structure with a quantum well structure between the N-contact layer and the P-contact layer. The light emitted by the diode is determined by the composition of the well layer within the quantum well structure. To increase internal quantum efficiency and reduce loss due to optical absorption, light-emitting diodes are designed to emit monochromatic light, i.e., light with a single peak in the spectrum.

[0004] Mixed-color light emitted from lighting, for example, white light, cannot be realized as a single-peak monochromatic light. Therefore, techniques for realizing white light generally involve using multiple light emitting diodes that emit different monochromatic lights together, or using phosphors that convert the wavelength of light emitted from the light emitting diodes.

[0005] The use of phosphors entails problems such as the cost of the phosphor itself and a decrease in efficiency known as the Stokes shift. Furthermore, typical white LEDs using yellow phosphors in Li-Fi, which transmits information using visible light with a wide frequency band, generally have slow data transmission speeds. Typical white LEDs using yellow phosphors are not suitable for visible light communication (VLC) due to their slow frequency response. Furthermore, a process of coating the phosphor onto the light-emitting diode is required, and the phosphor is prone to yellowing of the carrier that supports the phosphor.

[0006] On the other hand, using a mixture of a plurality of light emitting diodes complicates the process, and it is troublesome to prepare light emitting diodes made of different materials. Summary of the Invention [Problem to be solved by the invention]

[0007] Light having a multi-band spectrum can be realized using a single-chip light emitting diode, and the use of multiple light emitting diodes or phosphors can be avoided.

[0008] Previous attempts to realize multi-band spectrum light by varying the composition of each well layer in a quantum well structure have not yielded satisfactory results. In particular, electron-hole recombination occurs mainly in specific well layers, making it difficult to generate multi-band light.

[0009] The problem to be solved by the present disclosure is to provide a light emitting diode having a new structure capable of realizing multi-band spectrum light at a single chip level.

[0010] Another problem that the present disclosure aims to solve is to provide an LED light source suitable for visible light communication (VLC) such as Li-Fi. [Means for solving the problem]

[0011] In one or more embodiments according to the teachings of the present disclosure, a light emitting diode includes an n-type nitride semiconductor layer, an active layer disposed on the n-type nitride semiconductor layer, and a p-type nitride semiconductor layer disposed on the active layer, wherein the active layer has a single multiple quantum well structure in which multiple barrier layers and multiple well layers are stacked, and the active layer emits white light.

[0012] The active layer can emit light of two peak wavelengths as the driving current increases.

[0013] The light emitted from the active layer can change from yellow light to white light as the driving current increases.

[0014] The light emitting diode may further include a V-pit generation layer disposed between the n-type nitride semiconductor layer and the active layer, and a portion of the active layer may be formed within the V-pit of the V-pit generation layer.

[0015] The V-pit generating layer may have a thickness of more than 450 nm, and each V-pit formed in the V-pit generating layer may include a V-pit with an entrance width of more than 230 nm.

[0016] The light-emitting diode may further include a p-type AlGaN layer interposed between the active layer and the p-type nitride semiconductor layer, and an Al composition ratio x in the p-type AlGaN layer may be greater than 0 and less than 0.3.

[0017] The p-type AlGaN layer may have a thickness of less than 100 nm.

[0018] The active layer may have a multiple quantum well structure having a plurality of well layers and a plurality of barrier layers, and may further include a capping layer covering the well layer between the well layer and the barrier layer, and the capping layer may contain Al.

[0019] In one embodiment, the light emitting diode may have a flip-chip structure.

[0020] In one embodiment, the light emitting diode may have a plurality of light emitting cells.

[0021] The light emitting diode may include light emitting cells having different light emitting areas.

[0022] Furthermore, the light emitting diode may include light emitting cells connected in series.

[0023] In one or more embodiments according to the teachings of the present disclosure, a light emitting device includes a light emitting diode and a color filter. The light emitting diode includes an n-type nitride semiconductor layer, an active layer disposed on the n-type nitride semiconductor layer, and a p-type nitride semiconductor layer disposed on the active layer. The active layer has a single multiple quantum well structure in which multiple barrier layers and multiple well layers are stacked, and the active layer emits light of at least two peak wavelengths.

[0024] The color filters may be bandpass filters, long wavelength pass filters, or short wavelength pass filters. [Brief explanation of the drawings]

[0025] [Figure 1] 1 is a schematic cross-sectional view illustrating a light-emitting diode according to an embodiment of the present disclosure.

[0026] [Figure 2A] 2 is a schematic partial cross-sectional view showing an enlarged portion of FIG. 1 for explaining a light-emitting diode.

[0027] [Figure 2B] 3 is a schematic partial cross-sectional view showing an enlarged portion of FIG. 2 for explaining a light-emitting diode.

[0028] [Figure 3] FIG. 2 is a schematic perspective view showing an enlarged V-pit generation layer for explaining a light emitting diode.

[0029] [Figure 4A] 1 is a schematic plan view showing a flip-chip type light-emitting diode according to an embodiment of the present disclosure.

[0030] [Figure 4B] FIG. 4B is a schematic cross-sectional view taken along line AA in FIG. 4A.

[0031] [Figure 5A] 10 is a schematic plan view illustrating a light emitting diode having a plurality of light emitting cells according to another embodiment; FIG.

[0032] [Figure 5B] FIG. 5B is a schematic cross-sectional view taken along line BB in FIG. 5A.

[0033] [Figure 5C] FIG. 5B is a schematic cross-sectional view taken along line CC in FIG. 5A.

[0034] [Figure 6] 10 is a schematic plan view illustrating a light emitting diode having a plurality of light emitting cells according to another embodiment; FIG.

[0035] [Figure 7A] 10 is a graph showing the spectrum of a blue light-emitting diode according to a comparative example depending on the current.

[0036] [Figure 7B] 10 is a graph showing a spectrum depending on a current of a light emitting diode according to an example.

[0037] [Figure 8A] 10 is a graph showing color coordinates of a white light emitting diode package in a comparative example.

[0038] [Figure 8B]1 is a graph illustrating color coordinates according to current of a white light emitting diode package according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0039] Hereinafter, each embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. The embodiments described below are provided as examples to fully convey the concept of the present disclosure to those skilled in the art. Therefore, the present disclosure is not limited to the embodiments described below and may be embodied in other forms. In the drawings, the width, length, thickness, etc. of components may be exaggerated for convenience. Furthermore, when a component is described as being "on top of" or "on" another component, this includes not only the case where each component is "directly above" or "directly on" the other component, but also the case where another component is interposed between the other component and the other component. The same reference numerals refer to the same components throughout the specification.

[0040] FIG. 1 is a schematic cross-sectional view illustrating a light-emitting diode according to one embodiment of the present disclosure, FIG. 2A is a schematic partial cross-sectional view illustrating an enlarged portion of FIG. 1 to illustrate the light-emitting diode, FIG. 2B is a schematic partial cross-sectional view illustrating an enlarged portion of FIG. 2A to illustrate the light-emitting diode, and FIG. 3 is a schematic perspective view illustrating an enlarged V-pit generation layer to illustrate the light-emitting diode.

[0041] First, referring to FIG. 1 , a light-emitting diode may include a substrate 21, a nucleation layer 23, a high-temperature buffer layer 25, an n-type nitride semiconductor layer 27, a V-pit generation layer 29, an active layer 30, a p-type AlGaN layer 31, and a p-type nitride semiconductor layer 33.

[0042] The substrate 21 is for growing a gallium nitride-based semiconductor layer and may be a sapphire substrate, a SiC substrate, a GaN substrate, a Si substrate, a spinel substrate, or the like. The substrate 21 may have protrusions as shown in FIG. 1, and may be, for example, a patterned sapphire substrate. However, the present disclosure is not limited thereto, and may also be a substrate having a flat upper surface, for example, a sapphire substrate.

[0043] Nucleation layer 23 may be formed on substrate 21 at a low temperature of 400°C to 600°C using (Al,Ga)N, and may be formed of AlGaN or GaN, for example. The composition of nucleation layer 23 may vary depending on substrate 21. For example, if substrate 21 is a patterned sapphire substrate, nucleation layer 23 may be formed of AlGaN, and if substrate 21 is a sapphire substrate with a flat top surface, nucleation layer 23 may be formed of GaN. Nucleation layer 23 may be formed to a thickness of, for example, about 25 nm.

[0044] The high-temperature buffer layer 25 may be grown at a relatively high temperature to mitigate the generation of defects such as dislocations between the substrate 21 and the n-type nitride semiconductor layer 27. The high-temperature buffer layer 25 may be formed of undoped GaN or GaN doped with n-type impurities. During the formation of the high-temperature buffer layer 25, a feedthrough potential is generated due to the lattice mismatch between the substrate 21 and the high-temperature buffer layer 25. The high-temperature buffer layer 25 may be formed to a thickness of, for example, about 4.2 μm.

[0045] The n-type nitride semiconductor layer 27 is a nitride-based semiconductor layer doped with n-type impurities, and may be formed of, for example, a GaN layer doped with Si. The Si doping concentration in the n-type nitride semiconductor layer 27 is 5E17 / cm 2 ~5E19 / cm 2The n-type nitride semiconductor layer 27 may be grown by supplying a metal source gas into a chamber using a metal-organic chemical vapor deposition (MOCVD) technique at 1000°C to 1200°C (e.g., 1050°C to 1100°C) under a growth pressure of 150 Torr to 200 Torr. In this case, the n-type nitride semiconductor layer 27 may be formed continuously on the high-temperature buffer layer 25, and the feedthrough potential formed in the high-temperature buffer layer 25 may be transferred to the n-type nitride semiconductor layer 27. The n-type nitride semiconductor layer 27 may be formed to be relatively thinner than the high-temperature buffer layer 25, for example, to a thickness of about 2.5 μm.

[0046] The V-pit generation layer 29 is located on the n-type nitride semiconductor layer 27. In one embodiment of the present disclosure, the V-pit generation layer 29 may be formed of, for example, a GaN layer. The V-pit generation layer 29 may be grown at a temperature relatively lower than the growth temperature of the n-type nitride semiconductor layer 27, for example, about 900° C., so that each V-pit is formed in the V-pit generation layer 29.

[0047] By growing the V-pit generation layer 29 at a temperature relatively lower than that of the n-type nitride semiconductor layer 27, the crystal quality is artificially reduced and three-dimensional growth is promoted, thereby generating the V-pits 29v.

[0048] 3, each V-pit 29v may have a hexagonal pyramidal shape when the growth plane of the nitride semiconductor layer is the C-plane. Each V-pit 29v may be formed at the upper end of the feedthrough potential.

[0049] The V-pit generation layer 29 may be formed to a thickness thinner than the n-type nitride semiconductor layer 27, for example, about 450 nm to 600 nm. The size of each V-pit 29v formed in the V-pit generation layer 29 may be adjusted by adjusting the growth conditions and growth time of the V-pit generation layer 29. In one embodiment, the maximum width of the entrance of the V-pit 29v formed in the V-pit generation layer 29 may generally exceed about 230 nm.

[0050] The thickness of the V-pit generation layer 29 particularly affects the size of the V-pits 29v. Furthermore, the size of the V-pits 29v is considered to affect the generation of light with a multi-band spectrum.

[0051] In this embodiment, the V-pit generation layer 29 is described as a single layer, but is not limited thereto, and may be a multi-layer V-pit generation layer 29. For example, the V-pit generation layer 29 may include at least two layers of GaN, AlGaN, InGaN, and AlGaInN layers.

[0052] The active layer 30 is located on the V-pit generation layer 29. The active layer 30 emits light by recombination of electrons and holes. The active layer 30 may have a single quantum well structure or a multiple quantum well (MQW) structure in which barrier layers 30b and well layers 30w are alternately stacked.

[0053] The active layer 30 may be in contact with the V-pit generation layer 29, but the present disclosure is not limited thereto. The active layer 30 may be formed along the V-pit 29v. The thickness of the active layer 30 formed within the V-pit 29v is smaller than the thickness of the active layer 30 formed on the flat surface of the V-pit generation layer 29. The thickness of the active layer 30 within the V-pit 29v may vary depending on the depth of the V-pit 29v. The thickness of the active layer 30 at a depth approximately halfway through the V-pit 29v may be approximately one-third or less of the thickness of the active layer 30 formed on the flat surface of the V-pit generation layer 29. In particular, the thickness of the well layer 30w at a depth approximately halfway through the V-pit 29v may be approximately one-third or less of the thickness of the well layer 30w formed on the flat surface of the V-pit generation layer 29.

[0054] On the other hand, the well layer 30w is In x Al y Ga 1-x-yIt may be formed at N(0 < x < 1, 0 ≤ y < 1). The composition ratios of In, Al, and Ga can be selected according to the required light. In particular, the well layer 30w (hereinafter referred to as the first well layer portion) formed on the flat surface of the V-pit generation layer 29 has a composition that emits light in the long wavelength side spectrum of the multi-band. On the other hand, the well layer 30w (hereinafter referred to as the second well layer portion) formed in the V-pit 29v has a composition that emits light in the short wavelength side spectrum of the multi-band. For example, the In composition ratio in the first well layer portion is higher than the In composition ratio in the second well layer portion. The first well layer portion may be formed of InGaN so as to emit light in the yellow series, and the second well layer portion may be formed of InGaN so as to emit light in the green and / or blue series.

[0055] The second well layer portion may be formed with the same composition on each surface within the V-pit 29v, but is not limited thereto, and may be formed with different compositions on each surface. Thereby, the light-emitting diode of the present disclosure can embody light having at least two bands at the single chip level using the first well layer portion and the second well layer portion.

[0056] The barrier layer 30b may be formed of a nitride semiconductor layer such as GaN, InGaN, AlGaN, or AlInGaN having a wider bandgap than the well layer 30w. For example, when the first well layer portion is formed of InGaN so as to emit light in the yellow series, the barrier layer 30b may be formed of InGaN having a lower In content than the well layer 30w.

[0057] 2B, a capping layer 30c may be interposed between the well layer 30w and the barrier layer 30b. The capping layer 30c may be formed before the deposition of the barrier layer 30b to prevent indium (In) in the well layer 30w from dissociating during the deposition of the barrier layer 30b. The capping layer 30c may contain Al and may be formed of, for example, AlGaN or AlInGaN. The Al composition of the first capping layer portion, i.e., the capping layer portion disposed on the flat surface of the V-pit generation layer 29, and the second capping layer portion, i.e., the capping layer portion formed within the V-pit 29v, may be different from each other. The Al content in the first capping layer portion is higher than the Al content in the second capping layer portion. For example, the Al composition in the first capping layer portion may be 10 atomic % or more, or even 12 atomic % or more, relative to the overall composition in the capping layer, and the Al composition in the second capping layer portion may be about 5 atomic % or more, relative to the overall composition in the capping layer.

[0058] Each of the remaining capping layers 30c, except for the last capping layer 30c closest to the P-type nitride semiconductor layer 33, may be formed to a thickness generally similar to or smaller than that of the adjacent well layer 30w. The last capping layer 30c may be formed to be thicker than the adjacent well layer 30w.

[0059] The p-type AlGaN layer 31 is located on the active layer 30. The p-type AlGaN layer 31 may also be formed in the V-pit 29v. The Al composition ratio in the p-type AlGaN layer 31 is relatively low compared to the Al composition ratio used in the electron blocking layer. The Al composition ratio in the p-type AlGaN layer 31 may also be lower than the Al composition ratio in the capping layer 30c. For example, the p-type AlGaN layer 31 may be formed by the general formula Al x Ga 1-x N, where x may be greater than 0 and less than 0.3. Meanwhile, in one embodiment, the thickness of p-type AlGaN layer 31 may be less than about 100 nm, and in at least one variation, may be about 70 nm.

[0060] The p-type nitride semiconductor layer 33 may be formed of a semiconductor layer doped with p-type impurities such as Mg, for example, GaN. The p-type nitride semiconductor layer 33 may be a single layer or a multi-layer, and may include a p-type contact layer. As shown in FIG. 1, the p-type nitride semiconductor layer 33 may have a concave groove in the V-pit 29v. Since the V-pit 29v is not completely filled with the p-type nitride semiconductor layer 33, loss of light generated in the well layer 30w in the V-pit 29v can be prevented.

[0061] The light emitting diode can be fabricated in various types available in the art, such as a horizontal type and a flip chip type.

[0062] FIG. 4A is a schematic plan view of a flip-chip type light-emitting diode 100 according to an embodiment of the present disclosure, and FIG. 4B is a schematic cross-sectional view taken along line AA in FIG. 4A.

[0063] 4A and 4B, the flip-chip type LED includes a substrate 121, a first conductive type semiconductor layer 127, an active layer 130, a second conductive type semiconductor layer 133, a conductive oxide layer 135, a dielectric layer 137, a metal reflective layer 139, a lower insulating layer 141, a first pad metal layer 143a (FIG. 4A), a second pad metal layer 143b, and an upper insulating layer 145. The LED may further include a first bump pad 147a and a second bump pad 147b.

[0064] The substrate 121 is the same as the substrate 21 described above, and a detailed description thereof will be omitted to avoid redundancy. The substrate 121 may have a rectangular or square shape as shown in Fig. 4A, but is not necessarily limited thereto. The size of the substrate 121 is not particularly limited and may be selected from a variety of sizes.

[0065] The first conductive type semiconductor layer 127 is disposed on the substrate 121. The first conductive type semiconductor layer 127 is the same as the n-type nitride semiconductor layer 27 described above, and a detailed description thereof will be omitted to avoid duplication. As shown in FIG. 1, a nucleation layer 23 and a high-temperature buffer layer 25 may be interposed between the substrate 121 and the first conductive type semiconductor layer 127.

[0066] In some embodiments, the edge of the first conductive type semiconductor layer 127 is aligned with the edge of the substrate 121. However, the present invention is not limited thereto, and in other embodiments, the first conductive type semiconductor layer 127 may be located inside a region surrounded by the edge of the substrate 121. In this case, a portion of the top surface of the substrate 121 may be exposed along the periphery of the first conductive type semiconductor layer 127.

[0067] A mesa M is disposed on the first conductive type semiconductor layer 127. The mesa M can be located only inside the region surrounded by the first conductive type semiconductor layer 127, and therefore, each region near the edge of the first conductive type semiconductor layer 127 is not covered by the mesa M and is exposed to the outside.

[0068] The mesa M includes an active layer 130 and a second conductive type semiconductor layer 133. The active layer 130 is interposed between the first conductive type semiconductor layer 127 and the second conductive type semiconductor layer 133. Although not shown, a V-pit generation layer is interposed between the first conductive type semiconductor layer 127 and the active layer 130. The V-pit generation layer may be located only within the lower region of the mesa M, but is not limited thereto and may also be located over the entire upper surface of the first conductive type semiconductor layer 127. The V-pit generation layer is substantially similar to the V-pit generation layer 29 already described with reference to FIG. 1, and therefore a detailed description thereof will be omitted to avoid redundancy.

[0069] 1 to 3, the active layer 130 is similar to the active layer 30 described with reference to Figures 1 to 3, and therefore a detailed description thereof will be omitted to avoid redundancy. The active layer 130 emits light having multiple peak wavelengths as the current density increases.

[0070] Meanwhile, the second conductive type semiconductor layer 133 is the same as the p-type nitride semiconductor layer 33 described with reference to Fig. 1, and therefore a detailed description thereof will be omitted to avoid redundancy. Also, although not shown in Fig. 4B, a p-type AlGaN layer 31 is disposed between the second conductive type semiconductor layer 133 and the active layer 130, as described with reference to Fig. 1.

[0071] In some embodiments, the concentration of p-type impurities in the second conductivity type semiconductor layer 133 is 8×10 -18 ~4×10 -21 / cm 3 In another embodiment, the concentration of the p-type impurity in the second conductive type semiconductor layer 133 does not have a constant value, but may have a concentration profile that varies with thickness within the range. In particular, the surface of the second conductive type semiconductor layer 133 may have a higher impurity concentration.

[0072] As shown in FIG. 4A , the mesa M may have an indentation 140 extending therethrough, which may expose an upper surface of the first conductive type semiconductor layer 127. The indentation 140 may extend from one edge of the mesa M to the opposite edge. The length of the indentation 140 is not particularly limited and may be half or longer than the length of the mesa M. Although FIG. 4A shows two indentations 140, the number of indentations 140 may be one, three, or more. As the number of indentations 140 increases, the number of internal contacts 143a2 of the first pad metal layer 143a (described later) increases, improving current spreading performance.

[0073] Meanwhile, as shown in FIG. 4A, the indentation 140 has a rounded shape with a wider width at the end. By shaping the end of the indentation 140 in this manner, the lower insulating layer 141 can be patterned into a similar shape. In particular, if the lower insulating layer 141 includes a distributed Bragg reflector, the lower insulating layer 141 having a wider width at the end as shown in FIG. 4A can prevent excessive double steps from being formed on the sidewalls of the distributed Bragg reflector. Furthermore, the increased slope angle of the sidewalls can prevent cracks from occurring in the first pad metal layer 143a. Therefore, by configuring the shape of the end of the indentation 140 and the shape of the end of the first opening 141a2 of the lower insulating layer 141 as in this embodiment, the edges of the lower insulating layer 141 can be formed to have a gentle slope, thereby improving the yield of light-emitting diodes.

[0074] In this embodiment, the mesa M is illustrated and described as having a recess 140 formed therein, but instead of the recess 140, the mesa M may have at least one via hole penetrating the second conductive type semiconductor layer 133 and the active layer 130.

[0075] Meanwhile, the conductive oxide layer 135 is disposed on the upper portion of the mesa M and is in contact with the second conductive type semiconductor layer 133. The conductive oxide layer 135 may be disposed in the upper region of the mesa M over part or almost the entire region of the mesa M. For example, the conductive oxide layer 135 may cover 80% or more, or even 90% or more of the upper region of the mesa M.

[0076] The conductive oxide layer 135 is formed of an oxide layer that transmits light generated in the active layer 130. The conductive oxide layer 135 may be formed of, for example, indium tin oxide (ITO) or ZnO. The conductive oxide layer 135 is formed to a thickness sufficient for ohmic contact with the second conductive type semiconductor layer 133, for example, within a thickness range of 3 nm to 50 nm. More specifically, the thickness of the conductive oxide layer 135 may be within a thickness range of 6 nm to 30 nm. If the conductive oxide layer 135 is too thin, sufficient ohmic characteristics may not be achieved, resulting in an increase in forward voltage. Furthermore, if the conductive oxide layer 135 is too thick, loss due to light absorption occurs, reducing luminous efficiency.

[0077] Meanwhile, the dielectric layer 137 may cover the conductive oxide layer 135 and further cover the side surfaces of the second conductive type semiconductor layer 133, the active layer 130, and the first conductive type semiconductor layer 127. The edge of the dielectric layer 137 may be covered with the lower insulating layer 141. Therefore, the edge of the dielectric layer 137 is located farther from the edge of the substrate 121 than the edge of the lower insulating layer 141, as shown in FIG. 4B . However, the present invention is not limited thereto, and a portion of the dielectric layer 137 may be exposed to the outside of the lower insulating layer 141.

[0078] 4A, the dielectric layer 137 has openings 137a exposing the conductive oxide layer 135. A plurality of openings 137a may be disposed on the conductive oxide layer 135. Each opening 137a is used as a connecting passage to allow the metal reflective layer 139 to connect to the conductive oxide layer 135. The dielectric layer 137 also exposes the first conductive type semiconductor layer 127 around the mesa M and within the indentation 140.

[0079] The dielectric layer 137 is formed of an insulating material having a refractive index lower than that of the second conductive type semiconductor layer 133 and the conductive oxide layer 135. The dielectric layer 137 may be formed of, for example, SiO2.

[0080] The thickness of the dielectric layer 137 affects the forward voltage and light output of the light-emitting diode. The thickness of the dielectric layer 137 may be in the range of 200 nm to 1000 nm, specifically, in the range of 300 nm to 800 nm. A thickness of less than 200 nm is undesirable because it results in a high forward voltage and low light output. On the other hand, a thickness of more than 400 nm tends to saturate the light output and increase the forward voltage again. Therefore, it is preferable that the thickness of the dielectric layer 137 not exceed 1000 nm, and more preferably, the thickness may be 800 nm or less. Furthermore, the thickness of the dielectric layer 137 may be four or more times but 13 or less times the thickness of the second conductive type semiconductor layer 133 on the active layer 130.

[0081] Meanwhile, the metal reflective layer 139 is disposed on the dielectric layer 137 and connects to the conductive oxide layer 135 through each opening 137a. The metal reflective layer 139 includes a reflective metal, such as Ag or Ni / Ag. The metal reflective layer 139 may also include a barrier layer, such as Ni, to protect the reflective metal material layer and may also include an Au layer to prevent oxidation of the metal layer. A Ti layer may also be included below the Au layer to improve adhesion of the Au layer. The metal reflective layer 139 contacts the upper surface of the dielectric layer 137, and thus the thickness of the dielectric layer 137 is the same as the separation distance between the conductive oxide layer 135 and the metal reflective layer 139.

[0082] An ohmic contact is formed with the conductive oxide layer 135, and the metal reflective layer 139 is disposed on the dielectric layer 137. This prevents the ohmic resistance from increasing due to solder, etc. Furthermore, by disposing the conductive oxide layer 135, the dielectric layer 137, and the metal reflective layer 139 on the second conductive type semiconductor layer 133, it is possible to improve the light reflectivity and the light emitting efficiency.

[0083] The lower insulating layer 141 covers the mesa M and the metal reflective layer 139. The lower insulating layer 141 may also cover the first conductive type semiconductor layer 127 along the periphery of the mesa M and may also cover the first conductive type semiconductor layer 127 within the recess 140 inside the mesa M. The lower insulating layer 141 particularly covers the side surface of the mesa M. The lower insulating layer 141 may also cover the dielectric layer 137.

[0084] Meanwhile, the lower insulating layer 141 has first openings 141a1 and 141a2 exposing the first conductive type semiconductor layer and a second opening 141b exposing the metal reflective layer 139. The first opening 141a1 exposes the first conductive type semiconductor layer 127 along the periphery of the mesa M, and the first opening 141a2 exposes the first conductive type semiconductor layer 127 within the indentation 140. If a via hole is formed instead of the indentation 140, the first opening 141a2 exposes the first conductive type semiconductor layer 127 within the via hole.

[0085] As shown in FIG. 4A, the first opening 141a1 and the first opening 141a2 may be connected to each other, but the present invention is not limited thereto, and the first openings 141a1 and 141a2 may be spaced apart from each other.

[0086] In this embodiment, the first opening 141a1 in the lower insulating layer 141 is formed to include the edge of the first conductive type semiconductor layer 127 and to expose the entire peripheral region thereof. However, the present invention is not limited to this, and the first opening 141a1 in the lower insulating layer 141 may be formed in a strip shape along the periphery of the mesa M. In this case, the edge of the first conductive type semiconductor layer 127 may be covered by the lower insulating layer 141 or may be aligned with the edge of the lower insulating layer 141.

[0087] The second opening 141b exposes the metal reflective layer 139. A plurality of second openings 141b may be formed, and these second openings 141b may be disposed near one edge of the substrate 121, facing the recess 140. The location of the second openings 141b will be described later.

[0088] Meanwhile, the lower insulating layer 141 may be formed of a single layer of SiO2 or Si3N4, but is not limited thereto. For example, the lower insulating layer 141 may have a multi-layer structure including a silicon nitride film and a silicon oxide film. The lower insulating layer 141 may include a distributed Bragg reflector in which silicon oxide films and titanium oxide films are alternately stacked.

[0089] Meanwhile, the first pad metal layer 143a is disposed on the lower insulating layer 141 and is insulated from the mesa M and the metal reflective layer 139 by the lower insulating layer 141. The first pad metal layer 143a contacts the first conductive type semiconductor layer 127 through first openings 141a1 and 141a2 in the lower insulating layer 141. The first pad metal layer 143a may include an external contact 143a1 that contacts the first conductive type semiconductor layer 127 along the periphery of the mesa M and an internal contact 143a2 that contacts the first conductive type semiconductor layer 127 within the indentation 140 or the via hole. The external contact 143a1 contacts the first conductive type semiconductor layer 127 near the edge of the substrate 121 along the periphery of the mesa M, and the internal contact 143a2 contacts the first conductive type semiconductor layer 127 within the region surrounded by the external contact 143a1. The external contact 143a1 and the internal contact 143a2 may be connected to each other, but are not limited to this, and may be spaced apart. In some embodiments, the external contact 143a1 may be in continuous contact with the first conductive type semiconductor layer 127 along the periphery of the mesa M, but are not limited to this. In other embodiments, multiple external contacts 143a1 may be spaced apart from each other.

[0090] Meanwhile, the second pad metal layer 143b is disposed on the lower insulating layer 141 in the upper region of the mesa M, and is electrically connected to the metal reflective layer 139 through the second opening 141b in the lower insulating layer 141. The second pad metal layer 143b may be surrounded by the first pad metal layer 143a, and a boundary region 143ab may be formed therebetween. The lower insulating layer 141 is exposed in the boundary region 143ab, and this boundary region 143ab is covered with the upper insulating layer 145, which will be described later.

[0091] In some embodiments, the first pad metal layer 143a and the second pad metal layer 143b may be formed together using the same material in a single process. In other embodiments, the first pad metal layer 143a and the second pad metal layer 143b may be formed separately. The first and second pad metal layers 143a and 143b may include an ohmic reflective layer, such as an Al layer, which may be formed on an adhesion layer, such as Ti, Cr, or Ni. A single or multiple layer protection layer, such as Ni, Cr, or Au, may also be formed on the ohmic reflective layer. The first and second pad metal layers 143a and 143b may have a multilayer structure, for example, Cr / Al / Ni / Ti / Ni / Ti / Au / Ti.

[0092] The upper insulating layer 145 covers the first and second pad metal layers 143a and 143b. The upper insulating layer 145 may also cover the first conductive type semiconductor layer 127 along the periphery of the mesa M. In this embodiment, the upper insulating layer 145 may expose the first conductive type semiconductor layer 127 along the edge of the substrate 121. However, the present invention is not limited thereto, and the upper insulating layer 145 may cover the entire first conductive type semiconductor layer 127 or may be aligned with the edge of the substrate 121.

[0093] 4B, the upper insulating layer 145 has a first opening 145a exposing the first pad metal layer 143a and a second opening 145b exposing the second pad metal layer 143b. The first opening 145a and the second opening 145b may be disposed in an upper region of the mesa M or may be disposed opposite each other. In particular, the first opening 145a and the second opening 145b may be disposed adjacent to both side edges of the mesa M.

[0094] The upper insulating layer 145 may be formed of a single layer of SiO2 or Si3N4, but is not limited to this. In some embodiments, the upper insulating layer 145 may have a multi-layer structure including a silicon nitride film and a silicon oxide film. In other embodiments, the upper insulating layer 145 may include a distributed Bragg reflector formed by alternating layers of silicon oxide films and titanium oxide films.

[0095] Meanwhile, the first bump pad 147a electrically contacts the first pad metal layer 143a exposed through the first opening 145a of the upper insulating layer 145, and the second bump pad 147b electrically contacts the second pad metal layer 143b exposed through the second opening 145b. As shown in FIG. 4A, the first bump pad 147a may be disposed in the first opening 145a of the upper insulating layer 145, and the second bump pad 147b may be disposed in the second opening 145b of the upper insulating layer 145. However, the present invention is not limited thereto. The first bump pad 147a and the second bump pad 147b may completely cover and seal the first opening 145a and the second opening 145b, respectively. Furthermore, the second bump pad 147b may cover an upper region of the second opening 141b of the lower insulating layer 141. The second bump pads 147b may, but are not limited to, substantially cover the entire second openings 141b of the lower insulating layer 141. In another embodiment, a portion of each opening 141b may extend outside the second bump pads 147b, as shown in FIG.

[0096] 4A, the second bump pad 147b may be located only in the upper region of the second pad metal layer 143b. However, the present invention is not limited to this, and a portion of the second bump pad 147b may overlap the first pad metal layer 143a. However, an upper insulating layer 145 may be disposed between the first pad metal layer 143a and the second bump pad 147b to insulate them.

[0097] According to one or more embodiments of the present disclosure, a reflective structure of a conductive oxide layer 135, a dielectric layer 137, and a metal reflective layer 139 is used instead of a conventional ohmic reflective layer. This prevents a bonding material such as solder from penetrating into the contact area, ensuring stable ohmic contact resistance and improving the reliability of the light-emitting diode. Furthermore, by making the thickness of the dielectric layer 137 300 nm or more, high light output and low forward voltage can be achieved.

[0098] According to one or more embodiments of the present disclosure, the first bump pad 147a and the second bump pad 147b may all be disposed on the second conductive type semiconductor layer 133 and thus may be flip-bonded to emit light through the substrate 121. The first bump pad 147a is particularly electrically connected to the first conductive type semiconductor layer 127 from the second conductive type semiconductor layer 133 side, and for this purpose, the second conductive type semiconductor layer 133 is patterned to expose the first conductive type semiconductor layer 127. The flip-chip type light emitting diode includes a V-pit as already described with reference to FIGS. 1 to 3 and has peaks at multiple wavelengths.

[0099] According to the teachings of the present disclosure, it is possible to provide a flip-chip type light emitting diode that can realize white light without a phosphor. The phosphor process for manufacturing a white light diode can be omitted, reducing production costs. Furthermore, a thin white light source that is reduced by the thickness of the phosphor coating can be applied to applied products.

[0100] Alternatively or additionally, a color filter (not shown) may be disposed on the substrate 121 of the flip-chip LED. The color filter may be, for example, an interference filter formed by alternately stacking material layers with different refractive indices, such as a bandpass filter, a long-wavelength pass filter, or a short-wavelength pass filter, or may be an absorption filter. The color filter can be used to emit light of a specific peak wavelength among multiple peak wavelengths emitted from the LED and block light of other peak wavelengths. For example, a color filter for blocking short-wavelength light can be used to selectively transmit long-wavelength light, or conversely, a color filter for blocking long-wavelength light can be used to selectively transmit short-wavelength light. In the case of an interference filter, the thickness and number of layers of the color filter can be determined depending on the wavelength of light to be transmitted. Furthermore, the transmittance of transmitted light can be adjusted, and the color mixing ratio can be easily controlled by adjusting the transmittance of transmitted light.

[0101] FIG. 5A is a schematic plan view illustrating a light-emitting diode having a plurality of light-emitting cells according to another embodiment, FIG. 5B is a schematic cross-sectional view taken along line BB in FIG. 5A, and FIG. 5C is a schematic cross-sectional view taken along line CC in FIG. 5A.

[0102] 5A, 5B, and 5C, the light emitting diode 200 according to this embodiment includes a substrate 221, a first conductive type semiconductor layer 227, an active layer 230, a second conductive type semiconductor layer 233, a transparent electrode layer 235, insulating layers 241a, 241b, 241c, and 241d, a first electrode pad 245, a second electrode pad 247, a first extension 245a, a second extension 247a, and a third extension 247b. Here, each of the semiconductor layers 227, 230, and 233 is separated into a plurality of light emitting cells C1, C2, and C3, and the first to third extensions 245a, 247a, and 247b are disposed on each of the light emitting cells C1, C2, and C3.

[0103] In this embodiment, the substrate 221, the first conductive type semiconductor layer 227, the active layer 230, and the second conductive type semiconductor layer 233 are similar to those described with reference to Fig. 1, and therefore a detailed description of the overlapping contents will be omitted. Also, although not shown here, a nucleation layer and a high-temperature buffer layer may be interposed between the substrate 221 and the first conductive type semiconductor layer 227, and a V-pit generation layer may be interposed between the first conductive type semiconductor layer 227 and the active layer 230, as described with reference to Fig. 1. Also, a p-type AlGaN layer may be interposed between the active layer 230 and the second conductive type semiconductor layer 233.

[0104] The substrate 221 may have a rectangular or square shape, as shown in the plan view of Fig. 1, but is not necessarily limited thereto. The size of the substrate 221 is not particularly limited and may be selected in various ways.

[0105] Each of the semiconductor layers 227, 230, and 233 is separated into a plurality (n) of light emitting cells C1, C2, and C3 by cell isolation regions I1 and I2. Although three light emitting cells C1, C2, and C3 are shown in FIG. 5A, the number of light emitting cells is not limited to three. n may be an integer of 2 or greater, and particularly may be an integer of 3 or greater. Furthermore, when n is an odd number, it is advantageous because the electrode pads 245 and 247 can be arranged diagonally across the substrate 221.

[0106] Each of the light emitting cells C1, C2, and C3 may have a long rectangular shape and may be arranged parallel to each other, such that the even-numbered light emitting cell C2 is arranged between the odd-numbered light emitting cells C1 and C3.

[0107] Both side walls of each of the cell isolation regions I1 and I2 are formed using photolithography and etching processes, and have a relatively gentle shape in consideration of the reliability of each connection portion 246.

[0108] However, each side of the substrate 221 (see the left side of the substrate 221 in FIG. 5B ) may be formed using laser scribing, unlike the cell isolation regions I1 and I2, and therefore has a relatively steep slope. In particular, both the substrate 221 and the first conductive type semiconductor layer 227 may be separated from other light emitting diodes using laser scribing, and therefore the side surfaces of the substrate 221 and the first conductive type semiconductor layer 227 may be aligned with each other.

[0109] Meanwhile, the upper surface of the first conductive type semiconductor layer 227 may be exposed along the edge of each of the light emitting cells C1, C2, and C3. That is, the second conductive type semiconductor layer 233 is surrounded by the exposed upper surface of the first conductive type semiconductor layer 227. The upper surface of the first conductive type semiconductor layer 227 may be exposed along the entire periphery of the second conductive type semiconductor layer 233.

[0110] Meanwhile, the transparent electrode layer 235 is located on the second conductive type semiconductor layer 233 of each of the light emitting cells C1, C2, and C3. The transparent electrode layer 235 may be formed of a conductive oxide layer, for example, ITO or ZnO, and is in contact with the second conductive type semiconductor layer 233. That is, the transparent electrode layer 235 is in electrical contact with the second conductive type semiconductor layer 233 and has a lower resistivity than the second conductive type semiconductor layer 233, thereby dispersing current over a wide area of ​​the light emitting diode.

[0111] The transparent electrode layer 235 has substantially the same planar shape as the second conductive type semiconductor layer 233. However, the transparent electrode layer 235 may have a smaller area than the second conductive type semiconductor layer 233. The bottom surface of the transparent electrode layer 235 may contact the top surface of the second conductive type semiconductor layer 233.

[0112] When the transparent electrode layer 235 is formed of ZnO, it can contain other materials as long as Zn and O constitute the majority of the compound and the ZnO maintains the wurtzite crystal structure. For example, the ZnO transparent electrode layer 235 can include aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), and indium-doped zinc oxide (IZO). The ZnO transparent electrode 235 can also include materials with small amounts of other dopants and / or other impurities or inclusions, as well as materials that are non-stoichiometric due to the presence of vacancies and intercalation-type material defects.

[0113] The ZnO transparent electrode layer 235 may have a thickness that is approximately five times or more the general thickness of an ITO film. For example, the ITO transparent electrode layer 235 may be formed to a thickness of approximately 500 Å or less, but the ZnO transparent electrode layer 235, due to its low absorption, may be formed to a thickness of 1000 Å or more, or even approximately 5000 Å or more. The upper limit of the ZnO transparent electrode layer 235 is not particularly limited, but may be approximately 1 μm or less.

[0114] When the transparent electrode layer 235 is made of ZnO, it can be formed relatively thicker than ITO or other conductive oxides, which reduces the surface resistance and makes it easier to distribute current. However, in this embodiment, the transparent electrode layer 235 is not necessarily limited to ZnO.

[0115] 5A, the first electrode pad 245 may be disposed on the first light emitting cell C1, and the second electrode pad 247 may be disposed on the third light emitting cell C3. The first electrode pad 245 may be disposed on the exposed upper surface of the first conductive type semiconductor layer 227. However, the present invention is not limited thereto, and the first electrode pad 245 may be disposed on the second conductive type semiconductor layer 233 with an insulating layer interposed therebetween. The first electrode pad 245 may also be disposed near one corner of the first light emitting cell C1.

[0116] Meanwhile, the first extension 245a is electrically connected to the first conductive type semiconductor layer 227 exposed through the mesa etching process. The first extension 245a on the first light emitting cell C1 may extend from the first electrode pad 245, and the first extensions 245a on the other light emitting cells C2 and C3 may extend from the connecting portion 246, respectively.

[0117] The second electrode pad 247 may be disposed on the transparent electrode layer 235. The second electrode pad 247 may be disposed near the other corner of the substrate 221 opposite the first electrode pad 245, which facilitates the wire bonding process.

[0118] 5A, the second extension portion 247a and the third extension portion 247b on each of the light emitting cells C1, C2, and C3 may be positioned on the transparent electrode layer 235 to cover the first extension portion 245a. In this embodiment, since the second electrode pad 247 is not disposed on all of the light emitting cells C1 to C3, not all of the second extension portion 247a and the third extension portion 247b extend from the second electrode pad 247. As shown in FIG. 5A, the second extension portion 247a and the third extension portion 247b on the third light emitting cell C3 extend from the second electrode pad 247, but the second extension portion 247a and the third extension portion 247b on the first and second light emitting cells C1 and C2 are spaced apart from the second electrode pad 247 and extend from the connection portion 246 that electrically connects the light emitting cells.

[0119] The second extension 247a and the third extension 247b are located on the transparent electrode layer 235 above each of the light emitting cells C1, C2, and C3, and are electrically connected to the transparent electrode layer 235, respectively.

[0120] Meanwhile, each connecting portion 246 electrically connects adjacent light emitting cells. Specifically, each connecting portion 246 connects the first extension portion 245a of one light emitting cell to the second and third extension portions 247a, 247b of the adjacent light emitting cell. As shown in FIG. 5C, one end of the connecting portion 246 may be located on the first conductive type semiconductor layer 227 and connected to the first extension portion 245a, and the other end may be located on the second conductive type semiconductor layer 233. As can be seen from FIG. 5A, the other end of the connecting portion 246 located on the second conductive type semiconductor layer 233 is connected to the second and third extension portions 247a, 247b of the second light emitting cell C2.

[0121] As shown in FIG. 5A, each of the remaining light emitting cells (e.g., C2) other than the first light emitting cell C1 and the third light emitting cell C3 has two connectors 246 disposed near each diagonal corner. As shown in FIG. 5A, the connector 246 connected to the first light emitting cell C1 is disposed near the diagonal corner facing the first electrode pad 245, and the connector 246 connected to the third light emitting cell C3 is disposed near the diagonal corner facing the second electrode pad 247. Meanwhile, the first, second, and third extensions 245a, 247a, and 247b on the first light emitting cell C1 and the first, second, and third extensions on the second light emitting cell C2 have substantially similar shapes. In some embodiments, the first, second, and third extensions 245a, 247a, and 247b on the second light emitting cell C2 and the first, second, and third extensions on the third light emitting cell C3 also have substantially similar shapes. The first to third extensions 245a, 247a, and 247b of adjacent light emitting cells are arranged in an inverted shape, so that the first extension 245a is formed as a relatively long single line, and the second and third extensions 247a and 247b can be designed to have substantially the same or similar lengths, thereby achieving substantially uniform current distribution on both sides of the first extension 245a.

[0122] In some embodiments, the first electrode pad 245, the second electrode pad 247, the first extension 245a, the connecting portion 246, the second extension 247a, and the third extension 247b may be formed together using the same material in a single process. However, the present invention is not limited thereto, and in other embodiments, other materials and / or other processes may be used to form the first electrode pad 245, the second electrode pad 247, the first extension 245a, the connecting portion 246, the second extension 247a, and the third extension 247b, or a combination thereof.

[0123] 5A, the first insulating layer 241a may be located under the first electrode pad 245. The first insulating layer 241a reduces direct current flow from the first electrode pad 245 to the first conductive type semiconductor layer 227, contributing to current dispersion. The first insulating layer 241a may be located under a portion of the first electrode pad 245, so that an edge region of the first electrode pad 245 may be connected to the first conductive type semiconductor layer 227. By adjusting the width of the first insulating layer 241a and the width of the first electrode pad 245, the area where the first electrode pad 245 contacts the first conductive type semiconductor layer 227 can be adjusted, thereby controlling the forward voltage.

[0124] The second insulating layer 241b is disposed below the second electrode pad 247 to separate the second electrode pad 247 from the transparent electrode layer 235. For example, as shown in FIG. 5A , the second insulating layer 241b may be formed in a disk shape and may have a larger area than the second electrode pad 247. The second electrode pad 247 may be disposed on the insulating layer 241b to be separated from the transparent electrode layer 235. However, the present invention is not limited thereto. The second insulating layer 241b may be formed to have an opening so that the second electrode pad 247 partially contacts the transparent electrode layer 235. By disposing the second electrode pad 247 on the second insulating layer 241b, current concentration below the second electrode pad 247 can be reduced.

[0125] Meanwhile, a third insulating layer 241c may be interposed under the connection part 246 to prevent the first conductive type semiconductor layer 227 and the second conductive type semiconductor layer 233 in one light emitting cell from being short-circuited by the connection part 246.

[0126] In addition, the fourth insulating layer 241d may cover the sidewalls of the active layer 230 and the second conductive type semiconductor layer 233 exposed around the first electrode pad 245. The fourth insulating layer 241d prevents a bonding wire from being short-circuited to the second conductive type semiconductor layer 233 or the active layer 230 when bonding a wire to the first electrode pad 245. In some embodiments, the fourth insulating layer 241d may be formed in a continuous curved shape, and the first extension 245a may pass over the fourth insulating layer 241d. However, the present invention is not limited thereto. In other embodiments, a portion of the fourth insulating layer 241d may be omitted, and the first extension 245a may pass through the omitted portion of the fourth insulating layer 241d.

[0127] In some embodiments, the first through fourth insulating layers 241a, 241b, 241c, and 241d may be formed together using the same material in a single process. In particular, the insulating layers 241a, 241b, 241c, and 241d may be formed using a lift-off process or as distributed Bragg reflectors. In other embodiments, the first through fourth insulating layers 241a, 241b, 241c, and 241d may be formed separately.

[0128] According to one or more embodiments, the light emitting diode includes a plurality of light emitting cells C1, C2, and C3 separated by isolation regions I1 and I2, and these light emitting cells C1, C2, and C3 are electrically connected in series. However, the present invention is not limited thereto, and the light emitting cells C1, C2, and C3 may be connected in parallel or in series-parallel. In particular, when the light emitting cells C1, C2, and C3 are connected in series, the operating voltage of the light emitting diode can be increased.

[0129] FIG. 6 is a schematic plan view illustrating a light emitting diode 300 having a plurality of light emitting cells according to another embodiment.

[0130] 6, the light emitting diode 300 includes a plurality of light emitting cells C1, C2, C3, C4, and C5 similar to the light emitting diodes described with reference to FIGS. 5A, 5B, and 5C. The light emitting areas of the light emitting cells C1, C2, C3, C4, and C5 are different from one another.

[0131] The light emitting diode includes a substrate 321, a first conductive type semiconductor layer 327, an active layer, a second conductive type semiconductor layer 333, a first electrode pad 345, a second electrode pad 347, and extensions 345a, 345b, 347a, and 347b. Although not shown, a transparent electrode layer may be disposed on the second conductive type semiconductor layer 333 of each light emitting cell, similar to the light emitting diodes described with reference to FIGS. 5A, 5B, and 5C. The light emitting diode 300 may also include a nucleation layer, a high-temperature buffer layer, a V-pit generation layer, and a p-AlGaN layer, similar to the embodiments already described with reference to FIGS. 1 to 3.

[0132] 5A, 5B, and 5C, the stacked structure of each of the light emitting cells C1, C2, C3, C4, and C5, and the connection structure of the first electrode pad 345, the second electrode pad 347, and each of the extensions 345a, 345b, 347a, and 347b are similar to those described with reference to Figures 5A, 5B, and 5C, and therefore detailed description thereof will be omitted to avoid redundancy. Also, for electrical insulation, an insulating layer may at least partially cover each of the light emitting cells C1, C2, C3, C4, and C5, and may at least partially cover the regions between them.

[0133] Meanwhile, the light emitting cells C1, C2, C3, C4, and C5 may be separated from one another by cell isolation regions I1, I2, I3, and I4. For example, the first conductive type semiconductor layers 327 may also be separated from one another by cell isolation regions I1, I2, I3, and I4. In one embodiment, the light emitting cells arranged in the same row may share the first conductive type semiconductor layer 327. That is, three light emitting cells arranged in the same row in FIG. 6 may be arranged on consecutive first conductive type semiconductor layers 327. In another embodiment, the light emitting cells in the same row may also be separated from one another by cell isolation regions.

[0134] In this embodiment, the light emitting cells C1, C2, C3, C4, and C5 are connected in series and parallel, i.e., the light emitting cells arranged in the same row are connected in parallel, and these light emitting cells are connected in series with each other by the extensions 345a, 345b, 347a, and 347b between the first electrode pad 345 and the second electrode pad 347.

[0135] Meanwhile, the light emitting cells C1, C2, C3, C4, and C5 have different sizes. For example, the light emitting cell C3 may have a smaller light emitting area than the light emitting cell C2, and the light emitting cell C2 may have a smaller area than the light emitting cell C1. The light emitting cell C1 may have the same light emitting area as the light emitting cell C5, and the light emitting cell C2 may have the same light emitting area as the light emitting cell C4.

[0136] Under substantially the same current, the current density varies depending on the size of the light-emitting area. A light-emitting cell with a high current density can emit light with multiple peak wavelengths, while a light-emitting cell with a low current density can emit light with a yellow-based color. Therefore, by varying the size of each light-emitting cell, the hue of the light emitted from each light-emitting cell can be adjusted.

[0137] In this embodiment, the light emitting cells are arranged in order of decreasing light emitting area from the first electrode pad 345 to the second electrode pad 347, and then increasing again, but the present invention is not limited thereto. The light emitting cells having different light emitting areas may be arranged in various ways. Furthermore, the light emitting cells arranged in the same row may have light emitting areas of different sizes.

[0138] According to various embodiments of the present invention, a multi-cell light emitting diode that can realize white light without a phosphor can be provided. The phosphor process for manufacturing a white light diode can be omitted, thereby reducing production costs. Furthermore, a thin white light source that is reduced by the thickness of the phosphor coating can be applied to applied products.

[0139] FIG. 7A is a graph showing the spectrum of a blue light emitting diode of a comparative example as a function of current, and FIG. 7B is a graph showing the spectrum of a light emitting diode of an example as a function of current.

[0140] 7A, in the comparative example, the blue LED increases the intensity of blue light as the current increases, but the emission wavelength remains almost unchanged. Therefore, to realize white light, an LED of another color must be added to the blue LED, or a phosphor must be used.

[0141] 7B, the LED according to the embodiment of the present disclosure has a peak wavelength in the yellow region when the current is small, but as the current increases, peak wavelengths are observed in both the yellow and blue regions. That is, the LED according to the embodiment can realize mixed color light, for example, white light, in which blue light and yellow light are mixed, as the driving current increases.

[0142] 8A is a graph showing color coordinates of a white LED package using a phosphor as a comparative example, and FIG. 8B is a graph illustrating color coordinates as a function of current for a white LED package according to an embodiment of the present disclosure. Here, the LED packages of the comparative example and the embodiment were both manufactured using Seoul Semiconductor's 5630 package. However, the comparative example mounted a blue chip in the package and used a molding member with phosphor dispersed therein to realize white light. In contrast, the embodiment mounted a horizontal-type light emitting chip according to an embodiment of the present disclosure in the package.

[0143] First, referring to FIG. 8A, the light emitting diode package of the comparative example shows the color coordinates of one point, and this position corresponds to the white area.

[0144] 8B, the LED package of the embodiment emits light whose hue changes from yellow to white as the current increases, emitting yellow light at a current of 3 mA, but white light at 100 mA.

[0145] Table 1 briefly summarizes the electrical and optical characteristics of the comparative example and the example under a driving current of 100 mA.

[0146] [Table 1]

[0147] Referring to Table 1, it can be seen that the LED package of the example has almost similar x and y coordinates to the white LED package of the comparative example using a phosphor.

[0148] The light emitting diodes according to the embodiments of the present disclosure can emit light having multiple peak wavelengths in the visible light range without using a phosphor, and can thereby realize white light without using a phosphor.

[0149] Since the light emitting diode according to each embodiment of the present disclosure emits light with a plurality of clearly distinguishable peak wavelengths, it is advantageous to use a color filter to extract and use light of a desired peak wavelength.

[0150] The light-emitting diodes according to the embodiments of the present disclosure can be applied not only to the lighting field but also to the wireless communication field. In particular, since they can emit light with multiple peak wavelengths in the visible region, they can be suitably used in visible light communications (VLC) such as Li-Fi.

[0151] The visible range covers the range of 380 THz to 750 THz, which is approximately 10,000 times wider than the entire frequency range of conventional wireless communication. Conventional white light emitting diodes using phosphors are not suitable for use in VLC because the phosphor causes a response delay and slows the frequency response, but the light emitting diode according to this embodiment emits light with multiple peak wavelengths in the visible range without the need for a phosphor, and therefore can be used appropriately in VLC.

[0152] As described above, the specific description of the present disclosure has been given using examples with reference to the accompanying drawings. However, since the above description has only illustrated examples of the present disclosure, the present disclosure should not be understood as being limited to only the above examples, and the scope of the present disclosure should be understood in terms of the claims set forth below and their equivalents. [Explanation of symbols]

[0153] 21 PCB 23 Nucleation layer 25 High temperature buffer layer 27 n-type nitride semiconductor layer 29 Pit formation layer 29v pit 30 Active layer 30b Barrier layer 30c capping layer 30w well layer 31 p-type AlGaN layer 33 p-type nitride semiconductor layer 100 Flip-chip light-emitting diodes 121 PCB 127 First conductivity type semiconductor layer 130 Active layer 133 Second conductivity type semiconductor layer 135 Conductive oxide layer 137 Dielectric Layer 137a opening 139 Metal reflective layer 140 Bay 141 Lower insulating layer 141a1, 141a2 1st opening 141b 2nd opening 143a First pad metal layer 143a1 External contact part 143a2 Internal contact part 143ab border area 143b Second pad metal layer 145 Upper insulating layer 145a 1st opening 145b 2nd opening 147a 1st Bump Pad 147b 2nd bump pad 200 Light Emitting Diodes 221 Substrate 227 First conductivity type semiconductor layer 230 Active layer 233 Second conductivity type semiconductor layer 235 Transparent electrode layer 241a First insulating layer 241b Second insulating layer 241c Third insulating layer 241d Fourth insulating layer 245 First electrode pad 245a 1st extension 246 Connection section 247 Second electrode pad 247a 2nd extension 247b Third extension 300 Light Emitting Diodes 321 Substrate 327 First conductivity type semiconductor layer 333 Second conductivity type semiconductor layer 345 First electrode pad 345a, 345b extension 347 Second electrode pad 347a, 347b extension

Claims

1. an n-type nitride semiconductor layer; an active layer located on the n-type nitride semiconductor layer; and a p-type nitride semiconductor layer located on the active layer; the active layer has a plurality of barrier layers and a plurality of well layers; a first portion configured to emit light at a first peak wavelength and a second portion configured to emit light at a second peak wavelength different from the first peak wavelength, wherein the relative intensities of the light emitted by the first portion and the second portion vary as a drive current varies between 3 mA and 100 mA.

2. 10. The light emitting diode of claim 1, wherein the light emitted from the active layer changes from yellow light to white light with increasing drive current.

3. the light emitting diode further includes a V-pit generation layer disposed between the n-type nitride semiconductor layer and the active layer; 2. The light-emitting diode according to claim 1, wherein a portion of the active layer is formed in a V-pit of the V-pit generating layer.

4. the V-pit generating layer has a thickness greater than 450 nm; 4. The light-emitting diode according to claim 3, wherein each V-pit formed in the V-pit generation layer includes a V-pit whose entrance width exceeds 230 nm.

5. the light emitting diode further includes a p-type AlGaN layer interposed between the active layer and the p-type nitride semiconductor layer; 4. The light-emitting diode according to claim 3, wherein the Al composition ratio x in the p-type AlGaN layer is greater than 0 and less than 0.

3.

6. 6. The light emitting diode of claim 5, wherein the p-type AlGaN layer has a thickness of less than 100 nm.

7. a capping layer disposed between the well layer and the barrier layer and covering the well layer; 6. The light-emitting diode of claim 5, wherein the capping layer contains Al.

8. The light emitting diode of claim 1 , wherein the light emitting diode has a flip-chip structure.

9. The light emitting diode of claim 1 , wherein the light emitting diode comprises a plurality of light emitting cells.

10. The light emitting diode of claim 9 , wherein the light emitting cells have different light emitting areas.

11. The light emitting diode of claim 10 , wherein the light emitting cells are connected in series.

12. Light emitting diodes; and a color filter disposed over the light emitting diode; The light emitting diode is an n-type nitride semiconductor layer; an active layer located on the n-type nitride semiconductor layer; and a p-type nitride semiconductor layer located on the active layer; the active layer has a plurality of barrier layers and a plurality of well layers; a first portion configured to emit light at a first peak wavelength and a second portion configured to emit light at a second peak wavelength different from the first peak wavelength, wherein the relative intensities of the light emitted by the first portion and the second portion vary as a drive current varies between 3 mA and 100 mA.

13. the light emitting diode further includes a V-pit generation layer disposed between the n-type nitride semiconductor layer and the active layer; 13. The light-emitting device according to claim 12, wherein a portion of the active layer is formed in a V-pit of the V-pit generation layer.

14. the V-pit generating layer has a thickness greater than 450 nm; 14. The light emitting device according to claim 13, wherein each V-pit formed in the V-pit generation layer includes a V-pit whose entrance width exceeds 230 nm.

15. the light emitting diode further includes a p-type AlGaN layer interposed between the active layer and the p-type nitride semiconductor layer; The light-emitting device according to claim 13 , wherein the Al composition ratio x in the p-type AlGaN layer is greater than 0 and less than 0.

3.

16. 16. The light emitting device of claim 15, wherein the p-type AlGaN layer has a thickness of less than 100 nm.

17. a capping layer disposed between the well layer and the barrier layer and covering the well layer; 16. The light emitting device of claim 15, wherein the capping layer comprises Al.

18. The light emitting device according to claim 12 , wherein the light emitting diode has a flip-chip structure.

19. 13. The light emitting device according to claim 12, wherein the color filter is a band-pass filter, a long wavelength transmission filter, or a short wavelength transmission filter.

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