Imaging device

Abstract

This imaging device comprises: a first photoelectric conversion unit that converts light into an electrical charge; a first charge storage unit that stores the electrical charge; a first capacitor; an output circuit that is electrically connected to the first capacitor; and a first interposed transistor having a gate electrode, a source, and a drain. The first charge storage unit is electrically connected to the gate electrode and to either one of the source and the drain. The first charge storage unit and the first capacitor are electrically connected due to the first interposed transistor turning on.

Description

[Technical Field]

[0001] The present disclosure relates to an imaging device. [Background technology]

[0002] Various imaging devices have been proposed in the past. For example, Patent Documents 1 and 2 describe imaging devices that use photodiodes as photoelectric conversion units. Patent Document 3 describes an imaging device in which two photodiodes are provided in one pixel.

[0003] A structure in which a photoelectric conversion unit having a photoelectric conversion layer is disposed above a semiconductor substrate may also be employed. An imaging device having such a structure is called a stacked imaging device. Patent Document 4 describes an example of a stacked imaging device. Specifically, in Patent Document 4, two photoelectric conversion units each having a photoelectric conversion layer are provided in one pixel. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-253876 [Patent Document 2] Patent No. 4317115 [Patent Document 3] International Publication No. 2016 / 147885 [Patent Document 4] Japanese Patent Application Publication No. 2018-117347 Summary of the Invention [Problem to be solved by the invention]

[0005] The present disclosure provides a technique suitable for suppressing a decrease in the signal-to-noise ratio (SN ratio) that accompanies a decrease in the amount of light. [Means for solving the problem]

[0006] The present disclosure provides: a first photoelectric conversion unit that converts light into electric charges; a first charge accumulation unit that accumulates the charges; a first capacitor; an output circuit electrically connected to the first capacitor; a first intervening transistor having a gate electrode, a source, and a drain; The first charge accumulation unit is electrically connected to the gate electrode and one of the source and the drain. When the first intervening transistor is turned on, the first charge accumulation unit and the first capacitor are electrically connected. An imaging device is provided. [Effects of the Invention]

[0007] The technology according to the present disclosure is suitable for suppressing a decrease in the S / N ratio that accompanies a decrease in the amount of light. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram illustrating an example of the structure of an imaging device. [Figure 2] FIG. 2 is a schematic diagram showing the first signal processing circuit and the second signal processing circuit. [Figure 3] FIG. 3 is a schematic diagram showing an example of a circuit configuration of a pixel according to the first embodiment. [Figure 4] FIG. 4 is a timing diagram showing the operation of the imaging device. [Figure 5A] FIG. 5A is an explanatory diagram showing the potential of the first charge storage section, the potential under the gate of the first intervening transistor, and the potential of the first portion. [Figure 5B] FIG. 5B is an explanatory diagram showing the potential of the first charge storage section, the potential under the gate of the first intervening transistor, and the potential of the first portion. [Figure 5C] FIG. 5C is an explanatory diagram showing the potential of the first charge storage section, the potential under the gate of the first intervening transistor, and the potential of the first portion. [Figure 6]FIG. 6 is a graph showing the relationship between the amount of light incident on the imaging device and the second pixel signal, the first pixel signal, and the third pixel signal. [Figure 7] FIG. 7 is a graph showing the relationship between the second SN ratio, the first SN ratio, and the third SN ratio and the amount of light incident on the imaging device. [Figure 8] FIG. 8 is a schematic diagram showing the circuit configuration of a pixel of an imaging device according to a reference embodiment. [Figure 9] FIG. 9 is a graph showing the relationship between the second pixel signal and the first pixel signal and the amount of light incident on the imaging device of the reference embodiment. [Figure 10] FIG. 10 is a graph showing the relationship between the second SN ratio and the first SN ratio and the amount of light incident on the imaging device of the reference embodiment. [Figure 11] FIG. 11 is an explanatory diagram showing the change in the relationship of the SN ratio to the amount of light caused by increasing the gain of the high-sensitivity cell of the reference embodiment. [Figure 12] FIG. 12 is an explanatory diagram showing the change in the relationship of the SN ratio to the amount of light when the SPLIT of the reference embodiment is increased. [Figure 13] FIG. 13 is a schematic diagram showing the circuit configuration of a pixel of the imaging device according to the second embodiment. [Figure 14] FIG. 14 is an explanatory diagram for explaining the modulation degree of the first intervening transistor. [Figure 15] FIG. 15 is a schematic diagram showing the circuit configuration of a pixel of the imaging device according to the third embodiment. [Figure 16] FIG. 16 is a schematic diagram showing the circuit configuration of a pixel of an imaging device according to the fourth embodiment. [Figure 17] FIG. 17 is a schematic diagram showing the circuit configuration of a pixel of an imaging device according to the fifth embodiment. [Figure 18] FIG. 18 is a schematic diagram showing the circuit configuration of a pixel of an imaging device according to the sixth embodiment. [Figure 19] FIG. 19 is a schematic diagram showing the circuit configuration of a pixel of the imaging device according to the seventh embodiment. [Figure 20]FIG. 20 is a schematic diagram showing the circuit configuration of a pixel of the imaging device according to the eighth embodiment. [Figure 21] FIG. 21 is a schematic diagram showing the circuit configuration of a pixel of an imaging device according to the ninth embodiment. [Figure 22] FIG. 22 is a plan view showing the arrangement of microlenses according to the tenth embodiment. [Figure 23] FIG. 23 is a schematic diagram showing the system configuration of an imaging system according to the eleventh embodiment. [Figure 24] FIG. 24 is a schematic diagram illustrating a circuit configuration of a pixel of a one-pixel-one-cell system according to an example. DETAILED DESCRIPTION OF THE INVENTION

[0009] (Summary of one aspect of the present disclosure) An imaging device according to a first aspect of the present disclosure includes: a first photoelectric conversion unit that converts light into electric charges; a first charge accumulation unit that accumulates the charges; a first capacitor; an output circuit electrically connected to the first capacitor; a first intervening transistor having a gate electrode, a source, and a drain; The first charge storage unit is electrically connected to the gate electrode and one of the source and the drain. When the first intervening transistor is turned on, the first charge storage unit and the first capacitor are electrically connected to each other.

[0010] The technology according to the first aspect is suitable for suppressing a decrease in the S / N ratio that accompanies a decrease in the amount of light.

[0011] An imaging device according to a second aspect of the present disclosure includes: a first photoelectric conversion unit that converts light into electric charges; a first charge accumulation unit that accumulates the charges; a first capacitor; an output circuit electrically connected to the first capacitor; a first intervening transistor having a gate electrode, a source, and a drain; The first charge accumulation unit is electrically connected to the gate electrode and one of the source and the drain, and the other of the source and the drain is electrically connected to the first capacitor.

[0012] The technology according to the second aspect is suitable for suppressing a decrease in the S / N ratio that accompanies a decrease in the amount of light.

[0013] In a third aspect of the present disclosure, for example, the imaging device according to the first or second aspect may further include a first subsequent transistor, The first subsequent transistor may be turned on to electrically connect the output circuit to the first capacitor.

[0014] According to the first subsequent transistor of the third aspect, it is possible to switch whether or not the first capacitor and its connection destination are electrically connected via the first subsequent transistor.

[0015] In a fourth aspect of the present disclosure, for example, in an imaging device according to any one of the first to third aspects, the first photoelectric conversion unit may include a first electrode, a second electrode, and a photoelectric conversion layer disposed between the first electrode and the second electrode.

[0016] The first photoelectric conversion section of the fourth aspect is an example of the first photoelectric conversion section.

[0017] In a fifth aspect of the present disclosure, for example, in the imaging device according to any one of the first to third aspects, the first photoelectric conversion unit may be a photodiode.

[0018] The first photoelectric conversion section of the fifth aspect is an example of the first photoelectric conversion section.

[0019] In a sixth aspect of the present disclosure, for example, in the imaging device according to any one of the first to fifth aspects, the first capacitor may have a metal-insulator-metal structure.

[0020] The first capacitor of the sixth embodiment may be a high density capacitor.

[0021] In a seventh aspect of the present disclosure, for example, in the imaging device according to any one of the first to sixth aspects, the first charge accumulation unit may be electrically connected to one end of the first capacitor when the first intervening transistor is turned on; A DC potential may be applied to the other end of the first capacitor.

[0022] The use of the first capacitor in the seventh aspect is an example of the use of a capacitor.

[0023] In an eighth aspect of the present disclosure, for example, in the imaging device according to any one of the first to seventh aspects, the imaging device may be configured to be capable of being in a first state and a second state, the first state may be a state in which the first charge storage unit and the first capacitor are electrically connected via the first intervening transistor; The second state may be a state in which there is no capacitor electrically connected to the first charge storage unit.

[0024] The technique according to the eighth aspect is suitable for suppressing a decrease in the S / N ratio that accompanies a decrease in the amount of light.

[0025] In a ninth aspect of the present disclosure, for example, in an imaging device according to any one of the first to eighth aspects, the conductivity type of the gate electrode of the first intermediate transistor may be opposite to the conductivity type of the source and the drain of the first intermediate transistor.

[0026] According to the ninth aspect, it is easy to suppress dark current.

[0027] In a tenth aspect of the present disclosure, for example, in an imaging device according to any one of the first to ninth aspects, the imaging device may be configured such that after a signal corresponding to the potential of the first capacitor is read out, a signal corresponding to the potential of the first charge storage section is read out.

[0028] The signal readout method of the tenth aspect is one example of a signal readout method.

[0029] In an eleventh aspect of the present disclosure, for example, the imaging device according to any one of the first to tenth aspects may further include an additional capacitor and an additional intervening transistor having a gate electrode, a source, and a drain, the gate electrode of the additional intervening transistor and one of the source and the drain of the additional intervening transistor may be electrically connected to the first capacitor; The first capacitor and the additional capacitor may be electrically connected by turning on the additional intervening transistor.

[0030] According to the eleventh aspect, the light amount range in which the signal-to-noise ratio is high can be widened.

[0031] In a twelfth aspect of the present disclosure, for example, the imaging device according to any one of the first to eleventh aspects may further include a first subsequent transistor having a gate electrode, a source, and a drain, and a first amplifying transistor having a gate electrode, a source, and a drain, The first charge accumulation unit may be electrically connected to the gate electrode of the first amplification transistor, When the first subsequent transistor is turned on, the first capacitor, one of the source and the drain of the first subsequent transistor, the other of the source and the drain of the first subsequent transistor, and the gate electrode of the first amplification transistor may be electrically connected in this order.

[0032] The configuration of the imaging device of the twelfth embodiment is simple.

[0033] In a thirteenth aspect of the present disclosure, for example, the imaging device according to any one of the first to eleventh aspects may further include a first amplifying transistor having a gate electrode, a source, and a drain, and an additional amplifying transistor having a gate electrode, a source, and a drain, The first charge accumulation unit may be electrically connected to the gate electrode of the first amplification transistor, The first capacitor may be electrically connected to the gate electrode of the additional amplifying transistor.

[0034] According to the thirteenth aspect, a wide dynamic range can be easily achieved.

[0035] In a fourteenth aspect of the present disclosure, for example, the imaging device according to either one of the twelfth or thirteenth aspects may further include a first imaging cell and a second imaging cell including a second photoelectric conversion unit and a second charge accumulation unit, The first imaging cell and the second imaging cell may be included in one pixel of the imaging device, The first imaging cell may include the first photoelectric conversion unit and the first charge accumulation unit, The second charge accumulation section may accumulate the charge generated by the second photoelectric conversion section.

[0036] According to the fourteenth aspect, it is easy to adjust the characteristics of the imaging device.

[0037] In a fifteenth aspect of the present disclosure, for example, the imaging device according to any one of the first to eleventh aspects may further include a first imaging cell and a second imaging cell including a second photoelectric conversion unit and a second charge accumulation unit, The first imaging cell and the second imaging cell may be included in one pixel of the imaging device, The first imaging cell may include the first photoelectric conversion unit and the first charge accumulation unit, The second charge accumulation section may accumulate the charge generated by the second photoelectric conversion section.

[0038] According to the fifteenth aspect, it is easy to adjust the characteristics of the imaging device.

[0039] In a sixteenth aspect of the present disclosure, for example, the imaging device according to the fifteenth aspect may further include a first subsequent transistor having a gate electrode, a source, and a drain, The first imaging cell may further include a first amplifying transistor having a gate electrode, a source, and a drain; The second imaging cell may further include a second amplifying transistor having a gate electrode, a source, and a drain; The first charge accumulation unit may be electrically connected to the gate electrode of the first amplification transistor, The second charge storage unit may be electrically connected to the gate electrode of the second amplification transistor, When the first subsequent transistor is turned on, the first capacitor, one of the source and the drain of the first subsequent transistor, the other of the source and the drain of the first subsequent transistor, and the gate electrode of the second amplification transistor may be electrically connected in this order.

[0040] According to the sixteenth aspect, the second amplifying transistor of the second imaging cell can be used to read out a signal corresponding to the potential of the first capacitor.

[0041] In a seventeenth aspect of the present disclosure, for example, the imaging device according to the fifteenth aspect may further include a first subsequent transistor having a gate electrode, a source, and a drain, The first imaging cell may further include a first amplifying transistor having a gate electrode, a source, and a drain; The second imaging cell may further include a specific capacitor; The first capacitor may be electrically connected to the specific capacitor; The first charge accumulation unit may be electrically connected to the gate electrode of the first amplification transistor, When the first subsequent transistor is turned on, the first capacitor, one of the source and the drain of the first subsequent transistor, the other of the source and the drain of the first subsequent transistor, and the gate electrode of the first amplification transistor may be electrically connected in this order.

[0042] According to the seventeenth aspect, not only the first capacitor but also the specific capacitor contributes to a wide dynamic range, and it is easy to suppress misalignment.

[0043] In an eighteenth aspect of the present disclosure, for example, in the imaging device according to any one of the fourteenth to seventeenth aspects, The second imaging cell may further include a second capacitor and a second intervening transistor having a gate electrode, a source, and a drain; the gate electrode of the second intermediate transistor and one of the source and the drain of the second intermediate transistor may be electrically connected to the second charge accumulation section; When the second intervening transistor is turned on, the second charge storage unit and the second capacitor may be electrically connected to each other.

[0044] According to the eighteenth aspect, the light amount range in which the signal-to-noise ratio is high can be widened.

[0045] In a nineteenth aspect of the present disclosure, for example, in the imaging device according to any one of the fourteenth to eighteenth aspects, The first imaging cell may include a first microlens; The second imaging cell may include a second microlens; In a plan view, the area of ​​the second microlens may be larger than the area of ​​the first microlens.

[0046] According to the nineteenth aspect, it is easy to make the sensitivity of the second imaging cell higher than the sensitivity of the first imaging cell.

[0047] In a twentieth aspect of the present disclosure, for example, in the imaging device according to any one of the fourteenth to nineteenth aspects, the sensitivity of the second imaging cell may be higher than the sensitivity of the first imaging cell.

[0048] According to the twentieth aspect, a wide dynamic range can be easily achieved.

[0049] In the embodiments, terms such as "upper" and "lower" are used merely to specify the relative positions of components, and are not intended to limit the orientation of the imaging device when in use.

[0050] In the embodiments, the imaging device may have a flat shape. Specifically, the imaging device may be a flat chip. In the first definition, "planar view" refers to a view from the thickness direction of the imaging device. In the second definition, "planar view" refers to a view from the thickness direction of the gate electrode of the first intervening transistor. In the third definition, "planar view" refers to a view from the thickness direction of the semiconductor substrate. In the embodiments, if something can be said to be a "planar view" based on at least one of the first definition, the second definition, and the third definition, it will be treated as a "planar view."

[0051] In the following embodiments, adjustments of each element due to the difference in the polarity of the signal charge, such as changing the conductivity type of the impurity region, can be made as appropriate. Furthermore, terminology can be replaced as appropriate due to the difference in the polarity of the signal charge.

[0052] The imaging device according to an embodiment of the present disclosure is used, for example, in an in-vehicle camera for sensing. For example, by operating the first imaging cell and the second imaging cell at different frame rates, it becomes possible to acquire sensing data at high speed.

[0053] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component arrangements and connection forms, steps, step orders, etc. shown in the following embodiments are merely examples and are not intended to limit the present disclosure. The various aspects described in this specification can be combined with each other as long as no contradiction occurs. Furthermore, among the components in the following embodiments, components that are not recited in independent claims that represent the highest concept will be described as optional components. In the following description, components having substantially the same functions will be designated by common reference symbols, and their description may be omitted.

[0054] (First embodiment) The structure of an imaging device 100 according to this embodiment will be described with reference to Figs. 1 to 3. Fig. 1 is a block diagram schematically showing an example of the structure of the imaging device 100. Fig. 2 is a schematic diagram showing a first signal processing circuit P1 and a second signal processing circuit P2 according to this embodiment. Fig. 3 is a schematic diagram showing an example of the circuit configuration of a pixel 1 according to this embodiment. The pixel 1 may also be referred to as a unit pixel.

[0055] In the following example, a p-type silicon substrate is used as the semiconductor substrate. Positive charges are used as the signal charges. Specifically, holes are used as the signal charges. Transistors M10, M11, M12, M16, M17, M20, M21, M22, and M23 are n-type transistors. Specifically, these transistors are n-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).

[0056] However, negative charges may be used as the signal charges. Specifically, electrons may be used as the signal charges. In this case, p-type transistors may be used as the transistors M10, M11, M12, M16, M17, M20, M21, M22, and M23. Specifically, p-type MOSFETs may be used as these transistors.

[0057] (Structure of imaging device 100) As shown in Fig. 1, the imaging device 100 includes a plurality of pixels 1. The plurality of pixels 1 are arranged two-dimensionally. In reality, several million pixels 1 may be arranged two-dimensionally. Fig. 1 shows four of the pixels 1. These four pixels 1 are arranged in a 2 x 2 matrix.

[0058] The imaging device 100 may be a line sensor. In this case, the plurality of pixels 1 may be arranged one-dimensionally. Specifically, in this case, the plurality of pixels 1 may be arranged in the row direction or the column direction.

[0059] In the imaging device 100, one pixel 1 includes a first imaging cell 1a and a second imaging cell 1b.

[0060] 2 and 3, the first imaging cell 1a includes a first microlens ML1, a first photoelectric conversion unit PC1, and a first charge accumulation unit FD1. The first microlens ML1 and the first photoelectric conversion unit PC1 are provided above a semiconductor substrate (not shown). The first charge accumulation unit FD1 is a diffusion region provided within the semiconductor substrate.

[0061] Light is incident on the first photoelectric conversion unit PC1 through the first microlens ML1. The first photoelectric conversion unit PC1 converts this light into electric charges. The first charge accumulation unit FD1 accumulates these electric charges. As the accumulation of electric charges in the first charge accumulation unit FD1 progresses, the potential of the first charge accumulation unit FD1 increases.

[0062] In this embodiment, the first photoelectric conversion unit PC1 has a pair of electrodes E1a and E1b and a first photoelectric conversion layer D1. The first photoelectric conversion layer D1 is disposed between the pair of electrodes E1a and E1b. One of the pair of electrodes E1a and E1b is a first upper electrode E1a corresponding to a first electrode. The other of the pair of electrodes E1a and E1b is a first pixel electrode E1b corresponding to a second electrode. The first upper electrode E1a faces the first pixel electrode E1b. The first upper electrode E1a may also be referred to as a first opposing electrode.

[0063] A voltage can be applied to the first upper electrode E1a. This generates a potential difference between the pair of electrodes E1a and E1b. This applies an electric field to the first photoelectric conversion layer D1. This causes signal charges generated by photoelectric conversion in the first photoelectric conversion layer D1 to be guided to the first pixel electrode E1b. The signal charges are then sent from the first pixel electrode E1b to the first charge storage unit FD1 and stored in the first charge storage unit FD1.

[0064] In this embodiment, the first photoelectric conversion layer D1 is a photoelectric conversion film. Specifically, the first photoelectric conversion layer D1 is an organic film. However, the first photoelectric conversion layer D1 may also be an inorganic film.

[0065] In this embodiment, the first upper electrode E1a is a transparent electrode, which is, for example, an ITO (Indium Thin Oxide) film.

[0066] The first photoelectric conversion unit PC1 may be a photodiode. The first photoelectric conversion unit PC1 that is a photodiode may be provided in a semiconductor substrate. An aspect in which the first photoelectric conversion unit PC1 is a photodiode will be described in detail in the ninth embodiment.

[0067] The first imaging cell 1a may have a first light-shielding portion that blocks light from entering the first photoelectric conversion unit PC1. The first imaging cell 1a may have a first waveguide that guides light to the first photoelectric conversion unit PC1.

[0068] The second imaging cell 1b includes a second microlens ML2, a second photoelectric conversion unit PC2, and a second charge accumulation unit FD2. The second microlens ML2 and the second photoelectric conversion unit PC2 are provided above a semiconductor substrate (not shown). The second charge accumulation unit FD2 is a diffusion region provided within the semiconductor substrate.

[0069] Light is incident on the second photoelectric conversion unit PC2 through the second microlens ML2. The second photoelectric conversion unit PC2 converts this light into electric charges. The second charge accumulation unit FD2 accumulates these electric charges. As the accumulation of electric charges in the second charge accumulation unit FD2 progresses, the potential of the second charge accumulation unit FD2 increases.

[0070] In this embodiment, the second photoelectric conversion unit PC2 has a pair of electrodes E2a and E2b and a second photoelectric conversion layer D2. The second photoelectric conversion layer D2 is disposed between the pair of electrodes E2a and E2b. One of the pair of electrodes E2a and E2b is a second upper electrode E2a. The other of the pair of electrodes E2a and E2b is a second pixel electrode E2b. The second upper electrode E2a faces the second pixel electrode E2b. The second upper electrode E2a may also be referred to as a second opposing electrode.

[0071] A voltage can be applied to the second upper electrode E2a. This generates a potential difference between the pair of electrodes E2a and E2b. This applies an electric field to the second photoelectric conversion layer D2. This causes signal charges generated by photoelectric conversion in the second photoelectric conversion layer D2 to be guided to the second pixel electrode E2b. The signal charges are then sent from the second pixel electrode E2b to the second charge accumulation unit FD2 and accumulated in the second charge accumulation unit FD2.

[0072] In this embodiment, the second photoelectric conversion layer D2 is a photoelectric conversion film. Specifically, the second photoelectric conversion layer D2 is an organic film. However, the second photoelectric conversion layer D2 may also be an inorganic film.

[0073] In this embodiment, the second upper electrode E2a is a transparent electrode, such as an ITO film.

[0074] The second photoelectric conversion unit PC2 may be a photodiode. The second photoelectric conversion unit PC2 that is a photodiode may be provided in a semiconductor substrate. An aspect in which the second photoelectric conversion unit PC2 is a photodiode will be described in detail in the ninth embodiment.

[0075] The second imaging cell 1b may have a second light-shielding portion that blocks light from entering the second photoelectric conversion unit PC2. The second imaging cell 1b may have a second waveguide that guides light to the second photoelectric conversion unit PC2.

[0076] The first imaging cell 1a and the second imaging cell 1b may have different structures. Specifically, the imaging device 100 may have at least one feature selected from the features listed below. These features may contribute to making the sensitivity of the second imaging cell 1b higher than that of the first imaging cell 1a. In a plan view, the area of ​​the second microlens ML2 is larger than the area of ​​the first microlens ML1. In a plan view, the area of ​​the second photoelectric conversion unit PC2 is larger than the area of ​​the first photoelectric conversion unit PC1. In a plan view, the area of ​​the second pixel electrode E2b is larger than the area of ​​the first pixel electrode E1b. In a plan view, the area of ​​the second light-shielding portion is smaller than the area of ​​the first light-shielding portion. In plan view, the area of ​​the light entrance of the second waveguide is smaller than the area of ​​the light entrance of the first waveguide. The geometric center of the second photoelectric conversion unit PC2 in plan view is located on the optical axis of the second microlens ML2.

[0077] The first imaging cell 1a and the second imaging cell 1b can have different functions. Specifically, in this embodiment, the amount of light taken in per unit time by the second photoelectric conversion unit PC2 is greater than the amount of light taken in per unit time by the first photoelectric conversion unit PC1.

[0078] The first imaging cell 1a and the second imaging cell 1b may have different characteristics. Specifically, the imaging device 100 may have at least one feature selected from the features listed below. In this embodiment, the imaging device 100 has all of the features listed below. The second imaging cell 1b has higher sensitivity than the first imaging cell 1a. The second imaging cell 1b has lower noise than the first imaging cell 1a. The first imaging cell 1a is more saturated than the second imaging cell 1b.

[0079] The expression "the second imaging cell 1b has higher sensitivity than the first imaging cell 1a" will be explained. In this embodiment, this expression means that the second signal charge amount is greater than the first signal charge amount when a certain amount of white light is incident on the imaging device 100. The second signal charge amount is the amount of signal charge generated when light incident on the second imaging cell 1b is photoelectrically converted by the second photoelectric conversion unit PC2. The first signal charge amount is the amount of signal charge generated when light incident on the first imaging cell 1a is photoelectrically converted by the first photoelectric conversion unit PC1. The sensitivity depends on the photoelectric conversion unit, pixel electrode, waveguide, microlens, and light-shielding unit.

[0080] The ratio Sen2 / Sen1 of the sensitivity Sen2 of the second imaging cell 1b to the sensitivity Sen1 of the first imaging cell 1a is, for example, 3 or more. The ratio Sen2 / Sen1 may be 7 or more, or may be 10 or more. The ratio Sen2 / Sen1 is, for example, 200 or less. The ratio Sen2 / Sen1 may be 100 or less.

[0081] The expression "the second imaging cell 1b has lower noise than the first imaging cell 1a" will be explained. In this embodiment, this expression means that when a certain amount of white light is incident on the imaging device 100, the S / N ratio of the pixel signal derived from the light incident on the second imaging cell 1b is greater than the S / N ratio of the pixel signal derived from the light incident on the first imaging cell 1a. The pixel signal is a signal that is output to a peripheral circuit.

[0082] The expression "the first imaging cell 1a is more saturated than the second imaging cell 1b" will be explained. In this embodiment, this expression means that the first timing appears after the second timing when the amount of white light incident on the imaging device 100 gradually increases. The first timing is the timing when the increase in the level of the pixel signal derived from the light incident on the first imaging cell 1a reaches its peak. The second timing is the timing when the increase in the level of the pixel signal derived from the light incident on the second imaging cell 1b reaches its peak.

[0083] In this embodiment, the second imaging cell 1b is responsible for capturing images of dark scenes. Therefore, the second imaging cell 1b does not need to have high saturation characteristics. On the other hand, the second imaging cell 1b needs to have low noise characteristics.

[0084] In contrast, the first imaging cell 1a is responsible for capturing images of bright scenes. Therefore, it is relatively important that the first imaging cell 1a have high saturation characteristics. On the other hand, it is relatively less important that the first imaging cell 1a have low noise characteristics. This is because when capturing images of bright scenes, the amount of light is large and unavoidable shot noise becomes the dominant noise.

[0085] The imaging device 100 includes a plurality of first reset signal lines 6a, a plurality of first address signal lines 7a, a plurality of first vertical signal lines 9a, a first power supply wiring 8a, and a plurality of first feedback signal lines 10a. These are elements for the first imaging cells 1a. The first reset signal lines 6a are arranged for each row. The first address signal lines 7a are arranged for each row. The first vertical signal lines 9a are arranged for each column. The first power supply wiring 8a is arranged for each column. The first feedback signal lines 10a are arranged for each column.

[0086] The imaging device 100 includes a plurality of second reset signal lines 6b, a plurality of second address signal lines 7b, a plurality of second vertical signal lines 9b, second power supply wiring 8b, and a plurality of second feedback signal lines 10b. These are elements for the second imaging cells 1b. The second reset signal lines 6b are arranged for each row. The second address signal lines 7b are arranged for each row. The second vertical signal lines 9b are arranged for each column. The second power supply wiring 8b is arranged for each column. The second feedback signal lines 10b are arranged for each column.

[0087] The imaging device 100 is provided with a first peripheral circuit and a second peripheral circuit. The first peripheral circuit processes signals from the first imaging cell 1a. The second peripheral circuit processes signals from the second imaging cell 1b.

[0088] The first peripheral circuit includes a first vertical scanning circuit 2a, a first horizontal scanning circuit 3a, a first inverting amplifier 11a, a first column AD (Analog to Digital) conversion circuit 4a, and a first current source 5a. The second peripheral circuit includes a second vertical scanning circuit 2b, a second horizontal scanning circuit 3b, a second inverting amplifier 11b, a second column AD conversion circuit 4b, and a second current source 5b.

[0089] For the first imaging cell 1a, the first vertical scanning circuit 2a controls a plurality of first reset signal lines 6a and a plurality of first address signal lines 7a. The first vertical signal line 9a is connected to the first horizontal scanning circuit 3a. The first vertical signal line 9a transmits pixel signals to the first horizontal scanning circuit 3a. Specifically, the first column AD conversion circuit 4a is provided on the first vertical signal line 9a. The first column AD conversion circuit 4a converts analog pixel signals into digital pixel signals and provides them to the first horizontal scanning circuit 3a. The first power supply wiring 8a supplies a power supply voltage to the first imaging cell 1a of all pixels 1. The power supply voltage is, for example, Vdd. The first inverting amplifier 11a is connected to the first vertical signal line 9a. The first feedback signal line 10a transmits a feedback signal from the first inverting amplifier 11a to the first imaging cell 1a of the pixel 1. The first current source 5a, in cooperation with the first amplifying transistor M10, forms a source follower circuit.

[0090] For the second imaging cells 1b, the second vertical scanning circuit 2b controls a plurality of second reset signal lines 6b and a plurality of second address signal lines 7b. The second vertical signal line 9b is connected to the second horizontal scanning circuit 3b. The second vertical signal line 9b transmits pixel signals to the second horizontal scanning circuit 3b. Specifically, the second column AD conversion circuit 4b is provided on the second vertical signal line 9b. The second column AD conversion circuit 4b converts analog pixel signals into digital pixel signals and provides them to the second horizontal scanning circuit 3b. The second power supply wiring 8b supplies a power supply voltage to the second imaging cells 1b of all pixels 1. The power supply voltage is, for example, Vdd. The second inverting amplifier 11b is connected to the second vertical signal line 9b. The second feedback signal line 10b transmits a feedback signal from the second inverting amplifier 11b to the second imaging cells 1b of the pixel 1. The second current source 5b, in cooperation with the second amplifying transistor M20, forms a source follower circuit.

[0091] The reset signal lines 6a and 6b can be shared, depending on the configuration of the pixel 1. The same applies to the address signal lines 7a and 7b. The feedback signal lines 10a and 10b can be shared or omitted, depending on the configuration of the pixel 1. The same applies to the inverting amplifiers 11a and 11b, the vertical scanning circuits 2a and 2b, and the horizontal scanning circuits 3a and 3b.

[0092] The first inverting amplifier 11a may be provided for each column, may be provided in each pixel 1, or may be provided for a plurality of pixels 1. The same applies to the second inverting amplifier 11b.

[0093] (Circuit configuration of the first imaging cell 1a and the second imaging cell 1b) An example of the circuit configuration of the first imaging cell 1a and the second imaging cell 1b in the pixel 1 will be described with reference to FIGS.

[0094] The first imaging cell 1a functions as a highly saturated cell. The first imaging cell 1a has a first photoelectric conversion unit PC1 and a first signal processing circuit P1. The first photoelectric conversion unit PC1 converts light into signal charges. The first signal processing circuit P1 is electrically connected to the first photoelectric conversion unit PC1. The first signal processing circuit P1 reads out an electrical signal corresponding to the signal charges generated by the first photoelectric conversion unit PC1.

[0095] The first signal processing circuit P1 includes a first amplification transistor M10, a first selection transistor M11, and a first reset transistor M12.

[0096] The gate electrode of the first amplification transistor M10, the first charge accumulation unit FD1, and the first photoelectric conversion unit PC1 are electrically connected. In this embodiment, the first charge accumulation unit FD1 is one of the source and drain of the first reset transistor M12. However, the first charge accumulation unit FD1 may be a separate element from the first reset transistor M12 that is electrically connected to the gate electrode of the first amplification transistor M10 and the first photoelectric conversion unit PC1. One of the source and drain of the first selection transistor M11, one of the source and drain of the first amplification transistor M10, and the other of the source and drain of the first reset transistor M12 are electrically connected. The other of the source and drain of the first selection transistor M11 is electrically connected to a first voltage line VDD1. The other of the source and drain of the first amplification transistor M10 is electrically connected to a first signal line Out1.

[0097] The first amplification transistor M10 amplifies an electrical signal corresponding to the signal charge generated by the first photoelectric conversion unit PC1. The first selection transistor M11 selectively outputs the signal amplified by the first amplification transistor M10. The first reset transistor M12 resets the first charge accumulation unit FD1 connected to the first pixel electrode E1b of the first photoelectric conversion unit PC1.

[0098] The imaging device 100 includes a first intervening transistor M16, a first subsequent transistor M17, and a first capacitor Cs3. Specifically, the first imaging cell 1a includes the first intervening transistor M16, the first subsequent transistor M17, and a first capacitor Cs3. More specifically, the first signal processing circuit P1 includes the first intervening transistor M16, the first subsequent transistor M17, and a first capacitor Cs3.

[0099] In this embodiment, the first intervening transistor M16 may also be referred to as a first charge injection transistor. Specifically, the first intervening transistor M16 may also be referred to as a first electron injection transistor. The first subsequent transistor M17 may also be referred to as a first short transistor.

[0100] In this embodiment, the first charge accumulation unit FD1 is electrically connected to the gate electrode of the first intervening transistor M16 and one of the source and drain of the first intervening transistor M16. When the first intervening transistor M16 is turned on, the first charge accumulation unit FD1 and the first capacitor Cs3 are electrically connected via the first intervening transistor M16. This configuration is suitable for suppressing a decrease in the signal-to-noise ratio (SN ratio) that accompanies a decrease in the amount of light incident on the image capture device 100.

[0101] In this embodiment, when the first subsequent transistor M17 is turned on, the first capacitor Cs3, one of the source and drain of the first subsequent transistor M17, and the other of the source and drain of the first subsequent transistor M17 are electrically connected in this order.

[0102] In this embodiment, the other of the source and drain of the first intermediate transistor M16 is electrically connected to the first capacitor Cs3. One of the source and drain of the first subsequent transistor M17 is electrically connected to the first capacitor Cs3. The other of the source and drain of the first subsequent transistor M17 is electrically connected to the first charge storage unit FD1.

[0103] In this embodiment, the first charge storage unit FD1 is electrically connected to the gate electrode of the first amplification transistor M10. When the first subsequent transistor M17 is turned on, the first capacitor Cs3, one of the source and drain of the first subsequent transistor M17, the other of the source and drain of the first subsequent transistor M17, and the gate electrode of the first amplification transistor M10 are electrically connected in this order.

[0104] In this embodiment, the capacitance value of the first capacitor Cs3 is larger than the capacitance value of the first charge storage unit FD1. This is suitable for realizing a wide dynamic range imaging device 100. The ratio c3 / c1 of the capacitance value c3 of the first capacitor Cs3 to the capacitance value c1 of the first charge storage unit FD1 is, for example, 3 or more. The ratio c3 / c1 may be 6 or more, or may be 10 or more. The ratio c3 / c1 is, for example, 1000 or less. The ratio c3 / c1 may be 100 or less, or may be 50 or less.

[0105] The term "capacitor" will be explained. A capacitor is a concept that does not include parasitic capacitance. Parasitic capacitance is a concept that includes a diffusion region provided in a semiconductor substrate. A capacitor is more suitable for ensuring a capacitance value than parasitic capacitance. A typical example of a capacitor has a structure in which a dielectric such as an insulating film is sandwiched between electrodes. In this context, an electrode is not limited to an electrode made of metal, but should be interpreted to broadly include a polysilicon layer, etc. In this context, an electrode may be a part of a semiconductor substrate.

[0106] In this embodiment, the first capacitor Cs3 has a metal-insulator-metal structure (hereinafter abbreviated as MIM structure). This is suitable for realizing a high-density capacitor. The "M" in MIM refers to at least one of a metal and a metal compound. The "I" in MIM refers to an insulator, such as an oxide. In other words, MIM is a concept that encompasses MOM (Metal Oxide Metal).

[0107] An example of the insulating material of the first capacitor Cs3 is silicon oxide. Another example of the insulating material of the first capacitor Cs3 is a so-called high-k material, which has a higher dielectric constant than silicon oxide. The high-k material makes it easier to increase the capacitance value of the first capacitor Cs3. In one specific example, the insulating material of the first capacitor Cs3 contains hafnium (Hf) oxide or zirconium (Zr) oxide as a main component. Here, the main component refers to the component that is contained most abundantly by mass. In one example, the main component is a component that accounts for more than 50 mass%. In one specific example, the main component is a component that accounts for more than 80 mass%.

[0108] In this embodiment, when the first intervening transistor M16 is turned on, the first charge storage unit FD1 is electrically connected to one end of the first capacitor Cs3 via the first intervening transistor M16. A DC potential VBW1 is applied to the other end of the first capacitor Cs3. The DC potential VBW1 may be a potential biased from the ground potential or may be the ground potential.

[0109] Hereinafter, the portion of the first capacitor Cs3 that is electrically connected to the first intervening transistor M16 may be referred to as the first portion FD3.

[0110] In this embodiment, the imaging device 100 can be in a first state and a second state. In the first state, the first charge storage unit FD1 and the first capacitor Cs3 are electrically connected via the first intervening transistor M16. In the second state, no capacitor is electrically connected to the first charge storage unit FD1. This configuration is suitable for suppressing a decrease in the signal-to-noise ratio associated with a decrease in the amount of light.

[0111] In this embodiment, the second state can be described as a state in which only a parasitic capacitance exists as a capacitance component electrically connected to the first charge accumulation unit FD1.

[0112] In this embodiment, the conductivity type of the gate electrode of the first intervening transistor M16 is opposite to the conductivity type of the source and drain of the first intervening transistor M16. This configuration can reduce the depletion layer under the gate electrode of the first intervening transistor M16. Therefore, this configuration makes it easier to suppress dark current. Specifically, in this embodiment, the conductivity type of the gate electrode of the first intervening transistor M16 is p-type. The conductivity type of the source and drain of the first intervening transistor M16 is n-type. The gate electrode of the first intervening transistor M16 is, for example, a polysilicon electrode.

[0113] The gate length of the first intervening transistor M16 may be longer than the gate length of the first subsequent transistor M17. The gate length of the first intervening transistor M16 may be the same as the gate length of the first subsequent transistor M17. The gate length of the first intervening transistor M16 may be shorter than the gate length of the first subsequent transistor M17. Here, the gate length refers to the dimension of the gate electrode in the direction from the source to the drain or from the drain to the source.

[0114] The gate width of the first intervening transistor M16 may be longer than the gate width of the first subsequent transistor M17. The gate width of the first intervening transistor M16 may be the same as the gate width of the first subsequent transistor M17. The gate width of the first intervening transistor M16 may be shorter than the gate width of the first subsequent transistor M17. Here, the gate width refers to the dimension of the gate electrode in a direction perpendicular to the gate length direction in a plan view.

[0115] The gate thickness of the first intervening transistor M16 may be greater than the gate thickness of the first subsequent transistor M17. The gate thickness of the first intervening transistor M16 may be the same as the gate thickness of the first subsequent transistor M17. The gate thickness of the first intervening transistor M16 may be smaller than the gate thickness of the first subsequent transistor M17. Here, the gate thickness refers to the thickness of the gate electrode.

[0116] The second imaging cell 1b functions as a low-noise cell. The second imaging cell 1b has a second photoelectric conversion unit PC2 and a second signal processing circuit P2. The second photoelectric conversion unit PC2 converts light into signal charges. The second signal processing circuit P2 is electrically connected to the second photoelectric conversion unit PC2. The second signal processing circuit P2 reads out an electrical signal corresponding to the signal charges generated by the second photoelectric conversion unit PC2.

[0117] The second signal processing circuit P2 includes a second amplification transistor M20, a second selection transistor M21, a second reset transistor M22, a band control transistor M23, a capacitor Cc1, and a capacitor Cs1.

[0118] The gate electrode of the second amplification transistor M20, the second charge accumulation unit FD2, the second photoelectric conversion unit PC2, and one end of the capacitor Cc1 are electrically connected. In this embodiment, the second charge accumulation unit FD2 is one of the source and drain of the second reset transistor M22. However, the second charge accumulation unit FD2 may be a separate element from the second reset transistor M22 that is electrically connected to the gate electrode of the second amplification transistor M20 and the second photoelectric conversion unit PC2. One of the source and drain of the second selection transistor M21, one of the source and drain of the second amplification transistor M20, and one of the source and drain of the band control transistor M23 are electrically connected. The other of the source and drain of the second selection transistor M21 is electrically connected to a second voltage line VDD2. The other of the source and drain of the second reset transistor M22, the other of the source and drain of the band control transistor M23, the other end of the capacitor Cc1, and one end of the capacitor Cs1 are electrically connected. A DC potential VB1 is applied to the other end of the capacitor Cs1.

[0119] The second amplification transistor M20 amplifies an electrical signal corresponding to the signal charge generated by the second photoelectric conversion unit PC2. The second selection transistor M21 selectively outputs the signal amplified by the second amplification transistor M20. The second reset transistor M22 resets the second charge storage unit FD2 connected to the second pixel electrode E2b of the second photoelectric conversion unit PC2. The band control transistor M23, capacitors Cc1 and Cs1 are used to suppress kTC noise that occurs when the second reset transistor M22 is turned off. For details of the technology for suppressing kTC noise, see Patent Document 4, etc.

[0120] The operation of the imaging device 100 of this embodiment will be described below with reference to Fig. 4. Fig. 4 shows a timing chart illustrating the operation of the imaging device 100 of this embodiment.

[0121] 4, period 1H is one control cycle period for one row of a matrix made up of multiple pixels 1. Times t1, t2, t3, t4, t5, t6, and t7 belong to period 1H. Times t1, t2, t3, t4, t5, t6, and t7 appear in this order.

[0122] Voltage Vsel2 is the voltage of the gate electrode of the second selection transistor M21. Voltage Vrs2 is the voltage of the gate electrode of the second reset transistor M22. Voltage Vrs3 is the voltage of the gate electrode of the band control transistor M23. Voltage Vsel1 is the voltage of the gate electrode of the first selection transistor M11. Voltage Vrs1 is the voltage of the gate electrode of the first reset transistor M12. Voltage Vst is the voltage of the gate electrode of the first subsequent transistor M17.

[0123] In the example of FIG. 4, voltages Vsel2, Vrs2, Vrs3, Vsel1, Vrs1, and Vst basically change in two stages: low and high. However, these voltages may change in more stages. Specifically, in the example of FIG. 4, voltage Vrs3 changes to a middle level at time t6. The middle level is a level between low and high. A configuration in which voltage Vrs3 changes in two stages: low and high may also be employed. In one example of this configuration, voltage Vrs3 changes to a high level at time t6.

[0124] In the example of FIG. 4, at time t1, the voltage Vsel2 is at a high level. Therefore, the second selection transistor M21 is in an on state. The voltage Vrs2 is at a low level. Therefore, the second reset transistor M22 is in an off state. The voltage Vrs3 is at a low level. Therefore, the band control transistor M23 is in an off state. The voltage Vsel1 is at a high level. Therefore, the first selection transistor M11 is in an on state. The voltage Vrs1 is at a low level. Therefore, the first reset transistor M12 is in an off state. The voltage Vst is at a low level. Therefore, the first subsequent transistor M17 is in an off state.

[0125] At time t1, an electrical signal corresponding to the signal charge accumulated in the second charge accumulation unit FD2 is output to the second peripheral circuit via the second amplification transistor M20 and the second signal line Out2 in this order. Hereinafter, this electrical signal will be referred to as the pixel signal of the second charge accumulation unit FD2 or the second pixel signal V FD2 In this embodiment, the second pixel signal V FD2 is a voltage corresponding to the potential of the second charge storage unit FD2. FD2 The level of increases continuously as the amount of light incident on the imaging device 100 increases. The second signal line Out2 is connected to the second vertical signal line 9b shown in FIG.

[0126] At time t1, an electrical signal corresponding to the signal charge stored in the first charge storage unit FD1 is output to the first peripheral circuit via the first amplification transistor M10 and the first signal line Out1 in this order. Hereinafter, this electrical signal will be referred to as the pixel signal of the first charge storage unit FD1 or the first pixel signal V FD1 In this embodiment, the first pixel signal V FD1 is a voltage corresponding to the potential of the first charge accumulation unit FD1. The level of this electrical signal increases continuously as the amount of light incident on the imaging device 100 increases. The first signal line Out1 is connected to the first vertical signal line 9a shown in FIG.

[0127] After time t1, the voltage Vst is changed from low to high, turning on the first subsequent transistor M17. Therefore, at time t2, the first subsequent transistor M17 is in the on state. Therefore, at time t2, the first charge storage unit FD1 and the first portion FD3 are electrically connected via the first subsequent transistor M17.

[0128] At time t2, an electrical signal corresponding to the potential of the first charge storage unit FD1 and the potential of the first portion FD3 is output to the first peripheral circuit via the first amplification transistor M10 and the first signal line Out1 in this order. The level of this electrical signal continuously increases as the amount of light incident on the image pickup device 100 increases.

[0129] The electrical signal output at time t2 will be further described. In this embodiment, the capacitance value of the first capacitor Cs3 is greater than the capacitance value of the first charge storage unit FD1. Therefore, an electrical signal corresponding to a composite potential in which the potential of the first capacitor Cs3 is more strongly reflected than the potential of the first charge storage unit FD1 is output to the first peripheral circuit via the first amplification transistor M10 and the first signal line Out1, in this order.

[0130] The composite potential will be explained using numerical examples. When the light intensity is low, the potential of the first charge accumulation unit FD1 is 1 V, the potential of the first portion FD3 is 0 V, their composite potential is 0.1 V, and an electrical signal corresponding to this composite potential is output. When the light intensity increases slightly, the potential of the first charge accumulation unit FD1 is 2 V, the potential of the first portion FD3 is 0 V, their composite potential is 0.2 V, and an electrical signal corresponding to this composite potential is output. When the light intensity increases further, the potential of the first charge accumulation unit FD1 is 3 V, the potential of the first portion FD3 is 0.6 V, their composite potential is 0.8 V, and an electrical signal corresponding to this composite potential is output.

[0131] In this embodiment, the electrical signal corresponding to the composite potential is converted into the pixel signal of the first portion FD3 or the third pixel signal V FD3 It is sometimes referred to as.

[0132] At time t3, the voltages Vrs2 and Vrs3 are changed from low level to high level, turning on the second reset transistor M22 and the band control transistor M23, thereby resetting the potential of the second charge accumulation section FD2.

[0133] At time t3, the voltage Vrs1 is changed from low to high to turn on the first reset transistor M12, thereby resetting the potential of the first charge storage section FD1 and the potential of the first capacitor Cs3, i.e., the potential of the first section FD3.

[0134] At time t4, an electrical signal corresponding to the potential of the first charge storage unit FD1 and the potential of the first portion FD3 is output to the first peripheral circuit via the first amplification transistor M10 and the first signal line Out1, in this order. This electrical signal is a reset signal related to the composite potential. In this embodiment, the reset signal related to the composite potential is referred to as a reset signal for the first portion FD3.

[0135] After time t4, the voltage Vst is changed from high to low, turning off the first subsequent transistor M17. Therefore, at time t5, the first subsequent transistor M17 is in the off state. Therefore, at time t5, the electrical connection between the first charge storage unit FD1 and the first portion FD3 via the first subsequent transistor M17 is released.

[0136] At time t5, an electrical signal corresponding to the potential of the first charge storage unit FD1 is output to the first peripheral circuit via the first amplification transistor M10 and the first signal line Out1 in this order. This electrical signal is a reset signal for the first charge storage unit FD1.

[0137] After time t5, the voltage Vsel1 is changed from high to low to turn off the first selection transistor M11, so that at time t6 the first selection transistor M11 is in the off state.

[0138] At time t6, Vrs3 is changed from low level to middle level, which can reduce kTC noise in the second charge accumulation unit FD2 when the second reset transistor M22 is turned off.

[0139] At time t7, an electrical signal corresponding to the potential of the second charge storage unit FD2 is output to the second peripheral circuit via the second amplification transistor M20 and the second signal line Out2 in this order. This electrical signal is a reset signal for the second charge storage unit FD2.

[0140] After that, the second pixel signal V FD2 The reset signal of the second charge storage unit FD2 is subtracted from the second pixel signal V FD2 The noise of the first pixel signal V of the first charge storage unit FD1 is reduced. FD1 The reset signal of the first charge storage unit FD1 is subtracted from the first pixel signal V FD1 In addition, the noise of the third pixel signal V FD3The reset signal of the first portion FD3 is subtracted from the third pixel signal V FD3 The noise is reduced.

[0141] 4, in this embodiment, a signal corresponding to the potential of the first capacitor Cs3 is read out, and then a signal corresponding to the potential of the first charge storage unit FD1 is read out. Specifically, the signal corresponding to the potential of the first capacitor Cs3 is read out as the third pixel signal V FD3 The signal corresponding to the potential of the first charge storage unit FD1 is the first pixel signal V FD1 is.

[0142] 5A to 5C show the potential of the first charge storage section FD1, the potential under the gate of the first intervening transistor M16, and the potential of the first portion FD3. Changes in the potential of the first portion FD3 will be described below with reference to FIGS. 5A to 5C. As described above, the signal charge in this embodiment is a positive charge, specifically a hole. Therefore, FIGS. 5A to 5C also relate to the case where the signal charge is a positive charge.

[0143] 5A shows the potential of the first charge storage unit FD1, the potential under the gate of the first intervening transistor M16, and the potential of the first portion FD3 when the amount of light incident on the imaging device 100 is low. In this state, the first intervening transistor M16 is in an off state. The potential under the gate of the first intervening transistor M16 is lower than the potential of the first portion FD3. The potential of the first charge storage unit FD1 is higher than the potential of the first portion FD3.

[0144] As the amount of light increases, the signal charge generated by photoelectric conversion in the first photoelectric conversion unit PC1 increases. The first charge accumulation unit FD1 is electrically connected to the first photoelectric conversion unit PC1. Therefore, the potential of the first charge accumulation unit FD1 increases. The first charge accumulation unit FD1 is electrically connected to the gate electrode of the first intermediate transistor M16. Therefore, as the potential of the first charge accumulation unit FD1 increases, the potential under the gate of the first intermediate transistor M16 also increases.

[0145] When the amount of light further increases and the potential of the gate electrode of the first intermediate transistor M16 exceeds the first threshold potential, the first intermediate transistor M16 turns on, thereby electrically connecting the first charge accumulation unit FD1 and the first portion FD3 via the first intermediate transistor M16.

[0146] As the amount of light increases further, the potential of the first charge storage unit FD1 increases further. Accordingly, the potential under the gate of the first intervening transistor M16 also increases. Eventually, the potential under the gate of the first intervening transistor M16 becomes higher than the potential of the first portion FD3. Similar to the situation in FIG. 5A, the potential of the first charge storage unit FD1 is higher than the potential of the first portion FD3. A situation in which the magnitude relationship between these potentials holds is shown in FIG. 5B.

[0147] In the situation shown in Figure 5B, negative charges are injected from the first portion FD3 to the first charge storage unit FD1 via the first intervening transistor M16. Specifically, the negative charges are electrons. The arrows in Figure 5B schematically represent the injection of negative charges.

[0148] The injection of negative charges described above decreases the potential of the first charge storage portion FD1. Accordingly, the potential under the gate of the first intervening transistor M16 also decreases. Meanwhile, the potential of the first portion FD3 increases. Figure 5C shows a schematic representation of this change due to the injection of negative charges. Specifically, the potential before the injection of negative charges is shown by a dotted line, and the potential after the injection of negative charges is shown by a solid line.

[0149] In this embodiment, the injection of negative charges balances the potential of the first charge storage unit FD1 and the potential of the first portion FD3. In a situation where the amount of light incident on the imaging device 100 increases, the potential of the first charge storage unit FD1 and the potential of the first portion FD3 may increase while maintaining this balance.

[0150] A similar phenomenon occurs when the signal charge is negative.

[0151] The following technical points can be derived from the above explanation. That is, an increase in either positive or negative charges generated by photoelectric conversion in the first photoelectric conversion unit PC1 increases either positive or negative charges accumulated in the first charge accumulation unit FD1. An increase in either positive or negative charges accumulated in the first charge accumulation unit FD1 causes either an increase or a decrease in the potential of the first charge accumulation unit FD1. As either an increase or a decrease in the potential of the first charge accumulation unit FD1 occurs, a first phenomenon and a second phenomenon occur, in this order. The first phenomenon is that the first intermediate transistor M16 turns on. The second phenomenon is the supply of the other of positive and negative charges from the first capacitor Cs3 to the first charge accumulation unit FD1 via the first intermediate transistor M16. This supply causes either an increase or a decrease in the potential of the first charge accumulation unit FD1.

[0152] As can be understood from the above description, when the amount of light increases and the potential of the gate electrode of the first intermediate transistor M16 exceeds the first threshold potential, the potential of the first portion FD3 may change. This means that the potential of the first portion FD3 may become information that changes depending on the amount of light incident on the image pickup device 100.

[0153] In this embodiment, the second pixel signal V FD2 , the first pixel signal V of the first charge storage unit FD1 FD1 and the third pixel signal V of the first portion FD3 FD3 Regarding this, the following can be said:

[0154] The second imaging cell 1b is an imaging cell with higher sensitivity, lower noise, and lower saturation than the first imaging cell 1a. The second pixel signal V FD2 The SN ratio of the second SN ratio FD2 The second SN ratio is defined as SN FD2 In a region where the amount of light incident on the imaging device 100 is low, the value increases from near zero as the amount of light increases.

[0155] The first imaging cell 1a is an imaging cell with lower sensitivity, higher noise, and higher saturation than the second imaging cell 1b. The first pixel signal V FD1 The SN ratio of the first SN ratio FD1 First, the signal-to-noise ratio (SN) is defined as FD1 is the second signal-to-noise ratio FD2 In a light intensity region where the light intensity is higher than that of the reference light, the value increases from near zero as the light intensity increases.

[0156] The first portion FD3 belongs to the first imaging cell 1a, similar to the first charge storage portion FD1. The third pixel signal V FD3 The SN ratio of the third SN ratio, FD3 The third signal-to-noise ratio (SN) is defined as FD3 is the first signal-to-noise ratio FD1 In a light intensity region where the light intensity is higher than that of the reference light, the value increases from near zero as the light intensity increases.

[0157] FIG. 6 shows the relationship between the amount of light incident on the image pickup device 100 and the second pixel signal V FD2 , the first pixel signal V FD1 and the third pixel signal V FD3 7 is a graph showing the relationship between the second SN ratio SN and the amount of light incident on the image pickup device 100. FD2 , 1st SN ratio SN FD1 and the third signal-to-noise ratio FD36 and 7 are graphs showing the relationship between the amount of light incident on the imaging device 100 and the signal level. The horizontal axis in FIGS. 6 and 7 represents the amount of light incident on the imaging device 100. The unit of this amount of light is lux. The vertical axis in FIG. 6 represents the level of the output pixel signal. The unit of this level is V (volts). The vertical axis in FIG. 7 represents the signal-to-noise ratio. The unit of this signal-to-noise ratio is dB (decibels). It can be visually understood from FIGS. 6 and 7 that this embodiment provides three output lines that change depending on the amount of light. The output lines in FIG. 6 represent the pixel signals. In FIG. 7, the output lines represent the signal-to-noise ratio.

[0158] Specifically, one of the three output lines originates from the second imaging cell 1b, which is a high-sensitivity cell. Two of the three output lines originate from the first imaging cell 1a, which is a low-sensitivity cell. In the first imaging cell 1a, when the amount of light increases, the potential of the first portion FD3 begins to change later than the potential of the first charge storage portion FD1. In this way, two output lines originating from the first imaging cell 1a are generated.

[0159] FIG. 8 is a schematic diagram showing the circuit configuration of a pixel of an imaging device according to a reference embodiment. Unlike the first imaging cell 1a of FIG. 3, the first intervening transistor M16, the first subsequent transistor M17, and the first capacitor Cs3 are not present in the first imaging cell 1c according to the reference embodiment, but instead, a capacitor CsZ is present. One end of the capacitor CsZ is electrically connected to the first charge storage unit FD1. A DC potential is applied to the other end of the capacitor CsZ. In this example, the capacitance value of the capacitor CsZ is approximately the same as the capacitance value of the first capacitor Cs3. Strictly speaking, these capacitance values ​​may be the same.

[0160] In the first imaging cell 1c of FIG. 8, the first capacitor Cs3 is not present, so the third pixel signal V FD3 On the other hand, in the first imaging cell 1c, the capacitor CsZ is electrically connected to the first charge storage unit FD1. Furthermore, the capacitance value of the capacitor CsZ is approximately the same as the capacitance value of the first capacitor Cs3. Therefore, the first pixel signal V FD1 is the third pixel signal VFD3 Also, the first SN ratio of the reference form is similar to FD1 is the third SN ratio of this embodiment FD3 Similar to.

[0161] On the other hand, the second imaging cell 1b in Fig. 8 is the same as the second imaging cell 1b in Fig. 3. Therefore, the second pixel signal V FD2 is the second pixel signal V FD2 The second SN ratio of the reference configuration is the same as FD2 is the second SN ratio of this embodiment FD2 is the same as

[0162] FIG. 9 shows the relationship between the second pixel signal V and the amount of light incident on the imaging device of the reference embodiment. FD2 and the first pixel signal V FD1 10 is a graph showing the relationship between the second SN ratio SN and the amount of light incident on the imaging device of the reference embodiment. FD2 and the first SN ratio FD1 9 and 10 are graphs showing the relationship between the amount of light incident on the imaging device and the unit of this light amount is lux. The vertical axis of FIG. 9 is the level of the output pixel signal and the unit of this level is V (volts). The vertical axis of FIG. 10 is the SNR and the unit of this SNR is dB (decibels).

[0163] There are various techniques for realizing wide dynamic range imaging devices. Among these, the time division method, the space division method, the in-pixel memory method, and the one-pixel-two-cell method will be explained below.

[0164] In the time-division method, images are taken at different sensitivities in a time-division manner, and the resulting images are then synthesized.

[0165] In the space division method, images are captured using light receiving elements with different sensitivities, and the resulting images are then synthesized. The space division method is described in, for example, Patent Document 1.

[0166] In the in-pixel memory method, a memory is provided in each pixel to store charge that overflows from the photodiode. This increases the amount of charge that can be stored in one exposure period. The in-pixel memory method is described in, for example, Patent Document 2.

[0167] In a typical example of a one-pixel, two-cell system, two imaging cells with different sensitivities are configured within one pixel. Also, a memory for storing electric charges is provided in the low-sensitivity cell. The one-pixel, two-cell system is described in, for example, Patent Documents 3 and 4. Specifically, Patent Document 3 uses a photodiode as the photoelectric conversion unit. Patent Document 4 configures a stacked imaging device.

[0168] In the time division and space division methods, the dynamic range can be expanded by increasing the number of divisions, but increasing the number of divisions causes artifacts, reduces resolution, and degrades image quality.

[0169] In the in-pixel memory system, the memory capacity is limited, which limits the dynamic range that can be expanded.

[0170] In the one-pixel, two-cell system, a wide dynamic range is achieved using the first and second imaging cells. However, if there is a large difference between the light intensity range to which the first imaging cell is sensitive and the light intensity range to which the second imaging cell is sensitive, image quality may deteriorate in the intermediate range between the two light intensity ranges. This problem will be explained below with reference to Figures 8 to 10.

[0171] In the reference embodiment shown in Fig. 8, a first imaging cell 1c and a second imaging cell 1b are configured in one pixel, thereby realizing a one-pixel, two-cell system. In Fig. 9, the second pixel signal V FD2 and a line representing the first pixel signal V from the first imaging cell 1c. FD1 In FIG. 10, a line representing the second pixel signal V FD2 Second SNR FD2 and a line representing the first pixel signal V FD1 First, the signal-to-noise ratioFD1 A line representing and are drawn.

[0172] In FIG. 9, the corrected first pixel signal VY FD1 A line representing the corrected first pixel signal VY is drawn. FD1 is the first pixel signal V FD1 In FIG. 9, the second pixel signal V FD2 and the corrected first pixel signal VY FD1 The lines representing the two lines form a partial overlap. These two lines appear to form a single line.

[0173] In detail, the coefficients are determined by software so that the overlapping portion occurs. Then, at a connecting portion that is any portion belonging to the overlapping portion, the second pixel signal V FD2 and the first pixel signal V FD1 and data multiplied by a coefficient are concatenated. In this way, data of a composite signal is obtained. In the reference embodiment, a wide dynamic range is achieved by generating a composite signal in this way.

[0174] 10, the joint portion is schematically represented by a dotted line DLZ. FD2 Second SNR FD2 is high, while the first pixel signal V FD1 First, the signal-to-noise ratio FD1 is low. This means that the S / N ratio of the composite signal drops sharply at the spliced ​​portion. Hereinafter, the S / N ratio after this drop will be referred to as the spliced ​​S / N ratio. The reference embodiment has a problem in that the spliced ​​S / N ratio is low, and noise increases under medium light intensity conditions, easily degrading image quality.

[0175] This problem can be alleviated by the present embodiment shown in Figures 1 to 7. This point will be explained with reference to Figures 6 and 7.

[0176] The second pixel signal V in FIG. 6 according to this embodiment FD2The line representing the second pixel signal V in FIG. 9 for the reference embodiment FD2 The third pixel signal V in FIG. FD3 The line representing the first pixel signal V in FIG. FD1 Furthermore, in this embodiment, as shown in FIG. FD2 and the third pixel signal V FD3 The first pixel signal V FD1 There is a line representing

[0177] In FIG. 6, the corrected first pixel signal VX FD1 and the corrected third pixel signal VX FD3 A line representing the corrected first pixel signal VX is drawn. FD1 is the first pixel signal V FD1 is multiplied by the first coefficient. FD3 is the third pixel signal V FD3 is multiplied by the second coefficient. FD2 and the corrected first pixel signal VY FD1 The line representing the first partial overlapping portion and the corrected first pixel signal VY FD1 and the corrected third pixel signal VX FD3 The line representing the second partial overlapping portion forms the second partial overlapping portion. These three lines appear as if they were one line.

[0178] Specifically, the software determines a first coefficient so that a first overlap portion is generated, and determines a second coefficient so that a second overlap portion is generated. Then, at a first connection portion, which is any portion belonging to the first overlap portion, the second pixel signal V FD2 and the first pixel signal V FD1 In addition, in a second connection portion, which is any portion belonging to the second overlap portion, the first pixel signal V FD1 multiplied by the first coefficient, and the third pixel signal V FD3and data multiplied by the second coefficient are concatenated. In this way, data of the composite signal is obtained. In this embodiment, a wide dynamic range is achieved by generating the composite signal in this way.

[0179] In Fig. 7, the first connecting portion is schematically represented by a dotted line DLX. The second connecting portion is schematically represented by a dotted line DLY. The second SN ratio SN in Fig. 7 relating to this embodiment FD2 The line representing the second signal-to-noise ratio SN in FIG. 10 for the reference configuration FD2 This is the same as the line representing the third signal-to-noise ratio (SN) in Figure 7. FD1 The line representing the first signal-to-noise ratio SN in FIG. FD1 Furthermore, in FIG. 7 relating to this embodiment, the first signal-to-noise ratio SN FD1 The line representing the second signal-to-noise ratio, SN FD2 The line representing the third SN ratio SN FD3 Therefore, the degree of decrease in the S / N ratio at the first joint is limited. Hereinafter, this decreased S / N ratio will be referred to as the first joint S / N ratio. Also, the degree of decrease in the S / N ratio at the second joint is limited. Hereinafter, this decreased S / N ratio will be referred to as the second joint S / N ratio.

[0180] As can be understood from the above description, the first and second splicing SNRs of this embodiment tend to be higher than those of the reference embodiment, and therefore, this embodiment is more likely to suppress noise and image quality degradation under intermediate light levels than the reference embodiment.

[0181] The effects of this embodiment will be further described with reference to FIGS. 11 and 12. FIG. 11 shows the change in the relationship between the light amount and the SNR when the gain of the high-sensitivity cell 1b of the reference embodiment is increased. FIG. 12 shows the change in the relationship between the light amount and the SNR when the SPLIT of the reference embodiment is increased. The horizontal axis of FIGS. 11 and 12 represents the amount of light incident on the imaging device. The unit of this light amount is lux. The vertical axis of FIG. 11 represents the level of the output pixel signal. The unit of this level is V (volts). The vertical axis of FIG. 12 represents the SNR. The unit of this SNR is dB (decibels).

[0182] The dynamic range of the imaging device of the reference embodiment shown in FIG. 8 can be given by the following formula 1. In formula 1, DR is the dynamic range. S is the saturation level of the pixel signal determined based on the first charge storage unit FD1 and capacitor CsZ of the low-sensitivity cell 1c. N is the noise level of the entire imaging device. SPLIT is the sensitivity ratio (=sensitivity of high-sensitivity cell 1b / low-sensitivity cell 1c), which is the ratio of the sensitivity of the high-sensitivity cell 1b to the sensitivity of the low-sensitivity cell 1c. "*" is a multiplication symbol. Formula 1: DR[dB]=20log(S / N*SPLIT)

[0183] Here, in order to expand the dynamic range of the imaging device of the reference embodiment, the following adjustments can be considered. (i) N is reduced by increasing the gain of the high-sensitivity cell 1b. (ii) Increase the SPLIT by decreasing the sensitivity of the low-sensitivity cell 1c.

[0184] When the adjustment (i) above is performed, the saturation level of the high-sensitivity cell 1b is lowered. As shown by the white arrow in FIG. 11, the second SN ratio SN FD2 The line representing the second SN ratio SN is shifted to the left overall, and the upper right end of the line is shifted to the lower left. FD2 The line representing the second signal-to-noise ratio (SN) is drawn in bold. FD2As the line representing the dotted line DLZ shifts, the dotted line DLZ shifts to the dotted line DLZ2. In FIG. 11, the bottom end of the dotted line DLZ2 is located below the bottom end of the dotted line DLZ. This means that the adjustment (i) above will result in a decrease in the signal-to-noise ratio at the connection. The gain can be increased by adjusting the second inverting amplifier 11b.

[0185] When the adjustment (ii) above is performed, the first SNR (signal to noise ratio) is increased, as shown by the white arrow in Figure 12. FD1 In FIG. 12, the line representing the first signal-to-noise ratio (SN) after this shift is FD1 The line representing SN ratio is drawn in bold. FD1 As the line representing the distance shifts, the dotted line DLZ shifts to the dotted line DLZ3. In Fig. 12, the bottom end of the dotted line DL32 is located below the bottom end of the dotted line DLZ. This means that the SNR at the transition will decrease if the adjustment (ii) above is performed.

[0186] Thus, in the reference embodiment, when an attempt is made to expand the wide dynamic range by adjusting the imaging device, the stitching SNR decreases. As described above, a decrease in the stitching SNR leads to noise and image quality degradation under intermediate light levels. As such, it is not easy to achieve both a wide dynamic range and high image quality under intermediate light levels by adjusting the imaging device of the reference embodiment. As can be understood from the explanation using Figures 11 and 12, when the number of SNR lines obtained by the high-sensitivity cell is one and the number of SNR lines obtained by the low-sensitivity cell is one, it is difficult to achieve both.

[0187] In contrast to this, in this embodiment, a plurality of S / N ratio lines are obtained by the low-sensitivity cells, as shown in Fig. 7. This alleviates the difficulty of achieving both of these.

[0188] According to this embodiment, two imaging cells 1b and 1a with different circuit configurations can be provided within each pixel 1. The second imaging cell 1b functions as a low-noise, high-sensitivity imaging cell. The first imaging cell 1a functions as a high-saturation, low-sensitivity imaging cell. Therefore, even subjects with large differences in brightness can be captured without blown-out highlights or crushed shadows. A sufficient signal-to-noise ratio can be obtained even under medium light levels. Furthermore, in this embodiment, high-sensitivity imaging and low-sensitivity imaging can be performed simultaneously using the two imaging cells 1b and 1a. This reduces the time lag between these images.

[0189] Several other embodiments will be described below. In the following, elements common to the embodiments already described and the embodiments to be described thereafter will be given the same reference numerals, and their description may be omitted. The descriptions of the respective embodiments may be mutually applicable unless technically inconsistent. The respective embodiments may be combined with each other unless technically inconsistent.

[0190] (Second embodiment) FIG. 13 shows the circuit configuration of the pixel 1 of the imaging device 100 according to the second embodiment.

[0191] The imaging device 100 according to the second embodiment includes an output circuit 102. The output circuit 102 has an additional amplification transistor M30 and an additional selection transistor M31. Specifically, the first imaging cell 1a includes the output circuit 102. More specifically, the first signal processing circuit P1 includes the output circuit 102.

[0192] In the following example, positive charges are used as signal charges. Specifically, holes are used as signal charges. Transistors M10, M11, M12, M16, M17, M20, M21, M22, M23, M30, and M31 are n-type transistors. Specifically, these transistors are n-type MOSFETs.

[0193] However, negative charges may be used as the signal charges. Specifically, electrons may be used as the signal charges. In this case, p-type transistors may be used as the transistors M10, M11, M12, M16, M17, M20, M21, M22, M23, M30, and M31. Specifically, p-type MOSFETs may be used as these transistors.

[0194] The first charge storage unit FD1 is electrically connected to the gate electrode of the first amplification transistor M10. The first capacitor Cs3 is electrically connected to the gate electrode of the additional amplification transistor M30. The first capacitor Cs3 is also electrically connected to the output circuit 102.

[0195] One of the source and drain of the first subsequent transistor M17 is electrically connected to the first capacitor Cs3. One of the source and drain of the additional selection transistor M31, the other of the source and drain of the first subsequent transistor M17, and one of the source and drain of the additional amplification transistor M30 are electrically connected. The other of the source and drain of the additional selection transistor M31 is electrically connected to a third voltage line VDD3. The other of the source and drain of the additional amplification transistor M30 is electrically connected to a third signal line Out3.

[0196] The additional amplification transistor M30 amplifies an electrical signal corresponding to the potential of the first capacitor Cs3. The additional selection transistor M31 selectively outputs the signal amplified by the additional amplification transistor M30. The first subsequent transistor M17 resets the first capacitor Cs3. Thus, in this embodiment, the first subsequent transistor M17 functions as a reset transistor.

[0197] Specifically, in this embodiment, the additional selection transistor M31 is turned on, and then the third pixel signal V FD3is output to the first peripheral circuit via the additional amplifying transistor M30 and the third signal line Out3 in this order. The third signal line Out3 is connected to the first vertical signal line 9a shown in FIG.

[0198] Furthermore, after turning on the additional selection transistor M31, the first subsequent transistor M17 is turned on. This resets the potential of the first capacitor Cs3, i.e., the potential of the first portion FD3. Then, a reset signal corresponding to the potential of the first portion FD3 is output to the first peripheral circuit via the additional amplification transistor M30 and the third signal line Out3 in this order. The third pixel signal V FD3 The reset signal is subtracted from the third pixel signal V FD3 The noise is reduced.

[0199] According to the first embodiment, the imaging device 100 can be configured simply. According to the second embodiment, the dynamic range can be expanded more easily than in the first embodiment. This advantage of the second embodiment will be described below with reference to FIG. 14. FIG. 14 is an explanatory diagram for explaining the modulation degree of the first intermediate transistor M16.

[0200] In the second embodiment, the first intermediate transistor M16 has a gate oxide capacitance Cox and a depletion layer capacitance Cdep. Assume that the voltage of the gate electrode of the first intermediate transistor M16 fluctuates by ΔVg. In this case, the fluctuation width ΔVcha of the voltage of the channel under the gate of the first intermediate transistor M16 is given by the following equation 2: Formula 2: ΔVcha = ΔVg * Cox / (Cox + Cdep)

[0201] Cox / (Cox+Cdep) is called the modulation index. The modulation index is smaller than 1. For example, the modulation index is equal to or greater than 0.5 and equal to or less than 0.8. Because the modulation index is smaller than 1, fluctuations in the potential of the first portion FD3 are suppressed. This contributes to an expansion of the dynamic range.

[0202] In the first embodiment, when the first subsequent transistor M17 is in the on state, the first portion FD3 and the first charge storage unit FD1 are electrically connected via the first subsequent transistor M17. This configuration cancels the effect of expanding the dynamic range resulting from the modulation depth of the first intervening transistor M16. This cancellation occurs because the total number of charges stored in the first portion FD3 and the first charge storage unit FD1 remains unchanged even when charges are injected from the first portion FD3 to the first charge storage unit FD1. Meanwhile, as described above, the first embodiment allows for a simple configuration of the image pickup device 100.

[0203] (Third embodiment) FIG. 15 shows the circuit configuration of a pixel 1 of an imaging device 100 according to the third embodiment.

[0204] In the first embodiment, the third pixel signal V FD3 is output from the first imaging cell 1a. In contrast, in the third embodiment, the third pixel signal V FD3 is output from the second imaging cell 1b. Specifically, in the third embodiment, the first capacitor Cs3 can be electrically connected to the second charge storage unit FD2.

[0205] In the third embodiment, the first charge storage unit FD1 is electrically connected to the gate electrode of the first amplification transistor M10. The second charge storage unit FD2 is electrically connected to the gate electrode of the second amplification transistor M20. When the first subsequent transistor M17 is turned on, the first capacitor Cs3, one of the source and drain of the first subsequent transistor M17, the other of the source and drain of the first subsequent transistor M17, and the gate electrode of the second amplification transistor M20 are electrically connected in this order.

[0206] In the third embodiment, the second selection transistor M21 and the first subsequent transistor M17 are turned on, and then the third pixel signal V FD3is output to the second peripheral circuit via the first subsequent transistor M17, the second amplification transistor M20, and the second signal line Out2 in this order.

[0207] In the third embodiment, the second selection transistor M21 and the first subsequent transistor M17 are turned on, and then the band control transistor M23 and the second reset transistor M22 are turned on. This resets the potential of the second charge storage section FD2 and the potential of the first capacitor Cs3, i.e., the potential of the first portion FD3. A reset signal corresponding to the potential of the first portion FD3 is then output to the second peripheral circuit via the first subsequent transistor M17, the second amplification transistor M20, and the second signal line Out2, in this order. The third pixel signal V FD3 The reset signal is subtracted from the third pixel signal V FD3 The noise is reduced.

[0208] According to the third embodiment, the number of transistors can be reduced compared to the second embodiment.

[0209] (Fourth embodiment) FIG. 16 shows the circuit configuration of a pixel 1 of an imaging device 100 according to the fourth embodiment.

[0210] In the fourth embodiment, the first capacitor Cs3 is electrically connected to the capacitor Cs1. Hereinafter, the capacitor Cs1 may be referred to as the specific capacitor Cs1. Specifically, the first portion FD3 is electrically connected to the specific capacitor Cs1.

[0211] In the fourth embodiment, the first capacitor Cs3 cooperates with the specific capacitor Cs1 to form a composite capacitance unit, and when the first intervening transistor M16 is turned on, the first charge storage unit FD1 and the composite capacitor are electrically connected.

[0212] In the fourth embodiment, as in the third embodiment, the first charge storage unit FD1 is electrically connected to the gate electrode of the first amplification transistor M10. The second charge storage unit FD2 is electrically connected to the gate electrode of the second amplification transistor M20. When the first subsequent transistor M17 is turned on, the first capacitor Cs3, one of the source and drain of the first subsequent transistor M17, the other of the source and drain of the first subsequent transistor M17, and the gate electrode of the second amplification transistor M20 are electrically connected in this order. In the fourth embodiment, a second reset transistor M22 is used as the first subsequent transistor M17.

[0213] Furthermore, in the fourth embodiment, when the first subsequent transistor M17, i.e., the second reset transistor M22, is turned on, the specific capacitor Cs1, one of the source and drain of the first subsequent transistor M17, the other of the source and drain of the first subsequent transistor M17, and the gate electrode of the second amplification transistor M20 are electrically connected in this order.

[0214] Using the term "composite capacitance unit," the following can be said about the fourth embodiment: When the first subsequent transistor M17 is turned on, the composite capacitance unit, one of the source and the drain of the first subsequent transistor M17, the other of the source and the drain of the first subsequent transistor M17, and the gate electrode of the second amplification transistor M20 are electrically connected in this order.

[0215] In the fourth embodiment, the second selection transistor M21 and the first subsequent transistor M17 are turned on, and then the third pixel signal V FD3 is output to the second peripheral circuit via the first subsequent transistor M17, the second amplification transistor M20, and the second signal line Out2 in this order.

[0216] In the fourth embodiment, the second selection transistor M21 is turned on, and then the band control transistor M23 is turned on. This resets the potential of the composite capacitance section. Then, a reset signal according to the potential of the composite capacitance section is output to the second peripheral circuit via the first subsequent transistor M17, the second amplification transistor M20, and the second signal line Out2 in this order. The third pixel signal V FD3 The reset signal is subtracted from the third pixel signal V FD3 The noise is reduced.

[0217] In the fourth embodiment, the first capacitor Cs3 cooperates with the specific capacitor Cs1 to form a composite capacitance section, which is suitable for realizing an image pickup device 100 with high saturation and a wide dynamic range.

[0218] (Fifth embodiment) FIG. 17 shows the circuit configuration of the pixel 1 of the imaging device 100 according to the fifth embodiment.

[0219] In the fifth embodiment, similarly to the fourth embodiment, the first capacitor Cs3 is electrically connected to the specific capacitor Cs1. Specifically, the first portion FD3 is electrically connected to the capacitor Cs1. The first capacitor Cs3 cooperates with the specific capacitor Cs1 to form a composite capacitance section.

[0220] However, in the fifth embodiment, the third pixel signal V FD3 Specifically, in the fourth embodiment, the third pixel signal V FD3 is output from the second imaging cell 1b. In contrast, in the fifth embodiment, the third pixel signal V FD3 is output from the first imaging cell 1a.

[0221] In the fifth embodiment, the composite capacitance unit is electrically connected to one of the source and drain of the first subsequent transistor M17. The other of the source and drain of the first subsequent transistor M17 is electrically connected to the first charge storage unit FD1. In the fifth embodiment, the first reset transistor M12 is used as the first subsequent transistor M17.

[0222] In the fifth embodiment, the first charge storage unit FD1 is electrically connected to the gate electrode of the first amplification transistor M10. When the first subsequent transistor M17 is turned on, the first capacitor Cs3, one of the source and drain of the first subsequent transistor M17, the other of the source and drain of the first subsequent transistor M17, and the gate electrode of the first amplification transistor M10 are electrically connected in this order.

[0223] In addition, in the fifth embodiment, when the first subsequent transistor M17 is turned on, the specific capacitor Cs1, one of the source and drain of the first subsequent transistor M17, the other of the source and drain of the first subsequent transistor M17, and the gate electrode of the first amplification transistor M10 are electrically connected in this order.

[0224] Using the term "composite capacitance unit," the following can be said about the fifth embodiment: When the first subsequent transistor M17 is turned on, the composite capacitance unit, one of the source and drain of the first subsequent transistor M17, the other of the source and drain of the first subsequent transistor M17, and the gate electrode of the first amplification transistor M10 are electrically connected in this order.

[0225] In the fifth embodiment, the first selection transistor M11 and the first subsequent transistor M17 are turned on, and then the third pixel signal V FD3 is output to the first peripheral circuit via the first subsequent transistor M17, the first amplification transistor M10, and the first signal line Out1 in this order.

[0226] In the fifth embodiment, the second selection transistor M21 is turned on, and then the band control transistor M23 is turned on. This resets the potential of the composite capacitance section. Then, a reset signal according to the potential of the composite capacitance section is output to the first peripheral circuit via the first subsequent transistor M17, the first amplification transistor M10, and the first signal line Out1 in this order. The third pixel signal V FD3 The reset signal is subtracted from the third pixel signal V FD3 The noise is reduced.

[0227] In the fifth embodiment, misalignment is less likely to occur than in the third and fourth embodiments. This point will be described below.

[0228] In the graph of FIG. 6 relating to the first embodiment, the second pixel signal V FD2 and the first pixel signal V FD1 Not only the line representing the third pixel signal V FD3 The line representing passes through the origin, making it easy for software to create a single continuous line from these three lines.

[0229] On the other hand, in the third and fourth embodiments, the third pixel signal V FD3 The line representing the first pixel signal V does not pass through the origin and rises from a position where the light intensity is higher. FD1 and the third pixel signal V FD3 Although the first pixel signal V FD1 and the third pixel signal V FD3 This is because the first pixel signal V FD1 is output via the first amplification transistor M10. On the other hand, the third pixel signal V FD3 is output via the second amplifying transistor M20.

[0230] Third pixel signal V FD3 If the line representing V does not pass through the origin, the software FD2The line representing the first pixel signal V FD1 and the third pixel signal V FD3 It is difficult to create a continuous line from the line representing the third pixel signal V FD3 and the first pixel signal V FD1 The second joint portion between the part based on the first layer and the part based on the second layer is likely to be discontinuous. The joint misalignment refers to the phenomenon in which such a discontinuous joint portion occurs.

[0231] In contrast, in the fifth embodiment, the first pixel signal V FD1 Also, the third pixel signal V FD3 Therefore, the second pixel signal V FD2 and the first pixel signal V FD1 Not only the line representing the third pixel signal V FD3 The line representing also passes through the origin. Therefore, according to the fifth embodiment, connection gaps are unlikely to occur.

[0232] (Sixth embodiment) FIG. 18 shows the circuit configuration of the pixel 1 of the imaging device 100 according to the sixth embodiment.

[0233] The imaging device 100 according to the sixth embodiment includes a second capacitor Cs4, a second intermediate transistor M26, and a second subsequent transistor M27. The second intermediate transistor M26 may also be referred to as a second charge injection transistor. Specifically, the second intermediate transistor M26 may also be referred to as a second electron injection transistor. The second subsequent transistor M27 may also be referred to as a second short transistor.

[0234] Specifically, in the sixth embodiment, the second imaging cell 1b includes a second capacitor Cs4, a second intervening transistor M26, and a second subsequent transistor M27. More specifically, the second signal processing circuit P2 includes a second capacitor Cs4, a second intervening transistor M26, and a second subsequent transistor M27.

[0235] In the following example, positive charges are used as the signal charges. Specifically, holes are used as the signal charges. Transistors M10, M11, M12, M16, M17, M20, M21, M22, M23, M26, and M27 are n-type transistors. Specifically, these transistors are n-type MOSFETs.

[0236] However, negative charges may be used as the signal charges. Specifically, electrons may be used as the signal charges. In this case, p-type transistors may be used as the transistors M10, M11, M12, M16, M17, M20, M21, M22, M23, M26, and M27. Specifically, p-type MOSFETs may be used as these transistors.

[0237] In this embodiment, the gate electrode of the second intervening transistor M26 and one of the source and drain of the second intervening transistor M26 are electrically connected to the second charge storage unit FD2. When the second intervening transistor M26 is turned on, the second charge storage unit FD2 and the second capacitor Cs4 are electrically connected via the second intervening transistor M26.

[0238] In this embodiment, when the second subsequent transistor M27 is turned on, the second capacitor Cs4, one of the source and drain of the second subsequent transistor M27, and the other of the source and drain of the second subsequent transistor M27 are electrically connected in this order.

[0239] In this embodiment, the other of the source and drain of the second intermediate transistor M26 is electrically connected to the second capacitor Cs4. One of the source and drain of the second subsequent transistor M27 is electrically connected to the second capacitor Cs4. The other of the source and drain of the second subsequent transistor M27 is electrically connected to the second charge storage unit FD2.

[0240] In this embodiment, the first charge storage unit FD1 is electrically connected to the gate electrode of the first amplification transistor M10. The second charge storage unit FD2 is electrically connected to the gate electrode of the second amplification transistor M20. When the first subsequent transistor M17 is turned on, the first capacitor Cs3, one of the source and drain of the first subsequent transistor M17, the other of the source and drain of the first subsequent transistor M17, and the gate electrode of the first amplification transistor M10 are electrically connected in this order.

[0241] In this embodiment, when the second subsequent transistor M27 is turned on, the second capacitor Cs4, one of the source and drain of the second subsequent transistor M27, the other of the source and drain of the second subsequent transistor M27, and the gate electrode of the second amplification transistor M20 are electrically connected in this order.

[0242] In this embodiment, the capacitance value of the second capacitor Cs4 is larger than the capacitance value of the second charge storage unit FD2. The ratio c4 / c2 of the capacitance value c4 of the second capacitor Cs4 to the capacitance value c2 of the second charge storage unit FD2 is, for example, 3 or more. The ratio c4 / c2 may be 6 or more, or 10 or more. The ratio c4 / c2 is, for example, 1000 or less. The ratio c4 / c2 may be 100 or less, or 50 or less.

[0243] In this embodiment, the second capacitor Cs4 has an MIM structure.

[0244] In this embodiment, when the second intervening transistor M26 is turned on, the second charge storage unit FD2 is electrically connected to one end of the second capacitor Cs4 via the second intervening transistor M26. A DC potential VBW2 is applied to the other end of the second capacitor Cs4. The DC potential VBW2 may be a potential biased from the ground potential or may be the ground potential.

[0245] Hereinafter, the portion of the second capacitor Cs4 that is electrically connected to the second intervening transistor M26 may be referred to as the second portion FD4.

[0246] In this embodiment, the conductivity type of the gate electrode of the second intervening transistor M26 is opposite to the conductivity type of the source and drain of the second intervening transistor M26. Specifically, in this embodiment, the conductivity type of the gate electrode of the second intervening transistor M26 is p-type. The conductivity type of the source and drain of the second intervening transistor M26 is n-type. The gate electrode of the second intervening transistor M26 is, for example, a polysilicon electrode.

[0247] The gate length of the second intervening transistor M26 may be longer than the gate length of the second subsequent transistor M27. The gate length of the second intervening transistor M26 may be the same as the gate length of the second subsequent transistor M27. The gate length of the second intervening transistor M26 may be shorter than the gate length of the second subsequent transistor M27.

[0248] The gate width of the second intervening transistor M26 may be longer than the gate width of the second subsequent transistor M27. The gate width of the second intervening transistor M26 may be the same as the gate width of the second subsequent transistor M27. The gate width of the second intervening transistor M26 may be shorter than the gate width of the second subsequent transistor M27.

[0249] The gate thickness of the second intervening transistor M26 may be greater than the gate thickness of the second subsequent transistor M27. The gate thickness of the second intervening transistor M26 may be the same as the gate thickness of the second subsequent transistor M27. The gate thickness of the second intervening transistor M26 may be smaller than the gate thickness of the second subsequent transistor M27.

[0250] Hereinafter, the voltage of the gate electrode of the second subsequent transistor M27 will be referred to as voltage Vst2. In this embodiment, voltage Vst2 is changed from low to high to turn on the second subsequent transistor M27. This electrically connects the second charge storage unit FD2 and the second portion FD4 via the second subsequent transistor M27. Thereafter, an electrical signal corresponding to the potential of the second charge storage unit FD2 and the potential of the second portion FD4 is output to the second peripheral circuit via the second amplification transistor M20 and the second signal line Out2, in this order. The level of this electrical signal continuously increases as the amount of light incident on the imaging device 100 increases.

[0251] The electrical signal will be further described. In this embodiment, the capacitance value of the second capacitor Cs4 is greater than the capacitance value of the second charge storage unit FD2. Therefore, an electrical signal corresponding to a second composite potential in which the potential of the second capacitor Cs4 is more strongly reflected than the potential of the second charge storage unit FD2 is output to the second peripheral circuit via the second amplification transistor M20 and the second signal line Out2, in this order.

[0252] In this embodiment, the electrical signal is converted into the pixel signal of the second portion FD4 or the fourth pixel signal V FD4 It is sometimes referred to as.

[0253] 4th pixel signal V FD4 After outputting the voltages Vrs2 and Vrs3, the voltages Vrs2 and Vrs3 are changed from low to high, and the second reset transistor M22 and the band control transistor M23 are turned on, thereby resetting the potential of the second charge storage section FD2 and the potential of the second capacitor Cs4, i.e., the potential of the second section FD4.

[0254] Then, an electrical signal corresponding to the potential of the second charge storage section FD2 and the potential of the second portion FD4 is output to the second peripheral circuit via the second amplification transistor M20 and the second signal line Out2 in this order. This electrical signal is a reset signal related to the second composite potential. In this embodiment, the reset signal related to the second composite potential may be referred to as a reset signal for the second portion FD4.

[0255] Then, the fourth pixel signal V of the second portion FD4 FD4 The reset signal of the second portion FD4 is subtracted from the fourth pixel signal V FD4 The noise is reduced.

[0256] In this embodiment, a signal corresponding to the potential of the second capacitor Cs4 is read out, and then a signal corresponding to the potential of the second charge storage unit FD2 is read out. In the above example, the signal corresponding to the potential of the second capacitor Cs4 is read out as the fourth pixel signal V FD4 The signal corresponding to the potential of the second charge storage unit FD2 is the second pixel signal V FD2 is.

[0257] When the amount of light incident on the imaging device 100 increases from a low level, the signal charge accumulated in the second charge storage unit FD2 increases. In this embodiment, the signal charge is positive. As the signal charge increases, the potential of the second charge storage unit FD2 increases. When the potential of the second charge storage unit FD2 exceeds the second threshold potential, the second intervening transistor M26 turns on, and the second charge storage unit FD2 and the second portion FD4 are electrically connected via the second intervening transistor M26. As the amount of light further increases and the potential of the second charge storage unit FD2 further increases, the potential under the gate of the second intervening transistor M26 increases. As a result, the potential under the gate of the second intervening transistor M26 becomes higher than the potential of the second portion FD4. At this stage, as when the amount of light is low, the potential of the second charge storage unit FD2 is higher than the potential of the second portion FD4. Negative charges are injected from the second portion FD4 to the second charge storage unit FD2 via the second intervening transistor M26. Specifically, these negative charges are electrons. Due to the injection of these negative charges, the potential of the second charge storage section FD2 decreases. Accordingly, the potential under the gate of the second intervening transistor M26 also decreases. Meanwhile, the potential of the second section FD4 increases.

[0258] In this embodiment, the injection of negative charges balances the potential of the second charge storage unit FD2 and the potential of the second portion FD4. In a situation where the amount of light incident on the imaging device 100 increases, the potential of the second charge storage unit FD2 and the potential of the second portion FD4 may increase while maintaining this balance.

[0259] A similar phenomenon occurs when the signal charge is negative.

[0260] The following technical matters can be derived from the above explanation. That is, the following technical matters can be derived from the above explanation. That is, an increase in either positive or negative charges generated by photoelectric conversion in the second photoelectric conversion unit PC2 increases either positive or negative charges accumulated in the second charge accumulation unit FD2. An increase in either positive or negative charges accumulated in the second charge accumulation unit FD2 causes either an increase or a decrease in the potential of the second charge accumulation unit FD2. As either an increase or a decrease in the potential of the second charge accumulation unit FD2 occurs, a third phenomenon and a fourth phenomenon occur, in this order. The third phenomenon is that the second intermediate transistor M26 turns on. The fourth phenomenon is the supply of the other of positive and negative charges from the second capacitor Cs4 to the second charge accumulation unit FD2 via the second intermediate transistor M26. This supply causes either an increase or a decrease in the potential of the second charge accumulation unit FD2.

[0261] As shown in FIG. 6, in the first embodiment, the second pixel signal V FD2 The line representing the first pixel signal V FD1 and the third pixel signal V FD3 As shown in FIG. 7, in the first embodiment, three lines are obtained, namely, a line representing the second SN ratio SN FD2 The line representing the first signal-to-noise ratio (SN) FD3 The line representing the third signal-to-noise ratio SN FD3 Three lines are obtained:

[0262] According to the sixth embodiment, the second pixel signal V FD2 and the first pixel signal V FD1The fourth pixel signal V FD4 A line representing the second signal-to-noise ratio SN FD2 The line representing the first signal-to-noise ratio SN FD3 The fourth pixel signal V FD4 This can suppress the degradation of the SNR at the time of connection. Therefore, the light amount region with a high SNR can be expanded.

[0263] (Seventh embodiment) FIG. 19 shows the circuit configuration of a pixel 1 of an imaging device 100 according to the seventh embodiment.

[0264] In the seventh embodiment, one of the source and drain of the second subsequent transistor M27 is electrically connected to the second capacitor Cs4, and the other of the source and drain of the second subsequent transistor M27 is electrically connected to the first charge storage unit FD1.

[0265] In the seventh embodiment, when the second subsequent transistor M27 is turned on, the second capacitor Cs4, one of the source and drain of the second subsequent transistor M27, the other of the source and drain of the second subsequent transistor M27, and the gate electrode of the first amplification transistor M10 are electrically connected in this order.

[0266] In the sixth embodiment, the second capacitor Cs4 and the second charge storage unit FD2 are electrically connected when the second subsequent transistor M27 is turned on. This electrical connection can reduce the gain of the second imaging cell 1b. On the other hand, in the seventh embodiment, the second capacitor Cs4 and the first charge storage unit FD1 are electrically connected when the second subsequent transistor M27 is turned on. This electrical connection can reduce the gain of the first imaging cell 1a.

[0267] In the sixth and seventh embodiments, the first imaging cell 1a is a low-sensitivity cell, and the second imaging cell 1b is a high-sensitivity cell. According to the seventh embodiment, it is easy to ensure the gain of the high-sensitivity cell. This is advantageous from the viewpoint of reducing the noise level of the entire imaging device 100.

[0268] (Eighth embodiment) FIG. 20 shows the circuit configuration of a pixel 1 of an imaging device 100 according to the eighth embodiment.

[0269] The imaging device 100 according to the eighth embodiment includes an additional capacitor Cs5, an additional intervening transistor M36, and an additional subsequent transistor M37. The additional intervening transistor M36 may also be referred to as an additional charge injection transistor. Specifically, the additional intervening transistor M36 may also be referred to as an additional electron injection transistor. The additional subsequent transistor M37 may also be referred to as an additional short transistor.

[0270] Specifically, in the eighth embodiment, the first imaging cell 1a includes an additional capacitor Cs5, an additional intervening transistor M36, and an additional subsequent transistor M37. More specifically, the first signal processing circuit P1 includes an additional capacitor Cs5, an additional intervening transistor M36, and an additional subsequent transistor M37.

[0271] The first capacitor Cs3 is electrically connected to the gate electrode of the additional intervening transistor M36 and one of the source and drain of the additional intervening transistor M36. When the additional intervening transistor M36 is turned on, the first capacitor Cs3 and the additional capacitor Cs5 are electrically connected to each other via the additional intervening transistor M36.

[0272] In this embodiment, when the additional subsequent transistor M37 is turned on, the additional capacitor Cs5, one of the source and drain of the additional subsequent transistor M37, and the other of the source and drain of the additional subsequent transistor M37 are electrically connected in this order.

[0273] In this embodiment, the other of the source and drain of the additional intervening transistor M36 is electrically connected to the additional capacitor Cs5, and one of the source and drain of the additional subsequent transistor M37 is electrically connected to the additional capacitor Cs5.

[0274] In this embodiment, one of the source and drain of the first subsequent transistor 17, the other of the source and drain of the additional subsequent transistor M37, the first capacitor Cs3, the gate electrode of the additional intervening transistor M36, and one of the source and drain of the additional intervening transistor M36 are electrically connected. The other of the source and drain of the first subsequent transistor 17 is electrically connected to the first charge storage unit FD1.

[0275] In this embodiment, the first charge storage unit FD1 is electrically connected to the gate electrode of the first amplification transistor M10. When the first subsequent transistor M17 and the additional subsequent transistor M37 are turned on, the additional capacitor Cs5, one of the source and drain of the additional subsequent transistor M37, the other of the source and drain of the additional subsequent transistor M37, one of the source and drain of the first subsequent transistor M17, the other of the source and drain of the first subsequent transistor M17, and the gate electrode of the first amplification transistor M10 are electrically connected in this order.

[0276] In this embodiment, the capacitance value of the additional capacitor Cs5 is larger than the capacitance value of the first charge storage unit FD1. The ratio c5 / c1 of the capacitance value c5 of the additional capacitor Cs5 to the capacitance value c1 of the first charge storage unit FD1 is, for example, 3 or more. The ratio c5 / c1 may be 6 or more, or may be 10 or more. The ratio c5 / c1 is, for example, 1000 or less. The ratio c5 / c1 may be 100 or less, or may be 50 or less.

[0277] In this embodiment, the capacitance value c5 of the additional capacitor Cs5 is smaller than the capacitance value c3 of the first capacitor Cs3. However, the capacitance value c5 may be the same as the capacitance value c3. The capacitance value c5 may also be larger than the capacitance value c3.

[0278] In this embodiment, the additional capacitor Cs5 has an MIM structure.

[0279] In this embodiment, when the additional intervening transistor M36 is turned on, one end of the first capacitor Cs3 is electrically connected to one end of the additional capacitor Cs5 via the additional intervening transistor M36. A DC potential VBW3 is applied to the other end of the additional capacitor Cs5. The DC potential VBW3 may be a potential biased from the ground potential or may be the ground potential.

[0280] Hereinafter, the portion of the additional capacitor Cs5 electrically connected to the additional intervening transistor M36 may be referred to as an additional portion FD5.

[0281] In this embodiment, the conductivity type of the gate electrode of the additional intervening transistor M36 is opposite to the conductivity type of the source and drain of the additional intervening transistor M36. Specifically, in this embodiment, the conductivity type of the gate electrode of the additional intervening transistor M36 is p-type. The conductivity type of the source and drain of the additional intervening transistor M36 is n-type. The gate electrode of the additional intervening transistor M36 is, for example, a polysilicon electrode.

[0282] The gate length of the additional intervening transistor M36 may be longer than the gate length of the additional subsequent transistor M37. The gate length of the additional intervening transistor M36 may be the same as the gate length of the additional subsequent transistor M37. The gate length of the additional intervening transistor M36 may be shorter than the gate length of the additional subsequent transistor M37.

[0283] The gate width of the additional intervening transistor M36 may be longer than the gate width of the additional subsequent transistor M37. The gate width of the additional intervening transistor M36 may be the same as the gate width of the additional subsequent transistor M37. The gate width of the additional intervening transistor M36 may be shorter than the gate width of the additional subsequent transistor M37.

[0284] The gate thickness of the additional intervening transistor M36 may be greater than the gate thickness of the additional subsequent transistor M37. The gate thickness of the additional intervening transistor M36 may be the same as the gate thickness of the additional subsequent transistor M37. The gate thickness of the additional intervening transistor M36 may be smaller than the gate thickness of the additional subsequent transistor M37.

[0285] Hereinafter, the voltage of the gate electrode of the additional subsequent transistor M37 will be referred to as voltage Vst3. In this embodiment, voltages Vst and Vst3 are changed from low to high to turn on the first subsequent transistor M17 and the additional subsequent transistor M37. This electrically connects the first charge storage unit FD1, the first portion FD3, and the additional portion FD5. An electrical signal corresponding to the potentials of the first charge storage unit FD1, the first portion FD3, and the additional portion FD5 is then output to the first peripheral circuit via the first amplification transistor M10 and the first signal line Out1, in this order. The level of this electrical signal continuously increases as the amount of light incident on the imaging device 100 increases.

[0286] The electrical signal will be further described. In this embodiment, the capacitance value of the first capacitor Cs3 is greater than the capacitance value of the first charge storage unit FD1. Furthermore, the capacitance value of the additional capacitor Cs5 is greater than the capacitance value of the first charge storage unit FD1. Therefore, an electrical signal corresponding to a third composite potential in which the potential of the first capacitor Cs3 is more strongly reflected than the potential of the first charge storage unit FD1 and the potential of the additional capacitor Cs5 is more strongly reflected than the potential of the first charge storage unit FD1 is output to the first peripheral circuit via the first amplification transistor M10 and the first signal line Out1, in this order.

[0287] In this embodiment, the electrical signal is converted into the pixel signal of the additional portion FD5 or the fifth pixel signal V FD5 It is sometimes referred to as.

[0288] 5th pixel signal V FD5After outputting, the voltage Vrs1 is changed from low to high, and the first reset transistor M12 is turned on, thereby resetting the potential of the first charge storage section FD1, the potential of the first capacitor Cs3 (i.e., the potential of the first section FD3), and the potential of the additional capacitor Cs5 (i.e., the potential of the additional section FD5).

[0289] Then, an electrical signal corresponding to the potential of the first charge storage portion FD1, the potential of the first portion FD3, and the potential of the additional portion FD5 is output to the first peripheral circuit via the first amplification transistor M10 and the first signal line Out1 in this order. This electrical signal is a reset signal related to the third composite potential. In this embodiment, the reset signal related to the third composite potential may be referred to as a reset signal for the additional portion FD5.

[0290] Then, the fifth pixel signal V of the additional part FD5 FD5 The reset signal of the additional part FD5 is subtracted from the fifth pixel signal V FD5 The noise is reduced.

[0291] When the amount of light incident on the imaging device 100 increases from a low level, the signal charge accumulated in the first charge storage unit FD1 increases. In this embodiment, the signal charge is positive. As the signal charge increases, the potential of the first charge storage unit FD1 increases. When the potential of the first charge storage unit FD1 exceeds the first threshold potential, the first intervening transistor M16 turns on, and the first charge storage unit FD1 and the first portion FD3 are electrically connected via the first intervening transistor M16. As the amount of light further increases and the potential of the first charge storage unit FD1 further increases, the potential under the gate of the first intervening transistor M16 increases. As a result, the potential under the gate of the first intervening transistor M16 becomes higher than the potential of the first portion FD3. At this stage, as when the amount of light is low, the potential of the first charge storage unit FD1 is higher than the potential of the first portion FD3. Negative charges are injected from the first portion FD3 to the first charge storage unit FD1 via the first intervening transistor M16. Specifically, these negative charges are electrons. Due to the injection of these negative charges, the potential of the first charge accumulation unit FD1 decreases. Accordingly, the potential under the gate of the first intervening transistor M16 also decreases. Meanwhile, the potential of the first portion FD3 increases.

[0292] Furthermore, when the potential of the first portion FD3 exceeds the third threshold potential, the additional intervening transistor M36 is turned on, and the first portion FD3 and the additional portion FD5 are electrically connected via the additional intervening transistor M36. As the potential of the first portion FD3 further increases, the potential under the gate of the additional intervening transistor M36 increases. As a result, the potential under the gate of the additional intervening transistor M36 becomes higher than the potential of the additional portion FD5. At this stage, the potential of the first portion FD3 is higher than the potential of the additional portion FD5. Negative charges are injected from the additional portion FD5 to the first portion FD3 via the additional intervening transistor M36. Specifically, these negative charges are electrons. Due to this injection of negative charges, the potential of the first portion FD3 decreases. Accordingly, the potential under the gate of the additional intervening transistor M36 also decreases. Meanwhile, the potential of the additional portion FD5 increases.

[0293] In this embodiment, such injection of negative charges balances the potential of the first charge storage unit FD1, the potential of the first portion FD3, and the potential of the additional portion FD5. In a situation where the amount of light incident on the imaging device 100 increases, the potentials of the first charge storage unit FD1, the first portion FD3, and the additional portion FD5 may increase while maintaining this balance.

[0294] A similar phenomenon occurs when the signal charge is negative.

[0295] The following technical points can be derived from the above explanation. That is, when one of the potential rises or falls in the first portion FD3 of the first capacitor Cs3, the fifth and sixth phenomena occur, in this order. The fifth phenomenon is that the additional intervening transistor M36 turns on. The sixth phenomenon is the supply of positive or negative charges from the additional capacitor Cs5 to the first capacitor Cs3 via the additional intervening transistor M36. This supply causes the other of the potential rises or falls in the first portion FD3 of the first capacitor Cs3.

[0296] As shown in FIG. 6, in the first embodiment, the second pixel signal V FD2 The line representing the first pixel signal V FD1 and the third pixel signal V FD3 As shown in FIG. 7, in the first embodiment, three lines are obtained, namely, a line representing the second SN ratio SN FD2 The line representing the first signal-to-noise ratio (SN) FD3 The line representing the third signal-to-noise ratio SN FD3 Three lines are obtained:

[0297] In contrast, according to the eighth embodiment, the third pixel signal V FD3 The fifth pixel signal V FD5 A line representing the third signal-to-noise ratio SN FD3 The fifth pixel signal V FD5Further, a line representing the signal-to-noise ratio for

[0049] is obtained. According to the eighth embodiment, it is easy to realize a wide dynamic range.

[0298] In the eighth embodiment, the capacitance of the first capacitor Cs3 can be reduced compared to the first embodiment, and the capacitance of the additional capacitor Cs5 can be adjusted to account for this reduction. This can prevent a decrease in the transitional SNR. This can widen the range of light intensity where the SNR is high.

[0299] (Ninth embodiment) FIG. 21 shows the circuit configuration of a pixel 1 of an imaging device 100 according to the ninth embodiment.

[0300] In the ninth embodiment, the first photoelectric conversion unit PC1 is a first photodiode. The imaging device 100 of the ninth embodiment also includes a first transfer transistor TX1. The first photoelectric conversion unit PC1 is connected to a first charge accumulation unit FD1 via the first transfer transistor TX1. The first charge accumulation unit FD1 is electrically connected to a first amplification transistor M10.

[0301] Specifically, in the ninth embodiment, the first imaging cell 1a includes a first transfer transistor TX1, and more specifically, the first signal processing circuit P1 includes a first transfer transistor TX1.

[0302] In the ninth embodiment, the second photoelectric conversion unit PC2 is a second photodiode. The imaging device 100 of the ninth embodiment also includes a second transfer transistor TX2. The second photoelectric conversion unit PC2 is connected to a second charge accumulation unit FD2 via the second transfer transistor TX2. The second charge accumulation unit FD2 is electrically connected to a second amplification transistor M20.

[0303] Specifically, in the ninth embodiment, the second imaging cell 1b includes a second transfer transistor TX2. More specifically, the second signal processing circuit P2 includes a second transfer transistor TX2.

[0304] In the ninth embodiment, the first photodiode generates positive charges as signal charges. Specifically, the signal charges are holes.

[0305] In the ninth embodiment, the second photodiode generates positive charges as signal charges. Specifically, the signal charges are holes.

[0306] In the ninth embodiment, transistors M10, M11, M12, TX1, M20, M21, M22, M23, and TX2 are p-type transistors. Specifically, they are p-type MOSFETs. On the other hand, transistors M16, M17, M26, and M27 are n-type transistors. Specifically, they are n-type MOSFETs.

[0307] However, negative charges may be used as the signal charges. Specifically, electrons may be used as the signal charges. In this case, n-type transistors may be used as the transistors M10, M11, M12, TX1, M20, M21, M22, M23, and TX2. Specifically, n-type MOSFETs may be used as these transistors. Furthermore, p-type transistors may be used as the transistors M16, M17, M26, and M27. Specifically, p-type MOSFETs may be used as these transistors.

[0308] (Tenth embodiment) Part or all of the technology of the tenth embodiment can be applied to the first to ninth embodiments. Fig. 22 is a plan view showing the arrangement of microlenses according to the tenth embodiment.

[0309] The first imaging cell 1a has a first microlens ML1. Light is incident on the first photoelectric conversion unit PC1 through the first microlens ML1. The second imaging cell 1b has a second microlens ML2. Light is incident on the second photoelectric conversion unit PC2 through the second microlens ML2. In a plan view, the area of ​​the second microlens ML2 is larger than the area of ​​the first microlens ML1. This size relationship makes it easy to make the sensitivity of the second imaging cell 1b higher than that of the first imaging cell 1a.

[0310] In a plan view, the ratio S2 / S1 of the area S2 of the second microlens ML2 to the area S1 of the first microlens ML1 is, for example, 16 or more. The ratio S2 / S1 may be 36 or more. The ratio S2 / S1 is, for example, 400 or less. The ratio S2 / S1 may be 100 or less.

[0311] Typically, the first microlens ML1 has a convex surface. Light is refracted by this convex surface and collected at the first photoelectric conversion unit PC1. The second microlens ML2 has a convex surface. Light is refracted by this convex surface and collected at the second photoelectric conversion unit PC2.

[0312] In this embodiment, the first microlens ML1 has a circular shape in a plan view, but the first microlens ML1 may have another shape, such as an elliptical shape, in a plan view.

[0313] In this embodiment, the second microlenses ML2 have a circular shape in a plan view, but may have other shapes, such as an elliptical shape, in a plan view.

[0314] The imaging device according to this embodiment includes a plurality of pixels 1. Therefore, the imaging device according to this embodiment includes a plurality of first microlenses ML1, a plurality of second microlenses ML2, a plurality of first photoelectric conversion units PC1, a plurality of second photoelectric conversion units PC2, a plurality of first photoelectric conversion layers D1, a plurality of second photoelectric conversion layers D2, a plurality of first upper electrodes E1a, a plurality of second upper electrodes E2a, a plurality of first pixel electrodes E1b, and a plurality of second pixel electrodes E2b.

[0315] In this embodiment, the multiple first microlenses ML1 and the multiple second microlenses ML2 form a continuous lens group. This continuous lens group has multiple convex surfaces. Each convex surface belongs to either the first microlens ML1 or the second microlens ML2.

[0316] In this embodiment, the plurality of first photoelectric conversion layers D1 and the plurality of second photoelectric conversion layers D2 form a continuous film, but the individual photoelectric conversion layers D1 or D2 may be spaced apart from each other.

[0317] In this embodiment, the plurality of first upper electrodes E1a and the plurality of second upper electrodes E2a form a continuous electrode, although the individual upper electrodes E1a or E2a may be spaced apart from each other.

[0318] Hereinafter, one pixel electrode, either the first pixel electrode E1b or the second pixel electrode E2b, will be referred to as a single pixel electrode. The single pixel electrodes are spaced apart from one another. A shield electrode is disposed between adjacent single pixel electrodes. The shield electrode collects signal charges generated by photoelectric conversion in the photoelectric conversion layer D1 or D2. In this way, the shield electrode can suppress noise from entering the charge accumulation unit FD1 or FD2.

[0319] 22, in this embodiment, the multiple first microlenses ML1 are arranged on a first axis 111 and a second axis 112. The multiple second microlenses ML2 are arranged on the first axis 111 and the second axis 112. In a plan view, each first microlens ML1 is disposed in a gap between four adjacent ones of the multiple second microlenses ML2. A dotted frame 105 in FIG. 22 surrounds the four adjacent second microlenses ML2. The second axis 112 is perpendicular to the first axis 111.

[0320] In this embodiment, in one pixel 1, the first microlens ML1 and the second microlens ML2 are aligned along a third axis 113 that is different from the first axis 111 and the second axis 112 in a plan view. In Fig. 22, the symbols MLa and MLb indicate the first microlens ML1 and the second microlens ML2 that belong to the same pixel 1, respectively.

[0321] According to this embodiment, the first microlenses ML1, which are relatively small in plan view, and the second microlenses ML2, which are relatively small, can be arranged efficiently.

[0322] (Eleventh embodiment) An imaging system 204 according to an eleventh embodiment will be described with reference to FIG.

[0323] 23 shows the system configuration of an imaging system 204 according to this embodiment. The imaging system 204 includes a lens optical system 201, an imaging device 200, a system controller 203, and a camera signal processing unit 202. In this embodiment, the imaging system 204 is a camera system.

[0324] The lens optical system 201 includes, for example, an autofocus lens, a zoom lens, and an aperture. The lens optical system 201 focuses light onto the imaging surface of the imaging device 200.

[0325] As the imaging device 200, the imaging device 100 described in the first to tenth embodiments can be used.

[0326] The system controller 203 controls the entire imaging system 204. The system controller 203 can be realized by, for example, a microcomputer.

[0327] The camera signal processing unit 202 functions as a signal processing circuit that processes an output signal from the imaging device 200. The camera signal processing unit 202 performs processes such as gamma correction, color interpolation, spatial interpolation, and auto white balance. The camera signal processing unit 202 can be realized by, for example, a DSP (Digital Signal Processor).

[0328] The camera signal processing unit 202 can acquire imaging data from the imaging device 200 and perform sensing on the imaging data. For example, the camera signal processing unit 202 can calculate the distance to a following vehicle through sensing. As described above, the camera signal processing unit 202 may detect a specific subject in the acquired imaging data and start sensing in response to the detection.

[0329] The imaging system 204 includes a program constituting software for synthesizing pixel signals corresponding to the creation of the above-mentioned "one line." Specifically, the camera signal processing unit 202 includes this program. For details about the synthesis of pixel signals, please refer to the above description with reference to FIGS. 6 and 7.

[0330] As can be understood from the above description, the imaging system 204 includes the imaging device 200 and a program. The program constitutes software. The software generates a composite signal that changes in response to changes in the amount of light incident on the imaging device 200, based on the pixel signal from the first charge accumulation unit FD1 and the pixel signal from the first capacitor Cs3. Specifically, the software generates a composite signal that changes in response to changes in the amount of light incident on the imaging device 200, based on the pixel signal from the second charge accumulation unit FD2, the pixel signal from the first charge accumulation unit FD1, and the pixel signal from the first capacitor Cs3. The pixel signal from the second charge accumulation unit FD2 is the second pixel signal V in the previous embodiment. FD2 The pixel signal from the first charge storage unit FD1 is the first pixel signal V FD1 The pixel signal from the first capacitor Cs3 is the third pixel signal V FD3 is.

[0331] In the imaging system 204, programs constituting the software can be stored in a computer-readable recording medium, such as a random access memory (RAM), a read-only memory (ROM), a disk drive, a solid state drive (SSD), or a flash memory.

[0332] According to the technology disclosed herein, it is possible to acquire optimal sensing data, and it is also possible to provide an imaging system that can achieve low power consumption as a whole.

[0333] Various modifications can be applied to the technology according to the present disclosure.

[0334] For example, the first capacitor Cs3 of the first imaging cell 1a of the fourth embodiment shown in Fig. 16 may be omitted. In this case, the specific capacitor Cs1 can be considered to constitute the first capacitor. This also applies to the fifth embodiment shown in Fig. 17.

[0335] The configuration of the second imaging cell 1b of the sixth embodiment shown in FIG. 18 may be applied to the first imaging cell 1a.

[0336] In the above-described embodiments, the first intervening transistor M16, the first capacitor Cs3, and the first subsequent transistor M17 belong to the first imaging cell 1a. However, they may also belong to the second imaging cell 1b. Or, they may be arranged outside the first imaging cell 1a and the second imaging cell 1b. This also applies to the additional amplifying transistor M30 and the additional selection transistor M31 according to the second embodiment shown in FIG. 13. This also applies to the additional capacitor Cs5, the additional intervening transistor M36, and the additional subsequent transistor M37 according to the eighth embodiment shown in FIG. 20.

[0337] In the sixth embodiment shown in FIG. 18, the second capacitor Cs4, the second intervening transistor M26, and the second subsequent transistor M27 belong to the second imaging cell 1b. However, they may also belong to the first imaging cell 1a. Also, they may be arranged outside the first imaging cell 1a and the second imaging cell 1b. These points are the same for the seventh embodiment shown in FIG. 19.

[0338] In the eighth embodiment shown in FIG. 20 , the other of the source and drain of the first subsequent transistor M17 is electrically connected to the first charge storage unit FD1. However, as in the third embodiment shown in FIG. 15 , this electrical connection may be to the second charge storage unit FD2. As in the fourth embodiment shown in FIG. 16 , the second reset transistor M22 may be used as the first subsequent transistor M17, and the electrical connection may be to the second charge storage unit FD2. As in the fifth embodiment shown in FIG. 17 , the first reset transistor M12 may be used as the first subsequent transistor M17, and the electrical connection may be to the first charge storage unit FD1. The additional capacitor Cs5, additional intervening transistor M36, and additional subsequent transistor M37 of the eighth embodiment shown in FIG. 20 may be applied to the sixth embodiment shown in FIG. 18 , the seventh embodiment shown in FIG. 19 , or the ninth embodiment shown in FIG. 21 .

[0339] 21, both the first photoelectric conversion unit PC1 and the second photoelectric conversion unit PC2 are photodiodes. However, the first photoelectric conversion unit PC1 may have a pair of electrodes E1a and E1b and a first photoelectric conversion layer D1, and the second photoelectric conversion unit PC2 may be a photodiode. Alternatively, the first photoelectric conversion unit PC1 may be a photodiode, and the second photoelectric conversion unit PC2 may have a pair of electrodes E2a and E2b and a second photoelectric conversion layer D2.

[0340] In the imaging device 100 or 200 of each of the above-described embodiments, a first imaging cell 1a and a second imaging cell 1b are configured in one pixel 1. In the imaging device 100 or 200 of each of the above-described embodiments, a one-pixel, two-cell system is adopted, in which two imaging cells are configured in one pixel 1. However, in addition to the imaging cells 1a and 1b, another imaging cell may be configured in one pixel 1. Also, only one of the first imaging cell 1a and the second imaging cell 1b may be configured in one pixel 1. In other words, a one-pixel, one-cell system in which one imaging cell is configured in one pixel 1 may be adopted. The technology according to the present disclosure can also be applied to an imaging device using the one-pixel, one-cell system. A wide dynamic range can also be achieved with the one-pixel, one-cell system.

[0341] In a first example of the one-pixel-one-cell system, an imaging cell similar to the second imaging cell 1b shown on the right side of FIG. 18 is configured in one pixel 1. According to the first example, noise cancellation is possible. In a second example of the one-pixel-one-cell system, an imaging cell similar to the first imaging cell 1a shown on the left side of FIG. 18 is configured in one pixel 1. The second example does not enable noise cancellation, but is simple. It is also possible to adopt a one-pixel-one-cell system using an imaging cell similar to the first imaging cell 1a or second imaging cell 1b in other drawings.

[0342] Fig. 24 is a schematic diagram showing a circuit configuration of a one-pixel-one-cell type pixel according to an example. Specifically, the pixel in Fig. 24 includes an imaging cell 1x similar to the first imaging cell 1a in Fig. 3. As described above, a one-pixel-one-cell type pixel may include an imaging cell similar to the first imaging cell 1a or second imaging cell 1b in the other drawings.

[0343] In each embodiment, elements may be added or omitted as appropriate. For example, an element such as a transistor may be added between the first intermediate transistor M16 and the first capacitor Cs3. "When the first intermediate transistor M16 is turned on, the first charge storage unit FD1 and the first capacitor Cs3 are electrically connected" encompasses the case where this addition is made. [Industrial Applicability]

[0344] The imaging device according to the present disclosure can be used in a variety of camera systems and sensor systems, such as digital still cameras, medical cameras, surveillance cameras, vehicle-mounted cameras, digital single-lens reflex cameras, and digital mirrorless single-lens cameras. [Explanation of symbols]

[0345] 1 pixel 1a, 1b, 1c, 1x imaging cells 2a, 2b Vertical scanning circuit 3a,3b horizontal scanning circuit 4a, 4b Column AD conversion circuit 5a,5b Current source 6a, 6b Reset signal lines 7a, 7b Address signal lines 8a,8b power supply wiring 9a,9b Vertical signal line 10a, 10b Feedback signal lines 11a, 11b Inverting amplifier 100,200 imaging device 102 Output circuit 111,112,113 axes 201 Lens Optical System 202 Camera signal processing unit 203 System Controller 204 Imaging System Cc1, Cs1, Cs3, Cs4, Cs5, CsZ capacitors D1, D2 photoelectric conversion layer E1a,E2a Upper electrode E1b, E2b pixel electrodes FD1, FD2 charge storage section FD3,FD4,FD5 part M10, M20, M30 Amplification transistors M11, M21, M31 selection transistors M12, M22 Reset transistor M16, M26, M36 Intervening transistors M17, M27, M37 subsequent transistors M23 Bandwidth control transistor ML1, ML2 Micro Lenses Out1,Out2,Out3 signal line TX1,TX2 transfer transistors P1, P2 signal processing circuit PC1, PC2 photoelectric conversion section VDD1, VDD2, VDD3 voltage lines

Claims

1. a first photoelectric conversion unit that converts light into electric charges; a first charge storage unit that stores the charge; a first capacitor; an output circuit electrically connected to the first capacitor; a first intervening transistor having a gate electrode, a source, and a drain; Equipped with one of the source and the drain and the gate electrode are electrically connected to the first charge accumulation unit, the other of the source and the drain is electrically connected to the first capacitor; the first charge storage portion, the gate electrode, and one of the source and the drain are always at the same potential during one control cycle; When the first intervening transistor is turned on, the first charge storage unit and the first capacitor are electrically connected to each other; the output circuit includes a first amplifying transistor having a gate electrode electrically connected to the first capacitor; Imaging device.

2. a first photoelectric conversion unit that converts light into electric charges; a first charge storage unit that stores the charge; a first capacitor; an output circuit electrically connected to the first capacitor; a first intervening transistor having a gate electrode, a source, and a drain; Equipped with one of the source and the drain and the gate electrode are electrically connected to the first charge accumulation unit without a switch element; the other of the source and the drain is electrically connected to the first capacitor; the output circuit includes a first amplifying transistor having a gate electrode electrically connected to the first capacitor; Imaging device.

3. further comprising a first subsequent transistor; When the first subsequent transistor is turned on, the gate electrode of the first amplification transistor is electrically connected to the first capacitor. The imaging device according to claim 1 or 2.

4. the first photoelectric conversion unit includes a first electrode, a second electrode, and a photoelectric conversion layer disposed between the first electrode and the second electrode; The imaging device according to claim 1 .

5. the first photoelectric conversion unit is a photodiode; The imaging device according to claim 1 .

6. the first capacitor has a metal-insulator-metal structure; The imaging device according to claim 1 .

7. When the first intervening transistor is turned on, the first charge storage unit is electrically connected to one end of the first capacitor, A DC potential is applied to the other end of the first capacitor. The imaging device according to claim 1 .

8. the imaging device is configured to be capable of being in a first state and a second state; the first state is a state in which the first charge storage unit and the first capacitor are electrically connected via the first intervening transistor; the second state is a state in which there is no capacitor electrically connected to the first charge storage unit; The imaging device according to claim 1 .

9. the conductivity type of the gate electrode of the first intermediate transistor is opposite to the conductivity type of the source and the drain of the first intermediate transistor; The imaging device according to claim 1 .

10. the imaging device is configured such that, after a signal corresponding to the potential of the first capacitor is read out, a signal corresponding to the potential of the first charge accumulation unit is read out. The imaging device according to claim 1 .

11. an additional capacitor, and an additional intervening transistor having a gate electrode, a source, and a drain; the gate electrode of the additional intervening transistor and one of the source and the drain of the additional intervening transistor are electrically connected to the first capacitor; When the additional intervening transistor is turned on, the first capacitor and the additional capacitor are electrically connected to each other. The imaging device according to claim 1 .

12. a first subsequent transistor having a gate electrode, a source, and a drain; the first charge accumulation unit is electrically connected to the gate electrode of the first amplification transistor, When the first subsequent transistor is turned on, the first capacitor, one of the source and the drain of the first subsequent transistor, the other of the source and the drain of the first subsequent transistor, and the gate electrode of the first amplification transistor are electrically connected in this order. The imaging device according to claim 1 .

13. A first photoelectric conversion unit that converts light into an electric charge; a first charge storage unit that stores the charge; a first capacitor; an output circuit electrically connected to the first capacitor; a first intervening transistor having a gate electrode, a source, and a drain; a first amplifying transistor having a gate electrode; the gate electrode of the first intermediate transistor and one of the source and the drain of the first intermediate transistor are electrically connected to the first charge storage unit; the other of the source and the drain of the first intervening transistor is electrically connected to the first capacitor; the output circuit includes an additional amplifying transistor having a gate electrode; the first charge accumulation unit is electrically connected to the gate electrode of the first amplification transistor, the first capacitor is electrically connected to the gate electrode of the additional amplifying transistor; Imaging device.

14. a first imaging cell; and a second imaging cell including a second photoelectric conversion unit and a second charge accumulation unit; the first imaging cell and the second imaging cell are included in one pixel of the imaging device, the first imaging cell includes the first photoelectric conversion unit and the first charge accumulation unit, the second charge accumulation unit accumulates the charge generated by the second photoelectric conversion unit; The imaging device according to claim 12 or 13.

15. a first imaging cell; and a second imaging cell including a second photoelectric conversion unit and a second charge accumulation unit; the first imaging cell and the second imaging cell are included in one pixel of the imaging device, the first imaging cell includes the first photoelectric conversion unit and the first charge accumulation unit, the second charge accumulation unit accumulates the charge generated by the second photoelectric conversion unit; The imaging device according to claim 1 .

16. a first subsequent transistor having a gate electrode, a source, and a drain; the first imaging cell includes the first amplifying transistor; the second imaging cell further includes a second amplifying transistor having a gate electrode; the first charge accumulation unit is electrically connected to the gate electrode of the first amplification transistor, the second charge accumulation unit is electrically connected to the gate electrode of the second amplification transistor, When the first subsequent transistor is turned on, the first capacitor, one of the source and the drain of the first subsequent transistor, the other of the source and the drain of the first subsequent transistor, and the gate electrode of the second amplification transistor are electrically connected in this order. The imaging device according to claim 15.

17. a first subsequent transistor having a gate electrode, a source, and a drain; the first imaging cell includes the first amplifying transistor; The second imaging cell further includes a specific capacitor; the first capacitor is electrically connected to the specific capacitor; the first charge accumulation unit is electrically connected to the gate electrode of the first amplification transistor, When the first subsequent transistor is turned on, the first capacitor, one of the source and the drain of the first subsequent transistor, the other of the source and the drain of the first subsequent transistor, and the gate electrode of the first amplification transistor are electrically connected in this order. The imaging device according to claim 15.

18. the second imaging cell further includes a second capacitor and a second intervening transistor having a gate electrode, a source, and a drain; the gate electrode of the second intermediate transistor and one of the source and the drain of the second intermediate transistor are electrically connected to the second charge accumulation section; When the second intervening transistor is turned on, the second charge storage unit and the second capacitor are electrically connected to each other. The imaging device according to any one of claims 14 to 17.

19. the first imaging cell includes a first microlens; the second imaging cell includes a second microlens; In a plan view, the area of ​​the second microlens is larger than the area of ​​the first microlens. The imaging device according to any one of claims 14 to 18.

20. The sensitivity of the second imaging cell is higher than the sensitivity of the first imaging cell.

20. The imaging device according to claim 14.

21. A photoelectric conversion unit that converts light into an electric charge; a charge storage unit that stores the charge; A capacitor; a first transistor having a gate electrode electrically connected to the capacitor; a second transistor having a gate electrode, a source, and a drain; Equipped with the gate electrode of the second transistor is electrically connected to the charge storage portion; one of the source and the drain of the second transistor is electrically connected to the charge storage unit without passing through a switch; the other of the source and the drain of the second transistor is electrically connected to the capacitor; Imaging device.

Images