Semiconductor Devices

Abstract

To provide a semiconductor device capable of suppressing breakage of a gate insulating film.SOLUTION: A semiconductor device comprises: a first electrode; a first semiconductor layer of a first conductivity type connected with the first electrode, and including silicon carbide; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer; a third semiconductor layer of the first conductivity type provided on a part of the second semiconductor layer; a second electrode connected with the second and third semiconductor layers; a third electrode provided in an upper part of the first semiconductor layer, in the second semiconductor layer, and in the third semiconductor layer; an insulating film provided between the first, second, and third semiconductor layers and the third electrode; and a fourth semiconductor layer provided between the insulating film and the first and second semiconductor layers, being in contact with the insulating film and having an impurity concentration lower than those of the first and second semiconductor layers.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] Power semiconductor devices using silicon carbide instead of silicon have been developed. Compared to silicon-based semiconductor devices, silicon carbide semiconductor devices can withstand stronger electric fields, improving the balance between breakdown voltage and on-resistance. However, as the electric field in silicon carbide increases, the electric field applied to the gate insulating film also increases, resulting in a problem of reduced reliability of the gate insulating film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-197792 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiment is to provide a semiconductor device capable of suppressing breakdown of a gate insulating film. [Means for solving the problem]

[0005] a second semiconductor layer of a second conductivity type that includes silicon carbide and is provided on the first semiconductor layer; a third semiconductor layer of the first conductivity type that includes silicon carbide and is provided on a portion of the second semiconductor layer; a second electrode connected to the second semiconductor layer and the third semiconductor layer; third electrodes provided in an upper portion of the first semiconductor layer, inside the second semiconductor layer, and inside the third semiconductor layer; insulating films that include silicon oxide and are provided between the first semiconductor layer and the third electrode, between the second semiconductor layer and the third electrode, and between the third semiconductor layer and the third electrode; and a fourth semiconductor layer that is provided between the insulating film and the first semiconductor layer and between the insulating film and the second semiconductor layer, in contact with the insulating film, includes silicon carbide, and has an impurity concentration that is lower than the impurity concentration of the first semiconductor layer and the impurity concentration of the second semiconductor layer. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment. [Figure 2] 2(a) and 2(b) are cross-sectional views showing the operation of the semiconductor device according to the first embodiment. [Figure 3] 3(a) to 3(d) are diagrams showing a first method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] 4(a) to 4(d) are diagrams showing a second manufacturing method for the semiconductor device according to the first embodiment. [Figure 5] FIG. 5 is a cross-sectional view showing a semiconductor device according to the second embodiment. [Figure 6] FIG. 6 is a plan view showing a semiconductor device according to the third embodiment. [Figure 7] 7(a) is a cross-sectional view taken along line BB' in FIG. 6, and FIG. 7(b) is a cross-sectional view taken along line CC' in FIG. [Figure 8] 8(a) to 8(d) are diagrams showing a method for manufacturing a semiconductor device according to the third embodiment. [Figure 9] FIG. 9 is a cross-sectional view showing a semiconductor device according to the fourth embodiment. [Figure 10] FIG. 10 is a cross-sectional view showing a semiconductor device according to the fifth embodiment. [Figure 11] FIG. 11 is a cross-sectional view showing a semiconductor device according to the sixth embodiment. [Figure 12] FIG. 12 is a cross-sectional view showing a semiconductor device according to the seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] First Embodiment FIG. 1 is a cross-sectional view showing a semiconductor device according to this embodiment. The drawings are schematic and have been simplified as appropriate. The same applies to other drawings described later. Furthermore, the dimensional ratios of the components in the drawings do not necessarily match exactly.

[0008] 1, the semiconductor device 1 according to this embodiment is a trench-gate MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The semiconductor device 1 includes a drain electrode 10 (first electrode), a semiconductor portion 20, a source electrode 30 (second electrode), a gate electrode 40 (third electrode), and a gate insulating film 50 (insulating film).

[0009] Hereinafter, for convenience of explanation, this specification will adopt an XYZ Cartesian coordinate system. The direction connecting the drain electrode 10 and the source electrode 30 is referred to as the "Z direction," the direction in which the gate electrode 40 extends is referred to as the "Y direction," and the direction perpendicular to the Z direction and the Y direction is referred to as the "X direction." In addition, within the Z direction, the direction from the drain electrode 10 toward the source electrode 30 is also referred to as "up," and the opposite direction is also referred to as "down," but these expressions are also for convenience and are unrelated to the direction of gravity.

[0010] The drain electrode 10 and the source electrode 30 are plate-shaped and extend along the XY plane. The semiconductor portion 20 is disposed on the drain electrode 10. The source electrode 30 is disposed on the semiconductor portion 20. The gate electrode 40 is disposed inside the semiconductor portion 20. A plurality of gate electrodes 40 are arranged along the X direction. Each gate electrode 40 extends in the Y direction. Each gate electrode 40 is connected to a gate pad (not shown) provided on the semiconductor portion 20, and a voltage is applied to each gate electrode 40 from the gate pad. A gate insulating film 50 is disposed between the gate electrode 40 and the semiconductor portion 20, and insulates the gate electrode 40 from the semiconductor portion 20.

[0011] The semiconductor portion 20 includes silicon carbide (SiC) and is made of, for example, single crystal silicon carbide. Impurities that act as donors or acceptors are locally introduced into the semiconductor portion 20, making the conductivity type of each portion n-type or p-type. The impurities that act as donors are, for example, nitrogen (N), and the impurities that act as acceptors are, for example, aluminum (Al) or boron (B). The gate insulating film 50 includes silicon oxide (SiO).

[0012] The semiconductor portion 20 includes a drain layer 21 (first layer), a drift layer 22 (second layer), a base layer 23 (second semiconductor layer), a source layer 24 (third semiconductor layer), a low-concentration layer 25 (fourth semiconductor layer), and a buried p-type layer 26 (fifth semiconductor layer). For example, the conductivity type of the drain layer 21 is n ++ The conductivity type of the drift layer 22 is n - The conductivity type of the base layer 23 is p-type. The conductivity type of the source layer 24 is n-type. + The conductivity type of the low concentration layer 25 is n - The conductivity type of the buried p-type layer 26 is p ++ It is a shape.

[0013] The superscript symbols attached to the letters "n" and "p" that represent the conductivity type indicate the relative level of impurity concentration. For n-type, the order of increasing impurity concentration is "n ++ shape”, “n + ``shaped'', ``n-shaped'', ``n -The same applies to p-type. In this specification, "impurity concentration" refers to the effective impurity concentration that contributes to the conduction of a semiconductor, and when a region contains both impurities that act as donors and impurities that act as acceptors, it refers to the concentration excluding the offsetting amounts.

[0014] n ++ The drain layer 21 is disposed on the drain electrode 10, contacts the drain electrode 10, and is connected to the drain electrode 10. In this specification, "connection" refers to electrical connection. - The drift layer 22 having a shape similar to that of the drain layer 21 is disposed on the drain layer 21, contacts the drain layer 21, and is connected to the drain layer 21. The impurity concentration of the drift layer 22 is lower than the impurity concentration of the drain layer 21. The drain layer 21 and the drift layer 22 form a first semiconductor layer, but the first semiconductor layer may also be formed by the drift layer 22 alone.

[0015] The p-type base layer 23 is disposed on the drift layer 22 and is in contact with the drift layer 22. In the base layer 23, p + The drift layer 22 includes a p-type lower layer 23a and a p-type upper layer 23b. The lower layer 23a is in contact with the drift layer 22. The upper layer 23b is disposed on the lower layer 23a. The impurity concentration of the lower layer 23a is higher than the impurity concentration of the upper layer 23b.

[0016] n + The source layer 24 is disposed on a portion of the base layer 23. The source layer 24 is in contact with the upper layer 23b of the base layer 23. A plurality of source layers 24 are provided and are arranged along the X direction. Each source layer 24 extends in the Y direction.

[0017] The source electrode 30 is disposed on the base layer 23 and the source layer 24, and is connected to the upper layer 23b of the base layer 23 and the source layer 24. The gate electrode 40 is disposed in the upper part of the drift layer 22, inside the base layer 23, and inside the source layer 24. In other words, the gate electrode 40 penetrates the source layer 24 and the base layer 23 in the Z direction, and its lower end is located in the upper part of the drift layer 22.

[0018] The gate insulating film 50 covers the gate electrode 40 and is in contact with the gate electrode 40. The gate insulating film 50 is disposed between the drift layer 22 and the gate electrode 40, between the base layer 23 and the gate electrode 40, and between the source layer 24 and the gate electrode 40. A part of the upper surface of the semiconductor portion 20 is covered with the gate insulating film 50. Of the upper surface of the semiconductor portion 20, a region not covered with the gate insulating film 50 has a height in the Z direction slightly lower than a region covered with the gate insulating film 50.

[0019] n - The low-concentration layer 25 is disposed between the gate insulating film 50 and the drift layer 22, between the gate insulating film 50 and the base layer 23, and between the gate insulating film 50 and the source layer 24. The low-concentration layer 25 is in contact with the gate insulating film 50, the drift layer 22, the base layer 23, the source layer 24, and the source electrode 30. The impurity concentration of the low-concentration layer 25 is lower than the impurity concentration of the drift layer 22. The impurity concentration of the low-concentration layer 25 is also lower than the impurity concentration of the upper layer 23b of the base layer 23.

[0020] p ++ The buried p-type layer 26 is disposed between the drain electrode 10 and the gate electrode 40, and is disposed in the drift layer 22 directly below the low-concentration layer 25. The buried p-type layer 26 is in contact with the drift layer 22 and the low-concentration layer 25. The buried p-type layer 26 is separated from the gate insulating film 50 via the low-concentration layer 25. This allows the impurity concentration of the buried p-type layer 26 to be increased without introducing defects into the gate insulating film 50. The impurity concentration of the buried p-type layer 26 is higher than the impurity concentration of the upper layer 23b of the base layer 23. The buried p-type layer 26 is connected to the base layer 23 at a portion not shown. An aspect in which the buried p-type layer 26 is connected to the base layer 23 will be described in a third embodiment.

[0021] The following are examples of impurity concentrations in each layer: ++ The impurity concentration of the drain layer 21 is, for example, 1×10 19 cm-3 n - The impurity concentration of the drift layer 22 is, for example, 1×10 15 cm -3 3x10 or more 16 cm -3 The impurity concentration of the p-type base layer 23 is, for example, 5×10 16 cm -3 More than 1×10 19 cm -3 The impurity concentration of the portion of the upper layer 23b of the base layer 23 adjacent to the low concentration layer 25 is, for example, 1×10 17 cm -3 n + The impurity concentration of the source layer 24 is, for example, 5×10 16 cm -3 5x10 or more 17 cm -3 The following is the result.

[0022] n - The impurity concentration of the low concentration layer 25 is, for example, 1×10 14 cm -3 More than 1×10 15 cm -3 The following is true: ++ The impurity concentration of the buried p-type layer 26 is, for example, 5×10 18 cm -3 Over 2×10 19 cm -3 As described above, the impurity concentration of the low-concentration layer 25 is lower than the impurity concentration of the drift layer 22 and lower than the impurity concentration of the upper layer 23b of the p-type base layer 23. In addition, the impurity concentration of the buried p-type layer 26 is higher than the impurity concentration of the upper layer 23b of the p-type base layer 23.

[0023] The thickness of the drift layer 22 is, for example, 4 μm or more and 50 μm or less. This results in a breakdown voltage of the semiconductor device 1 of, for example, 650 V or more and 6.5 kV or less. Note that the higher the required breakdown voltage, the lower the impurity concentration of the drift layer 22 and the thicker the drift layer 22 must be. The thickness of the low-concentration layer 25 is, for example, 10 nm or more and 100 nm or less.

[0024] Next, the operation of the semiconductor device 1 according to this embodiment will be described. 2(a) and 2(b) are cross-sectional views showing the operation of the semiconductor device according to this embodiment. Figures 2(a) and (b) show region A in Figure 1. Figure 2(a) shows the off state, and Figure 2(b) shows the on state.

[0025] A voltage is applied between the drain electrode 10 and the source electrode 30, with the drain electrode 10 as the positive electrode and the source electrode 30 as the negative electrode. In this state, as shown in FIG. 2(a), when a voltage lower than the threshold voltage is applied to the gate electrode 40, n - The interface between the p-type drift layer 22 and the p-type base layer 23, and - Drift layer 22 and p ++ The depletion layer spreads from the interface of the buried p-type layer 26. - The low concentration layer 25 is also depleted and no current flows therethrough, thereby turning the semiconductor device 1 into an off state.

[0026] At this time, because the impurity concentration of the buried p-type layer 26 is high, a depletion layer extends significantly within the drift layer 22, starting from the interface with the buried p-type layer 26. As a result, the depletion layer becomes thicker near the buried p-type layer 26, and the electric field strength decreases accordingly. In particular, the spacing between the equipotential lines 102 increases near the point 101 where the electric field tends to concentrate, and the electric field strength decreases. As a result, the electric field strength applied to the gate insulating film 50 also decreases, improving the reliability of the gate insulating film 50.

[0027] On the other hand, as shown in FIG. 2(b), when a voltage higher than the threshold voltage is applied to the gate electrode 40, n - Electrons 103 are accumulated in the low concentration layer 25, which is shaped like a gate electrode, resulting in an accumulation mode, and a current flows through the drain electrode 10, drain layer 21, drift layer 22, low concentration layer 25, source layer 24, and source electrode 30. As a result, the semiconductor device 1 turns on.

[0028] Next, a method for manufacturing the semiconductor device 1 according to this embodiment will be described. First, the first manufacturing method will be described. 3(a) to 3(d) are diagrams showing a first method for manufacturing a semiconductor device according to this embodiment.

[0029] First, as shown in Figure 1, ++ A silicon carbide wafer having a shape similar to that shown in FIG.

[0030] Next, as shown in FIG. 3(a), starting from the top surface of the drain layer 21, - An epitaxial layer 61 made of silicon carbide is epitaxially grown. Next, impurities that will become acceptors are ion-implanted into a portion of the upper layer portion of the epitaxial layer 61 to form the buried p-type layer 26. The buried p-type layer 26 is formed in a strip shape extending in the Y direction.

[0031] Next, as shown in FIG. 3(b), an epitaxial layer 62 is formed on the epitaxial layer 61. The conductivity types of the epitaxial layer 62 are, in order from the bottom, n - shape, p + In this case, the epitaxial layer 61 except for the buried p-type layer 26 and the epitaxial layer 62 are n-type and p-type. - The p-shaped portion becomes the drift layer 22, and the p-shaped portion becomes the p-shaped portion in the epitaxial layer 62. + The p-type portion of the epitaxial layer 62 becomes the lower layer 23a of the base layer 23, and the p-type portion of the epitaxial layer 62 becomes the upper layer 23b of the base layer 23. - After forming the structure, p + A shaped portion and a p-shaped portion may be formed.

[0032] Next, as shown in FIG. 3(c), n is implanted in a part of the upper layer portion of the epitaxial layer 62. + Next, a trench 63 is formed in the epitaxial layer 62 in a region directly above the buried p-type layer 26. The trench 63 penetrates the source layer 24 and reaches the buried p-type layer 26.

[0033] Next, as shown in Figure 3(d), a thin n - Forming a molding layer 64. - The thickness of the molded layer 64 is 10 nm to 100 nm. - The portion of the etched layer 64 formed on the inner surface of the trench 63 becomes the low concentration layer 25 .

[0034] Next, as shown in FIG. 1, a gate insulating film 50 and a gate electrode 40 are formed in the trench 63. Heat treatment is performed as appropriate to activate the ion-implanted impurities. Next, a drain electrode 10 is formed on the lower surface of the drain layer 21, and a source electrode 30 is formed on the epitaxial layer 62 and the gate insulating film 50. Next, the silicon carbide wafer is diced into individual pieces. In this manner, the semiconductor device 1 is manufactured.

[0035] Next, a second manufacturing method will be described. 4(a) to 4(d) are diagrams showing a second method for manufacturing a semiconductor device according to this embodiment. In FIGS. 4(a) to 4(d), for convenience, the same position in the Z direction is indicated by a broken line. The same parts of the second manufacturing method as those of the first manufacturing method will not be described.

[0036] 4(a), an epitaxial layer 66 is epitaxially grown on the drain layer 21. On the epitaxial layer 66, a drift layer 22, a lower layer 23a and an upper layer 23b of the base layer 23, and a source layer 24 are formed. 4(b), a trench 63 is formed in the epitaxial layer 66. The trench 63 penetrates the source layer 24 and the base layer 23 and reaches the upper portion of the drift layer 22.

[0037] Next, as shown in FIG. 4(c), impurities that will become acceptors are ion-implanted into the bottom surface of the trench 63, thereby forming the buried p-type layer 26. Next, as shown in Figure 4(d), a thin n - A mold layer 64 is formed. The subsequent steps are the same as those in the first manufacturing method.

[0038] Next, the effects of this embodiment will be described. In this embodiment, a low-concentration layer 25 is provided in contact with the gate insulating film 50. By bringing the gate insulating film 50 into contact with the low-concentration layer 25 with a low impurity concentration, it is possible to suppress the introduction of defects into the gate insulating film 50 and improve the reliability of the gate insulating film 50. If a gate insulating film containing silicon oxide were to be brought into contact with a high-concentration layer with a high impurity concentration, the reliability life of the gate insulating film would be reduced. In this embodiment, bringing the gate insulating film 50 into contact with the low-concentration layer 25 solves this problem and improves the reliability of the gate insulating film 50.

[0039] Furthermore, in this embodiment, the buried p-type layer 26 is separated from the gate insulating film 50 via the low-concentration layer 25. This allows the impurity concentration of the buried p-type layer 26 to be increased, and a thick depletion layer can be formed around the buried p-type layer 26 when the semiconductor device 1 is in the off state. As a result, the electric field applied to the gate insulating film 50 is weakened, and damage to the gate insulating film 50 can be suppressed. In other words, the reliability of the gate insulating film 50 can be improved.

[0040] In order to suppress the electric field applied to the bottom of the gate insulating film 50, particularly the corners, it is preferable to increase the impurity concentration of the buried p-type layer 26. However, if the low-concentration layer 25 is not provided and the buried p-type layer 26 is in contact with the gate insulating film 50, increasing the impurity concentration of the buried p-type layer 26 reduces the reliability life of the gate insulating film 50, as described above. This poses a problem in that the impurity concentration of the buried p-type layer 26 cannot be increased. In this embodiment, by interposing the low-concentration layer 25 between the gate insulating film 50 and the buried p-type layer 26, the above-described problem can be avoided, and the impurity concentration of the buried p-type layer 26 can be increased while ensuring the reliability life of the gate insulating film 50. This suppresses the electric field applied to the bottom of the gate insulating film 50, particularly the corners, and suppresses breakdown of the gate insulating film 50.

[0041] <Second embodiment> FIG. 5 is a cross-sectional view showing the semiconductor device according to this embodiment. As shown in FIG. 5, in the semiconductor device 2 according to this embodiment, in addition to the configuration of the semiconductor device 1 according to the first embodiment, a deep n-type layer 27 (third layer) is provided in the semiconductor portion 20.

[0042] The conductivity type of the deep n-type layer 27 is n + The impurity concentration of the deep n-type layer 27 is higher than the impurity concentration of the drift layer 22. The impurity concentration of the deep n-type layer 27 is, for example, 5×10 16 cm -3 5x10 or more 17 cm -3 The deep n-type layer 27 is disposed between the drift layer 22 and the base layer 23, and extends along the XY plane. The deep n-type layer 27 is in contact with the drift layer 22, the lower layer 23a of the base layer 23, and the low-concentration layer 25. The deep n-type layer 27 may be in contact with the buried p-type layer 26, or may be separated from it.

[0043] In the semiconductor device 2 according to this embodiment, when in the on state, the electron current 105 that has passed through the low concentration layer 25 in the accumulation mode is diffused in the X direction via the deep n-type layer 27. This makes the current flowing through the drift layer 22 uniform, reducing the on-resistance. Other configurations, operations, and effects of this embodiment are the same as those of the first embodiment.

[0044] <Third embodiment> This embodiment is an example in which a wider area of ​​the semiconductor device according to the second embodiment is explained. FIG. 6 is a plan view showing the semiconductor device according to this embodiment. 7(a) is a cross-sectional view taken along line BB' in FIG. 6, and FIG. 7(b) is a cross-sectional view taken along line CC' in FIG. The plane shown in Fig. 6 corresponds to the cross section taken along line DD' in Fig. 7(a) and (b). For convenience, the same positions in the Z direction are indicated by multiple dashed lines in Fig. 7(a) and (b).

[0045] As shown in Fig. 6, a cell region Rc and a termination region Rt are defined in the semiconductor device 3 according to this embodiment. Fig. 6 shows an enlarged plan view of a portion of the semiconductor device 3, and in the overall plan view of the semiconductor device 3, the cell region Rc is located in the center of the semiconductor device 3, and the termination region Rt surrounds the cell region Rc. In the cell region Rc, a transistor region R1 and a connection region R2 are defined. A plurality of transistor regions R1 and a plurality of connection regions R2 are provided, and are arranged alternately along the Y direction, for example, periodically.

[0046] In the connection region R2 of the cell region Rc, a connection layer 28 is provided. end The connection layer 28 is also provided in the end region Rt. + The impurity concentration is, for example, 5×10 18 cm -3 Over 2×10 19 cm -3 7, the connection layer 28 is disposed between the drift layer 22 and the base layer 23, and is in contact with the drift layer 22, the low-concentration layer 25, and the base layer 23. When viewed from above, the connection layer 28 covers both ends of the low-concentration layer 25 in the Y direction. In the connection region R2 and the termination region Rt of the cell region Rc, the deep n-type layer 27 is not provided.

[0047] On the other hand, in the transistor region R1 of the cell region Rc, the lower layer 23a of the base layer 23, the buried p-type layer 26, and the deep n-type layer 27 are provided, but the connection layer 28 is not provided. Since the transistor region R1 and the connection region R2 are arranged adjacent to each other, the connection layer 28 is also in contact with the buried p-type layer 26 and the deep n-type layer 27. As a result, the connection layer 28 connects the buried p-type layer 26 to the base layer 23.

[0048] Next, a method for manufacturing the semiconductor device according to this embodiment will be described. 8(a) to 8(d) are diagrams showing a method for manufacturing a semiconductor device according to this embodiment. 8(a) and (b) show the same process, and (c) and (d) show the same process. Also, Figures 8(a) and (c) show the transistor region R1, and (b) and (d) show the connection region R2.

[0049] 8(a) and 8(b), a first epitaxial layer 67 is epitaxially grown on the drain layer 21. The conductivity type of the epitaxial layer 67 is n-type. - Next, impurities to be donors or acceptors are ion-implanted into the upper portion of the epitaxial layer 67. At this time, as shown in FIG. 8(a), in the transistor region R1, the upper portion of the epitaxial layer 67 is made into an n-type + 8B, in the connection region R2, the upper layer portion of the epitaxial layer 67 is formed as a p + The connection layer 28 is formed to a depth greater than that of the deep n-type layer 27. The portion of the epitaxial layer 67 excluding the deep n-type layer 27 and the connection layer 28 becomes the drift layer 22.

[0050] Next, as shown in FIGS. 8(c) and 8(d), a second epitaxial layer 68 is epitaxially grown on the epitaxial layer 67. The conductivity type of the epitaxial layer 68 is p-type. However, the conductivity type of the bottom layer of the epitaxial layer 68 is p-type. + The epitaxial layer 68 has a shape similar to that of the lower layer 23a of the base layer 23. The portion of the epitaxial layer 68 other than the lower layer 23a becomes the upper layer 23b of the base layer 23. Next, a trench 69 is formed in the epitaxial layers 67 and 68. The trench 69 penetrates the epitaxial layer 68 in the Z direction and reaches the upper portion of the epitaxial layer 67. The subsequent manufacturing method is the same as in the first embodiment.

[0051] In this embodiment, p +A connecting layer 28 having a shape similar to that of the buried p-type layer 26 connects the buried p-type layer 26 to the base layer 23. Therefore, the buried p-type layer 26 is connected to the source electrode 30 via the connecting layer 28 and the base layer 23. This allows a constant potential to be applied uniformly to the buried p-type layer 26, and the depletion layer can be spread uniformly in the off state. This makes the electric field distribution uniform in the off state, and further improves the reliability of the gate insulating film 50. The configuration, operation, and effects of this embodiment other than those described above are the same as those of the second embodiment.

[0052] <Fourth embodiment> FIG. 9 is a cross-sectional view showing the semiconductor device according to this embodiment. As shown in FIG. 9, the semiconductor device 4 according to this embodiment has a p conductivity type of the low concentration layer, as compared with the semiconductor device 1 according to the first embodiment (see FIG. 1). - That is, in the semiconductor device 4, instead of the low concentration layer 25 of the semiconductor device 1, a conductivity type of p - A low concentration layer 71 having a shape is provided.

[0053] In the semiconductor device 4 according to this embodiment, an inversion layer is formed in the low-concentration layer 71 in the on-state, and the semiconductor device 4 is conductive in the inversion mode. On the other hand, in the off-state, a depletion layer spreads from the interface between the drift layer 22 and the base layer 23. At this time, n - Since there is no low concentration layer in the shape of a gate electrode, leakage current can be more reliably suppressed.

[0054] Also in this embodiment, the gate insulating film 50 is in contact with the low-concentration layer 71 having a low impurity concentration, so the reliability of the gate insulating film 50 is high. Furthermore, the buried p-type layer 26 is separated from the gate insulating film 50 via the low-concentration layer 71, so it is possible to increase the impurity concentration of the buried p-type layer 26 while suppressing damage to the gate insulating film 50. Other configurations, operations, and effects of this embodiment are the same as those of the first embodiment.

[0055] <Fifth embodiment> FIG. 10 is a cross-sectional view showing the semiconductor device according to this embodiment. 10, the semiconductor device 5 according to this embodiment has a different conductivity type of the low-concentration layer compared to the semiconductor device 2 according to the second embodiment (see FIG. 5). In addition, in this embodiment, the base layer 23 does not have a two-layer structure consisting of a lower layer and an upper layer, but has a p-type single-layer structure.

[0056] That is, in the semiconductor device 5, a low concentration layer 72 is provided instead of the low concentration layer 25 of the semiconductor device 2. The low concentration layer 72 contains n - Lower part of the shape 72a and p - The second embodiment has an upper portion 72b having a shaped cross section. The lower portion 72a is in contact with the gate insulating film 50, the buried p-type layer 26, the drift layer 22, the deep n-type layer 27, and the base layer 23. The upper portion 72b is disposed on the lower portion 72a, and is in contact with the gate insulating film 50, the base layer 23, and the source layer 24. Other configurations, operations, and effects of the present embodiment are the same as those of the second embodiment.

[0057] Sixth Embodiment FIG. 11 is a cross-sectional view showing the semiconductor device according to this embodiment. As shown in FIG. 11, in the semiconductor device 6 according to this embodiment, the conductivity types of the upper and lower portions of the low concentration layer are reversed compared to the semiconductor device 5 according to the fifth embodiment.

[0058] That is, in the semiconductor device 6, a low concentration layer 73 is provided instead of the low concentration layer 72 of the semiconductor device 5. The low concentration layer 73 contains p - Lower part of the shape 73a and n - The upper portion 73b has a shaped portion. The lower portion 73a is in contact with the gate insulating film 50, the buried p-type layer 26, the drift layer 22, and the deep n-type layer 27. The lower portion 73a may be in contact with the base layer 23. The upper portion 73b is disposed on the lower portion 73a, and is in contact with the gate insulating film 50, the base layer 23, and the source layer 24. Other configurations, operations, and effects of the present embodiment are the same as those of the fifth embodiment.

[0059] Seventh Embodiment FIG. 12 is a cross-sectional view showing the semiconductor device according to this embodiment. 12, the semiconductor device 7 according to this embodiment differs from the semiconductor device 1 according to the first embodiment in the positional relationship between the gate insulating film 50, the source layer 24, and the low-concentration layer 25. That is, the source layer 24 is disposed on the low-concentration layer 25 and is in contact with the gate insulating film 50 and the low-concentration layer 25. In addition, the low-concentration layer 25 is separated from the source electrode 30 and is connected to the source electrode 30 via the source layer 24. This also makes it possible to obtain the same effects as those of the first embodiment. Other configurations, operations, and effects of this embodiment are the same as those of the first embodiment.

[0060] According to the embodiment described above, a semiconductor device capable of suppressing breakdown of the gate insulating film can be realized.

[0061] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can also be implemented in combination with each other. [Explanation of symbols]

[0062] 1, 2, 3, 4, 5, 6, 7: Semiconductor device 10: Drain electrode 20: Semiconductor part 21: Drain layer 22: Drift layer 23: Base layer 23a: Lower layer 23b: Upper layer 24: Source layer 25: Low concentration layer 26: Buried p-type layer 27: Deep n-type layer 28: Connection layer 30: Source electrode 40: Gate electrode 50: Gate insulating film 61, 62: Epitaxial layer 63: Trench 64:n - shape layer 66, 67, 68: Epitaxial layer 69: Trench 71:Low concentration layer 72:Low concentration layer 72a: Lower part 72b: Upper part 73:Low concentration layer 73a: Bottom 73b: Upper part 101: point 102: Equipotential lines 103:Electronic 105:Electronic current R1: Transistor area R2: Connection area Rc: Cell region Rt: Termination area

Claims

1. A first electrode; a first semiconductor layer of a first conductivity type, the first semiconductor layer including silicon carbide, connected to the first electrode; a second semiconductor layer of a second conductivity type, the second semiconductor layer including silicon carbide, and the second semiconductor layer being provided on the first semiconductor layer; a third semiconductor layer of the first conductivity type, the third semiconductor layer including silicon carbide and provided on a portion of the second semiconductor layer; a second electrode connected to the second semiconductor layer and the third semiconductor layer; a third electrode provided in an upper portion of the first semiconductor layer, in the second semiconductor layer, and in the third semiconductor layer; an insulating film including silicon oxide, the insulating film being provided between the first semiconductor layer and the third electrode, between the second semiconductor layer and the third electrode, and between the third semiconductor layer and the third electrode; a fourth semiconductor layer provided between the insulating film and the first semiconductor layer and between the insulating film and the second semiconductor layer, in contact with the insulating film, containing silicon carbide, and having an impurity concentration lower than the impurity concentration of the first semiconductor layer and the impurity concentration of the second semiconductor layer; a fifth semiconductor layer provided between the first electrode and the third electrode, in contact with the first semiconductor layer and the fourth semiconductor layer, of the second conductivity type, and having an impurity concentration higher than the impurity concentration of the second semiconductor layer; a plurality of second conductivity type connection layers arranged along the extension direction of the third electrode and in contact with the fifth semiconductor layer and the second semiconductor layer; Equipped with The first semiconductor layer is a first layer in contact with the first electrode; a second layer provided on the first layer and having an impurity concentration lower than that of the first layer; a third layer provided on the second layer, in contact with the second semiconductor layer and the fourth semiconductor layer, and having an impurity concentration higher than that of the second layer; and The semiconductor device has the third layers and the connection layers arranged alternately along the direction in which the third electrodes extend.

2. The second semiconductor layer is a lower layer in contact with the first semiconductor layer; an upper layer in contact with the third semiconductor layer and having an impurity concentration lower than the impurity concentration of the lower layer; The semiconductor device according to claim 1 ,

3. 3. The semiconductor device according to claim 1, wherein the fourth semiconductor layer is of the first conductivity type.

4. 3. The semiconductor device according to claim 1, wherein the fourth semiconductor layer is of the second conductivity type.

5. The fourth semiconductor layer is a lower portion in contact with the first semiconductor layer and having a first conductivity type; an upper portion contacting the second semiconductor layer and having a second conductivity type; 3. The semiconductor device according to claim 1, further comprising:

6. A first electrode; a first semiconductor layer of a first conductivity type, the first semiconductor layer including silicon carbide, connected to the first electrode; a second semiconductor layer of a second conductivity type, the second semiconductor layer including silicon carbide, and the second semiconductor layer being provided on the first semiconductor layer; a third semiconductor layer of the first conductivity type, the third semiconductor layer including silicon carbide and provided on a portion of the second semiconductor layer; a second electrode connected to the second semiconductor layer and the third semiconductor layer; a third electrode provided in an upper portion of the first semiconductor layer, in the second semiconductor layer, and in the third semiconductor layer; an insulating film including silicon oxide, the insulating film being provided between the first semiconductor layer and the third electrode, between the second semiconductor layer and the third electrode, and between the third semiconductor layer and the third electrode; a fourth semiconductor layer provided between the insulating film and the first semiconductor layer and between the insulating film and the second semiconductor layer, in contact with the insulating film, containing silicon carbide, and having an impurity concentration lower than the impurity concentration of the first semiconductor layer and the impurity concentration of the second semiconductor layer; Equipped with The fourth semiconductor layer is a lower portion in contact with the first semiconductor layer and having a second conductivity type; an upper portion contacting the second semiconductor layer and having a first conductivity type; A semiconductor device having:

7. 7. The semiconductor device according to claim 1, wherein the third semiconductor layer is in contact with the insulating film and the fourth semiconductor layer, and the fourth semiconductor layer is spaced apart from the second electrode.

8. A semiconductor device described in any one of claims 1 to 6, wherein the fourth semiconductor layer is also provided between the insulating film and the third semiconductor layer, and the third semiconductor layer is spaced apart from the insulating film.

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