Semiconductor device, semiconductor module, and wireless communication device

Abstract

This semiconductor device is provided with: a channel layer containing a first nitride semiconductor; a spacer layer that contains a second nitride semiconductor having a greater band gap than the first nitride semiconductor and that is provided on the channel layer; an intermediate layer that contains Alx1Iny1Ga(1-x1-y1)N (0<x1<1, 0<y1<1, 0<x1+y1<1) and that is provided on the spacer layer; and a barrier layer that contains Alx2In(1-x2)N (0<x2<1) and that is provided on the intermediate layer.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, a semiconductor module, and a wireless communication device. [Background technology]

[0002] In recent years, research and development of high electron mobility transistors (HEMTs) using nitride semiconductors has been actively conducted. Nitride semiconductors have a larger band gap than Si and GaAs, and also have polarization specific to hexagonal crystals. Therefore, HEMTs using nitride semiconductors are expected to be transistors that can achieve low resistance, high breakdown voltage, and high-speed operation.

[0003] Specifically, HEMTs are expected to be applied to power devices or RF (Radio Frequency) devices, etc. For example, HEMTs using AlGaN for the barrier layer have been put to practical use in base stations for satellite communications or wireless communications.

[0004] Furthermore, in recent years, HEMTs using AlInN for the barrier layer have been proposed (for example, Patent Document 1). HEMTs using AlInN for the barrier layer can obtain a higher two-dimensional electron gas concentration than HEMTs using AlGaN for the barrier layer, and are therefore expected to enable even higher output power. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2018-56299 Summary of the Invention

[0006] Here, AlInN has a lower crystal growth temperature compared to other nitride semiconductors such as AlGaN and GaN. Therefore, for example, when an n-type semiconductor layer is regrown or ion implantation is performed to reduce the resistance between the source or drain electrode and the channel, the crystal structure of AlInN may deteriorate due to the thermal history during these process steps. As a result, the sheet resistance of the channel of the HEMT may increase, and the device characteristics may deteriorate. Therefore, in the HEMT, it is desired to improve the heat resistance of the barrier layer containing AlInN.

[0007] Therefore, it is desirable to provide a semiconductor device with improved heat resistance, a semiconductor module including the semiconductor device, and a wireless communication device including the semiconductor device.

[0008] A semiconductor device according to an embodiment of the present disclosure includes a channel layer including a first nitride semiconductor, a spacer layer including a second nitride semiconductor having a larger bandgap than the first nitride semiconductor and provided on the channel layer, and Al x1 In y1 Ga (1-x1-y1) N (0 < x1 < 1, 0 < y1 < 1, 0 < x1 + y1 < 1), an intermediate layer provided on the spacer layer, and Al x2 In (1-x2) N (0 < x2 < 1), and a barrier layer provided on the intermediate layer.

[0009] A semiconductor module according to an embodiment of the present disclosure includes a channel layer including a first nitride semiconductor, a spacer layer including a second nitride semiconductor having a larger bandgap than the first nitride semiconductor and provided on the channel layer, and Al x1 In y1 Ga (1-x1-y1) N (0 < x1 < 1, 0 < y1 < 1, 0 < x1 + y1 < 1), an intermediate layer provided on the spacer layer, and Al x2 (1-x2) N (0 < x2 < 1), and includes a semiconductor device having a barrier layer provided on the intermediate layer.

[0010] A wireless communication device according to an embodiment of the present disclosure includes a channel layer including a first nitride semiconductor, a spacer layer including a second nitride semiconductor having a larger bandgap than the first nitride semiconductor, and provided on the channel layer, and Al x1 In y1 Ga (1-x1-y1) N(0 < x1 < 1, 0 < y1 < 1, 0 < x1 + y1 < 1), an intermediate layer provided on the spacer layer, and Al x2 In (1-x2) N(0 < x2 < 1), and includes a semiconductor device including a barrier layer provided on the intermediate layer.

[0011] According to a semiconductor device, a semiconductor module, and a wireless communication device according to an embodiment of the present disclosure, a channel layer including a first nitride semiconductor, a spacer layer including a second nitride semiconductor having a larger bandgap than the first nitride semiconductor, an intermediate layer including AlInGaN, and a barrier including AlInN are sequentially stacked. Thereby, for example, the semiconductor device can suppress the diffusion of the alloy between the channel layer and the barrier layer by heat treatment.

Brief Description of Drawings

[0012] [Figure 1] It is a longitudinal sectional view showing the configuration of a semiconductor device according to an embodiment of the present disclosure. [Figure 2] It is a graph showing the band line-up of the conduction band minimum of a laminate in which a channel layer, a spacer layer, and a barrier layer are stacked. [Figure 3] It is a graph showing the band line-up of the conduction band minimum of a laminate in which a channel layer, a spacer layer, an intermediate layer, and a barrier layer are stacked. [Figure 4] It is a longitudinal sectional view showing a step of a manufacturing method of a semiconductor device according to the same embodiment. [Figure 5] It is a longitudinal sectional view showing a step of a manufacturing method of a semiconductor device according to the same embodiment. [Figure 6] It is a longitudinal sectional view showing a step of a manufacturing method of a semiconductor device according to the same embodiment. [Figure 7]FIG. 2 is a vertical cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the embodiment. [Figure 8] FIG. 2 is a vertical cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the embodiment. [Figure 9] FIG. 2 is a vertical cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the embodiment. [Figure 10] FIG. 10 is a vertical cross-sectional view showing the configuration of a semiconductor device according to a first modified example. [Figure 11] FIG. 10 is a vertical cross-sectional view showing the configuration of a semiconductor device according to a second modification. [Figure 12] FIG. 10 is a vertical cross-sectional view showing the configuration of a semiconductor device according to a third modification. [Figure 13] FIG. 10 is a vertical cross-sectional view showing the configuration of a semiconductor device according to a fourth modification. [Figure 14] FIG. 1 is a schematic perspective view showing a configuration of a semiconductor module. [Figure 15] FIG. 1 is a block diagram showing a configuration of a wireless communication device. [Figure 16] FIG. 10 is a scatter diagram showing the measurement results of the sheet resistance of a two-dimensional electron gas layer formed in a stack according to an example and a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiment described below is a specific example of the present disclosure, and the technology according to the present disclosure is not limited to the following aspects. Furthermore, the arrangement, dimensions, dimensional ratios, etc. of each component of the present disclosure are not limited to the aspects shown in the drawings.

[0014] The explanation will be given in the following order. 1. Configuration of semiconductor device 2. Manufacturing method of semiconductor device 3. Variations 4. Application Examples 4.1.Semiconductor Module 4.2. Wireless Communication Devices

[0015] <1. Configuration of semiconductor device> First, the configuration of a semiconductor device according to an embodiment of the present disclosure will be described with reference to Fig. 1. Fig. 1 is a vertical cross-sectional view showing the configuration of a semiconductor device 100 according to this embodiment.

[0016] As shown in FIG. 1, the semiconductor device 100 includes a substrate 110, a first buffer layer 111, a second buffer layer 113, a channel layer 115, a spacer layer 121, an intermediate layer 123, a barrier layer 131, a regrown layer 141, a source electrode 143S, a drain electrode 143D, a gate insulating film 151, and a gate electrode 153.

[0017] The semiconductor device 100 according to this embodiment is a high electron mobility transistor (HEMT) having a channel formed by a two-dimensional electron gas layer (2DEG) generated by the difference in the magnitude of polarization between the channel layer 115 and the barrier layer 131. The two-dimensional electron gas layer (2DEG) is generated, for example, at the interface of the channel layer 115 on the barrier layer 131 side.

[0018] The substrate 110 is a support for the semiconductor device 100. For example, the substrate 110 may be a SiC substrate, a sapphire substrate, or a Si substrate. In the semiconductor device 100, the first buffer layer 111 and the second buffer layer 113 that reduce the lattice constant mismatch between the substrate 110 and the channel layer 115 are provided, and therefore the substrate 110 may be made of a material having a different lattice constant from that of the channel layer 115.

[0019] However, the substrate 110 may be a substrate made of a semiconductor material having a lattice constant close to that of the nitride semiconductor constituting the channel layer 115. For example, the substrate 110 may be a substrate made of a III-V compound semiconductor such as GaN or AlN. In such a case, the semiconductor device 100 can more easily form the channel layer 115 in which the nitride semiconductor is epitaxially grown.

[0020] The first buffer layer 111 and the second buffer layer 113 are made of epitaxially grown nitride semiconductors and are provided on the substrate 110. The first buffer layer 111 and the second buffer layer 113 can reduce the lattice mismatch between the substrate 110 and the channel layer 115 by controlling the lattice constant of the surface on which the channel layer 115 is provided. As a result, the first buffer layer 111 and the second buffer layer 113 can improve the crystalline state of the channel layer 115 and suppress warpage of the substrate 110.

[0021] For example, when the substrate 110 is a single-crystal Si substrate having a (111) plane as its primary surface and the channel layer 115 is a GaN layer, the first buffer layer 111 may be made of AlN and the second buffer layer 113 may be made of AlGaN. However, depending on the configurations of the substrate 110 and the channel layer 115, the first buffer layer 111 and the second buffer layer 113 may not be provided, or only the first buffer layer 111 may be provided.

[0022] The channel layer 115 is made of a nitride semiconductor having a band gap smaller than those of the spacer layer 121 and the barrier layer 131, and is provided on the second buffer layer 113. The channel layer 115 can accumulate carriers at the interface on the barrier layer 131 side due to the difference in the magnitude of polarization between the channel layer 115 and the barrier layer 131.

[0023] Specifically, the channel layer 115 is made of epitaxially grown Al x4 In y4 Ga (1-x4-y4) N (0≦x4≦1, 0≦y4≦1, 0≦x4+y4≦1). For example, the channel layer 115 may be made of epitaxially grown GaN, InGaN, InN, AlGaN, or AlInGaN. More specifically, the channel layer 115 may be made of undoped u-GaN to which no impurities are added. In such a case, the channel layer 115 can suppress impurity scattering of carriers, thereby further increasing carrier mobility.

[0024] The spacer layer 121 is composed of a nitride semiconductor having a larger bandgap than the channel layer 115 and is provided on the channel layer 115. The spacer layer 121 can reduce alloy scattering between the barrier layer 131 and the channel layer 115 and suppress a decrease in the carrier mobility of the two-dimensional electron gas layer (2DEG) due to alloy scattering.

[0025] Specifically, the spacer layer 121 may be composed of epitaxially grown Al x3 In y3 Ga (1-x3-y3) N (0 < x3 < 1, 0 ≦ y3 < 1, 0 < x3 + y3 < 1). For example, the spacer layer 121 may be composed of AlN, or may be composed of AlGaN or AlInGaN.

[0026] Also, the thickness of the spacer layer 121 is preferably, for example, 0.5 nm or more and 3 nm or less. When the thickness of the spacer layer 121 is 0.5 nm or more, the spacer layer 121 can be more easily formed. On the other hand, when the thickness of the spacer layer 121 is 3 nm or less, the spacer layer 121 can more appropriately control the bandgap profile of the semiconductor device 100, as will be described later, and thus can increase the carrier density of the two-dimensional electron gas layer (2DEG) generated in the channel layer 115.

[0027] The intermediate layer 123 is composed of epitaxially grown Al x1 In y1 Ga (1-x1-y1) N (0 < x1 < 1, 0 < y1 < 1, 0 < x1 + y1 < 1) and is provided on the spacer layer 121. Since Al x1 In y1 Ga (1-x1-y1) N constituting the intermediate layer is a quaternary nitride semiconductor, Al x2 In (1-x2)It is easier to obtain a mixed crystal with better single crystallinity than N. Therefore, the intermediate layer 123 can clarify the interface between the barrier layer 131 and the spacer layer 121 and suppress thermal disturbance of the interface, thereby suppressing thermal deterioration of the layer structure of the channel layer 115 and the barrier layer 131.

[0028] Al constituting the intermediate layer 123 x1 In y1 Ga (1-x1-y1) The Ga composition (1-x1-y1) of N is preferably 0.01 or more and 0.3 or less. When the Ga composition (1-x1-y1) of the intermediate layer 123 is 0.01 or more and 0.3 or less, the crystallinity of the intermediate layer 123 is further improved and thermally induced disturbance of the interface can be suppressed, thereby suppressing thermal deterioration of the layer structures of the channel layer 115 and the barrier layer 131.

[0029] Furthermore, the thickness of the intermediate layer 123 is preferably 0.5 nm or more and 10 nm or less. When the thickness of the intermediate layer 123 is 0.5 nm or more, the intermediate layer 123 can be more easily formed. On the other hand, when the thickness of the intermediate layer 123 is 10 nm or less, the intermediate layer 123 can more appropriately control the band gap profile of the semiconductor device 100, as will be described later, and therefore the carrier density of the two-dimensional electron gas layer (2DEG) generated in the channel layer 115 can be further increased. Note that the thickness of the intermediate layer 123 is more preferably 1.0 nm or more and 5.0 nm or less.

[0030] The barrier layer 131 is made of a nitride semiconductor having a larger band gap than the channel layer 115, and is provided on the intermediate layer 123. The barrier layer 131 can accumulate carriers in the channel layer 115 on the barrier layer 131 side by spontaneous polarization or piezoelectric polarization. As a result, in the semiconductor device 100, a two-dimensional electron gas layer (2DEG) with high mobility and high carrier concentration can be formed in the channel layer 115 on the barrier layer 131 side.

[0031] Specifically, the barrier layer 131 is made of epitaxially grown Al x2 In(1-x2) It is composed of N (where 0 < x2 < 1). For example, the barrier layer 131 is undoped u-Al without added impurities x2 In (1-x2) It may also be composed of N. In such a case, since the barrier layer 131 can suppress impurity scattering of carriers in the channel layer 115, the mobility of carriers can be further increased.

[0032] The carrier density of the two-dimensional electron gas layer (2DEG) can be controlled, for example, by the bandgap profile of each layer from the barrier layer 131 to the channel layer 115. Referring to FIGS. 2 and 3, the control of the carrier density of the two-dimensional electron gas layer (2DEG) will be described. FIG. 2 is a graph showing the band line-up of the conduction band minimum of a stacked body in which the channel layer 115, the spacer layer 121, and the barrier layer 131 are stacked. FIG. 3 is a graph showing the band line-up of the conduction band minimum of a stacked body in which the channel layer 115, the spacer layer 121, the intermediate layer 123, and the barrier layer 131 are stacked.

[0033] As shown in FIGS. 2 and 3, one factor determining the carrier density of the two-dimensional electron gas layer (2DEG) is the height of the conduction band minimum of the barrier layer 131.

[0034] For example, as the Al composition of each layer increases, the polarization of each layer increases, so the slope of the conduction band minimum increases. Also, as the thickness of each layer increases, the height of the conduction band minimum increases. Therefore, by appropriately controlling the thickness and composition of each layer from the barrier layer 131 to the channel layer 115 and controlling the height of the conduction band minimum of the barrier layer 131, the carrier density of the two-dimensional electron gas layer (2DEG) can be increased.

[0035] For example, the barrier layer 131 is Al x1 In y1 Ga (1-x1-y1) Al with a higher proportion of Al composition than Al x2 In(1-x2) It is preferably composed of N. That is, the barrier layer 131 is composed of a nitride semiconductor such that x1 < x2 with respect to the intermediate layer 123, so that a larger polarization can be obtained, and thus the carrier concentration of the two-dimensional electron gas layer (2DEG) can be increased. For example, the barrier layer 131 is composed of a nitride semiconductor with x2 greater than 0.7, so that a larger polarization can be obtained, and thus the carrier concentration of the two-dimensional electron gas layer (2DEG) can be increased further.

[0036] Also, the barrier layer 131 and the intermediate layer 123 are preferably composed of a nitride semiconductor such that x1 < x2 and y1 < (1 - x2). In such a case, the barrier layer 131 and the intermediate layer 123 can further increase the polarization of the barrier layer 131, and thus the carrier concentration of the two-dimensional electron gas layer (2DEG) can be increased further.

[0037] Furthermore, the thickness of the barrier layer is preferably 4 nm or more and 20 nm or less. In such a case, the barrier layer 131 can more appropriately control the bandgap profile of the semiconductor device 100, and thus the carrier density of the two-dimensional electron gas layer (2DEG) generated in the channel layer 115 can be increased. Note that the thickness of the barrier layer is more preferably 8 nm or more and 15 nm or less.

[0038] The regrowth layer 141 is composed of a nitride semiconductor containing n-type impurities and is provided in the barrier layer 131, the intermediate layer 123, the spacer layer 121, and the channel layer 115 on both sides sandwiching the gate electrode 153. Specifically, the regrowth layer 141 is provided by embedding a pair of recesses dug from the barrier layer 131 to the channel layer 115 with an n-type nitride semiconductor. For example, the regrowth layer 141 uses a selective mask to It may also be provided by selectively epitaxially growing a nitride semiconductor containing n-type impurities in the recesses provided in the corresponding regions for the source electrode 1,43S and the drain electrode 1,43D.

[0039] The regrown layer 141 has higher conductivity than the barrier layer 131, and therefore can electrically connect the source electrode 143S and the drain electrode 143D provided on the regrown layer 141 to the two-dimensional electron gas layer (2DEG) with low resistance. For example, the regrown layer is doped with n-type impurities such as Si or Ge at a concentration of 1.0×10 19 pieces / cm 3 Alternatively, the regrown layer 141 may be made of AlInGaN containing n-type impurities, which grows more easily at a lower temperature than GaN.

[0040] The source electrode 143S and the drain electrode 143D are made of a conductive material and are provided on the regrown layers 141 provided on both sides of the gate electrode 153. The source electrode 143S and the drain electrode 143D can be electrically connected to a two-dimensional electron gas layer (2DEG) generated in the channel layer 115 via the regrown layer 141. The source electrode 143S and the drain electrode 143D may have a structure in which Ti (titanium), Al (aluminum), Ni (nickel), and Au (gold) are sequentially stacked from the regrown layer 141 side.

[0041] The gate insulating film 151 is made of an insulating material and is provided on the barrier layer 131. Specifically, the gate insulating film 151 is made of a material that is insulating against the barrier layer 131 and the gate electrode 153. This allows the gate insulating film 151 to protect the surface of the barrier layer 131 from impurities such as ions and improve the surface of the barrier layer 131, thereby suppressing deterioration in the characteristics of the semiconductor device 100. For example, the gate insulating film 151 may be provided as a single layer or a multilayer film of Al2O3 or HfO2 with a thickness of about 10 nm.

[0042] The gate electrode 153 is made of a conductive material and provided on the gate insulating film 151. The gate electrode 153 is provided between the source electrode 143S and the drain electrode 143D, and forms a metal-insulator-semiconductor (MIS) gate together with the gate insulating film 151. For example, the gate electrode 153 may be provided by stacking Ni (nickel) and Au (gold) from the gate insulating film 151 side.

[0043] The gate electrode 153 can control the carrier concentration of a two-dimensional electron gas layer (2DEG) formed in the channel layer 115 by applying a voltage to the gate electrode 153. Specifically, the gate electrode 153 can control the carrier concentration of the two-dimensional electron gas layer (2DEG) generated in the channel layer 115 by the field effect by controlling the thickness of the depletion layer formed in the underlying barrier layer 131 by applying a voltage to the gate electrode 153.

[0044] As described above, the semiconductor device 100 according to this embodiment can suppress heat-induced disturbance of the interface between the channel layer 115 and the barrier layer 131, thereby suppressing heat-induced deterioration of the layer structures of the channel layer 115 and the barrier layer 131. Therefore, the technology according to the present disclosure can improve the heat resistance of the semiconductor device 100.

[0045] This allows the semiconductor device 100 according to this embodiment to perform crystal growth at a higher temperature when forming the regrowth layer 141, thereby improving the crystallinity of the regrowth layer 141. Therefore, the semiconductor device 100 can reduce the contact resistance between the source electrode 143S and the drain electrode 143D and the two-dimensional electron gas layer (2DEG), thereby improving output efficiency.

[0046] Furthermore, the semiconductor device 100 according to this embodiment can suppress the deterioration of the sheet resistance of the two-dimensional electron gas layer (2DEG) during the formation of the regrowth layer 141, thereby improving output efficiency. It can be raised.

[0047] Furthermore, the semiconductor device 100 according to this embodiment can use MOCVD (Metal Organic Chemical Vapor Deposition), a high-temperature process, to form the regrowth layer 141. This allows the semiconductor device 100 to more selectively form the regrowth layer 141, thereby simplifying process steps such as removing the regrowth layer 141 formed in unintended regions. Furthermore, the semiconductor device 100 can clean the regrowth surface by controlling the gas atmosphere before regrowth of the regrowth layer 141 in MOCVD using H, N, or NH. Therefore, the semiconductor device 100 can reduce contact resistance and carrier traps at the interface of the regrowth layer 141.

[0048] <2. Manufacturing Method of Semiconductor Device> Next, an example of a method for manufacturing the semiconductor device 100 according to this embodiment will be described with reference to Figures 4 to 9. Figures 4 to 9 are vertical cross-sectional views showing each step of the method for manufacturing the semiconductor device 100 according to this embodiment.

[0049] 4, for example, a first buffer layer 111, a second buffer layer 113, a channel layer 115, a spacer layer 121, an intermediate layer 123, and a barrier layer 131 are epitaxially grown in this order on a substrate 110. Although the substrate 110 may be a Si substrate, a sapphire substrate, a SiC substrate, a GaN substrate, an AlN substrate, a GaAs substrate, a ZnO substrate, or a ScAlMgO substrate, the following description will be given taking as an example a case where a Si substrate is used.

[0050] For example, first, a Si substrate having a (111) plane as its main surface is placed in an MOCVD apparatus and thermally cleaned at 1000°C for about 10 minutes. After that, AlN is epitaxially grown to a thickness of 100 nm to 300 nm at about 700°C to 1100°C to form a first buffer layer 111. Next, AlGaN having an Al composition of about 0.20 is epitaxially grown to a thickness of 100 nm to 500 nm at about 900°C to 1100°C on the first buffer layer 111 to form a second buffer layer 113. Subsequently, GaN is epitaxially grown to a thickness of 500 nm to 2000 nm on the second buffer layer 113 at about 900°C to 1100°C to form a channel layer 115.

[0051] Thereafter, AlN is epitaxially grown on the channel layer 115 at 900°C to 1100°C to a thickness of about 0.5 nm to 5 nm, thereby forming the spacer layer 121. Next, AlInGaN is epitaxially grown on the spacer layer 121 at 700°C to 900°C to a thickness of about 0.5 nm to 5 nm, thereby forming the intermediate layer 123. Subsequently, AlInN is epitaxially grown on the intermediate layer 123 at 700°C to 900°C to a thickness of about 5 nm to 20 nm, thereby forming the barrier layer 131.

[0052] 5, a film of SiN, SiO2, Al2O3, or the like is formed on the barrier layer 131 to form a gate insulating film 151. Subsequently, the gate insulating film 151 is wet-etched using a resist patterned to open regions corresponding to the source electrode 143S and the drain electrode 143D, thereby removing the gate insulating film 151 from the regions corresponding to the source electrode 143S and the drain electrode 143D.

[0053] Next, as shown in FIG. 6, the barrier layer 131, the intermediate layer 123, the spacer layer 121, and the channel layer 115 in the areas corresponding to the source electrode 143S and the drain electrode 143D are removed by dry etching to form an opening 141H having a depth of about 100 nm.

[0054] 7, n-type GaN is selectively epitaxially grown in the opening 141H using MOCVD, MBE (Molecular Beam Epitaxy), or sputtering to form a regrowth layer 141. At this time, for example, Si or Ge can be used as the n-type impurity.

[0055] Subsequently, as shown in FIG. 8, Ti, Al, Ni, and Au are sequentially stacked on the regrown layer 141 to form a source electrode 143S and a drain electrode 143D.

[0056] Thereafter, as shown in FIG. 9, Ni and Au are sequentially stacked on the gate insulating film 151 between the source electrode 143S and the drain electrode 143D to form a gate electrode 153.

[0057] Through the above steps, the semiconductor device 100 according to this embodiment can be formed.

[0058] <3. Modifications> Next, first to fourth modified examples of the semiconductor device 100 according to this embodiment will be described with reference to Figures 10 to 13. Note that Figures 10 to 13 only show the configuration above the second buffer layer 113. In the semiconductor devices according to the first to fourth modified examples, the configuration below the second buffer layer 113 is substantially the same as that of the semiconductor device 100 shown in Figure 1.

[0059] (First Modification) 10 is a longitudinal cross-sectional view showing the configuration of a semiconductor device 100A according to a first modification. The semiconductor device 100A according to the first modification differs from the semiconductor device 100 shown in FIG. 1 in that the composition of AlInGaN constituting the intermediate layer 123A varies in the stacking direction of the semiconductor device 100A.

[0060] Specifically, the intermediate layer 123A is formed by distributing Al in the direction from the spacer layer 121 side to the barrier layer 131 side. x1 In y1 Ga (1-x1-y1)The ratio (1 - x1 - y1) of the Ga composition of N(0 < x1 < 1, 0 < y1 < 1, 0 < x1 + y1 < 1) may be provided so as to decrease stepwise or continuously. That is, the intermediate layer 123A may be provided such that the ratio of the Ga composition decreases in the crystal growth direction. According to this, since the intermediate layer 123A can relax the composition difference of the nitride semiconductors constituting the spacer layer 121 and the barrier layer 131, it becomes possible to more easily epitaxially grow each layer.

[0061] (Second Modified Example) FIG. 11 is a longitudinal sectional view showing the configuration of a semiconductor device 100B according to the second modified example. The semiconductor device 100B according to the second modified example is different from the semiconductor device 100 shown in FIG. 1 in that a graded layer 125 is further provided between the intermediate layer 123 and the barrier layer 131.

[0062] Specifically, the graded layer 125 may be provided between the intermediate layer 123 and the barrier layer 131 and may be composed of AlInGaN in which the ratio of the Ga composition decreases stepwise or continuously in the direction from the intermediate layer 123 side to the barrier layer 131 side. The thickness of the graded layer 125 may be, for example, 0.5 nm or more and 5 nm or less. According to this, since the graded layer 125 can relax the composition difference of the nitride semiconductors constituting the intermediate layer 123 and the barrier layer 131, it becomes possible to more easily epitaxially grow each layer.

[0063] In FIG. 11, an example in which the graded layer 125 is provided between the intermediate layer 123 and the barrier layer 131 is shown, but this modified example is not limited to such an example. The graded layer **********125 may be provided between the spacer layer 121 and the intermediate layer 123. Even in such a case, since the graded layer 125 can relax the composition difference of the nitride semiconductors constituting the spacer layer 121 and the intermediate layer 123, it becomes possible to more easily epitaxially grow each layer.

[0064] (Third Modified Example) It should be noted that there seems to be an incomplete part in the English translation of the content in where "**********" is shown. Please check and correct the original text if needed.12 is a longitudinal cross-sectional view showing the configuration of a semiconductor device 100C according to a third modification. The semiconductor device 100C according to the third modification differs from the semiconductor device 100 shown in FIG. 1 in that a protective layer 133 is provided on a barrier layer 131.

[0065] Specifically, the protective layer 133 is made of AlInGaN and is provided on the barrier layer 131. The thickness of the protective layer 133 may be, for example, 0.5 nm or more and 5 nm or less. This allows the protective layer 133 to protect the barrier layer 131 from the film formation process of the gate insulating film 151 and the like, thereby suppressing deterioration in the crystallinity of the barrier layer 131 after its formation.

[0066] (Fourth Modification) 13 is a longitudinal cross-sectional view showing the configuration of a semiconductor device 100D according to a fourth modification. The semiconductor device 100D according to the fourth modification differs from the semiconductor device 100 shown in FIG. 1 in that the channel layer 115 is composed of an upper channel layer 115B and a lower channel layer 115A.

[0067] Specifically, the lower channel layer 115A may be made of, for example, GaN, and the upper channel layer 115B may be made of, for example, AlGaN, InGaN, or AlInGaN.

[0068] A two-dimensional electron gas layer (2DEG) is generated in the upper channel layer 115B due to the difference in polarization between the upper channel layer 115B and the spacer layer 121, intermediate layer 123, and barrier layer 131 provided on the upper channel layer 115B. Therefore, the upper channel layer 115B is made of a nitride semiconductor having a smaller band gap than the spacer layer 121, intermediate layer 123, and barrier layer 131. On the other hand, the lower channel layer 115A does not contribute to the generation of a two-dimensional electron gas layer (2DEG), and therefore is made of a nitride semiconductor taking into consideration ease of epitaxial growth and the like, without considering the size of the band gap.

[0069] Even when the channel layer 115 is made up of multiple layers, the semiconductor device 100D can achieve the same effects as the semiconductor device 100 shown in FIG.

[0070] The above modifications can also be combined with each other.

[0071] <4. Application Examples> (4.1. Semiconductor Module) Next, a semiconductor module that is a first application example of the technology according to the present disclosure will be described with reference to Fig. 14. Fig. 14 is a schematic perspective view showing the configuration of a semiconductor module 1.

[0072] 14, the semiconductor module 1 is an antenna-integrated module in which, for example, a plurality of edge antennas 20 formed in an array and front-end components such as a switch 10, a low-noise amplifier 41, a band-pass filter 42, and a power amplifier 43 are mounted as a module on a single chip 50. The semiconductor module 1 can be used, for example, as a transceiver for wireless communication.

[0073] The semiconductor module 1 includes the semiconductor device 100 according to this embodiment as a transistor constituting, for example, the switch 10, the low-noise amplifier 41, or the power amplifier 43. For example, in fifth-generation mobile communications (5G), which use radio waves in a higher frequency band, radio wave propagation loss becomes greater. Therefore, it is desirable for the semiconductor module 1 compatible with 5G to transmit radio waves at higher power. The semiconductor module 1 including the semiconductor device 100 according to this embodiment can improve device characteristics, thereby enabling high-output, low-power consumption, and highly reliable wireless communication. In other words, the semiconductor module 1 can be more suitably used for fifth-generation mobile communications (5G).

[0074] (4.2. Wireless Communication Device) Next, a wireless communication device that is a second application example of the technology according to the present disclosure will be described with reference to Fig. 15. Fig. 15 is a block diagram showing the configuration of a wireless communication device 2.

[0075] 15, the wireless communication device 2 includes an antenna ANT, an antenna switch circuit 3, a high-power amplifier HPA, a radio-frequency integrated circuit RFIC (Radio Frequency Integrated Circuit), a baseband unit BB, an audio output unit MIC, a data output unit DT, and an interface unit I / F (e.g., a wireless local area network (W-LAN) or Bluetooth (registered trademark)). The wireless communication device 2 is, for example, a mobile phone system having multiple functions such as voice and data communication and LAN connection.

[0076] In the wireless communication device 2, during transmission, a transmission signal is output from the baseband unit BB to the antenna ANT via the radio frequency integrated circuit RFIC, the high power amplifier HPA, and the antenna switch circuit 3. In addition, during reception in the wireless communication device 2, a received signal is input from the antenna ANT to the baseband unit BB via the antenna switch circuit 3 and the radio frequency integrated circuit RFIC. The received signal processed by the baseband unit BB is output to the outside of the wireless communication device 2, for example, from the audio output unit MIC, the data output unit DT, or the interface unit I / F.

[0077] The wireless communication device 2 includes the semiconductor device 100 according to this embodiment as transistors constituting the antenna switch circuit 3, the high-power amplifier HPA, the radio-frequency integrated circuit RFIC, the baseband unit BB, etc. This allows the wireless communication device 2 to further improve device characteristics, thereby enabling wireless communication with high output, low power consumption, and high reliability. [Example]

[0078] The feasibility and effects of the technology according to the present disclosure will be described in detail below using a stack including layers from a channel layer to a barrier layer, although the technology according to the present disclosure is not limited to the following example.

[0079] (Example) On the GaN channel layer, a 1-nm-thick Al 0.9 Ga 0.1 N spacer layer, 1 nm thick Al 0.8 In 0.1 Ga 0.1 An intermediate layer made of N and a 9-nm-thick Al 0.81 In 0.19 Barrier layers made of N were sequentially stacked to prepare a laminate according to the example.

[0080] (Comparative Example) On the GaN channel layer, a 1-nm-thick Al 0.9 Ga 0.1 A spacer layer made of N and a 9-nm-thick Al 0.81 In 0.19 Barrier layers made of N were sequentially stacked to prepare a stack according to the comparative example.

[0081] (Measurement results) The sheet resistance of the two-dimensional electron gas layer generated in the channel layer of the stacks according to the examples and comparative examples was measured by an eddy current method. The sheet resistance of the two-dimensional electron gas layer was measured at four points: immediately after the stack was formed, after heat treatment at 800°C for 3 minutes, after heat treatment at 850°C for 3 minutes, and after heat treatment at 900°C for 3 minutes. The measurement results are shown in the scatter diagram in Figure 16.

[0082] In Figure 16, the measurement results immediately after the formation of the laminate are shown as "as grown," the measurement results after heat treatment at 800°C for 3 minutes are shown as "800°C," the measurement results after heat treatment at 850°C for 3 minutes are shown as "850°C," and the measurement results after heat treatment at 900°C for 3 minutes are shown as "900°C."

[0083] As can be seen from the scatter diagram in FIG. 16 , the stack according to the example can suppress an increase in the sheet resistance of the two-dimensional electron gas layer due to heat treatment at 850°C or higher compared to the stack according to the comparative example. Specifically, the sheet resistance of the stack according to the comparative example increases by about 1.5 times after heat treatment at 850°C for 3 minutes, and increases by about 4 times after heat treatment at 900°C for 3 minutes. On the other hand, the sheet resistance of the stack according to the example only increases by about 1.2 times even after heat treatment at 900°C for 3 minutes. Therefore, it can be seen that the stack according to the example has improved heat resistance compared to the stack according to the comparative example. For example, the stack according to the example can suppress the sheet resistance of the two-dimensional electron gas layer to 280 Ω / □ or less even after heat treatment at 850°C for 3 minutes.

[0084] According to this, the semiconductor device according to this embodiment can be subjected to heat treatment at 850°C for 3 minutes by using the stack according to the example, thereby improving the crystallinity of the regrown layer. Therefore, the semiconductor device according to this embodiment can suppress the sheet resistance of the two-dimensional electron gas layer to 280Ω / □ or less, and can reduce the contact resistance between the source electrode and the drain electrode and the two-dimensional electron gas layer, thereby improving the output efficiency.

[0085] The technology according to the present disclosure has been described above by way of embodiments and modifications. However, the technology according to the present disclosure is not limited to the above embodiments, and various modifications are possible.

[0086] Furthermore, not all of the configurations and operations described in the embodiments are necessarily essential to the configurations and operations of the present disclosure. For example, among the components in each embodiment, any component not recited in an independent claim showing the highest concept of the present disclosure should be understood as an optional component.

[0087] The terms used throughout this specification and the appended claims should be construed as "non-limiting" terms. For example, the terms "comprising" or "included" should be construed as not being limited to the states described as being included. The term "having" should be construed as not being limited to the states described as having.

[0088] The terms used in this specification include terms used merely for convenience of explanation and not for the purpose of limiting the configuration and operation. For example, terms such as "right", "left", "upper", "lower", etc. merely indicate directions on the drawing being referred to. Also, the terms "inner" and "outer" merely indicate the directions towards the center of the element of interest and away from the center of the element of interest, respectively. The same applies to terms similar to these and terms of the same general meaning.

[0089] Note that the technology according to the present disclosure can also adopt the following configurations. According to the technology according to the present disclosure having the following configurations, the semiconductor device according to the present embodiment can suppress alloy diffusion between the channel layer and the barrier layer by heat treatment, and thus can suppress an increase in the sheet resistance of the two-dimensional electron gas layer even when heat treatment is performed at a higher temperature. Therefore, the semiconductor device according to the present embodiment can improve heat resistance. The effects achieved by the technology according to the present disclosure are not necessarily limited to the effects described herein, and can be any of the effects described in the present disclosure. (1) A channel layer including a first nitride semiconductor, A spacer layer including a second nitride semiconductor having a larger bandgap than the first nitride semiconductor, provided on the channel layer, Al x1 In y1 Ga (1-x1-y1) An intermediate layer including N(0 < x1 < 1, 0 < y1 < 1, 0 < x1 + y1 < 1), provided on the spacer layer, Al x2 In (1-x2) A barrier layer including N(0 < x2 < 1), provided on the intermediate layer A semiconductor device comprising (2) The semiconductor device according to (1) above, wherein the x1, the x2, and the y1 satisfy the relational expressions x1 < x2 and y1 < (1 - x2). (3) The semiconductor device according to (1) or (2) above, wherein the x2 is greater than 0.7. (4) The semiconductor device according to any one of (1) to (3) above, wherein the thickness of the intermediate layer is 0.5 nm or more and 10 nm or less. (5) The semiconductor device according to any one of (1) to (4) above, wherein the thickness of the barrier layer is 4 nm or more and 20 nm or less. (6) The Al x1 In y1 Ga (1-x1-y1) N in the intermediate layer has a decreasing Ga ratio from the spacer layer toward the barrier layer. The semiconductor device according to any one of (1) to (5) above. (7) The second nitride semiconductor is Al x3 In y3 Ga (1-x3-y3) N (0 < x3 < 1, 0 ≦ y3 < 1, 0 < x3 + y3 < 1). The semiconductor device according to any one of (1) to (6) above. (8) The semiconductor device according to any one of (1) to (7) above, wherein the thickness of the spacer layer is 0.5 nm or more and 3 nm or less. (9) The first nitride semiconductor is Al x4 In y4 Ga (1-x4-y4) N (0 ≦ x4 ≦ 1, 0 ≦ y4 ≦ 1, 0 ≦ x4 + y4 ≦ 1). The semiconductor device according to any one of (1) to (8) above. (10) A pair of regrowth layers containing n-type AlInGaN and provided respectively in a pair of recesses dug from the barrier layer to the spacer layer, A source electrode provided on one of the regrowth layers, A drain electrode provided on the other side of the regrowth layer and The semiconductor device according to any one of the above (1) to (9), further comprising. (11) The semiconductor device according to any one of the above (1) to (10), further comprising a gate electrode provided on the barrier layer via a gate insulating film. (12) A two-dimensional electron gas layer is generated in the channel layer, The semiconductor device according to any one of the above (1) to (11), wherein the sheet resistance of the two-dimensional electron gas layer is 280 Ω / □ or less. (13) A channel layer containing a first nitride semiconductor, A spacer layer containing a second nitride semiconductor having a larger bandgap than the first nitride semiconductor and provided on the channel layer, Al x1 In y1 Ga (1-x1-y1) N (0 <x1 <1, 0 <y1 <1, 0 <x1 + y1 <1), an intermediate layer provided on the spacer layer, Al x2 In (1-x2) N (0 <x2 <1), a barrier layer provided on the intermediate layer and A semiconductor device including A semiconductor module comprising. (14) A channel layer containing a first nitride semiconductor, A spacer layer containing a second nitride semiconductor having a larger bandgap than the first nitride semiconductor and provided on the channel layer, Al x1 In y1 Ga (1-x1-y1) N (0 <x1 <1, 0 <y1 <1, 0 <x1 + y1 <1), an intermediate layer provided on the spacer layer, Al x2 In (1-x2) N (0 <x2 <1), a barrier layer provided on the intermediate layer and A semiconductor device including A wireless communication device comprising.

[0090] This application claims priority based on Japanese Patent Application No. 2020-147166, filed on September 1, 2020, in the Japan Patent Office, the entire contents of which are incorporated herein by reference.

[0091] Those skilled in the art will recognize that various modifications, combinations, subcombinations, and variations may occur depending on design requirements and other factors, and are intended to be within the scope of the appended claims and their equivalents.

Claims

1. a channel layer including a first nitride semiconductor; a spacer layer including a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor and provided on the channel layer; Al ｘ１ In ｙ１ Ga （１－ｘ１－ｙ１） N (0<x1<1, 0<y1<1, 0<x1+y1<1), and an intermediate layer provided on the spacer layer; Al ｘ２ In （１－ｘ２） a barrier layer including N (0<x2<1) and provided on the intermediate layer; Equipped with The semiconductor device, wherein the Al x1 In y1 Ga (1-x1-y1) N contained in the intermediate layer has a Ga content that decreases from the spacer layer toward the barrier layer.

2. 2. The semiconductor device according to claim 1, wherein said x1, said x2, and said y1 satisfy the relational expressions x1<x2 and y1<(1-x2).

3. The semiconductor device according to claim 1 , wherein x2 is greater than 0.

7.

4. The semiconductor device according to claim 1 , wherein the thickness of said intermediate layer is not less than 0.5 nm and not more than 10 nm.

5. 2. The semiconductor device according to claim 1, wherein the barrier layer has a thickness of 4 nm to 20 nm.

6. The second nitride semiconductor is Al ｘ３ In ｙ３ Ga （１－ｘ３－ｙ３） 2. The semiconductor device according to claim 1, wherein N(0<x3<1, 0≦y3<1, 0<x3+y3<1).

7. 2. The semiconductor device according to claim 1, wherein the spacer layer has a thickness of 0.5 nm to 3 nm.

8. The first nitride semiconductor is Al ｘ４ In ｙ４ Ga （１－ｘ４－ｙ４） 2. The semiconductor device according to claim 1, wherein N(0≦x4≦1, 0≦y4≦1, 0≦x4+y4≦1).

9. a pair of regrown layers including n-type AlInGaN and provided in respective recesses dug from the barrier layer to the spacer layer; a source electrode disposed on one of the regrowth layers; a drain electrode provided on the other of the regrown layers; The semiconductor device according to claim 1 , further comprising:

10. The semiconductor device according to claim 1 , further comprising a gate electrode provided on said barrier layer via a gate insulating film.

11. a two-dimensional electron gas layer is generated in the channel layer; 2. The semiconductor device according to claim 1, wherein the sheet resistance of said two-dimensional electron gas layer is 280 Ω / □ or less.

12. a channel layer including a first nitride semiconductor; a spacer layer including a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor and provided on the channel layer; Al ｘ１ In ｙ１ Ga （１－ｘ１－ｙ１） N (0<x1<1, 0<y1<1, 0<x1+y1<1), and an intermediate layer provided on the spacer layer; Al ｘ２ In （１－ｘ２） a barrier layer including N (0<x2<1) and provided on the intermediate layer; wherein the Al x1 In y1 Ga (1-x1-y1) N contained in the intermediate layer has a Ga ratio decreasing from the spacer layer toward the barrier layer.

13. a channel layer including a first nitride semiconductor; a spacer layer including a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor and provided on the channel layer; Al ｘ１ In ｙ１ Ga （１－ｘ１－ｙ１） N (0<x1<1, 0<y1<1, 0<x1+y1<1), and an intermediate layer provided on the spacer layer; Al ｘ２ In （１－ｘ２） a barrier layer including N (0<x2<1) and provided on the intermediate layer; wherein the Al x1 In y1 Ga (1-x1-y1) N contained in the intermediate layer has a Ga ratio decreasing from the spacer layer toward the barrier layer.

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