Semiconductor Devices

Abstract

To provide a semiconductor device capable of improving withstanding voltage against surge current.SOLUTION: A semiconductor device comprises: a first electrode; a first semiconductor layer of a first conductivity type connected with the first electrode; a second semiconductor layer of the first conductivity type provided in a first region on the first semiconductor layer, having an impurity concentration higher than that of the first semiconductor layer; a third semiconductor layer of a second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer of the first conductivity type provided in a second region on the first semiconductor layer, having an impurity concentration higher than that of the first semiconductor layer and lower than that of the second semiconductor layer, and being separated from the second semiconductor layer via a part of the first semiconductor layer; a fifth semiconductor layer of the second conductivity type provided on a part of the fourth semiconductor layer; and a second electrode connected with the third, fourth, and fifth semiconductor layers.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] Schottky barrier diodes (SBDs) utilize the difference in work function between a metal and an n-type semiconductor to form a diode. To suppress leakage current, a junction barrier Schottky (JBS) structure has been proposed, in which a p-type layer is provided at a portion of the semiconductor-metal junction surface, and a depletion layer is formed starting from the pn interface under reverse bias. This shifts the position where the electric field intensity is at its maximum from the metal-semiconductor junction interface to the semiconductor side. For such semiconductor devices, improved surge current resistance is desirable. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2011 / 151901 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiment is to provide a semiconductor device capable of improving the withstand voltage against surge current. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes a first electrode, a first semiconductor layer of a first conductivity type connected to the first electrode, a second semiconductor layer of the first conductivity type provided in a first region on the first semiconductor layer, the second semiconductor layer having an impurity concentration higher than that of the first semiconductor layer, a third semiconductor layer of a second conductivity type provided on the second semiconductor layer, a fourth semiconductor layer of the first conductivity type provided in a second region on the first semiconductor layer, the fourth semiconductor layer having an impurity concentration higher than that of the first semiconductor layer and lower than that of the second semiconductor layer, the fourth semiconductor layer being separated from the second semiconductor layer by a portion of the first semiconductor layer, a fifth semiconductor layer of the second conductivity type provided on a portion on the fourth semiconductor layer, and a second electrode connected to the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a cross-sectional view showing the semiconductor device according to the embodiment. [Figure 3] 3(a) is a cross-sectional view taken along line AA' shown in FIG. 1, and FIG. 3(b) is a partially enlarged cross-sectional view showing region B of FIG. 3(a). [Figure 4] FIG. 4 is a cross-sectional view corresponding to the region C in FIG. 1, and shows the position of the line DD' in FIG. 3(a). [Figure 5] FIG. 5 is a cross-sectional view corresponding to the region C in FIG. 1, and shows the position of the line EE' in FIG. 3(a). [Figure 6] FIG. 6 is a cross-sectional view corresponding to the region C in FIG. 1, and shows the position of the line FF' in FIG. 3(a). [Figure 7] FIG. 7 is a graph showing an impurity concentration profile, with the horizontal axis representing the position along line GG' in FIG. 3(b) and the vertical axis representing the impurity concentration. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a normal operation of the semiconductor device according to the embodiment when a forward bias is applied. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a normal operation of the semiconductor device according to the embodiment when a reverse bias is applied. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a case where a reverse surge current flows in the semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an embodiment of the present invention will be described. FIG. 1 is a plan view showing a semiconductor device according to this embodiment. FIG. 2 is a cross-sectional view showing the semiconductor device according to this embodiment. 3(a) is a cross-sectional view taken along line AA' shown in FIG. 1, and FIG. 3(b) is a partially enlarged cross-sectional view showing region B of FIG. 3(a). FIG. 4 is a cross-sectional view corresponding to the region C in FIG. 1, and shows the position of the line DD' in FIG. 3(a). FIG. 5 is a cross-sectional view corresponding to the region C in FIG. 1, and shows the position of the line EE' in FIG. 3(a). FIG. 6 is a cross-sectional view corresponding to the region C in FIG. 1, and shows the position of the line FF' in FIG. 3(a). FIG. 7 is a graph showing an impurity concentration profile, with the horizontal axis representing the position along line GG' in FIG. 3(b) and the vertical axis representing the impurity concentration. It should be noted that the drawings are schematic and are appropriately emphasized or simplified, and the dimensional ratios and numbers of components are not necessarily consistent between the drawings.

[0008] As shown in Figures 1 and 2, the semiconductor device 1 according to this embodiment has a cell portion Rc through which current flows, a boundary portion Ri surrounding the cell portion Rc, and a termination portion Rt surrounding the boundary portion Ri. The semiconductor device 1 is composed of a single chip. When viewed from above, the cell portion Rc has a rectangular shape. The termination portion Rt is a frame-like portion that forms the outer edge of the chip. The boundary portion Ri is a frame-like portion that is disposed between the cell portion Rc and the termination portion Rt.

[0009] In the cell section Rc, a PiN diode region R1 and a JBS (junction barrier Schottky) region R2 are defined. When viewed from above, the multiple PiN diode regions R1 are arranged in a staggered pattern within the JBS region R2. The shape of each PiN diode region R1 is, for example, an octagonal island. Note that the arrangement of the multiple PiN diode regions R1 is not limited to a staggered pattern, and the shape of each PiN diode region R1 is not limited to an octagon.

[0010] For ease of explanation, the present specification will hereinafter adopt an XYZ Cartesian coordinate system. The direction in which the arrangement period of the PiN diode regions R1 is shortest is referred to as the "X direction," the direction from the cathode electrode 10 toward the anode electrode 50 (described later) is referred to as the "Z direction," and the direction perpendicular to the X and Z directions is referred to as the "Y direction." Within the Z direction, the direction from the cathode electrode 10 toward the anode electrode 50 is also referred to as "up," and the opposite direction is also referred to as "down," but these terms are also for convenience and are unrelated to the direction of gravity.

[0011] As shown in FIGS. 1 to 6, the semiconductor device 1 includes a cathode electrode 10, a semiconductor portion 20, a contact electrode 30, a Schottky electrode 40, an anode electrode 50, and an insulating film 60. The semiconductor portion 20 is disposed on the cathode electrode 10. The contact electrode 30 is disposed on the semiconductor portion 20 in the cell portion Rc. The Schottky electrode 40 and the anode electrode 50 are disposed on the semiconductor portion 20 in the cell portion Rc and the boundary portion Ri. The insulating film 60 is disposed on the semiconductor portion 20 in the boundary portion Ri and the termination portion Rt. In the boundary portion Ri, the insulating film 60 is disposed between the semiconductor portion 20 and the Schottky electrode 40. The insulating film 60 is formed of, for example, silicon oxide (SiO2). Note that the Schottky electrode 40 and the anode electrode 50 are not shown in FIG. 1.

[0012] The semiconductor portion 20 includes, for example, silicon carbide (SiC), and impurities are introduced into each portion to make the conductivity type n-type or p-type. +"N-type" indicates a higher impurity concentration than "n-type," and "n - "N-type" indicates a lower impurity concentration than "n-type." The same applies to p-type. In this specification, "impurity concentration" refers to the effective concentration that contributes to the conductivity of a semiconductor, and when a certain portion contains both impurities that act as acceptors and impurities that act as donors, it refers to the concentration excluding the offsetting amounts.

[0013] In the semiconductor portion 20, n + Drain layer 21, n - Drift layer 22, n + type layer 23, p type layer 24, p + n-type layer 25, n-type layer 26, p-type layer 27 and p - A resurf layer 28 is provided. + drain layer 21 and n - The drift layer 22 is provided in both the PiN diode region R1 and the JBS region R2. + p-type layer 23, p-type layer 24 and p-type layer + The insulating layer 25 is provided for each PiN diode region R1. + p-type layer 23, p-type layer 24 and p-type layer + The n-type layer 26 and the p-type layer 27 are provided in the JBS region R2. - The resurf layer 28 is provided on the termination portion Rt.

[0014] n + The drain layer 21 is disposed over the entire cathode electrode 10 and is in contact with the cathode electrode 10. + The conductivity type of the drain layer 21 is n + It is in the form of. - The drift layer 22 is n + The n-type drain layer 21 is disposed on the entire surface of the n-type drain layer 21. + The n-type drain layer 21 is in contact with the n-type drain layer 21. - The conductivity type of the drift layer 22 is n - It is of the form: n - The impurity concentration of the drift layer 22 is n +The impurity concentration of the drain layer 21 is lower than that of the drain layer 21.

[0015] n + The shape layer 23 is n - The n-type semiconductor layer 21 is disposed on the drift layer 22 in the PiN diode region R1. + Form layer 23 is n - The n-type drift layer 22 is in contact with the n-type drift layer 22. + The conductivity type of the conductive layer 23 is n + The impurity concentration is n - The impurity concentration of the drift layer 22 is higher than that of the impurity concentration of the drift layer 22.

[0016] The p-type layer 24 is + The p-type layers 24 are disposed on the p-type layers 23 in the PiN diode region R1. When viewed from above, the outer edges of the p-type layers 24 are + The outer periphery of the p-type layer 24 is slightly larger than the outer periphery of the p-type layer 23. - The portion other than the peripheral portion is n + The p-type layer 24 is disposed on the n-type layer 23. + Formation layers 23 and n - The p-type layer 24 is in contact with the p-type drift layer 22. The top surface of the p-type layer 24 is exposed at the top surface of the semiconductor portion 20. The conductivity type of the p-type layer 24 is p-type.

[0017] p + The p-type layer 25 is disposed on a portion of the p-type layer 24. + The outer edge of the p-type layer 25 is slightly smaller than the outer edge of the p-type layer 24. + Form layer 25 is n + It is located directly above the stratum 23. + The p-type layer 25 is in contact with the p-type layer 24. + The upper surface of the insulating layer 25 is exposed to the upper surface of the semiconductor portion 20. + The impurity concentration of the p-type layer 25 is higher than the impurity concentration of the p-type layer 24. In the PiN diode region R1, the p-type layer 24 and the p + a p-type portion consisting of a p-type layer 25 and an n-type portion consisting of a p-type layer 26 + Drain layer 21, n - drift layer 22 and n +The n-type portion made of the insulating layer 23 forms a pn diode.

[0018] The n-type layer 26 is - The n-type layer 26 is disposed on the n-type drift layer 22 in the JBS region R2. - The n-type layer 26 is in contact with the p-type drift layer 22. The n-type layer 26 may be in contact with the p-type layer 24 or may be separated from the p-type layer 24. + Layers 23 to n - The n-type ... - The width of the portion 22a of the n-type drift layer 22, i.e., the width of the n-type layer 26 and the n-type + The gap between the n-type layer 26 and the n-type layer 23 is, for example, about 0.3 to 0.7 μm. The conductivity type of the n-type layer 26 is n-type, and the impurity concentration thereof is n - The impurity concentration of the n-type drift layer 22 is higher than that of the n-type drift layer 23. + The impurity concentration of the layer 23 is lower than that of the layer 23, and n + The impurity concentration of the drain layer 21 is lower than that of the drain layer 21.

[0019] For example, the impurity concentration of the n-type layer 26 is 1×10 17 cm -3 degree, n + The impurity concentration of the impurity layer 23 is 1×10 18 cm -3 degree, n - The impurity concentration of the drift layer 22 is 1×10 16 cm -3 Therefore, as shown in FIG. 7, the impurity concentration profile along the line G-G' in FIG. 3(b) is about n - The minimum value is reached in the drift layer 22.

[0020] The p-type layer 27 is disposed on a portion of the n-type layer 26. The conductivity type of the p-type layer 27 is p-type. A plurality of p-type layers 27 are provided, and are shaped like stripes extending in the Y direction. The plurality of p-type layers 27 are periodically arranged in the X direction. A portion of the n-type layer 26 is disposed between two adjacent p-type layers 27 in the X direction. The lower surface of the p-type layer 27 is located higher than the lower surface of the n-type layer 26. The upper surface of the p-type layer 27 is exposed at the upper surface of the semiconductor portion 20. The upper surface of the portion of the n-type layer 26 disposed between the p-type layers 27 is also exposed at the upper surface of the semiconductor portion 20. The upper surface of the p-type layer 27 and the upper surface of the portion of the n-type layer 26 disposed between the p-type layers 27 are located on the same plane.

[0021] In one example, a plurality of p-type layers 27 arranged continuously along the X direction constitute one group, and the Y-direction ends of the plurality of p-type layers 27 belonging to each group are in contact with a common p-type layer 24. That is, the plurality of p-type layers 27 belonging to one group are arranged between two p-type layers 24 adjacent to each other in the Y direction. Furthermore, the plurality of p-type layers 27 belonging to each group are arranged between two p-type layers 24 adjacent to each other in the X direction.

[0022] p - The RESURF layer 28 is - The semiconductor device is disposed on the drift layer 22 at the termination portion Rt. - The RESURF layer 28 is n - The n-type drift layer 22 and the p-type layer 24 are in contact with each other. - The conductivity type of the RESURF layer 28 is p - The impurity concentration of the p-type layer 24 is lower than that of the p-type layer 24.

[0023] The contact electrode 30 is disposed on the semiconductor portion 20 in the PiN diode region R1. That is, the semiconductor device 1 is provided with a plurality of contact electrodes 30, which are arranged in a staggered pattern, for example. For example, when viewed from above, each contact electrode 30 has an octagonal shape. The contact electrodes 30 are p + It is placed on the shaping layer 25, and p +The contact electrode 30 is in contact with the insulating layer 25. + It is in ohmic contact with the insulating layer 25 .

[0024] The Schottky electrode 40 is disposed on the semiconductor portion 20 in both the PiN diode region R1 and the JBS region R2. The Schottky electrode 40 covers the contact electrodes 30 and is connected to the contact electrodes 30. In the JBS region R2, the Schottky electrode 40 is disposed on the n-type layer 26 and the p-type layer 27 and is in contact with the n-type layer 26 and the p-type layer 27. The Schottky electrode 40 forms a Schottky barrier diode together with the n-type layer 26. The Schottky electrode 40 is also in ohmic contact with the p-type layer 27.

[0025] The anode electrode 50 is disposed in the cell portion Rc and the boundary portion Ri on the Schottky electrode 40. The anode electrode 50 is in contact with the Schottky electrode 40 and is connected to the Schottky electrode 40.

[0026] Next, the operation of the semiconductor device 1 according to this embodiment will be described. FIG. 8 is a schematic cross-sectional view showing a normal operation of the semiconductor device according to this embodiment when a forward bias is applied. FIG. 9 is a schematic cross-sectional view showing a normal operation of the semiconductor device according to this embodiment when a reverse bias is applied. FIG. 10 is a schematic cross-sectional view showing a case where a surge current flows in the reverse direction in the semiconductor device according to this embodiment. 8 and 10, the path of the current I is indicated by a broken line.

[0027] 8, when the semiconductor device 1 is forward biased, that is, when a voltage is applied such that the anode electrode 50 becomes positive and the cathode electrode 10 becomes negative, a forward current I flows through the Schottky barrier diode consisting of the Schottky electrode 40 and the n-type layer 26 in the JBS region R2. As a result, a forward current I flows through the n-type layer 26 in the JBS region R2. At this time, the impurity concentration of the n-type layer 26 is n -Since the impurity concentration is higher than that of the drift layer 22, the resistance (on-resistance) of the forward current can be reduced.

[0028] As shown in FIG. 9, when the semiconductor device 1 is reverse biased, that is, when a voltage is applied such that the anode electrode 50 becomes negative and the cathode electrode 10 becomes positive, the Schottky electrode 40 and the n-type layer 26 interface, the p-type layer 27 and the n-type layer 26 interface, and the p-type layer 24 and the n-type layer 26 interface are electrically isolated from each other. + A depletion layer spreads within the semiconductor portion 20, starting from the interface with the insulating layer 23. This blocks the current.

[0029] In this case, because the p-type layer 27 is provided in the JBS region R2, the position where the electric field strength is highest can be shifted from the interface between the Schottky electrode 40 and the n-type layer 26 to within the semiconductor portion 20. Because the interface between the Schottky electrode 40 and the n-type layer 26 has many defects, reducing the electric field strength at this interface can reduce the leakage current during reverse bias.

[0030] When the power supply connected to the semiconductor device 1 is switched on / off, or when the load connected to the semiconductor device 1 fluctuates, a large surge current may instantaneously flow through the semiconductor device 1. In this case, as shown in FIG. + The p-type layer 23 breaks down, and the p-type layer 24 and n + A surge current flows through the pn diode formed by the n-type layer 23. This allows most of the surge current to flow through the PiN diode region R1, protecting the JBS region R2. As a result, the Schottky barrier diode formed by the Schottky electrode 40 and the n-type layer 26 can be prevented from being thermally destroyed by the surge current.

[0031] In the semiconductor device 1, the n-type layer 26 is + Since it is separated from the morphological layer 23, +This can prevent a surge current from flowing between the n-type layer 23 and the n-type layer 26. As a result, when a surge current flows through the PiN diode region R1, this surge current is prevented from leaking from the PiN diode region R1 to the JBS region R2, and the Schottky barrier diode can be more reliably protected from the surge current.

[0032] Next, the effects of this embodiment will be described. As described above, in the semiconductor device 1, n - By providing the n-type layer 26 on the n-type drift layer 22, the on-resistance can be reduced. + By separating the insulating layer 23, it is possible to prevent surge current from flowing into the Schottky barrier diode and to prevent thermal breakdown of the Schottky barrier diode.

[0033] According to the embodiment described above, it is possible to realize a semiconductor device that can improve the withstand voltage against surge current.

[0034] Although an embodiment of the present invention has been described above, this embodiment is presented as an example and is not intended to limit the scope of the invention. This novel embodiment can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. This embodiment and its modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0035] 1: Semiconductor device 10: Cathode electrode 20: Semiconductor part 21:n + Shaped drain layer 22:n - Shape drift layer 22a:n - A part of the drift layer 22 23:n + shape layer 24:p-type layer 25:p + shape layer 26:N-type layer 27: p-type layer 28:p - Shape Resurf layer 30: Contact electrode 40: Schottky electrode 50: Anode electrode 60: insulating film I: Current R1: PiN diode region R2:JBS area Rc: Cell section Ri: boundary Rt: Termination part

Claims

1. A first electrode; a first semiconductor layer of a first conductivity type connected to the first electrode; a second semiconductor layer provided in a first region on the first semiconductor layer, the second semiconductor layer being of a first conductivity type and having an impurity concentration higher than the impurity concentration of the first semiconductor layer; a third semiconductor layer of the second conductivity type provided on the second semiconductor layer; a fourth semiconductor layer provided in a second region on the first semiconductor layer, of the first conductivity type, having an impurity concentration higher than the impurity concentration of the first semiconductor layer and lower than the impurity concentration of the second semiconductor layer, and separated from the second semiconductor layer via a part of the first semiconductor layer; a fifth semiconductor layer of the second conductivity type provided on a portion of the fourth semiconductor layer; a second electrode connected to the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein the third semiconductor layer has an island shape and the fifth semiconductor layer has a stripe shape when viewed from above.

3. 3. The semiconductor device according to claim 1, further comprising a sixth semiconductor layer provided between the first electrode and the first semiconductor layer, the sixth semiconductor layer being of the first conductivity type and having an impurity concentration higher than that of the first semiconductor layer.

4. 4. The semiconductor device according to claim 3, wherein the sixth semiconductor layer has an impurity concentration higher than that of the fourth semiconductor layer.

5. The second electrode is a third electrode in contact with the third semiconductor layer; a fourth electrode in contact with the fourth semiconductor layer and the fifth semiconductor layer; 5. The semiconductor device according to claim 1, wherein

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