Semiconductor Devices

Abstract

To provide a semiconductor device capable of reducing on-resistance.SOLUTION: A semiconductor device includes a first electrode, a semiconductor portion disposed on the first electrode, a second electrode disposed in a first region on the semiconductor portion, a third electrode disposed in a second region on the semiconductor portion, an insulating member disposed in the first region and the second region within the semiconductor portion, a fourth electrode disposed in the first region and the second region within the insulating member, a fifth electrode disposed in the first region and the second region within the insulating member and between the first electrode and the fourth electrode, and a conductive member arranged in the second region and connected to the third electrode, the fourth electrode, and the fifth electrode.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor device. [Background technology]

[0002] Trench-gate MOSFETs are used as semiconductor devices for power control. In such semiconductor devices, a field plate electrode (hereinafter referred to as an "FP electrode") is sometimes provided below the trench gate to alleviate electric field concentration in the off-state and improve the breakdown voltage between the source and drain. On the other hand, in semiconductor devices for power control, it is desirable to reduce the resistance between the source and drain in the on-state (hereinafter referred to as the "on-resistance") as much as possible. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-009258 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiment is to provide a semiconductor device capable of reducing the on-resistance. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment comprises a first electrode, a semiconductor portion disposed on the first electrode, a second electrode disposed in a first region on the semiconductor portion, a third electrode disposed in a second region on the semiconductor portion, an insulating member disposed in the first region and the second region within the semiconductor portion, a fourth electrode disposed in the first region and the second region within the insulating member, a fifth electrode disposed between the first electrode and the fourth electrode in the first region and the second region within the insulating member, and a conductive member disposed in the second region and connected to the third electrode, the fourth electrode, and the fifth electrode. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a top view showing the semiconductor device according to this embodiment. [Figure 2] FIG. 2 is a partially enlarged top view showing an area A in FIG. [Figure 3] FIG. 3 is a cross-sectional view taken along line BB' shown in FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along line CC' shown in FIG. [Figure 5] FIG. 5 is a cross-sectional view taken along line DD' shown in FIG. [Figure 6] FIG. 6 is a cross-sectional view showing a semiconductor device according to a comparative example. [Figure 7] FIG. 7 is a partially enlarged top view showing the semiconductor device according to the second embodiment. [Figure 8] 8(a) is a cross-sectional view taken along line EE' in FIG. 7, and FIG. 8(b) is a cross-sectional view taken along line FF' in FIG. [Figure 9] FIG. 9 is a partially enlarged top view showing the semiconductor device according to the third embodiment. [Figure 10] 10(a) is a cross-sectional view taken along line GG' in FIG. 9, and FIG. 10(b) is a cross-sectional view taken along line HH' in FIG. [Figure 11] FIG. 11 is a partially enlarged top view showing the semiconductor device according to the fourth embodiment. [Figure 12]12(a) is a cross-sectional view taken along line II' in FIG. 11, and FIG. 12(b) is a cross-sectional view taken along line JJ' in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0007] First Embodiment FIG. 1 is a top view showing the semiconductor device according to this embodiment. FIG. 2 is a partially enlarged top view showing an area A in FIG. FIG. 3 is a cross-sectional view taken along line BB' shown in FIG. FIG. 4 is a cross-sectional view taken along line CC' shown in FIG. FIG. 5 is a cross-sectional view taken along line DD' shown in FIG. The drawings are schematic or conceptual, and are appropriately simplified or emphasized. Furthermore, even if the same components are shown in the drawings, the dimensional ratios and shapes may not necessarily be consistent. This also applies to the other drawings described below.

[0008] 1 to 5, the semiconductor device 1 according to this embodiment includes a drain electrode 11, a source electrode 12, a gate wiring 13, a plurality of gate electrodes 14, a plurality of FP (field plate) electrodes 15, a plurality of conductive members 16, a plurality of source contacts 17, a semiconductor portion 20, a plurality of insulating members 30, an insulating film 31, and an insulating film 32. Note that in FIG. 2, the insulating films 31 and 32 are not shown, and the source electrode 12 and the gate wiring 13 are indicated by two-dot chain lines. This also applies to similar top views described later.

[0009] For the sake of convenience, the present specification will hereinafter adopt an XYZ Cartesian coordinate system. The arrangement direction of the drain electrodes 11 and source electrodes 12 is referred to as the "Z direction," the arrangement direction of the multiple gate electrodes 14 as the "Y direction," and the extension direction of each gate electrode 14 as the "X direction." In addition, within the Z direction, the direction from the drain electrodes 11 toward the source electrodes 12 is also referred to as "up," and the opposite direction as "down," but these expressions are also for convenience and are unrelated to the direction of gravity.

[0010] The semiconductor device 1 includes a cell region 91 (first region), a finger region 92 (second region), a gate pad region 93, a connecting region 94, and a termination region 95. Each of these regions is defined within the XY plane. A frame-shaped termination region 95 is disposed on the periphery of the semiconductor device 1 when viewed from above. The cell region 91, the finger region 92, the gate pad region 93, and the connecting region 94 are disposed in a rectangular region surrounded by the termination region 95. The finger region 92 is disposed in the center of this rectangular region in the X direction and extends substantially through this rectangular region in the Y direction. The gate pad region 93 is disposed at one corner of the rectangular region surrounded by the termination region 95. The connecting region 94 is disposed along the inner edge of the termination region 95 so as to connect the finger region 92 to the gate pad region 93. The connecting region 94 is connected to one end of the finger region 92 in the Y direction and one end of the gate pad region 93 in the X direction.

[0011] The cell region 91 is arranged in a rectangular region surrounded by the termination region 95, excluding the finger region 92, the gate pad region 93, and the connecting region 94, and occupies most of the semiconductor device 1 when viewed in the Z direction. Two cell regions 91 are set, and are arranged on both sides of the finger region 92 in the X direction. In other words, the finger region 92 is arranged between the two cell regions 91. However, the positional relationship between the cell region 91, the finger region 92, the gate pad region 93, and the connecting region 94 is not limited to this.

[0012] The drain electrode 11 (first electrode) is made of, for example, a metal, has a plate shape, and is disposed over the entire or substantially the entire lower surface of the semiconductor device 1.

[0013] The semiconductor portion 20 is disposed on the drain electrode 11. The semiconductor portion 20 is made of a semiconductor material, for example, single-crystal silicon (Si). As will be described later, the semiconductor portion 20 contains impurities locally, which determine the conductivity type of each portion.

[0014] The insulating film 31 is disposed on the semiconductor portion 20. The insulating film 31 is made of, for example, silicon oxide (SiO). The insulating film 32 is disposed on the insulating film 31. The insulating film 32 is made of, for example, BPSG (boron phosphorous silicate glass: boron-phosphorus-doped silicon oxide).

[0015] The source electrode 12 (second electrode) and the gate wiring 13 (third electrode) are arranged on the insulating film 32. The source electrode 12 is arranged in a cell region 91 of the semiconductor device 1. The gate wiring 13 is arranged in a finger region 92, a gate pad region 93, and a connecting region 94 of the semiconductor device 1. The portion of the gate wiring 13 arranged in the finger region 92 is a wiring extending in the Y direction. The portion of the gate wiring 13 arranged in the gate pad region 93 is a rectangular pad and functions as a gate pad. The portion of the gate wiring 13 arranged in the connecting region 94 is a wiring extending in the X direction.

[0016] A plurality of insulating members 30 are disposed in the semiconductor portion 20. The insulating members 30 are periodically arranged along the Y direction, and each insulating member 30 extends in the X direction. The insulating members 30 are formed of an insulating material such as silicon oxide. The top surfaces of the insulating members 30 are exposed from the top surface of the semiconductor portion 20.

[0017] The gate electrode 14 (fourth electrode) is disposed in the upper part of the insulating member 30 and extends in the X direction. For example, one gate electrode 14 is disposed in one insulating member 30. Looking at the entire semiconductor device 1, a plurality of gate electrodes 14 are arranged along the Y direction. The gate electrodes 14 are formed of a conductive material, for example, polysilicon containing impurities.

[0018] The FP electrode 15 (fifth electrode) is disposed in the lower part of the insulating member 30 and extends in the X direction. That is, the FP electrode 15 is disposed between the drain electrode 11 and the gate electrode 14 in the insulating member 30. For example, one FP electrode 15 is disposed in one insulating member 30. Looking at the semiconductor device 1 as a whole, a plurality of FP electrodes 15 are arranged along the Y direction. The FP electrode 15 is formed of a conductive material, for example, polysilicon containing impurities.

[0019] Each insulating member 30, and the gate electrodes 14 and FP electrodes 15 disposed therein, are disposed over substantially the entire X-direction of the semiconductor device 1, and are disposed across two cell regions 91 and the finger region 92 therebetween. The widths of the insulating members 30, gate electrodes 14, and FP electrodes 15 in the finger region 92, i.e., their lengths in the Y-direction, are greater than their respective widths in the cell region 91.

[0020] In the semiconductor portion 20, the conductivity type is n + a drain layer 21 and an n - a p-type drift layer 22, a p-type base layer 23, and an n + a source layer 24 of the type, and + A contact layer 25 of the n type is provided. + Type" is "n - This indicates that the carrier concentration is higher than that of the "p type" + "N-type" indicates a higher carrier concentration than "p-type." "Carrier concentration" refers to the effective impurity concentration that functions as a donor or acceptor.

[0021] The drain layer 21 is in contact with the drain electrode 11 and is connected to the drain electrode 11. In this specification, "connection" refers to electrical connection. The drift layer 22 is disposed on the drain layer 21 and in contact with the drain layer 21. The drain layer 21 and the drift layer 22 form a first semiconductor layer. The base layer 23 (second semiconductor layer) is disposed on the drift layer 22 and in contact with the drift layer 22. The source layer 24 (third semiconductor layer) is disposed on a part of the base layer 23. The contact layer 25 is disposed on another part of the base layer 23. The base layer 23, the source layer 24, and the contact layer 25 are disposed in the cell region 91, and are not disposed in the finger region 92. The base layer 23 may be disposed in the finger region 92.

[0022] As described above, the source electrode 12 is disposed in the cell region 91. In the cell region 91, the source layer 24 and the contact layer 25 are connected to the source electrode 12 via the source contact 17. The source contact 17 extends in the Z direction, with its upper end in contact with the lower surface of the source electrode 12, penetrating the insulating film 32, the insulating film 31, and the source layer 24, and its lower end in contact with the upper surface of the contact layer 25.

[0023] Furthermore, a portion of the gate wiring 13 is arranged in the finger region 92. In the finger region 92, a conductive member 16 is arranged. One conductive member 16 is arranged for one gate electrode 14 and one FP electrode 15 arranged in one insulating member 30. When viewing the semiconductor device 1 as a whole, a plurality of conductive members 16 are arranged in a line along the Y direction. Furthermore, in this embodiment, the conductive members 16 are not arranged in the cell region 91.

[0024] The conductive member 16 is made of a conductive material, such as a metal, and is a laminated body of, for example, a titanium layer, a titanium nitride layer, and a tungsten layer. The conductive member 16 is, for example, a gate contact extending in the Z direction. An upper portion 16a of the conductive member 16 is disposed within the insulating films 31 and 32 and penetrates the insulating films 31 and 32 in the Z direction. A lower portion 16b of the conductive member 16 is disposed within the insulating member 30. The upper end of the conductive member 16 contacts the lower surface of the gate wiring 13. The lower end of the conductive member 16 contacts the upper surface of the FP electrode 15. The conductive member 16 also penetrates the gate electrode 14 in the Z direction and thereby contacts the gate electrode 14. As a result, the conductive member 16 is connected to the gate wiring 13, the gate electrode 14, and the FP electrode 15.

[0025] In the finger region 92, the gate wiring 13 forms one wiring extending in the Y direction. The gate wiring 13 is connected to all the conductive members 16 arranged along the Y direction. As a result, the gate wiring 13 is connected to all the gate electrodes 14 and all the FP electrodes 15 via the conductive members 16.

[0026] The gate electrode 14 faces the base layer 23 and the source layer 24 via a portion 30a of the insulating member 30. The portion 30a of the insulating member 30 forms the side surface of the upper portion of the insulating member 30 and functions as a gate insulating layer. The upper surface of the gate electrode 14 contacts the insulating film 31. The FP electrode 15 faces the drift layer 22 via a portion 30b of the insulating member 30. The portion 30b of the insulating member 30 forms the side surface and lower surface of the lower portion of the insulating member 30. Furthermore, a portion 30c of the insulating member 30 is interposed between the gate electrode 14 and the FP electrode 15. As a result, in the finger region 92, the gate electrode 14 is separated from the FP electrode 15 via the portion 30c.

[0027] With this configuration, a vertical MOSFET is formed in the cell region 91. In the finger region 92, the gate electrode 14 and the FP electrode 15 are connected to the gate wiring 13. The gate wiring 13 is connected to the outside of the semiconductor device 1 in the gate pad region 93.

[0028] Next, the effects of the semiconductor device 1 according to this embodiment will be described. A voltage is applied between the drain electrode 11 and the source electrode 12 so that the drain electrode 11 becomes a positive electrode and the source electrode 12 becomes a negative electrode. For example, a ground potential is applied to the source electrode 12, and a predetermined positive potential is applied to the drain electrode 11. - A depletion layer spreads from the interface between the p-type drift layer 22 and the p-type base layer 23 as a starting point.

[0029] In this state, when a gate potential equal to or greater than the threshold value of the MOSFET is applied to the gate wiring 13, this gate potential is transmitted to the gate electrode 14 via the conductive member 16. As a result, an inversion layer is formed in the portion of the base layer 23 that contacts the portion 30a of the insulating member 30. As a result, the semiconductor device 1 is turned on, and a current flows through the drain electrode 11, the drain layer 21, the drift layer 22, the inversion layer in the base layer 23, the source layer 24, the source contact 17, and the source electrode 12. In the on state, the potential difference between the drain electrode 11 and the source electrode 12 is small, and therefore the voltage applied to the semiconductor portion 20 is also small, and the breakdown voltage does not pose an issue.

[0030] On the other hand, when a gate potential below the threshold of the MOSFET, for example, a ground potential, is applied to the gate wiring 13, the inversion layer disappears from the base layer 23, and the semiconductor device 1 enters an off state. In the off state, the potential difference between the drain electrode 11 and the source electrode 12 increases, and a high voltage is applied to the semiconductor portion 20. Therefore, by applying a constant potential, for example, a ground potential, to the FP electrode 15, the concentration of the electric field in the semiconductor portion 20 can be alleviated, and the breakdown voltage can be improved.

[0031] In this way, when the semiconductor device 1 is in the off state, the same potential can be applied to the gate electrode 14 and the FP electrode 15. According to this embodiment, by providing the conductive member 16 in the finger region 92 and connecting the conductive member 16 to the gate wiring 13, the gate electrode 14, and the FP electrode 15, the same potential can be applied to the gate electrode 14 and the FP electrode 15 using a single finger region 92. Therefore, in the semiconductor device 1, it is not necessary to provide separate finger regions for the gate electrode that supplies a potential to the gate electrode 14 and for the FP electrode that supplies a potential to the FP electrode 15. This allows the cell region 91 to be wider, thereby reducing the on-resistance of the semiconductor device 1.

[0032] <Comparative Example> FIG. 6 is a cross-sectional view showing a semiconductor device according to this comparative example. As shown in FIG. 6, the semiconductor device 101 according to this comparative example has two gate finger regions 192a and one FP finger region 192b. A gate wiring 113a is disposed in the gate finger region 192a and connected to a gate electrode 114. An FP wiring 113b is disposed in the FP finger region 192b and connected to an FP electrode 115. Thus, the semiconductor device 101 can apply potentials to the gate electrode 114 and the FP electrode 115 independently. However, because the gate finger regions 192a and the FP finger regions 192b are disposed, the cell region 191 becomes narrow, resulting in a high on-resistance.

[0033] <Second embodiment> FIG. 7 is a partially enlarged top view showing the semiconductor device according to this embodiment. 8(a) is a cross-sectional view taken along line EE' in FIG. 7, and FIG. 8(b) is a cross-sectional view taken along line FF' in FIG. 8(a) and (b) show only the top of the semiconductor device.

[0034] 7, 8(a) and 8(b), in the semiconductor device 2 according to this embodiment, a plurality of conductive members 16 are arranged alternately in two columns 16A and 16B extending in the Y direction. That is, when viewed from the Z direction, the conductive members 16 are arranged alternately in the two columns 16A and 16B. Therefore, the positions in the X direction of two conductive members 16 connected to two gate electrodes 14 adjacent in the Y direction are different from each other.

[0035] According to this embodiment, by arranging the conductive members 16 alternately, the positions of the conductive members 16 in the X direction can be shifted between the insulating members 30 adjacent in the Y direction. This makes it possible to shorten the arrangement period of the insulating members 30 in the Y direction. As a result, the channel width of the semiconductor device 2 can be increased, and the on-resistance can be further reduced. Other configurations and effects of this embodiment are the same as those of the first embodiment.

[0036] <Third embodiment> FIG. 9 is a partially enlarged top view showing the semiconductor device according to this embodiment. 10(a) is a cross-sectional view taken along line GG' in FIG. 9, and FIG. 10(b) is a cross-sectional view taken along line HH' in FIG. 10(a) and (b) show only the top portion of the semiconductor device.

[0037] 9, 10(a) and 10(b), in the semiconductor device 3 according to this embodiment, the lower portion 16b of each conductive member 16 extends in the X direction, and when viewed from the Z direction, the lower portion 16b of each conductive member 16 is also disposed in the cell region 91. On the other hand, the upper portion 16a of each conductive member 16 is disposed only in the finger region 92. As described above, the lower portion 16b of each conductive member 16 is the portion disposed within the insulating member 30, and the upper portion 16a is the portion disposed within the insulating film 31 and the insulating film 32.

[0038] As a result, the center of the gate electrode 14 in the width direction, i.e., the center in the Y direction, is formed by the lower part 16b of the conductive member 16. Both sides of the gate electrode 14 in the width direction, i.e., both sides in the Y direction, are formed of polysilicon, as in the first embodiment.

[0039] According to this embodiment, the resistance of the gate electrode 14 can be reduced by configuring the central portion of the gate electrode 14 in the width direction with the lower portion 16b of the conductive member 16. Other configurations and effects of this embodiment are the same as those of the first embodiment.

[0040] <Fourth embodiment> FIG. 11 is a partially enlarged top view showing the semiconductor device according to this embodiment. 12(a) is a cross-sectional view taken along line II' in FIG. 11, and FIG. 12(b) is a cross-sectional view taken along line JJ' in FIG. 12(a) and (b) show only the top portion of the semiconductor device.

[0041] 11, 12(a) and 12(b), in the semiconductor device 4 according to this embodiment, the conductive members 16 extend to the lower ends of the FP electrodes 15. Similarly to the third embodiment, the lower portions 16b of the conductive members 16 extend in the X direction, and when viewed from the Z direction, the lower portions 16b of the conductive members 16 are also disposed in the cell region 91. As a result, the center portion of the gate electrode 14 in the width direction is formed by the upper portions of the lower portions 16b of the conductive members 16, and the entire FP electrode 15 is formed by the lower portions of the lower portions 16b of the conductive members 16. Thus, the FP electrode 15 is integrally formed with the conductive members 16. The upper portions 16a of the conductive members 16 are disposed only in the finger region 92.

[0042] According to this embodiment, the lower portion 16b of the conductive member 16 constitutes a part of the gate electrode 14 and the entire FP electrode 15, so that the resistance of the gate electrode 14 and the FP electrode 15 can be reduced.

[0043] Furthermore, according to this embodiment, both widthwise ends of the gate electrode 14 are formed of polysilicon, and the widthwise center portion of the gate electrode 14 and the FP electrode 15 are formed of a conductive member 16 containing metal. As a result, a potential difference occurs between both widthwise ends of the gate electrode 14 and the conductive member 16 due to the difference in work function between the polysilicon portion and the metal-containing portion. As a result, a depletion layer expands within the drift layer 22, starting from the interface between the insulating member 30 and the drift layer 22, and electrons near the insulating member 30 are repelled. This reduces the capacitance between the FP electrode 15 and the drift layer 22 and the output capacitance of the semiconductor device 4. This shortens the time required to charge and discharge the output capacitance when the semiconductor device 4 is switched, thereby reducing switching loss in the semiconductor device 4. Other configurations and effects of this embodiment are similar to those of the first embodiment.

[0044] According to the above-described embodiment, a semiconductor device capable of reducing the on-resistance can be realized.

[0045] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can also be implemented in combination with each other.

[0046] The present invention includes the following aspects.

[0047] (Appendix 1) A first electrode; a semiconductor portion disposed on the first electrode; a second electrode disposed on the first region on the semiconductor portion; a third electrode disposed in a second region on the semiconductor portion; an insulating member disposed in the first region and the second region within the semiconductor portion; a fourth electrode disposed in the first region and the second region within the insulating member; a fifth electrode disposed between the first electrode and the fourth electrode in the first region and the second region within the insulating member; a conductive member disposed in the second region and connected to the third electrode, the fourth electrode, and the fifth electrode; A semiconductor device comprising:

[0048] (Appendix 2) The semiconductor portion is a first semiconductor layer of a first conductivity type connected to the first electrode; a second semiconductor layer of a second conductivity type disposed on the first semiconductor layer; a third semiconductor layer of the first conductivity type, disposed on a portion of the second semiconductor layer and connected to the second electrode; and the fourth electrode faces the second semiconductor layer and the third semiconductor layer via a part of the insulating member; 2. The semiconductor device according to claim 1, wherein the fifth electrode faces the first semiconductor layer via another part of the insulating member.

[0049] (Appendix 3) 3. The semiconductor device according to claim 1, wherein the conductive member includes a metal.

[0050] (Appendix 4) 4. The semiconductor device according to claim 1, wherein the conductive member penetrates the fourth electrode in a first direction in which the first electrode and the second electrode are arranged.

[0051] (Appendix 5) a plurality of the insulating members, the fourth electrodes, the fifth electrodes, and the conductive members are provided, the plurality of insulating members, the plurality of fourth electrodes, and the plurality of fifth electrodes are respectively arranged along a second direction intersecting a first direction in which the first electrodes and the second electrodes are arranged, each of the insulating members, each of the fourth electrodes, and each of the fifth electrodes extends in a third direction intersecting the first direction and the second direction; 5. The semiconductor device according to claim 1, wherein the fourth electrodes and the fifth electrodes are commonly connected to the third electrode in the second region.

[0052] (Appendix 6) 6. The semiconductor device according to claim 5, wherein the plurality of conductive members are not arranged in the first region.

[0053] (Appendix 7) 7. The semiconductor device according to claim 5, wherein the plurality of conductive members are arranged along the second direction.

[0054] (Appendix 8) 7. The semiconductor device according to claim 5, wherein the positions in the third direction of the two conductive members connected to the two fourth electrodes adjacent in the second direction are different from each other.

[0055] (Appendix 9) a lower portion of each of the conductive members extends in the third direction; 6. The semiconductor device according to claim 5, wherein the lower portion of the conductive member is also disposed in the first region.

[0056] (Appendix 10) 10. The semiconductor device according to claim 1, wherein the fourth electrode and the fifth electrode contain silicon.

[0057] (Appendix 11) 10. The semiconductor device according to any one of claims 1 to 9, wherein the fifth electrode is formed integrally with the conductive member.

[0058] (Appendix 12) 12. The semiconductor device according to any one of claims 1 to 11, wherein the second region is disposed between two of the first regions. [Explanation of symbols]

[0059] 1, 2, 3, 4 Semiconductor device 11 Drain electrode 12 Source electrode 13 Gate wiring 14 gate electrode 15 FP electrode 16 Conductive material Column 16A, 16B 16a upper part 16b bottom 17 Source Contacts 20 Semiconductor part 21 Drain layer 22 Drift Layer 23 Base Layer 24 Source Layer 25 Contact layer 30 Insulating material 30a, 30b, 30c parts 31, 32 Insulating film 91 cell area 92 Finger Area 93 Gate pad area 94 Consolidation area 95 Termination area 101 Semiconductor device 113a Gate wiring 113b FP wiring 114 gate electrode 115 FP electrode 191 cell area 192a Gate finger region 192b FP finger region

Claims

1. A first electrode; a semiconductor portion disposed on the first electrode; a second electrode disposed on the first region on the semiconductor portion; a third electrode disposed in a second region on the semiconductor portion; an insulating member disposed in the first region and the second region within the semiconductor portion; a fourth electrode disposed in the first region and the second region within the insulating member; a fifth electrode disposed between the first electrode and the fourth electrode in the first region and the second region within the insulating member; a conductive member that is disposed at least in the second region, is connected to the third electrode, the fourth electrode, and the fifth electrode, and penetrates the fourth electrode in a first direction in which the first electrode and the second electrode are arranged; A semiconductor device comprising:

2. The semiconductor portion is a first semiconductor layer of a first conductivity type connected to the first electrode; a second semiconductor layer of a second conductivity type disposed on the first semiconductor layer; a third semiconductor layer of the first conductivity type, disposed on a portion of the second semiconductor layer and connected to the second electrode; and the fourth electrode faces the second semiconductor layer and the third semiconductor layer via a part of the insulating member; The semiconductor device according to claim 1 , wherein the fifth electrode faces the first semiconductor layer via another part of the insulating member.

3. The semiconductor device according to claim 1 , wherein the conductive member includes a metal.

4. A first electrode; a semiconductor portion disposed on the first electrode; a second electrode disposed on the first region on the semiconductor portion; a third electrode disposed in a second region on the semiconductor portion; an insulating member disposed in the first region and the second region within the semiconductor portion; a fourth electrode disposed in the first region and the second region within the insulating member; a fifth electrode disposed between the first electrode and the fourth electrode in the first region and the second region within the insulating member; a conductive member disposed at least in the second region and connected to the third electrode, the fourth electrode, and the fifth electrode; Equipped with The second region is disposed between two of the first regions.

5. a plurality of the insulating members, the fourth electrodes, the fifth electrodes, and the conductive members are provided, the plurality of insulating members, the plurality of fourth electrodes, and the plurality of fifth electrodes are respectively arranged along a second direction intersecting a first direction in which the first electrodes and the second electrodes are arranged, each of the insulating members, each of the fourth electrodes, and each of the fifth electrodes extends in a third direction intersecting the first direction and the second direction; 5. The semiconductor device according to claim 1, wherein the plurality of fourth electrodes and the plurality of fifth electrodes are commonly connected to the third electrode in the second region.

6. The semiconductor device according to claim 5 , wherein the plurality of conductive members are not arranged in the first region.

7. The semiconductor device according to claim 5 , wherein the plurality of conductive members are arranged in the second direction.

8. 6. The semiconductor device according to claim 5, wherein the positions in the third direction of the two conductive members connected to the two fourth electrodes adjacent in the second direction are different from each other.

9. a lower portion of each of the conductive members extends in the third direction; The semiconductor device according to claim 5 , wherein the lower portion of the conductive member is also disposed in the first region.

10. 5. The semiconductor device according to claim 1, wherein the fourth electrode and the fifth electrode contain silicon.

11. 5. The semiconductor device according to claim 1, wherein the fifth electrode is formed integrally with the conductive member.

12. 4. The semiconductor device according to claim 1, wherein the second region is disposed between two of the first regions.

13. The semiconductor portion is a first semiconductor layer of a first conductivity type connected to the first electrode; a second semiconductor layer of a second conductivity type disposed on the first semiconductor layer; a third semiconductor layer of the first conductivity type, disposed on a portion of the second semiconductor layer and connected to the second electrode; and the fourth electrode faces the second semiconductor layer and the third semiconductor layer via a part of the insulating member; The semiconductor device according to claim 4 , wherein the fifth electrode faces the first semiconductor layer via another part of the insulating member.

14. The semiconductor device according to claim 4 , wherein the conductive member includes a metal.

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