Silicon carbide semiconductor device and manufacturing method

Abstract

The present disclosure relates to a power semiconductor device (100) comprising a silicon carbide (SiC) structure (110) comprising a SiC epilayer (112), at least one ohmic contact (120) formed on a first major surface (114) of the SiC structure (110), and at least one Schottky barrier contact (130) formed on a second major surface (116) of the SiC structure (110). The at least one Schottky barrier contact (130) includes a metal layer (136) and a carbon-group interlayer (134) disposed between the metal layer (136) and the second major surface (116) of the SiC structure (110). The present disclosure relates to methods of manufacturing Schottky barrier diodes (400), vertical field effect transistors such as power MOSFETs (500), and power semiconductor devices (100).

Description

[Technical Field]

[0001] The present disclosure relates to power semiconductor devices, such as Schottky barrier diodes or vertical FETs, that include silicon carbide semiconductor structures having at least one ohmic contact and at least one Schottky barrier contact, and methods for their manufacture. [Background technology]

[0002] Silicon carbide (SiC) semiconductor Schottky barrier diodes (SBDs) generally have low leakage current, forward voltage drop, and reverse recovery time, making them suitable for many applications such as automotive applications, including electric vehicle charging, renewable energy generation and distribution, etc.

[0003] SiC SBDs can be formed by metallizing a SiC semiconductor structure in a two-step process. First, a low-resistance ohmic contact is deposited on the SiC substrate, followed by sintering at a relatively high temperature of 900-1000°C. In the second step, a nickel (Ni) layer is deposited on the epitaxial layer of the SiC semiconductor structure to obtain a Schottky barrier contact on the other side.

[0004] U.S. Patent Application Publication No. 2006 / 178016 discloses silicon carbide-based device contacts and contact fabrication methods that utilize a layer of polysilicon on a SiC substrate, with a contact metal layer deposited on top of the polysilicon. Both Schottky and ohmic contacts can be formed. The polysilicon layer can be continuous or patterned, and can be undoped or doped to be n-type or p-type.

[0005] Chinese Patent Publication No. 109 686 797 discloses a silicon carbide Schottky diode and a manufacturing method thereof. The silicon carbide Schottky diode includes a composite Schottky contact structure including a silicon carbide epitaxial layer, a Schottky metal layer, and a graphene layer disposed between the silicon carbide epitaxial layer and the Schottky metal layer, where the graphene layer is used to block interpenetration between silicon carbide atoms of the silicon carbide epitaxial layer and metal atoms of the Schottky metal layer, thereby reducing leakage current of the composite Schottky contact structure.

[0006] Inaba Masafumi et al., "Very Low Schottky Barrier Height at Carbon Nanotube and Silicon Carbide Interface" (APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS, 2 HUNTINGTON QUADRANGLE, MELVILLE, NY 11747, vol. 106, no. 12, 23 March 2015, ISSN: 0003-6951, DOI: 10.1063 / 1.4916248), discloses that electrical contacts with silicon carbide (SiC) with low contact resistivity and high current durability are important for future SiC power devices, especially small vertical devices. Carbon nanotube (CNT) forests formed by decomposition of silicon carbide (SiC) are dense forests, ideal for use as heat-dissipating ohmic contacts in SiC power transistors.

[0007] U.S. Patent No. 6,139,624 discloses a method for producing electrical contacts on SiC surfaces. A carbon coating, preferably a graphite coating, is first formed on the silicon carbide surface. The carbon coating is then converted to a metal carbide coating by the addition of a carbide-forming metal.

[0008] U.S. Patent Application Publication No. 2019 / 296156 discloses a semiconductor device including a first electrode, a second electrode, a silicon carbide layer disposed between the first electrode and the second electrode, a first n-type silicon carbide region disposed in the silicon carbide layer, and a first nitrogen region disposed in the silicon carbide layer, the first nitrogen region being disposed between the first n-type silicon carbide region and the first electrode, the first nitrogen region having a first nitrogen concentration higher than a first n-type impurity concentration of the first n-type silicon carbide region.

[0009] U.S. Patent Application Publication No. 2018 / 166540 discloses that a semiconductor device may include an n-type layer disposed on a first surface of an n+ type silicon carbide substrate, a trench disposed in the n-type layer, a p-type region, an n+ type region, and a p+ type region disposed in an upper portion within the n-type layer, a gate insulating layer disposed on the n-type layer, the n+ type region, and the p-type region, a gate electrode disposed on the gate insulating layer, an insulating layer disposed on the gate electrode, a source electrode disposed on the insulating layer and in the trench, and a drain electrode disposed on a second surface of the n+ type silicon carbide substrate, wherein the source electrode includes an ohmic junction region and a Schottky junction region. Summary of the Invention [Problem to be solved by the invention]

[0010] It is an object of the present disclosure to present an alternative, preferably more efficient, method for forming a power semiconductor device including a SiC structure and the corresponding power semiconductor device. In particular, it is desirable to describe a power semiconductor device that is less susceptible to adverse conditions during fabrication, thus enabling an improved manufacturing process. [Means for solving the problem]

[0011] Embodiments of the present disclosure relate to power semiconductor devices with SiC structures, Schottky barrier diodes, vertical field effect transistors, and methods for manufacturing power semiconductor devices according to the independent claims.

[0012] According to a first aspect of the present disclosure, a power semiconductor device is disclosed. The device includes a silicon carbide (SiC) structure including a SiC layer, at least one ohmic contact formed on a first major surface of the SiC structure, and at least one Schottky barrier contact formed on a second major surface of the SiC structure. The at least one Schottky barrier contact includes a metal layer and a carbon-group intermediate layer disposed between the metal layer and the second major surface of the SiC structure.

[0013] The carbon-group interlayer can have a thickness in the range of 10-100 nm and can be formed by depositing a chemical element from the carbon group onto the second primary surface of the SiC structure. Such a thickness is sufficient to achieve improved thermal stability of the Schottky barrier contact while maintaining the desired Schottky barrier formation.

[0014] In particular, the inventors have discovered that a Schottky barrier contact comprising a stack including a carbon-group interlayer and a metal layer does not degrade at higher annealing temperatures, e.g., annealing temperatures of about 1000° C. Thus, the resistance of the Schottky barrier contact to adverse conditions during semiconductor device fabrication is reduced, and, among other advantages, the simultaneous formation of at least one ohmic contact and at least one Schottky barrier contact is enabled.

[0015] According to at least one embodiment, the SiC layer is 17 cm -3 Less than, especially 10 13 cm -3 ~10 17 cm -3 For example, an epitaxially grown SiC layer has a dopant concentration in the range of 3·10 14 cm -3 ~5·10 14 cm -3 Alternatively, the SiC layer may be doped with 10 nitrogen atoms.7 ~10 9 The SiC layer may be a high-purity, semi-insulating layer with an electrical resistivity of ohm·cm. Among other advantages, the inventors have found that a SiC layer with a relatively low dopant concentration is a suitable foundation for the above stack in that such a low dopant concentration SiC layer does not react with the Schottky barrier contact material during annealing and similar high-temperature processing steps.

[0016] According to a second aspect of the present disclosure, there is provided a Schottky barrier diode, comprising: a power semiconductor device according to the first aspect; an anode terminal connected to at least one Schottky barrier contact; and a cathode terminal connected to at least one ohmic contact.

[0017] Such Schottky barrier diodes are easy to manufacture and have relatively low leakage current, low forward voltage drop and low reverse recovery time.

[0018] According to a third aspect of the present disclosure, there is provided a vertical field effect transistor (FET), particularly a power MOSFET, comprising: a power semiconductor device according to the first aspect; a source terminal connected to at least one Schottky barrier contact; a drain terminal connected to at least one ohmic contact; and a gate terminal connected to an insulated gate electrode arranged on the second major surface of the SiC structure.

[0019] Such vertical FETs with integrated body diodes do not require an additional device to act as a freewheeling diode. The integration of Schottky diodes into vertical FETs is made possible by the increased thermal budget of the Schottky contact. Furthermore, integrating Schottky diodes into MOSFETs or similar power semiconductor structures is an option for reducing the body diode turn-on voltage from over 2.5 V to less than 1 V.

[0020] According to a fourth aspect of the present disclosure, there is provided a method for manufacturing a power semiconductor device, the method comprising: forming, in particular epitaxially growing, a silicon carbide (SiC) layer of the SiC structure; depositing a carbon-group intermediate layer on the SiC layer; depositing a first metal layer on a backside of the SiC structure; depositing a second metal layer of a Schottky contact on the carbon-group interlayer; After depositing the first metal layer and the second metal layer, annealing at least the first metal layer at an annealing temperature to form at least one ohmic contact; Includes.

[0021] The above method steps allow for the formation of ohmic contacts and Schottky barrier contacts using the same process steps and at the same temperature. The disclosed method increases the thermal budget of the formed Schottky barrier contacts and significantly reduces the integration effort. This also allows for other high temperature steps to be performed after the formation of the Schottky barrier contacts.

[0022] The above-described power semiconductor devices and methods for forming same are particularly suitable for the fabrication of Schottky barrier diodes, vertical FETs, and other semiconductor devices that include at least one Schottky barrier contact structure.

[0023] Thus, features and advantages described in connection with power semiconductor devices generally, and Schottky barrier diodes or vertical FETs in particular, can be used in any of the disclosed devices. Moreover, certain aspects, such as selection of materials, dimensions, or similar parameters, disclosed with respect to various devices are also applicable to corresponding steps in the manufacturing methods, and vice versa.

[0024] The accompanying drawings are included to provide a further understanding. In the drawings, elements of the same structure and / or function may be referenced by the same or corresponding reference numerals. It should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale. [Brief explanation of the drawings]

[0025] [Figure 1] 1 is a schematic cross-sectional view of a power semiconductor device. [Figure 2] 1 is a schematic flow chart of method steps for manufacturing a power semiconductor device. [Figure 3] 1A-1C show current-voltage (IV) characteristics of a Schottky barrier contact before and after annealing at different annealing temperatures and at different processing stages during the fabrication of a Schottky barrier diode. [Figure 4] 1A-1D illustrate different processing stages during the manufacture of a Schottky barrier diode. [Figure 5] 1A-1D illustrate different processing stages during the manufacture of a Schottky barrier diode. [Figure 6] 1A-1D illustrate different processing stages during the manufacture of a Schottky barrier diode. [Figure 7] 1A-1D illustrate various processing stages during the fabrication of a vertical power MOSFET. [Figure 8] 1A-1D illustrate various processing stages during the fabrication of a vertical power MOSFET. [Figure 9] 1A-1D illustrate various processing stages during the fabrication of a vertical power MOSFET. [Figure 10] 1A-1D illustrate various processing stages during the fabrication of a vertical power MOSFET. DETAILED DESCRIPTION OF THE INVENTION

[0026] While the present disclosure is susceptible to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and have been described in detail. It should be understood, however, that the intention is not to limit the disclosure to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the present disclosure as defined by the appended claims.

[0027] FIG. 1 illustrates a first embodiment of a power semiconductor device 100. The device 100 includes a SiC structure 110 including a SiC layer 112 having a first major surface 114, which is the lower side in FIG. 1 , and a second major surface 116, which is the opposite side in FIG. 1 . In the illustrated embodiment, the SiC layer 112 extends all the way from the first major surface 114 to the second major surface 116. That is, the SiC structure 110 corresponds to the SiC layer 112. However, in other embodiments, the SiC layer 112 may be an epitaxial SiC layer (SiC epilayer) grown on a SiC substrate (not shown). That is, the SiC structure 110 includes a SiC substrate and a SiC epilayer. In this case, the first major surface 114 is formed by the back surface of the SiC substrate.

[0028] In the illustrated embodiment, power semiconductor device 100 further includes an ohmic contact 120 formed on first major surface 114. For example, a first metal layer 122, such as a nickel layer, may be deposited on lower major surface 114 and then sintered and / or annealed to form ohmic contact 120.

[0029] If SiC layer 112 extends from first major surface 114 all the way to second major surface 116, an n+ layer or region may be formed in at least a corresponding area of ​​first major surface 114 by ion implantation or plasma immersion ion implantation (PIII) followed by high temperature activation at 1600°C prior to forming at least one ohmic contact 120.

[0030] The power semiconductor device 100 further comprises a layer stack 132 comprising an intermediate layer 134 and a second metal layer 136 formed on the intermediate layer 134. The layer stack 132 forms a Schottky barrier contact 130 on the second major surface 116 of the underlying SiC layer 112. To this end, a suitable metallic material, such as nickel (Ni), may be used to form a Schottky barrier for the band structure of the semiconductor material of the SiC layer 112. As shown in FIG. 1 , the intermediate layer 134 is disposed directly on the second major surface 116 of the SiC layer 112, and the second metal layer 136 is disposed directly on the intermediate layer 134.

[0031] To make the second metal layer 136 more resilient to higher temperatures, for example during annealing of the ohmic contact 120, the intermediate layer 134 comprises a suitable material, in particular a material from the carbon family (also called IUPAC group 14 or group IV), which includes elements with four valence electrons. In the described embodiment, carbon (C) is used for the intermediate layer 134. Alternatively, other carbon family materials with relatively high melting points, such as silicon (Si), germanium (Ge), or lead (Pb), may be used.

[0032] The presence of intermediate layer 134 prevents direct contact between the material of second metal layer 136 and layer 112. Thus, during high temperatures, such as annealing of ohmic contact 120, no chemical reaction occurs at the interface between SiC structure 110 and Schottky barrier contact 130 formed on its second surface 116.

[0033] FIG. 2 illustrates schematically the steps of a method for manufacturing a power conversion device such as the power semiconductor device 100 of FIG.

[0034] In a first step S1, a SiC layer 112 is epitaxially grown on a suitable substrate to form a SiC structure 110. In the described embodiment, the epitaxial SiC layer 112 is grown at 10 17 cm -3 Less than, or even 10 17 cm-3 For example, the epitaxial SiC layer 112 is doped with a suitable dopant at a relatively low concentration of less than 3·10 14 cm -3 ~5·10 14 cm -3 The thickness of the SiC layer 112 is determined by the desired function, voltage and / or current class of the semiconductor device 100, and may be in the range of a few microns to a tenth of a micron, e.g., 5 to 15 μm.

[0035] In a further step S2, an intermediate layer 134 is deposited on the SiC layer 112 to form one of the major surfaces of the SiC structure 110, for example the second surface 116 shown in Figure 1. The intermediate layer 134 is formed by depositing a chemical element from the carbon family.

[0036] In a further step S3, which may be performed at any stage of the manufacturing process after step S1 but before the annealing step S5, a conductive layer is deposited on the opposite side of the SiC structure 110. In the described example, a first metal layer 122 is deposited on the backside of the semiconductor device. For example, 100 nm of nickel may be deposited on the SiC substrate carrying the epitaxial SiC layer 112. Alternatively, a different method or material for forming the ohmic contact may be used. For example, instead of nickel, titanium aluminum or a titanium aluminum nickel alloy may be deposited, for example, by first depositing titanium, then aluminum, and optionally nickel, and then heating the resulting metal stack at a temperature of, for example, 1000°C to form the corresponding alloy. Similarly, silver paste may be used as an ohmic contact on the backside of the substrate.

[0037] In a further step S4, which may be performed at any stage in the manufacturing process after step S2 and before the annealing step S5, a metal suitable for forming the Schottky barrier contact 130 is deposited on the intermediate layer 134. For example, 10-100 nm of nickel may be deposited in a second metal layer 136 on the intermediate layer 134.

[0038] In a further step S5, at least a portion of the power semiconductor device 100 is annealed. The annealing step S5 may include sintering and / or rapid thermal annealing (RTA) performed at temperatures exceeding 600°C. Note that at this stage, both sides of the semiconductor device 100 are covered with the metal layers 122 and 136, respectively. Therefore, the first metal layer 122 and the second metal layer 136 deposited in steps S3 and S4 undergo the same heat treatment. For example, both surfaces may be sintered by RTA for 10 minutes in either a vacuum or an ambient atmosphere containing a protective gas such as argon. As a result, an ohmic contact 120 is formed on the backside of the semiconductor device 110. However, due to the presence of the intermediate layer 134, the layer stack 132 including the second metal layer 136 maintains its function as a Schottky barrier contact 130.

[0039] Figure 3 shows the electrical characteristics of power semiconductor device 100 during and after fabrication by the method of Figure 2. In particular, the solid line in Figure 3 shows the current-voltage (IV) characteristics of power semiconductor device 100 before annealing in step S5. The dashed and dotted lines show the IV characteristics of device 100 after annealing at 600°C and 1000°C for 10 minutes, respectively.

[0040] 3, there is no significant difference in the I-V curves of the unannealed structure and the semiconductor device 100 annealed at 600° C. That is, for the particular configuration of the nickel and carbon layer stack 132, annealing at a temperature of 600° C. has only a limited effect on both the formation of the ohmic contact 120 and the formation of the Schottky barrier contact 130.

[0041] As shown by the dotted curve in Figure 3, lower leakage voltage and forward voltage drop can be observed for power semiconductor device 100 annealed at 1000°C. Note that this effect has also been observed at lower annealing temperatures. For example, significantly lower leakage voltage and forward voltage drop were observed at annealing temperatures above 800°C for the described nickel / carbon layer stack 132 on the described SiC structure 110.

[0042] In the investigated power semiconductor device 100, the Schottky barrier height Φ B was about 1.5 eV (obtained by analyzing its CV characteristics, not shown). In contrast, the power semiconductor device 100 annealed at 600° C. had a Schottky barrier height Φ B The power semiconductor device 100 annealed at 1000° C. has a Schottky barrier height Φ B was 1.8 eV. That is, by also annealing the layer stack 132 including the intermediate layer 134 and the metal layer 136, the Schottky behavior of the resulting power semiconductor device 100 was improved compared to the non-annealed state.

[0043] In the following, the manufacturing processes of different power semiconductor devices including at least one Schottky barrier junction are described. In particular, Figures 4 to 6 describe the fabrication of a Schottky barrier diode, and Figures 7 to 10 describe the fabrication of a vertical power MOSFET.

[0044] 4 illustrates the initial stages of creating a Schottky barrier diode, starting with a SiC structure 410. The SiC structure 410 includes a substrate having an epilayer. In particular, a 4H—SiC n-type epilayer 412 is grown on a SiC substrate 414. In the described embodiment, the SiC substrate 414 is approximately 10 18 cm -3 In comparison, the n-type SiC epilayer 412 has a relatively high concentration of dopants such as nitrogen (N). 14 cm -3 ~10 16 cm -3 The n-type epitaxial layer 412 has a relatively low dopant concentration of 0.015 μm. The thickness of the n-type epitaxial layer 412 may be in the range of 5 to 15 μm.

[0045] FIG. 5 illustrates the formation of an edge termination area 416 in an n-type SiC epilayer 412. The edge termination area 416 is formed, for example, by ion implantation or plasma immersion ion implantation (PIII) of p-type dopants into the n-type epilayer 412. If desired, deep dopant implantation can be achieved, for example, using pre-amorphization. After the dopant implantation, a high-temperature annealing step for activation is performed. For example, activation may be performed at an access temperature of 1600°C. In the described embodiment, prior to annealing, the surface of the n-type epilayer 412 is protected, for example, by a graphite cap or a layer of diamond-like carbon (DLC), not shown in FIG. 5. After the high-temperature annealing, the graphite cap is removed, for example, by O2 ashing.

[0046] FIG. 6 illustrates the formation of different contacts on both major surfaces of a SiC structure 410. A metal layer 422 is deposited on a SiC substrate 414 by electron beam (e-beam) or thermal evaporation deposition. For example, a nickel layer approximately 100 nm thick may be deposited on the backside of the SiC structure 410. On the opposite side of the SiC structure 410, i.e., on the surface of the SiC epilayer 412, a layer stack 432 is formed, including an intermediate layer 434 and an additional metal layer 436. For example, a 10-100 nm carbon intermediate layer 434 may be deposited first, followed by a 50-100 nm nickel layer. As shown in FIG. 6, an edge termination area 416 can limit the horizontal extension of layers 434 and 436 to a central region of the epilayer 412.

[0047] Both metal layers 422 and 436 are then annealed using rapid thermal processing (RTP). For example, the SiC structure 410 with all deposited layers may be treated at temperatures above 800°C for 1-10 minutes or more. As a result, an ohmic contact 420 is formed on the backside of the substrate 414. Conversely, a Schottky contact 430 of the Schottky barrier diode 400 is formed or improved on the n-type SiC epilayer 412.

[0048] 7 shows a SiC structure 510 for forming a vertical power MOSFET. The SiC structure 510 includes a SiC substrate 514 and an n-type SiC epilayer 512 similar to those described above with respect to FIG.

[0049] 8 shows the SiC structure 510 after forming heavily doped wells in the source area 540 of the MOSFET. In particular, two p+ wells 542 are formed in the n-type SiC epilayer 512. The p+ wells 542 are 10 16 cm -3 Within each p+ well 542, an n+ well 544 is formed, for example, by ion implantation or plasma immersion ion implantation. The n+ well 544 may also have a doping concentration at the access of, for example, 10 16cm -3 In the described embodiment, the surface of the SiC structure 510 is then protected, for example, by a graphite cap or a DLC layer, after which the source structure 540 formed by wells 542 and 544 is activated at high temperature. After activation, the graphite cap is removed by plasma etching.

[0050] 9 illustrates the formation of a gate structure 550. In particular, a metal gate electrode 552 may be formed between layers of dielectric material to form an interlayer dielectric 554 that surrounds the gate electrode 552 on all sides.

[0051] FIG. 10 illustrates the formation of ohmic contacts 520 and Schottky contacts 530 on a SiC structure 510. As discussed above with respect to FIG. 6, the ohmic contacts 520 may be formed by depositing a suitable ohmic contact metal material, such as nickel (Ni), to form a metal layer 522 on the backside of the substrate 514. The Schottky barrier contact 530 may be formed by a layer stack 532 including a suitable Schottky metal layer 536, such as nickel (Ni), gold (Au), molybdenum (Mo), titanium (Ti), or platinum (Pt), on a carbon-group interlayer 534. In contrast to the situation shown in FIG. 6, in which the Schottky barrier contact 430 is formed in the central region of the SiC structure 410 between two edge termination areas 416, in the embodiment shown in FIG. 10, two Schottky contacts 530 are formed adjacent to a p+ well 542 outside the source area 540. The Schottky contacts 530 and the ohmic contacts 520 are annealed together in a single processing step at temperatures exceeding 600° C. The ohmic contact 520 forms the drain terminal 560 of the completed vertical power MOSFET 500 .

[0052] The power MOSFET 500 shown in FIG. 10 has an integrated Schottky contact 530, which can be used in many applications. This has the advantage that no additional device is required to act as a freewheeling diode. Due to the relatively large bandgap, the turn-on voltage of the body diode exceeds 2.5 V. Integrating the Schottky diode into the MOSFET 500 is one option for reducing the turn-on voltage to less than 1 V. In contrast to conventional manufacturing methods, the thermal budget for forming the ohmic contact 520 is similar to that for forming the Schottky contact 530, simplifying the integration of the Schottky contact 530 into the power MOSFET 500. Forming the ohmic contact 520 and the Schottky contact 530 in the same step and at the same temperature significantly reduces the integration effort.

[0053] It also allows for other high temperature steps to be performed after the contact formation shown in FIG. 8, such as further ohmic contact formation, polysilicon activation, oxide hardback, etc.

[0054] The embodiments shown in Figures 1-10 above represent exemplary embodiments of improved power semiconductor devices and steps for their fabrication. As such, they do not constitute an exhaustive list of all embodiments of improved power semiconductor devices and fabrication methods. Actual devices and fabrication methods may differ from the illustrated embodiments, for example, with respect to materials, processing parameters, and processing steps. [Explanation of symbols]

[0055] Reference sign 100 Power Semiconductor Devices 110 SiC structure 112 SiC layer 114 First principal surface 116 Second main surface 120 Ohmic Contact 122 First Metal Layer 130 Schottky barrier contact 132 layer stack 134 Middle Class 136 Second Metal Layer 400 Schottky barrier diode 410 SiC structure 412 SiC epilayer 414 SiC substrate 416 Edge Termination Area 420 Ohmic Contact 422 First Metal Layer 430 Schottky barrier contact 432 layer stack 434 Middle Class 436 Second Metal Layer 500 Power MOSFET 510 SiC structure 512 SiC epilayer 514 SiC substrate 520 Ohmic Contact 522 First Metal Layer 530 Schottky Contact 532 layer stack 534 Middle Class 536 Second Metal Layer 540 Source Area 542 p+ well 544 n+ well 550 Gate Structure 552 gate electrode 554 Interlayer Dielectric 560 Drain terminal

Claims

1. A power semiconductor device (100), a silicon carbide (SiC) structure (110, 410, 510) comprising a silicon carbide (SiC) epilayer (412, 512), the SiC structure having a first major surface (114) and an opposite second major surface (116) formed by the SiC epilayer (412, 512); at least one ohmic contact (120, 420, 520) formed on the first major surface (114) of the SiC structure (110, 410, 510); At least one Schottky barrier contact (130, 430, 530) formed on the second major surface (116) of the SiC structure (110, 410, 510), the at least one Schottky barrier contact (130, 430, 530) comprising a metal layer (136, 436, 536) and a carbon-group intermediate layer (134, 434, 534), the carbon-group intermediate layer (134, 434, 534) being in contact with the metal layer (136, 436, 536). and the second major surface (116) of the SiC structure (110, 410, 510), the metal layer (136, 436, 536) having a thickness in the range of 10 to 100 nm and including one of carbon, germanium, or lead deposited directly on the SiC epilayer (412, 512), the metal layer (136, 436, 536) being deposited directly on the carbon-group intermediate layer (134, 434, 534); and A power semiconductor device (100) comprising:

2. 2. The power semiconductor device of claim 1, wherein the SiC structure further comprises a SiC substrate, and the at least one ohmic contact is formed on a surface of the SiC substrate.

3. The SiC epitaxial layers (412, 512) are 10 １４ cm －３ ~10 １６ cm －３ and the SiC substrate (414, 514) has a first dopant concentration of 10 １８ cm －３ The power semiconductor device (100) of claim 2, having a second dopant concentration of

4. The SiC epitaxial layers (112, 412, 512) are 10 １７ cm －３ The power semiconductor device (100) of claim 1 or 2, wherein the SiC layer is a semiconducting SiC layer having a dopant concentration of less than 0.05 wt %.

5. 4. The power semiconductor device (100) of claim 1, further comprising at least one edge termination area (416) in the SiC epilayer (412), the at least one edge termination area (416) limiting the horizontal extension of the carbon-group intermediate layer (434) and the metal layer (436) to a central region of the epilayer (412).

6. The power semiconductor device (100) of any one of claims 1 to 3, wherein the metal layer (136, 436, 536) of the at least one Schottky barrier contact (130, 430, 530) comprises at least one of nickel, gold, molybdenum, titanium, or platinum.

7. The at least one ohmic contact (120, 420, 520) is Nickel layer, a titanium aluminum Ti / Al alloy layer, or Titanium aluminum nickel Ti / Al / Ni alloy layer The power semiconductor device (100) according to any one of claims 1 to 3, comprising one of:

8. A Schottky barrier diode (400), A power semiconductor device (100) according to any one of claims 1 to 3; an anode terminal connected to at least one Schottky barrier contact (430); a cathode terminal connected to at least one ohmic contact (420); A Schottky barrier diode (400).

9. A vertical field effect transistor, A power semiconductor device (100) according to any one of claims 1 to 3; a source terminal connected to at least one Schottky barrier contact (530); a drain terminal (560) connected to at least one ohmic contact (520); a gate terminal connected to an insulated gate electrode (552) disposed on the second major surface (116) of the SiC structure (510); A vertical field effect transistor comprising:

10. 10. The vertical field effect transistor of claim 9, further comprising at least two heavily doped wells (542, 544) arranged in the SiC epilayer (512), the insulated gate electrode (552) being arranged in an area between the at least two heavily doped wells (542, 544), and two Schottky barrier contacts (530) formed adjacent to the at least two heavily doped wells (542, 544).

11. 1. A method for manufacturing a power semiconductor device, comprising: forming (S1) a silicon carbide (SiC) layer (112, 412, 512) of a silicon carbide (SiC) structure (110, 410, 510); depositing (S2) a carbon-group intermediate layer (134, 434, 534) on the SiC layer (112, 412, 512), the carbon-group intermediate layer (134, 434, 534) having a thickness in the range of 10 to 100 nm and including one of carbon, germanium, or lead; depositing (S3) a first metal layer (122, 422, 522) on the backside of the SiC structure (110, 410, 510); depositing (S4) a second metal layer (136, 436, 536) of a Schottky barrier contact (130, 430, 530) on the carbon-group intermediate layer (134); After depositing the first metal layer (122, 422, 522) and the second metal layer (136, 436, 536), annealing (S5) at least the first metal layer (122, 422, 522) at an annealing temperature to form at least one ohmic contact (120); A method comprising:

12. 12. The method of claim 11, wherein the step (S1) of forming a SiC layer (112, 412, 512) of the SiC structure (110, 410, 510) comprises epitaxially growing a SiC epilayer (412, 512) on a substrate (414, 514).

13. The method of claim 12, wherein the first metal layer (122, 422, 522) is annealed at an annealing temperature of 600 degrees Celsius or greater.

14. 14. The method of claim 11, wherein in the annealing step, the carbon-group intermediate layer (134, 434, 534), the first metal layer (122, 422, 522), and the second metal layer (136, 436, 536) are annealed together, such that after the annealing, the at least one Schottky barrier contact (130, 430, 530) is formed on a front side of the SiC structure (110, 410, 510) and the at least one ohmic contact (120, 420, 520) is formed on the back side of the SiC structure (110, 410, 510).

15. 14. The method of any one of claims 11 to 13, wherein the carbon-group intermediate layer (134, 434, 534), the first metal layer (122, 422, 522) and / or the second metal layer (136, 436, 536) are deposited using one of electron beam deposition or thermal evaporation deposition.

16. Prior to the step of depositing a carbon-based intermediate layer (534) on the SiC layer (512), forming at least one heavily doped first well of a first conductivity type in the SiC layer (512); forming at least one heavily doped second well of a second conductivity type within the at least one heavily doped first well; further comprising the carbon-group intermediate layer (136) is formed adjacent to the at least one heavily doped first well; The method according to any one of claims 11 to 13, wherein the SiC layer (112) is a SiC layer of the second conductivity type.

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