nitride semiconductor devices

Abstract

This nitride semiconductor device (100) is provided with: a substrate (1); and a first nitride semiconductor layer (3) which is provided with a recess part (6), a second nitride semiconductor layer (4) which is provided in a region other than the recess part, while having a large band gap in comparison to the first nitride semiconductor layer, and a third nitride semiconductor layer (8) which comprises the inner wall of the recess part and covers the first and second nitride semiconductor layers (3, 4), while having a large band gap in comparison to the first nitride semiconductor layer (3), said first to third nitride semiconductor layers being sequentially provided on the substrate (1). With respect to this nitride semiconductor device (100), the contact angle (13) which is in contact with a side wall (7) of the recess part and the interface between the first nitride semiconductor layer (3) and the second nitride semiconductor layer (4) is not less than 140° but less than 180°.

Description

[Technical Field]

[0001] The present disclosure relates to nitride semiconductor devices. [Background technology]

[0002] Group III nitride semiconductors have a high breakdown voltage due to their wide band gap. Furthermore, heterostructures such as AlGaN / GaN can be easily formed. The difference in the band gap and the piezoelectric charge generated by the difference in lattice constant between AlGaN and GaN can generate a high-mobility, high-concentration electron channel (two-dimensional electron gas) on the GaN layer side of the AlGaN / GaN interface. Controlling this two-dimensional electron gas makes it possible to form high electron mobility transistors (HEMTs). Due to their high breakdown voltage, high speed, and large current characteristics, Group III nitride semiconductors are being applied to electronic devices such as power field-effect transistors (FETs) and diodes.

[0003] For example, Patent Document 1 discloses a semiconductor device having a semiconductor laminate structure in which a buffer layer, a channel layer made of GaN, and a low-C barrier layer made of AlGaN are epitaxially grown in this order on an Si substrate. A recess is formed in the low-C barrier layer, and a high-C barrier layer is provided so as to cover the recess and the low-C barrier layer. Furthermore, a gate layer is formed on the recess, and a source electrode and a drain electrode are formed on both sides of the gate layer, spaced apart from the gate layer, on the barrier layer.

[0004] The semiconductor device disclosed in Patent Document 1 is a field-effect transistor in which the drain current flowing between the source electrode and the drain electrode via the two-dimensional electron gas layer can be controlled by the voltage applied to the gate layer. The length of the opening of the recess in the direction of alignment of the source electrode and the drain electrode is longer than the length of the bottom of the recess in the direction of alignment. In other words, the recess has a tapered sidewall. Tapering means that the recess sidewall is inclined at an angle of 90° or less from the gate layer side toward the outside with respect to the two-dimensional electron gas layer.

[0005] According to the semiconductor device disclosed in Patent Document 1, by tapering the sidewalls of the recess portion, it is possible to alleviate the electric field concentration at the recess end, which is the area where the electric field is concentrated second most after the gate layer end. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 6555542 Summary of the Invention [Problem to be solved by the invention]

[0007] It is believed that the on-resistance of the group III nitride semiconductor device disclosed in Patent Document 1 can be reduced to some extent by using a recess structure. However, as a power semiconductor, a further reduction in on-resistance is required.

[0008] Therefore, a main object of the present disclosure is to provide a nitride semiconductor device that can further reduce the on-resistance. [Means for solving the problem]

[0009] A nitride semiconductor device according to one embodiment of the present disclosure comprises: a substrate; a first nitride semiconductor layer sequentially disposed on the substrate and having a recessed portion formed therein; a second nitride semiconductor layer having a larger band gap than the first nitride semiconductor layer and disposed in an area other than the recessed portion; and a third nitride semiconductor layer having a larger band gap than the first nitride semiconductor layer, including an inner wall of the recessed portion, and covering the first and second nitride semiconductor layers, wherein a contact angle between a sidewall of the recessed portion and an interface between the first nitride semiconductor layer and the second nitride semiconductor layer is equal to or greater than 140° and less than 180°. [Effects of the Invention]

[0010] According to the nitride semiconductor device according to the present disclosure, the on-resistance can be further reduced. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a cross-sectional view showing a cross-sectional structure of a nitride semiconductor device according to an embodiment and first and second modifications. [Figure 2] FIG. 2 is a diagram showing characteristics of the nitride semiconductor device according to the embodiment. [Figure 3] FIG. 3 is a diagram showing characteristics of the nitride semiconductor device according to the embodiment. [Figure 4] FIG. 4 is a diagram showing characteristics of the nitride semiconductor device according to the second modification of the embodiment. [Figure 5] FIG. 5 is a diagram showing characteristics of the nitride semiconductor device according to the second modification of the embodiment. [Figure 6] FIG. 6 is a cross-sectional view showing a cross-sectional structure of nitride semiconductor devices according to third, fourth, fifth, eighth, ninth and tenth modifications of the embodiment. [Figure 7] FIG. 7 is a cross-sectional view showing a cross-sectional structure of nitride semiconductor devices according to sixth and seventh modifications of the embodiment. [Figure 8] FIG. 8 is a cross-sectional view showing a cross-sectional structure of a nitride semiconductor device according to an eleventh modification of the embodiment. [Figure 9A] FIG. 9A is a cross-sectional view showing a cross-sectional structure in one step of a method for manufacturing a nitride semiconductor device according to an embodiment. [Figure 9B] FIG. 9B is a cross-sectional view showing a cross-sectional structure in a step of the method for manufacturing the nitride semiconductor device according to the embodiment. [Figure 9C] FIG. 9C is a cross-sectional view showing a cross-sectional structure in a step of the method for manufacturing a nitride semiconductor device according to the embodiment. [Figure 9D] FIG. 9D is a cross-sectional view showing a cross-sectional structure in a step of the method for manufacturing a nitride semiconductor device according to the embodiment. [Figure 9E] FIG. 9E is a cross-sectional view showing a cross-sectional structure in a step of a method for manufacturing a nitride semiconductor device according to the embodiment. [Figure 10] FIG. 10 is a plan view showing the planar structure of the nitride semiconductor device according to the embodiment. [Figure 11] FIG. 11 is a plan view showing the planar structure of the nitride semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] (Summary of the Disclosure) A nitride semiconductor device according to one embodiment of the present disclosure comprises: a substrate; a first nitride semiconductor layer sequentially disposed on the substrate and having a recessed portion formed therein; a second nitride semiconductor layer having a larger band gap than the first nitride semiconductor layer and disposed in an area other than the recessed portion; and a third nitride semiconductor layer having a larger band gap than the first nitride semiconductor layer, including an inner wall of the recessed portion, and covering the first and second nitride semiconductor layers, wherein a contact angle between a sidewall of the recessed portion and an interface between the first nitride semiconductor layer and the second nitride semiconductor layer is equal to or greater than 140° and less than 180°.

[0013] This reduces the bending of the two-dimensional electron gas near the contact angle, allowing for smoother electron flow. It also increases the concentration of the two-dimensional electron gas near the contact angle, reducing the on-resistance and increasing the maximum drain current.

[0014] Furthermore, for example, the contact angles at which each of the side walls on both sides of the recess contacts the interface between the first nitride semiconductor layer and the second nitride semiconductor layer may both be equal to or greater than 140° and less than 180°.

[0015] This allows the electrons to flow smoothly near the contact angles on both sides of the recess and increases the concentration of the two-dimensional electron gas, thereby further reducing the on-resistance and increasing the maximum drain current.

[0016] Furthermore, for example, the average of the contact angles between each of the sidewalls on both sides of the recess and the interface between the first nitride semiconductor layer and the second nitride semiconductor layer may be equal to or greater than 145° and less than 180°.

[0017] This allows the electrons to flow smoothly near the contact angles on both sides of the recess and increases the concentration of the two-dimensional electron gas, thereby further reducing the on-resistance and increasing the maximum drain current.

[0018] Furthermore, for example, the contact angle may be larger than a taper angle, which is an angle at which a sidewall of the second nitride semiconductor layer facing the recessed portion meets an upper surface of the second nitride semiconductor layer.

[0019] This makes it possible to lower the on-resistance, increase the maximum drain current, and realize faster operation of the nitride semiconductor device.

[0020] Furthermore, for example, a taper angle, which is the angle at which the sidewall of the second nitride semiconductor layer facing the recessed portion meets the upper surface of the second nitride semiconductor layer, may be equal to or greater than 120° and less than 180°.

[0021] This allows the film thickness and / or composition of the third nitride semiconductor layer to be uniform, thereby further reducing the on-resistance and further increasing the maximum drain current.

[0022] Furthermore, for example, the difference between the contact angle and a taper angle, which is the angle at which the sidewall of the second nitride semiconductor layer facing the recess portion meets the upper surface of the second nitride semiconductor layer, may be within a range of ±20°.

[0023] This makes it possible to reduce the on-resistance, increase the maximum drain current, and increase the operating speed.

[0024] Furthermore, for example, the inclination of the tangent of the sidewall of the recessed portion and the sidewall of the second nitride semiconductor layer facing the recessed portion may be fixed to one value.

[0025] This allows the film thickness and / or composition of the third nitride semiconductor layer to be uniform, thereby further reducing the on-resistance and further increasing the maximum drain current.

[0026] Furthermore, for example, the angle formed between the sidewall of the recessed portion and the sidewall of the second nitride semiconductor layer facing the recessed portion may be within a range of 180°±30°.

[0027] This allows the film thickness and / or composition of the third nitride semiconductor layer to be uniform, thereby further reducing the on-resistance and further increasing the maximum drain current.

[0028] Furthermore, for example, the thickness of the third nitride semiconductor layer along the sidewall of the second nitride semiconductor layer may be 50% or more in the vertical direction compared to the thickness of the third nitride semiconductor layer along the bottom of the recess.

[0029] This allows the film thickness and / or composition of the third nitride semiconductor layer to be uniform, thereby further reducing the on-resistance and further increasing the maximum drain current.

[0030] Furthermore, for example, the third nitride semiconductor layer may contain Al, and the Al composition of the third nitride semiconductor layer may be 25% or less.

[0031] This makes it possible to suppress the leakage current.

[0032] Furthermore, for example, the third nitride semiconductor layer may contain Al, and the Al composition of the third nitride semiconductor layer may be within a variation range of ±5%.

[0033] This allows the composition of the third nitride semiconductor layer to be uniform, thereby further reducing the on-resistance and further increasing the maximum drain current.

[0034] Furthermore, for example, a nitride semiconductor device according to one aspect of the present disclosure may further include a source electrode and a drain electrode arranged at a distance from the recess portion so as to sandwich the recess portion therebetween, and the contact angle on the drain electrode side may be larger than the contact angle on the source electrode side.

[0035] By increasing the contact angle on the drain electrode side, the electric field concentration on the drain electrode side can be alleviated, reducing the gate leakage current.In addition, by decreasing the contact angle on the source electrode side, the gate-source capacitance can be reduced, thereby realizing high-speed operation of the nitride semiconductor device.

[0036] Hereinafter, nitride semiconductor devices according to embodiments will be specifically described with reference to the drawings.

[0037] It should be noted that the embodiments described below each illustrate a specific example of the present disclosure. The numerical values, shapes, materials, components, arrangement positions and connection forms of the components shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components that are not recited in independent claims are described as optional components.

[0038] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0039] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel, orthogonal, or coincident, terms indicating the shape of elements, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0040] Furthermore, in this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "above" and "below" are applied not only to a case where two components are arranged with a gap between them and another component exists between them, but also to a case where two components are arranged closely together and the two components are in contact with each other.

[0041] Specifically, the direction in which each semiconductor layer, gate electrode, drain electrode, source electrode, etc. are located relative to the substrate is referred to as "upper." In addition, the main surface of each semiconductor layer and each electrode facing the substrate may be referred to as the "lower surface," and the main surface on the opposite side may be referred to as the "upper surface."

[0042] In this specification, unless otherwise specified, the term "plan view" means viewing the main surface of the substrate from the front, i.e., viewing the main surface of the substrate from a direction perpendicular to the main surface. The direction perpendicular to the main surface of the substrate is the thickness direction of the substrate, which is the stacking direction of each layer.

[0043] In this specification, the term "cross-sectional view" means a front view of a predetermined cross section. Unless otherwise specified, the predetermined cross section is a cross section of the nitride semiconductor device taken along a plane that is perpendicular to the main surface of the substrate and parallel to the direction in which the source electrode, gate electrode, and drain electrode are arranged.

[0044] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0045] (Embodiment) In the nitride semiconductor device according to the embodiment, the contact angle between the sidewall of the recess and the interface between the channel layer and the barrier layer is 140° or more and less than 180°. First, the configuration of the nitride semiconductor device according to the embodiment will be described below with reference to Fig. 1. Fig. 1 is a cross-sectional view showing the cross-sectional structure of a nitride semiconductor device 100 according to the present embodiment.

[0046] The nitride semiconductor device 100 shown in FIG. 1 has an appropriate buffer layer 2 (e.g., a single layer or multiple layers of a Group III nitride semiconductor such as GaN, AlGaN, AlN, InGaN, InN, or AlInGaN) on an appropriate Si substrate 1 (other substrates include, for example, a sapphire, SiC, GaN, or AlN substrate). The nitride semiconductor device 100 has a channel layer 3 made of GaN (other substrates include, for example, a Group III nitride semiconductor such as InGaN, InN, AlGaN, or AlInGaN) on the buffer layer 2, and a first barrier layer 4 made of AlGaN (other substrates include, for example, a Group III nitride semiconductor such as GaN, InGaN, AlGaN, AlN, or AlInGaN) on the channel layer 3. The channel layer 3 is an example of a first nitride semiconductor layer. The first barrier layer 4 is an example of a second nitride semiconductor layer. The first barrier layer 4 has a larger band gap than the channel layer 3. If the first barrier layer 4 is made of AlGaN and the channel layer 3 is made of GaN, a highly concentrated two-dimensional electron gas layer 5 is generated on the channel layer 3 side near the interface between the first barrier layer 4 and the channel layer 3 due to the difference in band gap and the piezoelectric charges generated by the difference in lattice constant between AlGaN and GaN.

[0047] The channel layer 3 and the first barrier layer 4 are provided with a recess 6 that penetrates the first barrier layer 4 from the surface side and reaches the channel layer 3. The nitride semiconductor device 100 has a second barrier layer 8 made of AlGaN (other materials include, for example, Group III nitride semiconductors such as GaN, InGaN, AlGaN, AlN, and AlInGaN) that is formed to cover the recess 6, its sidewalls 7, and the outermost surface of the first barrier layer 4. The sidewalls 7 of the recess are sidewalls (end faces) of the first barrier layer 4 that face the recess 6. The second barrier layer 8 is an example of a third nitride semiconductor layer, at least a portion of which is provided along the inner surface (bottom and sidewalls) of the recess 6. The second barrier layer 8 also has a larger band gap than the channel layer 3. If the second barrier layer 8 is made of AlGaN and the channel layer 3 is made of GaN, a high-concentration two-dimensional electron gas layer (not shown when the nitride semiconductor device is on) is generated on the channel layer 3 side near the interface of the channel layer 3 with the second barrier layer 8 due to the difference in band gap and the piezoelectric charges generated by the difference in lattice constant between AlGaN and GaN.

[0048] The nitride semiconductor device 100 has a selectively formed gate layer 11 (also known as p-GaN, p-InGaN, p-InN, p-AlGaN, p-AlInGaN, or other group III nitride semiconductors) above the recessed portion 6. The gate layer 11 may be p-GaN containing Mg, i-GaN (insulated-GaN) containing C or other impurities (also known as i-GaN, i-InGaN, i-InN, i-AlGaN, i-AlInGaN, or other group III nitride semiconductors), or n-GaN containing n-type impurities such as Si (also known as n-InGaN, n-AlGaN, n-InN, n-AlInGaN, or other group III nitride semiconductors). It is generally desirable for the gate layer 11 to cover a portion where the total thickness of the first barrier layer 4 and the second barrier layer 8 is large, at an end of the gate layer 11 facing the drain electrode 10, where a high electric field is formed within the nitride semiconductor device 100. That is, the gate layer 11 may cover at least the recessed portion 6 on the drain electrode 10 side, or may cover the entire opening of the recessed portion 6 .

[0049] The nitride semiconductor device 100 has a source electrode 9 and a drain electrode 10 on the second barrier layer 8, spaced apart on the left and right of the gate layer 11. The source electrode 9 and the drain electrode 10 are each made of one or a combination of two or more metals such as Ti, Al, Mo, and Hf, which are in ohmic contact with any of the two-dimensional electron gas layer 5, the first barrier layer 4, the second barrier layer 8, and the channel layer 3, and are electrically connected to the two-dimensional electron gas layer 5. For example, the source electrode 9 and the drain electrode 10 may be located on the surface of the second barrier layer 8 or the first barrier layer 4, or may be in contact with any of the two-dimensional electron gas layer 5, the first barrier layer 4, and the channel layer 3 using a known ohmic recess technique (not shown).

[0050] The nitride semiconductor device 100 has a gate electrode 12 on a gate layer 11. The gate electrode 12 may be on the gate layer 11 as shown in FIG. 1, or may have a so-called MES structure in direct contact with the second barrier layer 8 when the gate layer 11 is not present (not shown). In the case of the MES structure, the gate electrode 12 is an electrode in Schottky contact with the second barrier layer 8 above the recessed portion 6. Alternatively, instead of the gate layer 11 below the gate electrode 12, a so-called MIS structure or MOS structure in which an insulating film such as SiNx, SiOx, or AlOx is sandwiched may be used (not shown).

[0051] From the viewpoint of safety, normally-off operation is desirable for power semiconductors. When the gate layer 11 is a p-type group III nitride semiconductor, a pn junction is formed in the vicinity of the recess portion 6 directly below the gate layer 11. When no gate voltage is applied to the gate electrode 12, the two-dimensional electron gas is depleted, resulting in a so-called normally-off state. The thickness of the second barrier layer 8 varies depending on the threshold voltage (Vth) to be set. In this case, when the second barrier layer 8 is made of AlGaN, the thickness of the second barrier layer 8 in a portion directly below the gate layer 11 must be within the range of 10 nm to 25 nm, preferably approximately 20 nm, when the Al composition of the AlGaN in the second barrier layer 8 is 20%. In this case, when the gate layer 11 is made of p-GaN, the thickness of the gate layer 11 must be within the range of 50 nm to 500 nm, preferably approximately 200 nm. When the p-type impurity in the gate layer 11 is Mg, the doping concentration must be 1E19 cm -3 Over 10E19cm -3 Within the following range, preferably 5E19cm -3 It is sufficient if Mg is 5E19cm -3 The carrier concentration of p-GaN doped to a certain extent is substantially 1E17 cm because the activation rate of Mg is very low, at less than a few percent. -3 More than 5E17cm -3 1, the area directly below the recessed portion 6 is depleted, no two-dimensional electron gas exists, and the nitride semiconductor device 100 is in a normally-off state.

[0052] The gate electrode 12 may be an electrode made of one or a combination of two or more metals such as Ti, Ni, Pd, Pt, Au, W, WSi, Ta, TiN, Al, Mo, Hf, and Zr. When the gate layer 11 is a p-type Group III nitride semiconductor, the gate electrode 12 may be in ohmic contact or Schottky contact with the gate layer 11, but ohmic contact provides higher reliability of the gate electrode. For this reason, it is desirable to use, as the gate electrode 12, an electrode made of one or a combination of two or more metals with low contact resistance such as Ni, Pt, Pd, Au, Ti, Cr, In, Sn, and Al.

[0053] In the nitride semiconductor device 100 according to the present embodiment, a contact angle 13 between the sidewall of the recess and the interface between the first barrier layer 4 and the channel layer 3 is equal to or greater than 140° and less than 180°.

[0054] [Operation] Next, the operation of the nitride semiconductor device 100 according to this embodiment will be described.

[0055] When the nitride semiconductor device 100 is a normally-off FET using p-GaN for the gate layer 11, when the voltage applied to the gate electrode 12 is 0 V, a depletion layer due to the pn junction expands directly below the gate layer 11, no two-dimensional electron gas exists, and the nitride semiconductor device 100 is in an off state ( FIG. 1 ). When a positive gate voltage is applied to the gate electrode 12 with the source electrode 9 grounded and a positive voltage applied to the drain electrode 10, the depletion layer due to the pn junction directly below the gate layer 11 shrinks, and when the gate voltage exceeds the threshold voltage (Vth), a source-drain current begins to flow, and the nitride semiconductor device 100 enters an on state (not shown). In other words, the source-drain current can be controlled by the voltage applied to the gate electrode 12.

[0056] [Effects, etc.] Next, the effects of the nitride semiconductor device 100 according to this embodiment will be described. According to this embodiment, it is possible to improve the concentration of two-dimensional electron gas immediately below the sidewall of the recess portion 6, significantly reduce the on-resistance, and significantly increase the maximum drain current.

[0057] Figure 2 shows a correlation diagram between the smaller of the contact angles 13 on the left and right sides of the recess 6 on the source electrode 9 side and the drain electrode 10 side, and the on-resistance normalized with a threshold voltage of 1.2 V. As shown in Figure 2, the smaller contact angle 13 increases, and it can be seen that the on-resistance is significantly reduced at a boundary of 140°.

[0058] 3 shows the correlation between the smaller contact angle 13 of the left and right contact angles 13 on the source electrode 9 side and the drain electrode 10 side of the recess 6 and the normalized maximum drain current. As shown in FIG. 3, the smaller contact angle 13 increases, and it can be seen that the maximum drain current increases significantly at a boundary of 140°.

[0059] These characteristic improvements are due to the fact that the larger contact angle 13 reduces the bending of the two-dimensional electron gas layer 5 in the vicinity of the contact angle 13 of the recessed portion 6, allowing electrons to flow more smoothly, and also because the concentration of the two-dimensional electron gas in the vicinity of the contact angle 13 is improved. Note that, since the recessed portion 6 penetrates the first barrier layer 4 from the surface side to reach the channel layer 3, the contact angle 13 is at most less than 180°.

[0060] [First Modification] Next, a nitride semiconductor device according to a first modification of the embodiment will be described. The structure of the nitride semiconductor device according to this modification is almost the same as that of the embodiment, and will be described with reference to FIG.

[0061] In the first modified example of the embodiment, the left and right contact angles 13 on the source electrode 9 side and the drain electrode 10 side of the recessed portion 6 are both 140° or more and less than 180°. Although this modified example is described using a Group III nitride semiconductor, the present disclosure is not limited thereto. Furthermore, the structure of the nitride semiconductor device according to this modified example shows a minimum configuration, and is not limited thereto.

[0062] By using this modified example, in addition to the effects of the embodiment, it is possible to further improve the concentration of two-dimensional electron gas directly below the sidewall of the recess portion 6, reduce the on-resistance, and increase the maximum drain current.

[0063] The on-resistance and maximum drain current depend on the total resistance between the source electrode 9 and the drain electrode 10. In the nitride semiconductor device according to this modification, the left and right contact angles 13 on the source electrode 9 side and the drain electrode 10 side of the recessed portion 6 in the embodiment shown in FIG. 1 are both 140° or more and less than 180°. This makes it possible to minimize the resistance at both contact angles 13, which in turn makes it possible to reduce the on-resistance and further increase the maximum drain current.

[0064] [Second Modification] Next, a nitride semiconductor device according to a second modification of the embodiment will be described. The structure of the nitride semiconductor device according to this modification is almost the same as that of the embodiment, and will be described with reference to FIG.

[0065] In the second modified example of the embodiment, the average of the left and right contact angles 13 on the source electrode 9 side and the drain electrode 10 side of the recess portion 6 is equal to or greater than 145° and less than 180°. Although this modified example is described using a Group III nitride semiconductor, the present disclosure is not limited thereto. Furthermore, the structure of the nitride semiconductor device according to this modified example shows a minimum configuration, and is not limited thereto.

[0066] By using this modification, in addition to the effects of the embodiment or the first modification, it is possible to further improve the concentration of two-dimensional electron gas directly below the sidewall of the recess portion 6, reduce the on-resistance, and increase the maximum drain current.

[0067] Fig. 4 shows a correlation diagram between the average of the left and right contact angles 13 on the source electrode 9 side and the drain electrode 10 side of the recess portion 6 and the on-resistance normalized with a threshold voltage of 1.2 V. As shown in Fig. 4, the average contact angle 13 increases, and it can be seen that the on-resistance is significantly reduced at a boundary of 145°.

[0068] 5 shows a correlation diagram between the average contact angle 13 on the left and right sides of the recess 6 on the source electrode 9 side and the drain electrode 10 side, and the normalized maximum drain current. As shown in FIG. 5, similar to the on-resistance, the average contact angle 13 increases, and the maximum drain current increases significantly at a boundary of 145°.

[0069] These characteristic improvements are due to the fact that the average of the left and right contact angles 13 exceeds 145°, which reduces the curvature of the two-dimensional electron gas layer 5 near the contact angle 13 of the recessed portion 6, allowing electrons to flow more smoothly, and also because the concentration of the two-dimensional electron gas near the contact angle 13 is improved. This makes it possible to reduce the on-resistance and further increase the maximum drain current. Note that, because the recessed portion 6 penetrates the first barrier layer 4 from the surface side to reach the channel layer 3, the contact angle 13 is at most less than 180°.

[0070] [Third Modification] Next, a nitride semiconductor device according to a third modification of the embodiment will be described with reference to Fig. 6. Fig. 6 is a diagram showing a cross-sectional structure of a nitride semiconductor device 101 according to the third modification of the embodiment. As shown in Fig. 6, in the nitride semiconductor device 101 according to this modification, a contact angle 13 between a sidewall 7 of the recessed portion and the interface between the channel layer 3 and the first barrier layer 4 is larger than a taper angle 14, which is the angle at which the sidewall 7 of the recessed portion meets the outermost surface of the second barrier layer 8.

[0071] In the third modification of the embodiment, contact angle 13 between sidewall 7 of the recessed portion and the interface between channel layer 3 and first barrier layer 4 is larger than taper angle 14, which is the angle at which sidewall 7 of the recessed portion meets the outermost surface of second barrier layer 8. Taper angle 14 is defined as the angle at the outermost surface of second barrier layer 8, where sidewall 7 of the recessed portion meets the outermost surface of second barrier layer 8. However, if sidewall 7 of the recessed portion is not straight but curved or curved in the concave / convex direction, taper angle 14 is defined as the angle between an extension of the tangent to the steepest portion of sidewall 7 of the recessed portion and an extension of the outermost surface of second barrier layer 8. Although this modification is described using a Group III nitride semiconductor, the present disclosure is not limited thereto. Furthermore, the structure of nitride semiconductor device 101 according to this modification represents a minimum configuration and is not limited thereto.

[0072] In addition to the effects of the embodiment or the first or second modification, this modification can minimize the horizontal length of the gate layer 11, i.e., the length of the gate layer 11 from the direction of the source electrode 9 toward the direction of the drain electrode 10. This reduces the gate capacitance (gate-source capacitance and gate-drain capacitance), thereby enabling the nitride semiconductor device 101 to operate at a higher speed.

[0073] In general, it is desirable that the gate layer 11 covers the portion where the total film thickness of the first barrier layer 4 and the second barrier layer 8 is the thickest at the end of the gate layer 11 facing the drain electrode 10, which is subject to a high electric field in the nitride semiconductor device 101. This is because the influence of electrons or holes trapped by a high electric field in the surface states on the semiconductor surface can be physically kept away from the two-dimensional electron gas layer 5. This makes it possible to suppress the so-called current collapse (current slump) phenomenon.

[0074] However, if the taper angle 14 is large, the end of the gate layer 11 facing the drain electrode 10 must be extended toward the drain electrode 10 to cover the portion where the total thickness of the first barrier layer 4 and the second barrier layer 8 is large, resulting in an increase in gate-drain capacitance. Furthermore, in semiconductor processes, generally, increasing the taper angle 14 also results in an extension toward the source electrode 9, which increases the gate-source capacitance. The gate capacitance (gate-source capacitance and gate-drain capacitance) is a parameter directly related to the operating speed of the nitride semiconductor device 101, and a large gate capacitance ultimately impairs the high-speed operation of the nitride semiconductor device 101. Therefore, in this modification, the length of the gate layer 11 from the source electrode 9 toward the drain electrode 10 can be minimized, thereby reducing the gate capacitance (gate-source capacitance and gate-drain capacitance), thereby enabling the nitride semiconductor device 101 to operate at a high speed.

[0075] [Fourth Variation] Next, a nitride semiconductor device according to a fourth modification of the embodiment will be described. The structure of the nitride semiconductor device according to this modification is substantially the same as that of the third modification of the embodiment, and will be described with reference to FIG. 6. In the fourth modification of the embodiment, the taper angle 14, which is the angle at which the sidewall 7 of the recessed portion meets the outermost surface of the second barrier layer 8, is 120° or more and less than 180°. Furthermore, although this modification is described using a Group III nitride semiconductor, the present disclosure is not limited thereto. Furthermore, the structure of the nitride semiconductor device according to this modification shows a minimum configuration, and is not limited thereto.

[0076] By using this modification, in addition to the effects of the embodiment or the first, second, and third modifications, it is possible to further uniformize the film thickness and / or composition of the second barrier layer 8, thereby reducing the on-resistance and increasing the maximum drain current.

[0077] If the taper angle 14 is small, i.e., if the recess sidewall 7 has a steep angle, the thickness of the second barrier layer 8 formed by epitaxial regrowth in contact with the recess sidewall 7 becomes thin. This occurs because, when an Al-containing group-III nitride semiconductor is grown as the second barrier layer 8 by metalorganic chemical vapor deposition (MOCVD), the lateral epitaxial growth rate is extremely slow compared to the vertical epitaxial growth rate. As a result, the thickness of the second barrier layer 8 in contact with the recess sidewall 7 becomes extremely thin, or the Al composition becomes extremely high or low, resulting in nonuniformity. As a result, the concentration of the two-dimensional electron gas layer 5 directly below the layer becomes locally reduced. Furthermore, if the taper angle 14 of the group-III nitride semiconductor is around 120°, facets may be generated in the crystal plane orientation, resulting in nonuniform thickness of the second barrier layer 8 and the generation of voids. This results in a local decrease in the concentration of the two-dimensional electron gas layer 5 directly below the two-dimensional electron gas layer 5. This local decrease in the concentration of the two-dimensional electron gas layer 5 results in an increase in the on-resistance and a decrease in the maximum drain current. Therefore, it is desirable that the taper angle 14 be equal to or greater than 120° and less than 180°.

[0078] [Fifth Variation] Next, a nitride semiconductor device according to a fifth modification of the embodiment will be described. The structure of the nitride semiconductor device according to this modification is substantially the same as that of the third modification of the embodiment, and will be described with reference to FIG. 6. In the fifth modification of the embodiment, the difference between the contact angle 13 and the taper angle 14 is within a range of ±20°. Furthermore, although this modification is described using a Group III nitride semiconductor, the present disclosure is not limited thereto. Furthermore, the structure of the nitride semiconductor device according to this modification shows a minimum configuration, and is not limited thereto.

[0079] By using this modification, in addition to the effects of the embodiment or the first, second, third, and fourth modifications, it becomes possible to uniformize the film thickness and / or composition of the second barrier layer 8, reduce the on-resistance, increase the maximum drain current, and reduce the gate capacitance.

[0080] In this modification, as shown in the embodiment, it is desirable that contact angle 13 is 140° or more and less than 180°. Furthermore, as shown in the fourth modification of the embodiment, it is desirable that taper angle 14 is 120° or more and less than 180°. That is, it is desirable that the difference between contact angle 13 and taper angle 14 is +20° or less ("+" means that the contact angle is larger than the taper angle). Furthermore, as shown in the third modification of the embodiment, if taper angle 14 is too large compared to contact angle 13, the gate capacitance (gate-source capacitance and gate-drain capacitance) increases, impairing the high-speed operation of the nitride semiconductor device. Therefore, it is desirable that the difference between contact angle 13 and taper angle 14 is -20° or more ("-" means that the taper angle is larger than the contact angle).

[0081] [Sixth and Seventh Modifications] Next, nitride semiconductor devices according to sixth and seventh modifications of the embodiment will be described with reference to Fig. 7. Fig. 7 is a cross-sectional view showing the cross-sectional structure of a nitride semiconductor device 102 according to the sixth and seventh modifications of the embodiment.

[0082] 7, in the nitride semiconductor device 102 according to this modification, the slope of the tangent between the sidewall of the recessed portion 6 (the portion forming the contact angle 13) and the sidewall of the first barrier layer 4 facing the recessed portion 6 is uniform (smooth enough). In other words, the first barrier layer 4 and the channel layer 3 constituting the sidewall 7 of the recessed portion are continuously connected.

[0083] In the seventh modification of the embodiment, the angle at which the interface between the channel layer 3 and the first barrier layer 4 meets the sidewall of the first barrier layer 4, i.e., the sum of the angle (not shown) of the lower end of the first barrier layer 4 and the contact angle 13, is within a range of 180°±30°. Although this modification is described using a Group III nitride semiconductor, the present disclosure is not limited thereto. The structure of the nitride semiconductor device 102 according to this modification represents a minimum configuration, and is not limited thereto.

[0084] By using this modified example, in addition to the effects of the embodiment or the first, second, third, fourth, and fifth modified examples, the film thickness and / or composition of the second barrier layer 8 in contact with the sidewall 7 of the recessed portion can be made uniform, and as a result, the concentration of two-dimensional electron gas (not shown) in the on state immediately below the recessed portion 6 and in the vicinity of the contact angle 13 can be made uniform, thereby reducing the on-resistance and increasing the maximum drain current.

[0085] When the taper angle 14 is close to or smaller than 120°, the angle of the bottom of the sidewall of the first barrier layer 4 facing the recess 6 may be steeper than the angle obtained by subtracting the taper angle 14 from 180° (e.g., 60° when the taper angle 14 is 120°). In other words, the sidewall of the first barrier layer 4 facing the recess 6 becomes steeper (vertical) as it extends downward. This is because, during the regrowth process of the second barrier layer 8, the channel layer 3 directly below the bottom of the sidewall of the first barrier layer 4 facing the recess 6 is etched by the high temperature during regrowth and the hydrogen carrier gas, and is decomposed together with the first barrier layer 4 above it. As a result, the angle of the bottom of the sidewall of the first barrier layer 4 facing the recess 6 becomes steeper than the angle obtained by subtracting the taper angle 14 from 180°. This slows down the lateral growth rate of the second barrier layer 8 growing on the sidewall 7 of the recess, causing the second barrier layer 8 growing in contact with the sidewall 7 of the recess to have an uneven thickness and / or composition, reducing the two-dimensional electron gas around the contact angle 13, increasing the on-resistance, and reducing the maximum drain current.

[0086] To prevent this, it is desirable that the sidewall of recess 6 (the portion forming contact angle 13) and the sidewall of first barrier layer 4 facing recess 6 are smooth enough to define a single tangent slope. In other words, it is desirable that first barrier layer 4 facing recess 6 and channel layer 3 are continuously connected. Specifically, if the sum of contact angle 13 and the angle (not shown) of the lower end of the sidewall of first barrier layer 4 facing recess 6 is within the range of 180°±30°, the second barrier layer 8 growing in contact with sidewall 7 of the recess will not be formed with non-uniform thickness and / or composition.

[0087] [Eighth, Ninth and Tenth Modifications] Next, nitride semiconductor devices according to eighth, ninth, and tenth modifications of the embodiment will be described. The structures of the nitride semiconductor devices according to these modifications are substantially the same as those of the third modification of the embodiment, and will be described with reference to FIG.

[0088] In an eighth modification of the embodiment, the thickness of the second barrier layer 8 in contact with the sidewall 7 of the recessed portion is 50% or more in the vertical direction compared to the thickness of the second barrier layer 8 along the bottom of the recessed portion 6. In a ninth modification of the embodiment, the Al composition of the second barrier layer 8 is 10% or more and 25% or less. In a tenth modification of the embodiment, the Al composition of the second barrier layer 8 is within a ±5% variation range. Although this modification is described using a Group III nitride semiconductor, the present disclosure is not limited thereto. The structure of the nitride semiconductor device according to this modification shows a minimum configuration, and is not limited thereto.

[0089] By using this modification, in addition to the effects of the embodiment or the first, second, third, fourth, fifth, sixth, and seventh modifications, the film thickness and / or composition of the second barrier layer 8 in contact with the sidewall 7 of the recess portion is made uniform, which results in the two-dimensional electron gas (not shown) immediately below the recess portion 6 when on, thereby reducing the on-resistance and increasing the maximum drain current.

[0090] As shown in the embodiment or the first, second, third, fourth, fifth, sixth, and seventh modifications, the contact angle 13 or taper angle 14 is increased, and the first barrier layer 4 constituting the recess sidewall 7 and the channel layer 3 are continuously connected, so that the film thickness of the second barrier layer 8 formed by regrowth is uniform on the first barrier layer 4, the recess 6, and the recess sidewall 7. This is because the recess sidewall 7 does not become steep (approaching vertical), and is therefore not affected by the slow lateral growth rate of regrowth.

[0091] The thickness of the second barrier layer 8 in contact with the sidewall 7 of the recess 6 is preferably at least 50% of the thickness of the second barrier layer 8 along the bottom of the recess 6 in the vertical direction. This allows the two-dimensional electron gas (not shown) directly below the recess 6 during on-state to be uniform, reducing the on-resistance and increasing the maximum drain current. This also allows the Al composition of the second barrier layer 8 to be uniform, for example, within a range of 10% to 25%. If the Al composition of the second barrier layer 8 is less than 10%, a source leakage current (drain-source leakage current) occurs in the nitride semiconductor device, so it is preferably 10% or more. Furthermore, if the Al composition of the second barrier layer 8 is greater than 25%, the gate leakage current of the nitride semiconductor device increases, so it is preferably 25% or less. Furthermore, it is desirable that the Al composition of the second barrier layer 8 be as uniform as possible in order to homogenize the two-dimensional electron gas (not shown) in the on state immediately below the recessed portion 6. Specifically, it is desirable that the Al composition of the second barrier layer 8 be within a variation range of ±5%.

[0092] [Eleventh Variation] Next, a nitride semiconductor device according to an eleventh modification of the embodiment will be described with reference to FIG. 8 . FIG. 8 is a cross-sectional view showing the cross-sectional structure of a nitride semiconductor device 103 according to the eleventh modification of the embodiment. As shown in FIG. 8 , in the nitride semiconductor device 103 according to this modification, of the contact angles on the left and right of the recessed portion 6, contact angle 15 on the drain side is larger than contact angle 16 on the source side. Furthermore, although this modification is described using a Group III nitride semiconductor, the present disclosure is not limited thereto. Furthermore, the structure of the nitride semiconductor device 103 according to this modification shows a minimum configuration, and is not limited thereto.

[0093] In addition to the effects of the embodiment or the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth modifications, this modification can alleviate the electric field on the drain electrode 10 side of the gate layer 11, where the electric field strength is highest in the nitride semiconductor device 103, thereby reducing gate leakage current. This is because the drain-side contact angle 15 is reduced, and the gate layer 11 directly above the drain-side contact angle 15 has a forward tapered shape, acting as a field plate and alleviating the electric field distribution. Conversely, making the source-side contact angle 16 smaller than the drain-side contact angle 15 can reduce the gate layer 11 and reduce the gate capacitance (e.g., gate-source capacitance). Because the gate-source capacitance is a parameter directly related to the operating speed of a nitride semiconductor device, reducing the gate capacitance enables the nitride semiconductor device to operate at a higher speed.

[0094] [Manufacturing method] Next, a method for manufacturing the nitride semiconductor device 100 according to the embodiment shown in FIG. 1 will be described with reference to FIGS. 9A to 9E. Each of FIGS. 9A to 9E is a cross-sectional view showing a cross-sectional structure at one step in the method for manufacturing the nitride semiconductor device 100 according to this embodiment. Note that this manufacturing method describes a minimum configuration, and is not limited to this. Furthermore, the order of steps in this manufacturing method is not limited to this.

[0095] First, a suitable buffer layer 2 (e.g., a single layer or multiple layers of a Group III nitride semiconductor such as GaN, AlGaN, AlN, InGaN, InN, or AlInGaN) is formed on a suitable (111) Si substrate 1 (or a substrate such as sapphire, SiC, GaN, or AlN) using a known epitaxial growth technique such as MOCVD. Then, a channel layer 3 made of GaN (e.g., a single layer or multiple layers of a Group III nitride semiconductor such as InGaN, InN, AlGaN, or AlInGaN) is formed thereon. Then, a first barrier layer 4 made of AlGaN (e.g., a Group III nitride semiconductor such as GaN, InGaN, AlGaN, AlN, or AlInGaN) is formed thereon (see FIG. 9A). The first barrier layer 4 has a larger band gap than the channel layer 3. When the first barrier layer 4 is made of AlGaN and the channel layer 3 is made of GaN, a highly concentrated two-dimensional electron gas layer 5 is generated on the channel layer 3 side near the interface between the first barrier layer 4 and the channel layer 3 due to the difference in band gap and the piezoelectric charges generated by the difference in lattice constant between AlGaN and GaN.

[0096] Next, a resist pattern 17 for forming the recess 6 is formed using a known photolithography technique (see FIG. 9B ). One method for reducing the angle of the sidewall 7 of the recess and increasing the contact angle 13 to 140° or greater involves post-baking the resist pattern 17. The post-baking temperature varies depending on the resist type, but it is generally performed at a temperature between 120°C and 160°C for 1 minute to 30 minutes. This reduces the sidewall of the resist pattern 17 and reduces the taper angle 18 of the resist pattern 17. The recess 6 is formed using a dry etching technique such as inductively coupled reactive ion etching (ICP-RIE). However, if the dry etching conditions are highly anisotropic, the taper angle 18 of the resist pattern 17 is transferred almost directly to the contact angle 13 of the recess 6. It is desirable that the taper angle 18 of the resist pattern 17 be 60° or less, but if the taper angle 18 of the resist pattern 17 is made too small, the opening length of the upper end of the recess 6 becomes too large, and the gate layer 11 that covers it, which will be formed later, also becomes large, resulting in an increase in gate capacitance. Therefore, it is desirable that the taper angle 18 of the resist pattern 17 be 30° or more at the smallest.

[0097] Furthermore, in this method, the taper angle 18 of the resist pattern 17 is affected by the width of the resist pattern 17 from the relevant recess 6 to the adjacent recess 6. This is because the resist pattern 17 is shrunk and stretched by post-baking, and the smaller the width of the resist pattern 17 from the relevant recess 6 to the adjacent recess 6, the gentler the taper angle 18 of the resist pattern 17. Under highly anisotropic etching conditions, the taper angle 18 of the resist pattern 17 is transferred almost directly to the contact angle 13 of the recess 6. Therefore, it is desirable to perform sufficient post-baking so that the taper angles 18 of the resist patterns 17 on both sides of the recess 6 are similar (within ±20° if possible).

[0098] Another method for flattening the contact angle 13 between the sidewall 7 of the recess and the interface between the first barrier layer 4 and the channel layer 3 is to use conditions that result in the formation of a large amount of polymeric products during dry etching. When polymeric products adhere to the sidewalls of the resist pattern 17 and the sidewall 7 of the recess during dry etching, the etching rate of the sidewall 7 of the recess decreases, resulting in a large contact angle 13.

[0099] The recess 6 with a large contact angle 13 is formed by post-baking the resist pattern 17, or by dry etching conditions that result in the formation of a large amount of polymeric products, or by both, or by other methods. The contact angle 13 is preferably 140° or greater and less than 180°. The recess depth must penetrate the first barrier layer 4 at all points on the wafer surface, with the bottom of the recess reaching the channel layer 3. The penetration depth is preferably at least 0.5 nm from the perspective of the penetration depth margin from the bottom surface of the first barrier layer 4. Furthermore, if the recess depth is too deep, the two-dimensional electron gas layer 5 will be significantly curved and become resistive. Therefore, the recess depth is preferably 0.5 nm or greater and 100 nm or less. Next, the resist pattern 17 is removed using known oxygen ashing techniques, organic resist removal techniques, or the like (see Figure 9C).

[0100] Next, using MOCVD or the like, a second barrier layer 8 made of AlGaN (also made of, for example, a Group III nitride semiconductor such as GaN, InGaN, AlGaN, AlN, or AlInGaN) and a gate layer 11 (also made of, for example, a Group III nitride semiconductor such as p-InGaN, p-AlGaN, p-AlInGaN, i-GaN, i-InGaN, i-AlGaN, i-AlInGaN, n-GaN, n-InGaN, n-AlGaN, or n-AlInGaN) are successively regrown to cover the recess 6, the sidewall 7 of the recess, and the upper surface of the first barrier layer 4 (see FIG. 9D ). The gate layer 11 may be p-GaN containing Mg, i-GaN (insulated-GaN, other group III nitride semiconductors such as i-InGaN, i-InN, i-AlGaN, and i-AlInGaN) containing C, or n-GaN (other group III nitride semiconductors such as n-InGaN, n-InN, n-AlGaN, and n-AlInGaN) containing n-type impurities such as Si. When the second barrier layer 8 contains Al, it grows to a generally uniform thickness in the vertical direction along the recessed portion 6, the sidewalls 7 of the recessed portion, and the upper surface of the first barrier layer 4, as shown in FIG. 9D , or grows slightly thinner in the vertical direction only along the sidewalls 7 of the recessed portion. In contrast, when GaN not containing Al is used for the gate layer 11, it is planarized to fill the recessed portion 6, as shown in FIG. 9D .

[0101] The second barrier layer 8 also has a larger band gap than the channel layer 3. If the second barrier layer 8 is made of AlGaN and the channel layer 3 is made of GaN, a high-concentration two-dimensional electron gas layer is generated on the channel layer 3 side near the interface of the channel layer 3 in contact with the second barrier layer 8 due to the difference in band gap and the piezoelectric charge generated by the difference in lattice constant between AlGaN and GaN. However, if the gate layer 11 is a p-type group III nitride semiconductor, a pn junction is formed directly below the gate layer 11, and when no gate voltage is applied to the gate layer 11, the two-dimensional electron gas layer on the channel layer 3 side near the interface of the channel layer 3 in contact with the second barrier layer 8 is depleted, resulting in a normally-off state. In this case, the thickness of the second barrier layer 8 varies depending on the set threshold voltage (Vth). In the case where the second barrier layer 8 is made of AlGaN, the thickness of the AlGaN film directly below the gate layer 11 must be in the range of 10 nm to 25 nm, preferably about 20 nm, if the Al composition of the AlGaN of the second barrier layer 8 is 20%. In this case, when the gate layer 11 is p-GaN, the thickness of the gate layer 11 is in the range of 50 nm to 500 nm, preferably about 200 nm. When the p-type impurity is Mg, the doping concentration is 1E19 cm -3 Over 10E19E -3 Within the following range, preferably 5E19cm -3 It is sufficient if Mg is 5E19cm -3 The carrier concentration of p-GaN doped to a certain extent is practically 1E17 cm because the activation rate of Mg is very low, less than a few percent. -3 More than 5E17cm -3 It is about the following.

[0102] Next, a resist pattern is formed using known photolithography techniques, and the gate layer 11 is selectively removed using known dry etching techniques. Note that if the gate layer 11 is p-GaN and the second barrier layer 8 is AlGaN, the selectivity of the selective dry etching may be as low as approximately 10 times (the etching rate of p-GaN is 10 times faster than that of AlGaN). In this case, it is necessary to etch the area other than the gate layer 11 and perform over-etching down to the second barrier layer 8 to completely remove the p-GaN other than the gate layer 11 (not shown). This is because if the gate layer 11 remains on the second barrier layer 8, gate leakage current increases. The over-etching depth is preferably 0 nm to 40 nm, but it is also acceptable to completely remove the second barrier layer 8 in the area other than the gate layer 11.

[0103] Next, if the gate layer 11 contains Mg as a p-type impurity, activation annealing is performed in nitrogen gas at a temperature of 800°C for about 30 minutes to activate the Mg (not shown). This activation annealing breaks the hydrogen bonds that inactivate the p-type element Mg, improving the activation rate of Mg. The gate layer 11 containing the p-type impurity depletes the two-dimensional electron gas layer on the channel layer 3 side near the interface of the channel layer 3 with the second barrier layer 8 by the pn junction when no gate voltage is applied to the gate layer 11 (see FIG. 9E).

[0104] Next, the source electrode 9 and the drain electrode 10 are formed at a distance from the gate layer 11 using known techniques such as photolithography, vapor deposition, lift-off, sputtering, and dry etching. The source electrode 9 and the drain electrode 10 are made of one or a combination of two or more metals, such as Ti, Al, Mo, and Hf, that are in ohmic contact with the two-dimensional electron gas layer 5, the first barrier layer 4, the second barrier layer 8, and the channel layer 3, and are electrically connected to the two-dimensional electron gas layer 5. For example, the source electrode 9 and the drain electrode 10 may be located on the surface of the second barrier layer 8 or the first barrier layer 4, or may be in contact with the two-dimensional electron gas layer 5, the first barrier layer 4, or the channel layer 3 using known ohmic recess techniques (not shown). The source electrode 9 and the drain electrode 10 may be annealed to reduce contact resistance.

[0105] Finally, the gate electrode 12 is formed using known techniques such as photolithography, vapor deposition, lift-off, sputtering, and dry etching (see FIG. 1). The gate electrode 12 may be an electrode made of one or a combination of two or more metals, such as Ti, Ni, Pd, Pt, Au, W, WSi, Ta, TiN, Al, Mo, Hf, and Zr. However, if the gate layer 11 is p-type, the gate electrode 12 may be in ohmic or Schottky contact with the gate layer 11, although ohmic contact provides higher gate electrode reliability. For this reason, it is desirable to use, as the gate electrode 12, an electrode made of one or a combination of two or more metals with low contact resistance, such as Ni, Pt, Pd, Au, Ti, Cr, In, Sn, and Al.

[0106] [Plane structure] Next, a description will be given of the planar structure of the nitride semiconductor device 100 according to this embodiment. Note that the planar structures of the nitride semiconductor devices 101, 102, and 103 according to the respective modifications shown in Fig. 6 to Fig. 8 are also the same, and therefore descriptions thereof will be omitted below.

[0107] Fig. 10 is a plan view showing the planar structure of a nitride semiconductor device 100 according to this embodiment. Fig. 10 is a plan view of Fig. 1 seen from above, showing a state in which the source electrode 9 and the drain electrode 10 have been formed but before the gate electrode 12 has been formed. For example, Fig. 1 shows a cross section taken along line II in Fig. 10. Note that this structure shows a minimum configuration and is not limited to this.

[0108] The gate layer 11 is formed to surround the source electrode 9. This forms a normally-off pn junction between the source and drain directly below the gate layer 11, blocking the leakage path between the source and drain during off-state operation and reducing source-drain leakage current. The gate layer 11 is aggregated (aggregated on the left side in FIG. 10 ). The aggregated gate 19 is connected to a gate pad in the isolation region 20 (not shown). The isolation region 20 is located outside the source electrode 9, drain electrode 10, and gate layer 11, but a portion of the edge of the aggregated gate layer 11 (on the left side in the figure) and a portion of the aggregated gate 19 form the isolation region 20. Multiple sets of source electrodes 9 and drain electrodes 10 are repeatedly formed as shown in FIG. 10 . However, it is preferable for reliability that the outermost electrodes (the upper and lower sides in FIG. 10 ) be source electrodes 9, as this mitigates the electric field distribution outside the isolation region 20.

[0109] 9A to 9E, when forming a recess 6 directly below the gate layer 11, the taper angle 18 of the resist pattern 17 is affected by the width of the resist to the adjacent recess 6. This is because the resist pattern 17 is shrunk and stretched by post-baking, and the smaller the width of the resist pattern 17 from one recess 6 to the adjacent recess 6, the smaller the taper angle 18 of the resist pattern 17. When dry etching is performed using this resist pattern 17 under highly anisotropic conditions, the taper angle 18 of the resist pattern 17 is transferred almost directly to the contact angle 13 of the recess 6. Therefore, in a finger pattern in which multiple recesses 6 are arranged in parallel, only the inner and outer contact angles 13 of the fingers of the outermost recess 6 (the upper and lower sides in FIG. 10) become small. To avoid this, post-baking can be performed sufficiently so that the taper angles 18 of the resist patterns 17 on the left and right of the recess 6 are similar (within ±20° if possible), or, for example, the fingers of the uppermost and lowermost gate layers 11 in the arrangement of Fig. 10 can be inactivated by ion implantation to form inactivated regions (not shown). Alternatively, a layout such as that shown in Fig. 11 in which a dummy gate layer 21 with a recess 6 that is not electrically connected to the element isolation region 20 is formed further outside the fingers of the outermost gate layer 11 is preferable.

[0110] (Other embodiments) While nitride semiconductor devices according to one or more aspects have been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and configurations constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0111] For example, in the above-described embodiment and each modification, examples have been described in which each semiconductor layer is formed using a group III nitride semiconductor, but the present disclosure is not limited thereto. Furthermore, the structures shown in the above-described embodiment and each modification represent minimum configurations, and the present disclosure is not limited thereto.

[0112] Furthermore, for example, the contact angle on the drain side and the contact angle on the source side may be equal to or different from each other. Furthermore, for example, the sidewall of the recess 6 (part of the channel layer 3) and the sidewall of the first barrier layer 4 facing the recess 6 do not have to be continuously connected. The sidewall 7 of the recess may be a flat inclined surface or a curved surface.

[0113] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to the above-described embodiments within the scope of the claims or their equivalents. [Industrial Applicability]

[0114] The present disclosure can be used as a nitride semiconductor device capable of reducing on-resistance, and can be used in, for example, power devices such as field-effect transistors. [Explanation of symbols]

[0115] 1 board 2. Buffer layer 3 Channel Layer 4 First Barrier Layer 5 Two-dimensional electron gas layer 6 Recessed part 7 Recessed side wall 8 Second Barrier Layer 9 Source electrode 10 Drain electrode 11 Gate Layer 12 gate electrode 13 Contact angle 14 Taper angle 15 Drain side contact angle 16 Contact angle on source side 17 Resist Pattern 18 Taper angle of resist pattern 19 Gate Aggregation 20 Element isolation region 21 Dummy gate layer 100, 101, 102, 103 Nitride semiconductor device

Claims

1. A substrate; a first nitride semiconductor layer provided on the substrate and having a recess; a second nitride semiconductor layer having a band gap larger than that of the first nitride semiconductor layer and provided in a region other than the recessed portion; a third nitride semiconductor layer having a band gap larger than that of the first nitride semiconductor layer, including an inner wall of the recess portion, and covering the first and second nitride semiconductor layers; a contact angle between a sidewall of the recessed portion and an interface between the first nitride semiconductor layer and the second nitride semiconductor layer is equal to or greater than 140° and less than 180°; the contact angle is larger than a taper angle, which is an angle between a sidewall of the second nitride semiconductor layer facing the recess portion and an upper surface of the second nitride semiconductor layer; Nitride semiconductor devices.

2. a contact angle between each of the sidewalls on both sides of the recessed portion and the interface between the first nitride semiconductor layer and the second nitride semiconductor layer is equal to or greater than 140° and less than 180°; The nitride semiconductor device according to claim 1 .

3. an average of contact angles between each of the sidewalls on both sides of the recess and the interface between the first nitride semiconductor layer and the second nitride semiconductor layer is equal to or greater than 145° and less than 180°; 3. The nitride semiconductor device according to claim 1.

4. a taper angle, which is an angle between a sidewall of the second nitride semiconductor layer facing the recess portion and an upper surface of the second nitride semiconductor layer, is 120° or more and less than 180°; The nitride semiconductor device according to claim 1 .

5. a difference between the contact angle and a taper angle, which is an angle between a sidewall of the second nitride semiconductor layer facing the recess portion and an upper surface of the second nitride semiconductor layer, is within a range of ±20°; The nitride semiconductor device according to claim 1 .

6. a sidewall of the recess portion and a sidewall of the second nitride semiconductor layer facing the recess portion have a single inclination of a tangent; The nitride semiconductor device according to claim 1 .

7. an angle formed between a sidewall of the recessed portion and a sidewall of the second nitride semiconductor layer facing the recessed portion is within a range of 180°±30°; The nitride semiconductor device according to claim 1 .

8. A substrate; a first nitride semiconductor layer provided on the substrate and having a recess; a second nitride semiconductor layer having a band gap larger than that of the first nitride semiconductor layer and provided in a region other than the recessed portion; a third nitride semiconductor layer having a band gap larger than that of the first nitride semiconductor layer, including an inner wall of the recess portion, and covering the first and second nitride semiconductor layers; a contact angle between a sidewall of the recessed portion and an interface between the first nitride semiconductor layer and the second nitride semiconductor layer is equal to or greater than 140° and less than 180°; a thickness of the third nitride semiconductor layer along a sidewall of the second nitride semiconductor layer is 50% or more in a vertical direction compared to a thickness of the third nitride semiconductor layer along a bottom of the recess portion; Nitride semiconductor devices.

9. the third nitride semiconductor layer contains Al; the Al composition of the third nitride semiconductor layer is 25% or less; The nitride semiconductor device according to claim 1 .

10. the third nitride semiconductor layer contains Al; the Al composition of the third nitride semiconductor layer is within a variation range of ±5%; The nitride semiconductor device according to claim 1 .

11. A substrate; a first nitride semiconductor layer provided on the substrate and having a recess; a second nitride semiconductor layer having a band gap larger than that of the first nitride semiconductor layer and provided in a region other than the recessed portion; a third nitride semiconductor layer having a band gap larger than that of the first nitride semiconductor layer, including an inner wall of the recess portion, and covering the first and second nitride semiconductor layers; a contact angle between a sidewall of the recessed portion and an interface between the first nitride semiconductor layer and the second nitride semiconductor layer is equal to or greater than 140° and less than 180°; the semiconductor device further includes a source electrode and a drain electrode disposed spaced apart from the recessed portion so as to sandwich the recessed portion therebetween, The contact angle on the drain electrode side is larger than the contact angle on the source electrode side. Nitride semiconductor devices.

Images