semiconductor switching devices

Abstract

To provide methods and devices for semiconductor cells having a drift region, a well region, and a channel region.SOLUTION: In a system 70 comprising an array of semiconductor device cells, a semiconductor cell 72 includes a semiconductor layer having a surface 4 defining stair steps, the stair steps oriented in a first direction 23, where a drift region and a well region 18 define a set of well region segments 17. A source region 20 is disposed adjacently to the well region and surrounded by the well region. A channel region 28 defines a set of channel region segments 28a proximal to the semiconductor layer surface, the channel region segments having respective first longitudinal axes 31a extending in a second direction 25 transverse to the first direction 23. The well region, the source region, and the channel region cooperatively define a first axial length D1 extending across the surface. The semiconductor layer surface has a higher electrical resistance in the first direction than in the second direction.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present disclosure relates to methods and apparatus for semiconductor devices and semiconductor cells having drift, well, and channel regions for operatively conducting or not conducting current. [Background technology]

[0002] Semiconductor devices, such as silicon carbide (SiC) power devices, are widely used in conventional electrical systems to switch or convert power for consumption by loads. Semiconductor devices, such as integrated circuits, can incorporate a variety of devices, including transistors. A common type of transistor uses a gate that is insulated from a channel that can cause conduction between the source and drain of the transistor based on a gate-to-source voltage. A suitable bias creates an electric field that attracts charge carriers into the channel, which then provides a conduction path between the source and drain. Such transistors are sometimes called metal-oxide-semiconductor field-effect transistors, or MOSFETs.

[0003] MOSFETs can be fabricated as discrete power transistors for high-power applications, or as integrated circuits with millions of transistors. Discrete power transistors are typically made up of thousands of individual transistor "cells" combined into a single power device to handle relatively large currents and voltages.

[0004] Individual transistor "cells" also contain several internal components that can create resistance to the current flowing through the device. Power MOSFETs typically use a vertical structure with the source and drain terminals located on opposite sides of the wafer (or chip). This results in current conduction from drain to source through the wafer, which shunts current and reduces on-state resistance. Generally, when a semiconductor device is conducting current, the on-state resistance of the device represents its conduction losses, which affect the efficiency of the device and its cost. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1A is a plan view of a conventional SiC wafer, and FIG. 1B is an enlarged view of a portion of the SiC wafer of FIG. 1A. [Figure 2] FIG. 1 is a schematic diagram of a typical planar MOSFET device. [Figure 3] FIG. 1 is a schematic diagram illustrating the resistance for various regions of a typical MOSFET device. [Figure 4] 3 is a chart depicting the relative resistance contributions of regions of the MOSFET device structure of FIG. 2; [Figure 5] FIG. 1 is a top view of the surface of a SiC layer containing a typical MOSFET device structure with a striped cell layout. [Figure 6] FIG. 1 is a top view of the surface of a SiC layer containing a typical MOSFET device structure with a striped cell layout. [Figure 7] FIG. 1 is a top view of the surface of a SiC layer containing a typical MOSFET device structure with a cellular layout. [Figure 8] FIG. 1 is a top view of a system comprising an array of semiconductor device cells in accordance with various aspects described herein. [Figure 9] FIG. 1 is a top view of a system including an alternative arrangement of semiconductor device cells in accordance with various aspects described herein. [Figure 10]FIG. 9 is a cross-sectional view of the semiconductor device cell of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0006] Aspects of the present disclosure may be implemented in any environment, device, or method for cooling a heat-generating module, regardless of the function performed by the heat-generating module.

[0007] As used herein, the term "set" or a "set" of elements may be any number of elements, including only one. When introducing elements of various embodiments of the present disclosure, the articles "a," "an," and "the" are intended to mean that there are one or more elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements. In addition, it should be understood that references to "one aspect" or "aspects" of the present disclosure are not intended to be interpreted as excluding the existence of additional aspects that also incorporate the referenced features.

[0008] It will be understood that the shape, position, and alignment of features disclosed herein are shown and described as being relatively ideal (e.g., square, rectangular, and hexagonal cells and shielding regions with perfectly straight and aligned features) for simplicity. However, as will be understood by those skilled in the art, process variations and technical constraints may result in cellular designs with less than ideal shapes, or even irregular features may be consistent with the present disclosure. Thus, the term "substantially," as used herein to describe feature shape, position, or alignment, is meant to encompass ideal or target shapes, positions, and alignments, as well as imperfectly implemented shapes, positions, and alignments that result from variations in semiconductor manufacturing processes, as will be understood by those skilled in the art.

[0009] Additionally, semiconductor device cells are described herein as being disposed or fabricated "at," "in," "on," or "along" the surface of a semiconductor layer. This is intended to include semiconductor device cells having portions disposed within the bulk of the semiconductor layer, portions disposed proximate to the surface of the semiconductor layer, portions disposed flush with the surface of the semiconductor layer, and / or portions disposed above or on top of the surface of the semiconductor layer.

[0010] As used herein, the term "channel density" may refer to the ratio of the perimeter of the channel region of a particular device cell to the total area of ​​the device cell.

[0011] It will be apparent to those skilled in the art that while terms such as "voltage," "current," and "power" may be used herein, these terms may be interrelated when describing aspects of electrical circuits or circuit operation.

[0012] All directional references (e.g., radial, axial, up, down, upward, downward, left, right, lateral, front, rear, top, bottom, upward, downward, vertical, horizontal, clockwise, counterclockwise) are used for identification purposes only to aid the reader's understanding of this disclosure and do not create any limitation as to their particular location, orientation, or use.

[0013] References to connections (e.g., attached, coupled, connected, and coupled) should be interpreted broadly and, unless otherwise indicated, can include intermediate members between groups of elements and can include relative movement between the elements. As such, references to connections do not necessarily infer that two elements are directly connected and in a fixed relationship relative to each other. In a non-limiting example, connections or disconnections can be selectively configured to make, enable, disable, etc., electrical connections between respective elements. The exemplary figures are for illustrative purposes only, and the dimensions, positions, order, and relative sizes reflected in the figures attached hereto may vary.

[0014] As used herein, a controllable switching element or "switch" is an electrical device that is controllable to toggle between a first mode of operation in which the switch is in a very low resistance or "on" state or otherwise a conducting mode in which current is intended to flow from the switch input to the switch output, and a second mode of operation in which the switch is in a very high resistance or "off" state or otherwise a non-conducting mode in which current is intended to prevent flow between the switch input and the switch output. In a non-limiting example, connections or disconnections, such as enabled or disabled connections, by a controllable switching element can be selectively configured to make, enable, disable, etc., electrical connections between the respective elements.

[0015] Additionally, while various embodiments may be discussed below in the context of SiC MOSFET devices for ease of description and understanding, it should be understood that the present approach is applicable to other types of MOSFETs, such as, but not limited to, SiC DMOSFETs, UMOSFETs, and VMOSFETs. It is contemplated that various material systems (e.g., silicon (Si), germanium (Ge), aluminum nitride (AlN), gallium nitride (GaN), AlGaN alloys, gallium oxide (GaO), diamond (C), cubic boron nitride (BN), or any other suitable large bandgap semiconductor) may be used. It is further contemplated that other types of device structures utilizing n-channel or p-channel designs (e.g., UMOSFETs, VMOSFETs, trench MOSFETs, insulated gate bipolar transistors (IGBTs), insulated base MOS controlled thyristors (IBMCTs), or any other suitable FET and / or MOS devices) may be used in various non-limiting embodiments.

[0016] MOSFETs are typically made through a multi-step sequence of photolithographic and chemical processing steps (such as surface passivation, thermal oxidation, planar diffusion, and junction isolation) during which electronic circuits are gradually created on a wafer made of pure semiconductor material such as silicon. The wafer is typically cut or sliced ​​with an abrasive saw, such as an annular diamond saw, from a single crystal ingot or boule of semiconductor material such as silicon. The wafer serves as both the mechanical substrate and the semiconductor material for forming the MOSFET.

[0017] Typically, the boule is grown in a known manner from a seed crystal placed in molten silicon. The seed crystal is generally defined by a regular, well-ordered, repeating atomic structure called a "unit cell" that collectively forms a lattice structure. During production, the silicon atoms in the molten silicon align with the same crystallographic orientation as the seed crystal, and wafers cut from the boule retain this crystallographic orientation. When the wafer is sliced ​​from the boule, the crystals on the wafer face are aligned with one of several relative orientations known as the orientations or growth planes of crystalline silicon.

[0018] In some processes, electronic devices are fabricated directly in or on a semiconductor wafer. In other processes, a layer of semiconductor material is grown on the wafer, for example by epitaxy. The epitaxial layer may have a lower impurity concentration or may be of a different semiconductor type than the wafer. The electronic devices are formed in what is known as the "active" layer, which is typically about 1 micron thick.

[0019] For illustrative purposes, referring simultaneously to FIGS. 1A and 1B, a SiC wafer 9 is shown. FIG. 1A depicts a top view of the SiC wafer 9 being cut from a bore (not shown) by sawing in a known manner. FIG. 1B depicts an enlarged perspective view of a portion of the SiC wafer 9 of FIG. 1A. The SiC wafer 9 has a flat first surface 4 (e.g., a top surface). The crystal orientation of the SiC wafer 9 may be oblique to the first surface 4, and the saw cut may be along a plane offset from the crystal orientation 8. More specifically, due to requirements for epitaxial growth, the SiC wafer 9 may be cut with a slight intentional misalignment (e.g., in the range of 4 to 8 degrees) between the crystal orientation 8 and the first surface 4 of the SiC wafer 9.

[0020] Due to the crystalline structure of the SiC wafer 9, this miscut or misalignment typically results in non-uniform, elongated, parallel striations 19 or “stair-like steps” defined on the first side 4 of the SiC wafer 9 and extending in a first direction 23 across the first side 4 of the SiC wafer 9. Each of the striations 19 can define a respective striation longitudinal axis 21. As shown, each striation 19 is offset from its immediately adjacent striation 19. For example, each striation 19 can be offset from its adjacent striation 19 by a respective depth H, in the range of approximately 1 to 5 nanometers. Looking at the SiC wafer 9 as illustrated in FIG. 1B , it will be appreciated that a second direction 25 (from left to right or right to left across the page) can also be defined on the first side 4. The second direction 25 can be a transverse axis, e.g., perpendicular to the first direction 23.

[0021] In operation, a semiconductor device fabricated on a SiC wafer 9 having a series of striations 19 defined on the first side 4 may have a first electrical resistance R1 to a first current in a first direction 23 (i.e., parallel to the longitudinal axis 21 of the striations 19) across the first side 4. Conversely, a semiconductor device fabricated on a SiC wafer 9 having striations 19 on the first side 4 may have a second resistance R2 to a second current in a second direction 25. The second resistance R2 may be greater than the first resistance R1.

[0022] Generally, while an ideal power switch conducts current with zero electrical resistance when in a low-resistance "on" or conducting state, a real power MOSFET will necessarily exhibit finite electrical resistance. Therefore, for a given MOSFET chip size, it is desirable to reduce the total resistance (e.g., on-state resistance) to the smallest possible value without reducing the device's off-state resistance, switching speed, or both.

[0023] A conventional power MOSFET typically consists of a periodic arrangement of unit cells. Each unit cell may have a respective electrical resistance, and the total on-state electrical resistance of the MOSFET can be calculated by dividing the unit cell resistance by the number of unit cells in the power MOSFET device. In addition, each unit cell resistance can be defined by the set of respective resistance values ​​of the structural components of the cell that are coupled in series. The on-state resistance of a particular MOSFET can therefore be defined based at least in part on the relative geometric configuration of the various functional components within each cell, as well as the relative orientation of the functional components on the cell.

[0024] When a MOSFET is "on," or conducting, electrons flow through each individual cell from the "source metal" on the top surface of the SiC semiconductor body, through various structures defined within the SiC semiconductor body, and into the "drain metal" on the back surface of the body. Each respective MOSFET unit cell surface can include four mutually exclusive, non-overlapping regions, referred to herein as the source contact region, the n+ / p-well region, the channel / accumulation region (herein the "channel region"), and the junction field effect transistor (JFET) region. The four regions can be electrically coupled in series and can occupy substantially the entire area of ​​the respective cell. A MOSFET can include a source, drain, and channel that can be said to be planar because they lie in a common horizontal plane above the substrate.

[0025] The resistive contributions of the source contact and channel region to the on-state electrical resistance of a MOSFET are inversely proportional to their respective areas. The resistive contribution of the n+ / p-well region to the on-state electrical resistance of a MOSFET is also inversely proportional to its area. Because the resistive contribution of the channel region is relatively larger than that of the n+ / p-well region or the source contact region, the on-state electrical resistance of a MOSFET can be reduced by maximizing the relative area of ​​the channel region in the unit cell to the n+ / p-well region or the source contact region. Therefore, conventional techniques typically employ MOSFET structures that maximize the relative ratio of the channel region area by arranging the cell geometry to minimize the relative ratio of the n+ / p-well region area, the source contact region area, or both to the channel region.

[0026] Typically, for SiC MOSFETs, such optimization may be limited by current manufacturing technology. For example, conventional techniques have focused on reducing the on-state resistance of the MOSFET using periodic cells created by surrounding a minimum-sized source contact region with a minimum-sized n+ region relative to the channel region. However, the minimum manufacturable source contact region dimensions (using conventional manufacturing techniques) may be larger than the calculated or determined optimal area. Furthermore, to avoid manufacturing-related device failures, the channel region must be separated from the source contact region by a minimum width of n+ / p-well region. However, the geometry of the n+ / p-well region, in particular, is relatively unconstrained by such manufacturing issues.

[0027] Thus, as described in more detail herein, in non-limiting embodiments, cells can be arranged to minimize the relative ratio of n+ / p-well region areas while minimizing the source contact region area and channel region area. In this manner, embodiments described herein can achieve a larger net relative ratio of channel region area to source contact region or n+ region or both compared to conventional techniques, thereby achieving improved (i.e., lower) on-state resistance for each cell compared to conventional devices.

[0028] For example, in non-limiting embodiments, a cellular structure can be employed that includes an arrangement of cells spaced further apart than conventional devices. The increased space or area between adjacent cells can result in alternating bands or segments of n+ / p-wells and channel regions. In this novel arrangement, the relative ratio of channel area to n+ / p-wells, or source contact regions, or both, can be advantageously increased beyond levels achievable using conventional techniques that increase the relative ratio of channel area by minimizing n+ / p-wells, or source contact regions, or a combination thereof. As described in more detail herein, unwanted increases in on-state resistance resulting from increased areas of n+ / p-well regions (e.g., in alternating bands) can be negated or overcome within predefined dimensional ranges due to the reduction in on-state resistance achieved by the corresponding increase in the area of ​​the channel region, resulting in a net reduction in the on-state resistance of each cell compared to conventional designs.

[0029] Furthermore, in embodiments as disclosed herein, the channel regions can be oriented to take advantage of a lower resistance path in a first direction across the semiconductor wafer or chip, i.e., the channel regions can be arranged with increased area so that the current flowing through them is primarily horizontal (i.e., when looking at the page as shown in the figures).

[0030] 2 illustrates an active cell of a conventional planar n-channel MOSFET, such as a DMOSFET, hereinafter MOSFET device 10. It can be understood that certain commonly understood design elements (e.g., top metallization, passivation, edge termination, etc.) may be omitted to more clearly illustrate and describe certain components of MOSFET device 10, as well as other devices discussed hereinafter.

[0031] The illustrated MOSFET device 10 of FIG. 2 includes a semiconductor layer 2 (e.g., an epitaxial SiC semiconductor layer) having a first side 4 and a second side 6. The semiconductor layer 2 includes a drift region 16 having a first conductivity type (e.g., an n-type drift region 16) and a well region 18 having a second conductivity type (e.g., a p-well region 18) adjacent to the drift region 16 and disposed near the first side 4. The semiconductor layer 2 also includes a source region 20 having the first conductivity type (e.g., an n-type source region 20) adjacent to the well region 18 and near the first side 4. A dielectric layer 24 (also referred to as a gate insulating layer or gate dielectric layer) is disposed on a portion of the first side 4 of the semiconductor layer 2, and a gate electrode 26 is disposed on the dielectric layer 24. The second side 6 of the semiconductor layer 2 is a substrate layer 14 (e.g., a SiC substrate layer), and a drain contact 12 is disposed at the bottom of the MOSFET device 10 along the substrate layer 14. A source contact 22 is disposed on top of the semiconductor layer 2 partially covering the source region 20 and the well region 18 .

[0032] During on-state operation, a suitable gate voltage (e.g., above the threshold voltage (VTH) of MOSFET device 10) can cause an inversion layer to form in channel region 28 due to carrier accumulation and an extended conduction path in JFET region 29, allowing current to flow from drain contact 12 (i.e., drain electrode) to source contact 22 (i.e., source electrode). It should be understood that in the MOSFET devices discussed herein, channel region 28 can be generally defined as the upper portion of well region 18 disposed beneath gate electrode 26 and dielectric layer 24.

[0033] FIG. 3 is a schematic cross-sectional view of the MOSFET device 10 of FIG. 2. The source contact 22 of the MOSFET device 10 illustrated in FIG. 3 generally provides an ohmic contact to the source electrode and is disposed over both a portion of the source region 20 and a portion of the well region 18. The source contact 22 is generally a metal interface comprising one or more metal layers located between these semiconductor portions of the MOSFET device 10 and the metal source electrode. For ease of understanding, the portion of the source region 20 (e.g., the n+ source region 20) of the MOSFET device 10 that is disposed below the source contact 22 will be more specifically referred to herein as the source contact region 42 of the MOSFET device 10. Similarly, the portion of the well region 18 (e.g., the p-well region 18) of the MOSFET device 10, which may be p+ doped to a higher level than the remainder of the well region 18, will be more specifically referred to herein as the body region 44 (e.g., the p+ body region 44) of the MOSFET device 10. For ease of understanding, the portion of body region 44 that is disposed below (e.g., covered by or directly electrically connected to) source contact 22 is referred to herein as the body contact region 44 (e.g., p+ body contact region 44) of MOSFET device 10. For consistency, the portions of source contact 22 are designated herein based on the portion of the semiconductor device that is disposed below source contact 22. For example, the portion of source contact 22 that is disposed above body contact region 44 is referred to herein as the body contact portion of source contact 22. Similarly, the portion of source contact 22 that is disposed above source contact region 42 of MOSFET device 10 is referred to herein as the source contact portion of source contact 22.

[0034] As illustrated schematically in Figure 3, various regions of MOSFET device 10 each have an associated resistance, with the total resistance of MOSFET device 10 (e.g., on-state resistance, Rds(on)) being expressed as the sum of each of these resistances. For example, as illustrated in Figure 3, the on-state resistance Rds(on) of MOSFET device 10 can be approximated as the sum of resistance Rs30 (e.g., the resistance of source region 20 and source contact 22), resistance Rch32 (e.g., the inversion channel resistance of channel region 28 illustrated in Figure 3), resistance Racc34 (e.g., the resistance of the accumulation layer between dielectric layer 24 and the portion of drift region 16 disposed between well regions 18), resistance RJFET36 (e.g., the resistance of the non-depleted neck region between well regions 18), resistance Rdrift38 (e.g., the resistance for drift region 16), and substrate resistance 40. It should be noted that the resistances illustrated in FIG. 3 are not intended to be exhaustive, and other resistances (e.g., drain contact resistance, diffusion resistance, etc.) may potentially be present within the MOSFET device 10.

[0035] 3 may dominate the conduction losses of the MOSFET device 10, and addressing these factors can have a significant impact on the on-state resistance Rds(on). For example, in devices where the drift resistance 38, substrate resistance 40, and contact resistance are negligible, such as low voltage devices or devices that suffer from low inversion layer mobility (e.g., SiC devices), the channel resistance (Rch 32) may account for a significant portion of the device's conduction losses.

[0036] By way of further example, in medium and high voltage devices, the JFET region resistance (RJFET 36) can account for a significant portion of the total conduction losses. In some cases, the MOSFET channel and JFET can comprise approximately 55% of the on-state resistance of a typical semiconductor device.

[0037] 4, a chart is shown illustrating an example of the relative resistance contributions of various regions of the MOSFET device structure of FIG. 2. The relative resistance for each region is plotted as a function of distance (e.g., path length) of the respective region. It can be seen that the inversion channel resistance Rch32 of the channel region 28 may be the largest contributor to the on-state resistance Rds(on) of the MOSFET device 10, while the resistance Rs30 (e.g., the resistance of the source region 20 and the resistance of the source contact 22) and the substrate resistance Rsub40 (e.g., the resistance of the substrate layer 14) contribute the least resistance to the on-state resistance Rds(on) of the MOSFET device 10.

[0038] FIG. 5 illustrates a top view of a conventional semiconductor layer 2 including a MOSFET device structure 41 having a conventional striped cell layout (i.e., a non-cellular layout). The illustrated striped layout of FIG. 5 includes a channel region 28, a source region 20, a source contact region 42, a body contact region 44, and a JFET region 29. It can be appreciated that the set of source contact regions 42 and the set of body contact regions 44 can be formed as continuous stripes along the surface of the semiconductor for the illustrated striped layout of FIG. 5. In terms of dimensions, the MOSFET device structure 41 can be described as having a particular channel length 43, a distance 45 from the channel region 28 to the ohmic region, a width 47 of the ohmic region, and a width 49 of the JFET region. While the conventional striped cell layout illustrated in FIG. 5 exhibits good reliability (e.g., long-term high-temperature performance), the relatively large channel resistance (Rch) 32 and JFET resistance (RJFET) 36 (as shown in FIG. 3) of the MOSFET device structure 41 result in a relatively large on-state resistance Rds(on), which degrades the electrical performance of the device.

[0039] Another example of a conventional device layout is illustrated in FIG. 6, which is a top or plan view of a striped ladder device layout 50 with segmented source / body contacts (i.e., a non-cellular layout). The illustrated striped ladder device layout 50 includes a channel region 28, a source region 20, a set of segmented source / body contacts 46 (including body contact region 44 and source contact region 42), and a JFET region 29. FIG. 6 further illustrates dimensions of the illustrated striped ladder device layout 50, including a channel length 43, a channel-to-ohmic region distance 45, an ohmic region width 47, a JFET region width 49, a source contact region segment length 51, a body contact region segment length 52, a subset of a device area 53 represented by a dotted rectangle 53, a JFET area 54 (represented by a cross-hatched area 54) within the subset of device area 53, and a width 55 of the channel within the subset of JFET area 54.

[0040] For further comparison, another example of a conventional device layout is illustrated in Figure 7, which is a top or plan view of a square cellular device layout 60 that does not include segmented source / body contacts. Square cellular device layout 60 includes channel region 28, source region 20, body contact region 44, source contact region 42, and JFET region 29. Figure 7 further illustrates the dimensions of square cellular device layout 60 for the illustrated cell of square cellular device layout 60, including channel length 62, channel-to-ohmic region distance 63, ohmic region width 64, JFET region width 65, body contact region width 67, device cell area represented by dotted rectangle 68, and JFET area per cell represented by cross-hatched area 69.

[0041] While the device layout illustrated in FIG. 7 may enable higher Rds(on) relative to a striped cell layout such as that illustrated in FIG. 5, it is recognized that such a design may have a significantly higher electric field in the portion of the JFET region 29 between the corners of the channel regions 28 of adjacent device cells under blocking conditions. In SiC MOS devices, the electric field in the dielectric layer 24 disposed over the JFET region 29 (illustrated in FIGS. 2 and 3) may be approximately 10 times larger than that in Si devices when the device cells are operated under reverse bias. While SiC generally tolerates higher electric fields, the dielectric layer 24 may experience breakdown over long periods of operation, creating reliability issues in SiC device cells.

[0042] With the foregoing in mind, the present embodiments are directed to semiconductor device designs and layouts that enable improved semiconductor device characteristics. In particular, aspects described herein can advantageously reduce the resistance of MOSFET device components to reduce or minimize the device's on-state conduction losses (e.g., minimize the on-state resistance Rds(on)). For example, non-limiting aspects can include cellular device designs and layouts that implement increased MOSFET channel region 28 widths or increased channel region 28 densities over conventional designs to reduce channel resistance (Rch32) and thereby reduce on-state conduction losses.

[0043] As described in more detail below, non-limiting embodiments as described herein enable a reduction in device pitch, thus increasing the channel perimeter per unit area for MOSFET devices, or increasing the density of channel regions 28. Additionally, in non-limiting embodiments, channel regions 28 can be oriented to extend longitudinally along a first direction of lower resistance across the semiconductor layer (i.e., horizontally when looking at the page as shown in the figures), thereby further reducing the on-state resistance Rds(on).

[0044] FIG. 8 depicts a top or plan view illustrating a system 70 (e.g., a semiconductor device such as a MOSFET) including an array of semiconductor device cells 72, according to a non-limiting embodiment. As described in more detail herein, the semiconductor device cells 72 can be configured to facilitate reducing the on-state resistance Rds(on) of the MOSFET device 10. Each semiconductor device cell 72 can be disposed on a first surface 4 of a semiconductor layer 2 (e.g., a silicon carbide (SiC) semiconductor layer). The first surface 4 defines a series of striations 19 (shown in FIG. 1B ), which extend in a first direction 23, e.g., along the y-axis. Returning to FIG. 8 , the semiconductor device cells 72 can define a vertical pitch or first span D1 extending across the extent of the first surface 4 of the semiconductor device cells 72, e.g., in the first direction 23, e.g., along the y-axis. The semiconductor device cells 72 may also define a horizontal pitch or second span D2 extending across the extent of the first face 4 of the semiconductor device cells 72 in a second direction 25, for example along the x-axis (i.e., perpendicular to the first direction 23). It will be appreciated that the area of ​​the semiconductor device cells 72 may be determined based on the product of the first span D1 and the second span D2.

[0045] In a non-limiting embodiment, the body contact region 44 of the semiconductor device cell 72 may be surrounded by a source region 20 of a first conductivity type (e.g., n-type or p-type). The periphery of the source region 20 may be surrounded by a well region 18 of a second conductivity type (e.g., the other of n-type or p-type). It can be understood that the portion of the source region 20 disposed below the source contact 22 can function as part of the source contact region 42 of the semiconductor device cell 72.

[0046] The semiconductor device cell 72 may include a drift region (not shown) having a first conductivity type. A well region 18 having a second conductivity type (e.g., p-type or n-type) may be disposed adjacent to the drift region. In embodiments, the well region 18 may comprise a set of elongated well region segments 17 spaced apart from one another. Each well region segment 17 may define a respective second or well region segment longitudinal axis 17a extending in the first direction 23. For example, as shown, in some embodiments, the longitudinal axis 17a of each well region segment may extend across the first surface 4, e.g., along the y-axis. In non-limiting embodiments, the longitudinal axes 17a of two or more well region segments may be generally parallel to one another. A source region 20 may be disposed directly adjacent to and surrounded by the well region 18.

[0047] A channel region 28 having the second conductivity type can be disposed proximate the first face 4. The channel region 28 can include a set of elongated first channel region segments 28a spaced apart from one another and having first longitudinal axes 31a extending in the first direction 23. In a non-limiting embodiment, the first longitudinal axes 31a of two or more channel region segments can be generally parallel to one another. Additionally, in some embodiments, the first longitudinal axes 31a of two or more channel region segments can be generally parallel to the longitudinal axes 17a of two or more well region segments. In a non-limiting embodiment, the channel region 28 can further include a set of elongated second channel region segments 28b spaced apart from one another and having second longitudinal axes 31b extending in the second direction 25. In a non-limiting embodiment, the first channel region segments 28a and the second channel region segments 28b can each define at least a portion of the periphery of the channel region 28.

[0048] Each first channel region segment 28a can have a first length L1 extending in a first direction 23 along a respective first longitudinal axis 31a and a first width W1 extending in a second direction 25. The first length L1 is greater than the first width W1. In addition, each second channel region segment 28b can have a second length L2 extending in a second direction 25 along a respective second longitudinal axis 31b and a second width W2 extending in the first direction 23. In a non-limiting embodiment, the second length L2 is greater than the second width W2. In addition, the second length L2 is less than the first length L1.

[0049] In a non-limiting embodiment, the first length L1 of each first channel region segment 28 a is greater than the second length L2 of each second channel region segment 28 b. In an embodiment, a first sum of the first lengths L1 of the set of first channel region segments 28 a on the semiconductor device cell 72 is greater than a second sum of the second lengths L2 of the second channel region segments 28 b on the semiconductor device cell 72. Additionally or alternatively, a third sum of the first lengths L1 of the set of first channel region segments 28 a and the second widths W2 of the set of second channel region segments 28 b is greater than a fourth sum of the second lengths L2 of the set of second channel region segments 28 b and the first widths W1 of the set of first channel region segments 28 a.

[0050] In an embodiment, the second electrical resistance R2 along the second direction 25 across the first face 4 is greater than the second electrical resistance R2 along the first direction 23 across the first face 4. Thus, in a non-limiting embodiment, the first channel region segment 28 a and the second channel region segment 28 b are arranged to maximize the portion of the channel region 28 that extends in the first direction 23 across the first face 4 and minimize the portion of the channel region 28 that extends in the second direction 25 to reduce or minimize the effective electrical resistance of the channel region 28 in operation. In this manner, the first channel region segment 28 a and the second channel region segment 28 b cooperate to provide a purely lower resistance path in the first direction 23 across the first face 4 of the semiconductor device cell 72 than in the second direction 25.

[0051] In a non-limiting embodiment, pairs of immediately adjacent first channel region segments 28a can be spaced apart from one another along their respective longitudinal axes 31a to define gaps 33 therebetween. Each gap 33 can define a respective third span D3 in the second direction 25 (i.e., perpendicular to the respective first longitudinal axes 31a). In a non-limiting embodiment, each well region segment 17 can be disposed within the gaps 33, and the longitudinal axes 17a of each well region segment of the well can be parallel to the respective first longitudinal axes 31a.

[0052] Additionally, the first channel region segments 28 a may be at least partially surrounded by well regions 18. For example, in non-limiting embodiments, the periphery of the first channel region segments 28 a may be cooperatively surrounded by respective well region segments 17 and JFET regions 29. As illustrated in FIG. 8 , the peripheries of the sets of first channel region segments 28 a, the sets of well region segments 17, and portions of the JFET regions 29 may be arranged to define a series of alternating substantially parallel elongated bands or stripes. Thus, non-limiting embodiments may increase the density of conducting channel regions 28 per unit cell area while reducing the electrical resistance to current flow across the channel regions 28 in the first direction 23 over conventional techniques.

[0053] In a non-limiting embodiment, body contact region 44 having the second conductivity type can be disposed over a portion of well region 18. In a non-limiting embodiment, body contact region 44 can be disposed substantially in the center of source region 20 defined by first surface 4.

[0054] In a non-limiting embodiment, the well region 18, the source region 20, and the channel region 28 can cooperatively or cumulatively define a first span D1 or pitch extending across the first face 4 of the semiconductor device cell 72. In a non-limiting embodiment, the first span D1 can be substantially parallel to the first longitudinal axis 31 a of the first channel region segment or the longitudinal axis 17 a of the well region segment, or both. In an embodiment, the first span D1 can extend substantially the entire length of the first face 4 of the semiconductor device cell 72. In a non-limiting embodiment, each well region segment 17 can define a respective third span D3 or pitch extending across the first face 4, e.g., along the y-axis.

[0055] In non-limiting embodiments, the first span D1 can be in the range of 6 microns and 18 microns. In some non-limiting embodiments, the third span D3 can be in the range of 0.3 microns to 1.6 microns. In still other non-limiting embodiments, the third span D3 can be in the range of 5% to 20% of the first span D1. Other embodiments are not so limited, and the dimensions of the first span D1 or the third span D3, or both, can be varied as desired for various applications without departing from the scope of the disclosure herein.

[0056] Regardless of the dimensions of the first span D1 and the third span D3 or their relative dimensions to one another or both, the specific dimensions of the first span D1 and the third span D3 and the longitudinal orientation of the first channel region segment 28a are arranged or defined for the specific purpose of lowering the resistance contribution of the channel region 28 (i.e., making the resistance contribution of the inversion channel resistance relatively high), even at the expense of a resulting relatively small increase in the resistance contribution of the well region 18.

[0057] Figure 9 depicts a top or plan view illustrating an arrangement of a system 80 including semiconductor device cells 72 according to another non-limiting embodiment. The non-limiting embodiment of Figure 9 is similar to the embodiment depicted in Figure 8, with one difference that the semiconductor device cells 72 are arranged in a cellular-type layout. Concurrent reference is also made to Figure 10, which depicts a cross-sectional view of the semiconductor device cells 72 of Figure 8 taken along line IX-IX.

[0058] 9 and 10 , the semiconductor device cells 72 are configured to facilitate reducing the on-state resistance Rds(on) of the system 80. Each semiconductor device cell 72 is disposed on a first surface 4 of a semiconductor layer 2 (e.g., a SiC semiconductor layer 2). The first surface 4 defines a series of striations 19 (shown in FIG. 1B ), which may extend in a first direction 23, e.g., along the y-axis. Returning to FIG. 8 , the semiconductor device cells 72 may define a horizontal pitch or first span D1 extending across the extent of the first surface 4 of the semiconductor device cells 72, e.g., in the first direction 23 along the y-axis. The semiconductor device cells 72 may also define a vertical pitch or second span D2 extending across the extent of the first surface 4 of the semiconductor device cells 72 in a second direction 25, e.g., along the x-axis. It will be appreciated that the area of ​​the semiconductor device cell 72 may be determined based on the product of the first span D1 and the second span D2.

[0059] A dielectric layer 24 (eg, a gate insulating layer) is disposed on a portion of the first surface 4 of the semiconductor layer 2, and a gate electrode 26 is disposed on the dielectric layer 24.

[0060] The body contact region 44 of the semiconductor device cell 72 is surrounded by a source region 20 of a first conductivity type (e.g., n-type or p-type). The periphery of the first conductivity type source region 20 may be surrounded by a well region 18 of a second conductivity type. The portion of the source region 20 disposed below the source contact 22 may function as part of the source contact region 42 of the semiconductor device cell 72. The semiconductor device cell 72 may include a drift region 16 having the first conductivity type.

[0061] A well region 18 having a second conductivity type can be disposed adjacent to the JFET region 29. In embodiments, the well region 18 can include a set of well region segments 17 spaced apart from one another and defining a longitudinal axis 17a of each well region segment. Each well region segment 17 can define its longitudinal axis 17a extending in the first direction 23. For example, as shown, in some embodiments, the longitudinal axis 17a of each well region segment can extend across the first surface 4, e.g., along the y-axis. In non-limiting embodiments, the longitudinal axes 17a of two or more well region segments can be generally parallel to one another. A source region 20 can be disposed directly adjacent to and surrounded by the well region 18.

[0062] A channel region 28 having the second conductivity type is disposed proximate the first face 4. The channel region 28 comprises a set of elongated first channel region segments 28a spaced apart from one another and having first longitudinal axes 31a extending in the first direction 23. In a non-limiting embodiment, the first longitudinal axes 31a of two or more channel region segments can be generally parallel to one another. Additionally, in some embodiments, the first longitudinal axes 31a of two or more channel region segments can be generally parallel to the longitudinal axes 17a of two or more well region segments. In a non-limiting embodiment, the channel region 28 further comprises a set of elongated second channel region segments 28b spaced apart from one another and having second longitudinal axes 31b extending in the second direction 25. In a non-limiting embodiment, the first channel region segments 28a and the second channel region segments 28b each define at least a portion of the periphery of the channel region 28.

[0063] Each first channel region segment 28a has a respective first length L1 extending in a first direction 23 along the longitudinal axis 31a of the respective first channel region segment and a first width W1 extending in a second direction 25. The first direction 23 may be perpendicular to the second direction 25. The first length L1 is greater than the first width W1. In addition, each second channel region segment 28b has a second length L2 extending in the second direction 25 along the longitudinal axis 31b of the respective second channel region segment and a second width W2 extending in the first direction 23. In a non-limiting embodiment, the second length L2 is greater than the second width W2. In addition, the second length L2 is less than the first length L1.

[0064] In a non-limiting embodiment, the first length L1 of each first channel region segment 28 a is greater than the second length L2 of each second channel region segment 28 b. In an embodiment, a first sum of the first lengths L1 of the set of first channel region segments 28 a on the semiconductor device cell 72 is greater than a second sum of the second lengths L2 of the second channel region segments 28 b on the semiconductor device cell 72. Additionally or alternatively, a third sum of the first lengths L1 of the set of first channel region segments 28 a and the second widths W2 of the set of second channel region segments 28 b is greater than a fourth sum of the second lengths L2 of the set of second channel region segments 28 b and the first widths W1 of the set of first channel region segments 28 a.

[0065] In an embodiment, the second electrical resistance R2 along the second direction 25 across the first surface 4 is greater than the second electrical resistance R2 along the first direction 23 across the first surface 4. Thus, in a non-limiting embodiment, the first channel region segment 28 a and the second channel region segment 28 b are arranged to maximize the portion of the channel region 28 that extends in the first direction 23 across the first surface 4 and minimize the portion of the channel region 28 that extends in the second direction 25 to reduce or minimize the effective electrical resistance of the channel region 28 in operation. In this manner, the first channel region segment 28 a and the second channel region segment 28 b cooperate to provide a purely lower resistance path across the semiconductor layer surface 4 in the first direction 23 through the channel region 28 than in the second direction 25.

[0066] In a non-limiting embodiment, one or more respective first channel region segments 28a can be spaced apart from another immediately adjacent first channel region segment 28a to define a gap 33 therebetween. Each gap 33 can define a respective third span D3 extending in the second direction 25 (i.e., perpendicular to the longitudinal axis 31a of the respective first channel region segment). In a non-limiting embodiment, each well region segment 17 can be disposed within the gap 33, such that the longitudinal axis 17a of each well region segment can be parallel to the first longitudinal axis 31a of the respective first channel region segment. The periphery of each first channel region segment 28a can be at least partially surrounded by a well region 18. For example, in a non-limiting embodiment, a channel region segment 28a can be cooperatively surrounded by a respective well region segment 17 and a JFET region 29. The sets of first channel region segments 28 a, the sets of well region segments 17, and portions of JFET region 29 can be arranged to define a series of alternating substantially parallel bands or stripes. In this sense, as shown, semiconductor device cell 72 can be described as disposing well region segments 17 on opposite sides of first channel region segments 28 a. Thus, non-limiting embodiments can minimize cell size to increase the density of conducting channel regions 28 per unit cell, while reducing electrical resistance to current flow across channel regions 28 in first direction 23.

[0067] In some non-limiting embodiments, body contact region 44 having the second conductivity type can be disposed over a portion of well region 18. Body contact region 44 can be disposed substantially in the center of the plane of source region 20 defined by first surface 4.

[0068] In a non-limiting embodiment, the well region 18, the source region 20, and the channel region 28 can cooperatively or cumulatively define a first span D1 or pitch extending across the first face 4 of the semiconductor device cell 72, e.g., along the y-axis. In a non-limiting embodiment, the longitudinal axis 31 of the channel region segment and the longitudinal axis 17a of the well region segment can be substantially parallel. In an embodiment, the first span D1 can span substantially the entire length of the first face 4 of the semiconductor device cell 72. In a non-limiting embodiment, each well region segment 17 can define a respective third span D3 or pitch extending across the first face 4 in a second direction 25, e.g., along the x-axis.

[0069] In non-limiting embodiments, the first span D1 can be in the range of 6 microns and 18 microns. In some non-limiting embodiments, the third span D3 can be in the range of 0.3 microns and 1.6 microns. In still other non-limiting embodiments, the third span D3 can be in the range of 5% to 20% of the first span D1. Other embodiments are not so limited, and the dimensions of the first span D1 or the third span D3, or both, can be varied as desired for various applications without departing from the scope of the disclosure herein.

[0070] Regardless of the dimensions of the first span D1 and the third span D3 or their relative dimensions to one another, or both, the specific dimensions of the first span D1 and the third span D3 and the longitudinal orientation of the first channel region segment 28a and the second channel region segment 28b are arranged or defined with the specific purpose of lowering the resistive contribution of the channel region 28 (i.e., making the resistive contribution of the inversion channel resistance relatively high), even at the expense of a resulting relatively small increase in the resistive contribution of the well region 18. In particular, the present embodiment lowers device state losses (e.g., minimizes on-state resistance Rds(on)) by increasing the channel width and / or increasing the channel density, as well as by arranging the channel orientation across the cell to reduce the channel resistance.

[0071] Unless otherwise stated, different features and structures of various embodiments can be used in combination with each other as desired. The fact that one embodiment may not be shown in all embodiments is not meant to be interpreted as being unable to do so, but is done for the sake of brevity. Thus, various features of different embodiments can be mixed and matched as desired to form new embodiments, regardless of whether the new embodiments are explicitly described. Any combination or permutation of features described herein is covered by the present disclosure.

[0072] This description uses examples to disclose aspects of the disclosure, including the best mode, and also to enable any person skilled in the art to practice aspects of the disclosure, including making and using any devices or systems and practicing any incorporated methods. The scope of the disclosure is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that differ from the literal language of the claims, or if they include equivalent structural elements that differ only insignificantly from the literal language of the claims.

[0073] The features disclosed in the above description, in the following claims, and / or in the accompanying drawings can, both individually and in any combination thereof, be relevant to realise embodiments in various forms thereof.

[0074] Various features, aspects, and advantages of the present disclosure may be embodied in any permutation of the aspects of the present disclosure, including, but not limited to, the following technical solutions as defined in the enumerated aspects.

[0075] 1. A semiconductor device comprising a semiconductor device cell (72), the semiconductor device cell (72) comprising: a series of parallel striations (19) on the semiconductor device cell (72), the striations (19) extending in a first direction (23) across a surface of a semiconductor layer (2), the semiconductor layer (2) including a drift region (16) having a first conductivity type; well regions (18) having a second conductivity type disposed adjacent to a surface (4) of the semiconductor layer, the well regions (18) defining a set of well region segments (17); and source regions (20) having the first conductivity type disposed adjacent to the well regions (18), the source regions (20) being surrounded at their peripheries by the well regions (18). a region (20); and a channel region (28) having a second conductivity type and proximate to a surface (4) of the semiconductor layer, the channel region (28) defining a set of elongated channel region segments (28a) and a set of elongated second channel region segments (28b), each first channel region segment (28a) having a respective first length (L1) extending in a first direction (23), and each second channel region segment (28b) having a respective second length (L2) extending in a second direction (25) perpendicular to the first direction (23), the first length (L1) being greater than the second length (L2), and the periphery of the channel region (28) being surrounded by a well region (18).

[0076] 2. A semiconductor device cell according to any preceding paragraph, wherein a first electrical resistance (R1) across a plane of the semiconductor layer (2) in a first direction (23) is less than a second electrical resistance (R2) in a second direction (25) across the plane of the semiconductor layer (2).

[0077] 3. The semiconductor device cell of any preceding paragraph, wherein a first sum of the first lengths of the set of first channel region segments (28a) is greater than a second sum of the second lengths of each of the set of second channel region segments (28b).

[0078] 4. The semiconductor device cell of any preceding paragraph, wherein each first channel region segment (28a) further comprises a first width (W1) extending in the second direction (25), and wherein the first length (L1) is greater than the first width (W1).

[0079] 5. The semiconductor device cell of any preceding paragraph, wherein each second channel region segment (28b) further comprises a second width (W2) extending in the first direction (23), and wherein the second length (L2) is greater than the second width (W2).

[0080] 6. The semiconductor device cell of any preceding paragraph, wherein a third sum of the first length of each of the set of first channel region segments (28a) plus the second width of each of the set of second channel region segments (28b) is greater than a fourth sum of the second length of each of the set of second channel region segments (28b) plus the first width of each of the set of first channel region segments (28a).

[0081] 7. A semiconductor device cell according to any preceding paragraph, wherein the well region (18), the source region (20), and the channel region (28) cooperatively define a first span (D1) extending across the face of the semiconductor layer (2).

[0082] 8. A semiconductor device cell according to any preceding paragraph, further comprising a JFET region (29), a portion of the JFET region (29) being surrounded by the channel region (28).

[0083] 9. The semiconductor device cell of any preceding paragraph, wherein pairs of immediately adjacent channel region segments (28a) are spaced apart from one another to define gaps (33) therebetween, the gaps (33) defining respective third spans (D3) and extending in the second direction (25), and wherein each well region segment (17) is disposed within the gaps (33).

[0084] 10. The semiconductor device cell of any preceding paragraph, wherein the first span (D1) is within the range of 6 microns and 18 microns.

[0085] 11. The semiconductor device cell of any preceding paragraph, wherein the third span (D3) is within the range of 0.3 microns to 1.6 microns.

[0086] 12. The semiconductor device cell of any preceding paragraph, wherein the third span (D3) is within a range between 8% and 15% of the first span (D1).

[0087] 13. The semiconductor device cell of any preceding paragraph, wherein each well region segment (17) defines a respective second longitudinal axis (17a), the first longitudinal axis (31) and the second longitudinal axis (17a) being parallel to each other.

[0088] 14. A semiconductor device cell according to any preceding paragraph, wherein the sets of channel region segments (28a), the sets of well region segments (17), and portions of the JFET region (29) are arranged to define a series of alternating substantially parallel bands.

[0089] 15. The semiconductor device cell of any preceding paragraph, further comprising a body contact region (44) having the second conductivity type disposed over a portion of the well region (18), the body contact region (44) being disposed substantially centrally in the plane of the source region defined by the surface (4).

[0090] 16. A semiconductor device according to any preceding paragraph, wherein the channel region defines a purely lower resistance path across the face of the semiconductor layer in a first direction than in a second direction.

[0091] 17. A semiconductor device further comprising a set of semiconductor device cells, the set of semiconductor device cells comprising: a semiconductor layer having a surface thereon defining a series of parallel striations, the semiconductor layer extending in a first direction across the surface of the semiconductor layer, the semiconductor layer including a drift region having a first conductivity type; a well region having a second conductivity type disposed proximate the surface of the semiconductor layer, the well region defining a set of well region segments; and a source region having the first conductivity type disposed adjacent the well region, the source region being surrounded by the well region. 10. The semiconductor device of any preceding claim, comprising: a source region; and a channel region having a second conductivity type proximate the surface of the semiconductor layer, the channel region defining a set of elongated first channel region segments and a set of elongated second channel region segments, each first channel region segment having a respective first length extending in a first direction and each second channel region segment having a respective second length extending in a second direction perpendicular to the first direction, the first length being greater than the second length, and the channel region being surrounded on its periphery by a well region.

[0092] 18. The semiconductor device of any preceding paragraph, wherein a fifth sum of the first lengths of each of the set of first channel region segments is greater than a sixth sum of the second lengths of each of the set of second channel region segments.

[0093] 19. The semiconductor device of any preceding paragraph, wherein each first channel region segment further comprises a first width extending in the second direction, the first length being greater than the first width.

[0094] 20. The semiconductor device of any preceding paragraph, wherein each second channel region segment further comprises a second width extending in the first direction, the second length being greater than the second width.

[0095] 21. The semiconductor device of any preceding paragraph, wherein a seventh sum of the first length of each of the first set of channel region segments plus the second width of each of the second set of channel region segments is greater than an eighth sum of the second length of each of the second set of channel region segments plus the first width of each of the first set of channel region segments. [Explanation of symbols]

[0096] 2. Semiconductor layer 4. First surface, semiconductor layer surface 6 Second Side 8 Crystal Orientation 9. SiC wafers 10 MOSFET devices 12 Drain Contact 14 substrate layers 16 Drift Region 17 well area segments 17a Second Longitudinal Axis 18 well area 19 striations, steps 20 Source Region 21 Striation Longitudinal Axis 22 Source Contact 23 First Direction 24 dielectric layer 25 Second Direction 26 gate electrode 28 Channel Region 28a First channel region segment 28b second channel region segment 29 JFET area 30 Source region resistance 31 first longitudinal axis 31a first longitudinal axis 31b Second Longitudinal Axis 32 Channel resistance, inversion channel resistance 33 Gap 34 Resistance 36 JFET area resistance, JFET resistance 38 Drift Resistance 40 Substrate resistance 41 MOSFET device structure 42 Source contact area 43 Channel Length 44 Main body contact area, main body area 45 distance 46 Source / body contact 47 width 49 width 50 Stripe Ladder Device Layout 51 Segment Length 52 Segment Length 53 Device Area 54 JFET area 55 width 60 Square Cellular Device Layout 62 channel length 63 distance 64 width 65 width 67 width 68 Device Cell Area 69 Crosshatched Area 70 Systems 72 Semiconductor device cells 80 Systems D1 First span, first axis length D2 Second span D3 Third Span L1 First length L2 Second length W1 First width W2 Second width R1 First electrical resistance R2 Second electrical resistance

Claims

1. A semiconductor device comprising a semiconductor device cell (72), the semiconductor device cell (72) comprising: a series of parallel striations (19) on the semiconductor device cell (72), the striations (19) extending in a first direction (23) across a semiconductor layer surface (4) of the semiconductor layer (2), the semiconductor layer (2) including a drift region (16) having a first conductivity type; a well region (18) having a second conductivity type disposed adjacent to the semiconductor layer surface (4), the well region (18) defining a set of well region segments (17); a source region (20) having the first conductivity type disposed adjacent to the well region (18), the periphery of the source region (20) being surrounded by the well region (18); a channel region (28) having the second conductivity type and proximate to the semiconductor layer surface (4), the channel region (28) defining a first set of elongated channel region segments (28a) and a second set of elongated second channel region segments (28b), each first channel region segment (28a) of the first set having a respective first length (L1) extending in the first direction (23), and each second channel region segment (28b) of the second set having a respective second length (L2) extending in a second direction (25) perpendicular to the first direction (23); wherein the first length (L1) is greater than the second length (L2), and the periphery of the channel region (28) is surrounded by the well region (18).

2. 2. The semiconductor device of claim 1, wherein a first electrical resistance (R1) across the semiconductor layer surface (4) of the semiconductor layer (2) in the first direction (23) is less than a second electrical resistance (R2) in the second direction (25) across the semiconductor layer surface (4) of the semiconductor layer (2).

3. 2. The semiconductor device of claim 1, wherein a first sum of the first lengths (L1) of the respective ones of the set of first channel region segments (28a) is greater than a second sum of the second lengths (L2) of the respective ones of the set of second channel region segments (28b).

4. A semiconductor device as described in claim 1, wherein each of the first channel region segments (28a) further has a first width (W1) extending in the second direction (25), and the first length (L1) is greater than the first width (W1).

5. A semiconductor device as described in claim 4, wherein each of the second channel region segments (28b) further has a second width (W2) extending in the first direction (23), and the second length (L2) is greater than the second width (W2).

6. 6. The semiconductor device of claim 5, wherein a third sum, which is the sum of the first length (L1) of each of the set of first channel region segments (28 a) and the second width (W2) of each of the set of second channel region segments (28 b), is greater than a fourth sum, which is the sum of the second length (L2) of each of the set of second channel region segments (28 b) and the first width (W1) of each of the set of first channel region segments (28 a).

7. 2. The semiconductor device of claim 1, wherein the well region (18), the source region (20), and the channel region (28) cooperatively define a first span (D1) extending across the semiconductor layer surface (4).

8. A semiconductor device as described in claim 1, wherein the series of parallel striations (19) are the result of a misalignment between the crystal orientation of the semiconductor layer (2) and the semiconductor layer surface (4).

9. 8. The semiconductor device of claim 7, wherein a pair of immediately adjacent first channel region segments (28a) are spaced apart from one another to define gaps (33) therebetween, the gaps (33) defining respective third spans (D3) and extending in the second direction (25), and wherein each well region segment (17) is disposed within the gaps (33).

10. 10. The semiconductor device of claim 9, wherein the first span (D1) is within the range of 6 microns and 18 microns.

11. 11. The semiconductor device of claim 10, wherein the third span (D3) is in the range of 0.3 microns to 1.6 microns.

12. The semiconductor device of claim 10, wherein the third span (D3) is in the range between 8% and 15% of the first span (D1).

13. A first channel region segment (28a) having a first longitudinal axis (31a) extending in said first direction (23); 10. The semiconductor device of claim 9, wherein each well region segment (17) defines a respective second longitudinal axis (17a), said first longitudinal axis (31a) and second longitudinal axis (17a) being parallel to each other.

14. A semiconductor device as described in claim 9, wherein the set of first channel region segments (28a), the set of well region segments (17), and portions of the JFET region (29) are arranged in a staggered manner to define a series of substantially parallel bands.

15. 2. The semiconductor device of claim 1, further comprising a body contact region (44) having the second conductivity type disposed over a portion of the well region (18), the body contact region (44) being disposed substantially in the center of a plane of the source region defined by the semiconductor layer surface (4).

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