Pixel array, image sensor, and method of operating a pixel array

Abstract

A pixel array (10) is provided that is configured for a high sensitivity mode and a low sensitivity mode, respectively. The photodiode (20) is configured to convert electromagnetic radiation into a respective charge signal, and the transfer gate (30) is configured to transfer the respective charge signal to the capacitance (40). The reset gate (50) is configured to reset the capacitance. The amplifier (60) is configured to generate a respective amplified signal, which is a low sensitivity signal or a high sensitivity signal, respectively. The low sensitivity signal and the high sensitivity signal are based on a common noise level. A first capacitor (70) coupled to the first switch (90) is configured to store the high sensitivity signal, and a second capacitor (80) coupled to the second switch (100) is configured to store the low sensitivity signal. Additionally, an image sensor (200), an optoelectronic device (300), and a method for operating the pixel array are provided.

Description

[Technical Field]

[0001] Priority Claims and Cross-References This patent application claims priority to U.S. Provisional Application No. 63 / 263,861, filed November 10, 2021, and German Application No. 102021120779.7, filed August 10, 2021, which are incorporated herein by reference in their entireties.

[0002] The present invention relates to pixel arrays, image sensors, optoelectronic devices, and methods for operating pixel arrays. [Background technology]

[0003] CMOS image sensors are used in a wide range of applications, such as camera modules, smartphones, tablet computers, and laptops. For some applications, a high dynamic range (HDR), e.g., greater than 85 dB, is required. The dynamic range (DR) is limited on the one hand by the noise floor in low-light conditions and on the other hand by saturation effects in high-light conditions.

[0004] To address the saturation problem, several techniques have been developed, which can be classified into linear response techniques and nonlinear response techniques. For example, logarithmic compression, knee compression, timestamp conversion, and light-to-frequency conversion belong to the nonlinear response techniques. Linear response techniques can be further classified into multiple exposure techniques and single exposure techniques. Multiple exposure techniques include methods using multiple frames with different integration times, or methods using line interleaving or pixel interleaving with different integration times. Single exposure techniques include, for example, multiple gain readout or multiple sensitivity combining.

[0005] Most available DR techniques are designed for rolling shutter pixels, but suffer from the problem that they are not suitable for global shutters. In rolling shutter mode, pixels of a pixel matrix are illuminated by a light source. During illumination, the pixels are sequentially exposed and read out row by row. This means that the pixel matrix is ​​illuminated during the entire readout process. While rolling shutter mode enables high resolution of the image sensor, it can come with other drawbacks, such as long illumination times and dynamic or color artifacts, especially when combined with one of the aforementioned DC techniques.

[0006] In global shutter mode, all pixels in the pixel matrix are exposed to light for the same time period. Therefore, a significantly shorter illumination time is required than in rolling shutter mode. At the end of the integration time, the charge transfer operation for all rows of the pixel matrix occurs simultaneously. The signal is stored in pixel-level memory and then read out. Known global shutter pixel arrays, including those using one of the aforementioned DR techniques, suffer from the problems of requiring additional circuitry and having a large pixel pitch. Summary of the Invention [Problem to be solved by the invention]

[0007] The object to be achieved is to provide a pixel array having a high dynamic range and a method for operating such a pixel array. Further objects are to provide an image sensor comprising an array of pixels according to the pixel array and an optoelectronic device comprising such an image sensor. [Means for solving the problem]

[0008] These objects are achieved by the subject matter of the independent claims. Further developments and embodiments are set forth in the dependent claims.

[0009] Here and hereinafter, the terms "pixel array" and "pixel" refer to a light-receiving element that may be arranged, together with other pixels, in a two-dimensional array, also called a matrix. Pixels in the array are arranged in rows and columns. The terms "row" and "column" may be used interchangeably, as they depend only on the orientation of the pixel array. Pixels may also include circuitry for controlling signals to and from the pixels. Thus, pixels may form so-called active pixels. Pixels may receive light in any wavelength range. The term "light" may refer to electromagnetic radiation in general, including, for example, infrared (IR) radiation, ultraviolet (UV) radiation, and visible (VIS) light.

[0010] In one embodiment, the pixel array is configured to convert electromagnetic radiation in a high-sensitivity mode and a low-sensitivity mode, respectively. The pixels include at least one photodiode. The photodiode is configured to convert the electromagnetic radiation into a respective charge signal. The pixel array may, in particular, form a global shutter pixel. The photodiode may, in particular, be a pinned photodiode. The photodiode may be disposed in a substrate, in particular a semiconductor substrate.

[0011] The high-sensitivity mode and the low-sensitivity mode are operating modes of a pixel. The high-sensitivity mode and the low-sensitivity mode can be executed consecutively. This can mean that the high-sensitivity mode and the low-sensitivity mode are executed within one frame. In particular, the low-sensitivity mode can be executed before the high-sensitivity mode. The low-sensitivity mode of a pixel can be provided for high-light conditions, i.e., high illumination. In this case, the charge signal generated by the photodiode is already large and does not need to be "artificially" increased, for example, by high gain, long exposure time, etc. If such a charge signal is increased, for example, by high conversion gain (HCG), saturation effects can occur. For example, saturation can occur because the potential well of the photodiode and / or storage element in the pixel is not large enough to carry all the photo-induced charge carriers. The high-sensitivity mode of a pixel can be provided for low-light conditions, i.e., low illumination. In this case, the charge signal generated by the photodiode is small and should be increased, for example, by high gain or long exposure time, to obtain a good signal-to-noise ratio (SNR).

[0012] In other words, the low sensitivity mode may be an operating mode in which the pixel exposure time is short, in particular shorter than the exposure time of the high sensitivity mode. Alternatively, in the low sensitivity mode, a low conversion gain (LCG) is applied. In yet another alternative, the charge signal is kept small by a small photodiode area or a respective filter. The high sensitivity mode may be an operating mode in which the pixel exposure time is long, in particular longer than the exposure time of the low sensitivity mode. Alternatively, in the high sensitivity mode, the signal gain may be large. In yet another alternative, the charge signal is increased by a large photodiode area or the like. In yet another embodiment, the high sensitivity mode and the low sensitivity mode are realized by barrier modulation of a transfer gate.

[0013] The pixel array further comprises at least one transfer gate disposed between the photodiode and the capacitance, the transfer gate configured to transfer the respective charge signal from the photodiode to the capacitance.

[0014] The transfer gate may be implemented as a transfer switch. For example, the transfer gate may be part of a transfer transistor having a first terminal connected to the photodiode and a second terminal connected to a capacitance. By applying a transfer signal to the transfer gate, the transfer transistor becomes conductive so that charge carriers diffuse from the photodiode toward the capacitance. Thus, the capacitance may be implemented as a floating diffusion capacitance. The capacitance forms a storage element. The capacitance may be referred to as a floating diffusion capacitor. The capacitance may form a doped well in a semiconductor substrate. The capacitance may be configured to convert the respective charge signals into respective voltage signals. It may be desirable to store signals in the voltage domain rather than the charge domain for dark current reasons and to reduce the parasitic light sensitivity (PLS) of the pixel.

[0015] The capacitance includes a termination node electrically coupled to the transfer gate. The transfer gate is therefore disposed between the photodiode and the termination node of the capacitance. The termination node of the capacitance may be referred to as a floating diffusion node, or FD node, or diffusion node. The capacitance further includes a further termination node that may be grounded.

[0016] The capacitance may be the capacitance of the diffusion node. The capacitance may be implemented as a pn junction. In one example, there is no separate capacitor connected to the diffusion node. The capacitance may result solely from, for example, at least one parasitic capacitance. Therefore, the terms "capacitance" and "diffusion node" may be used interchangeably hereinafter.

[0017] The pixel array further comprises a reset gate electrically coupled to the capacitance, in particular, the reset gate is electrically coupled to the FD node, the reset gate is provided for resetting the capacitance.

[0018] The reset gate may be implemented as a reset switch. For example, the reset gate may be part of a reset transistor having a first terminal connected to the pixel power supply voltage and a second terminal connected to the FD node. By applying a reset signal to the reset gate, the reset transistor becomes conductive so that any redundant charge carriers are removed by applying the pixel power supply voltage.

[0019] The pixel array further includes an amplifier. The amplifier is electrically connected to the capacitance, particularly to a termination node, i.e., an FD node, of the capacitance. In particular, an input terminal of the amplifier is electrically connected to the termination node of the capacitance. The amplifier is configured to generate respective amplified signals based on the respective charge signals and the sensitivity modes. The amplified signals are each one of a low sensitivity signal and a high sensitivity signal. The low sensitivity signal and the high sensitivity signal are based on a common noise level. This may mean that the noise levels of the low sensitivity signal and the high sensitivity signal are correlated. The common noise level may be a common noise level in the spatial domain or the time domain. In particular, the common noise level may be a reset noise level.

[0020] A high sensitivity signal may be referred to as a high conversion gain (HCG) signal. A low sensitivity signal may be referred to as a low conversion gain (LCG) signal.

[0021] The amplifiers may form a common-drain amplifier, also known as a source follower. The gate terminal of the source follower is connected to the FD node and serves as the input terminal of the amplifier. The common terminal may be connected to a power supply voltage. Respective amplified signals are generated at the output terminals of the amplifiers. The amplifiers may be used as voltage buffers. The amplifiers may be configured to buffer the signal, thus isolating the FD node from further pixel components. The amplifiers may further be configured to amplify photo-induced charge carriers.

[0022] The amplified signal can be either a low-sensitivity signal or a high-sensitivity signal depending on the respective sensitivity mode the pixel is operating in at each moment. The low-sensitivity signal is based on the video signal and the noise level. The noise level includes temporal noise such as thermal noise and reset noise, and fixed pattern noise (FPN). FPN refers to the fluctuation in the signal between pixels "fixed" at a specific spatial location. Thermal noise is mainly generated by the random, thermally agitated movement of electrons in the conductor. Reset noise refers to the reset operation for the FD node, which needs to be reset every frame before charge integration begins. This reset operation results in sampling noise.

[0023] According to one embodiment of the present disclosure, the high-sensitivity signal may be based on the low-sensitivity signal. Therefore, the high-sensitivity signal is based on the same noise level as the low-sensitivity signal, particularly a common reset noise level and / or a common fixed-pattern noise level. The high-sensitivity signal may include the low-sensitivity signal and an additional video signal. In other words, the noise of the high-sensitivity signal and the noise of the low-sensitivity signal are correlated. Therefore, the low-sensitivity signal can be used as a reference level of the high-sensitivity signal so that the noise of the high-sensitivity signal can be effectively canceled out. This operation may be referred to as correlated double sampling (CDS). Therefore, the high-sensitivity signal can be accessed by CDS so that a pure video signal can be obtained.

[0024] The pixel array further includes a first capacitor configured to store the high-sensitivity signal. The first capacitor may be implemented as a metal-oxide-semiconductor (MOS) capacitor. Alternatively, the first capacitor may be formed as a metal-insulator-metal (MIM) capacitor. The first capacitor includes a termination node and a further termination node. The further termination node may be grounded or connected to a further power supply voltage.

[0025] The pixel array further includes a second capacitor configured to store the low-sensitivity signal. The second capacitor may be implemented as a MOS capacitor or a MIM capacitor. The second capacitor includes a termination node and a further termination node. The further termination node may be grounded or connected to a further power supply voltage.

[0026] The pixel array further includes a first switch disposed between the output terminal of the amplifier and the first capacitor. This can mean that the first switch connects the termination node of the first capacitor to the output terminal of the amplifier. The first switch is provided to transfer each amplified signal to the first capacitor. The first switch may be formed by a first switching transistor. The first switching transistor may have a gate terminal configured to receive a first switch signal that causes the first switching transistor to become conductive so that the amplified signal is transferred. A first terminal of the first switching transistor is connected to the output terminal of the amplifier. A second terminal of the first switching transistor is connected to the termination node of the first capacitor.

[0027] The pixel array further includes a second switch disposed between the output terminal of the amplifier and the second capacitor. This can mean that the second switch connects the termination node of the second capacitor to the output terminal of the amplifier. The second switch is provided to transfer each amplified signal to the second capacitor. The second switch can be formed by a second switching transistor. The second switching transistor can have a gate terminal configured to receive a second switch signal that causes the second switching transistor to become conductive so that the amplified signal is transferred. A first terminal of the second switching transistor can be connected to the output terminal of the amplifier or to the second terminal of the first switching transistor. The second terminal of the second switching transistor is connected to the termination node of the second capacitor.

[0028] To achieve the described functionality of the pixel array, only two capacitors are required. This allows the pixel array to be small. This means that the pixel pitch can be scaled while still incorporating HDR, which in turn reduces cost and module size. For example, if the pixels are arranged in a matrix, the pixel pitch can be less than 2 μm. In addition, the proposed pixel arrangement is compatible with many HDR techniques. Advantageously, the two capacitors store two different signals, a high-sensitivity signal and a low-sensitivity signal. Thus, the dynamic range of the pixel array can be expanded. Furthermore, both the high-sensitivity signal and the low-sensitivity signal can be based on a common noise level, particularly consisting of thermal noise and reset noise. Therefore, the low-sensitivity signal can be used as a reference level for the high-sensitivity signal. This means that the high-sensitivity signal can be accessed by the CDS. Since the high-sensitivity signal is used in low-light conditions, thermal noise is a relevant parameter. Advantageously, thermal noise and reset noise can be effectively suppressed by the CDS. In high-light conditions, the low-sensitivity signal is further processed. Here, thermal noise is less relevant since photon shot noise dominates at high illumination levels.

[0029] In at least one further embodiment, the high-sensitivity signal includes a low-sensitivity signal and an additional video signal. This may mean that the high-sensitivity signal is equal to the low-sensitivity signal plus the additional video signal. The additional video signal may represent a pure video signal without noise. Advantageously, the noise of the high-sensitivity signal is correlated with the noise of the low-sensitivity signal so that CDS can be performed. Therefore, the noise of the high-sensitivity signal can be effectively canceled out.

[0030] In at least one further embodiment, the pixel array further comprises at least one further amplifier, the further amplifier having an input terminal electrically connected to the first and / or second capacitor, i.e., the termination node of the respective capacitor, and configured to generate a pixel output signal at an output terminal of the further amplifier.

[0031] The further amplifier may form a further common-drain amplifier, i.e., a further source follower. The gate terminal of the further amplifier is connected to the termination node of the first and / or second capacitor. This may mean that the first and second capacitors are arranged in parallel, so that the gate terminal of the further amplifier can be connected to both termination nodes. Alternatively, the further amplifier is connected to the termination node of the first capacitor, and the second further amplifier is connected to the termination node of the second capacitor. It is also possible for the first and second capacitors to be cascaded, so that the further amplifier is connected directly only to the termination node of the second capacitor. The common terminal of the further amplifier is connected to the pixel power supply voltage. The pixel output signal is applied at the output terminal of the further amplifier. The further amplifier may be used as a voltage buffer. The amplifier may be configured to buffer the signal, thus decoupling the capacitor stage from the readout circuit.

[0032] In at least one further embodiment, the pixel array further comprises a select gate between the output terminal of the further amplifier and the column bus, the select gate being provided for transferring the pixel output signal to the column bus.

[0033] The select gate may be implemented as a select switch. For example, the select gate is part of a select transistor having a first terminal connected to the output terminal of the further amplifier and a second terminal connected to a column bus. By applying a select signal to the select gate, the select transistor becomes conductive so that the pixel output signal is transferred to a readout circuit via the column bus. For example, the readout circuit comprises an analog-to-digital converter (ADC) with a sample-and-hold function. The column bus may or may not be included by the pixel array. Alternatively, only a portion of the column bus is constituted by the pixel. Advantageously, the output signal of each pixel in the array can be individually accessed.

[0034] In at least one further embodiment, the pixel further comprises a precharge gate electrically coupled to the output terminal of the amplifier, the precharge gate configured to precharge the first capacitor and the second capacitor.

[0035] The precharge gate may be implemented as a precharge switch. For example, the precharge gate is part of a precharge transistor having a first terminal connected to the amplifier's output terminal and a second terminal connected to ground (GND). By applying a precharge signal to the precharge gate, the precharge transistor becomes conductive so that the first and second capacitors can be precharged. This may specifically mean that the first and second capacitors are discharged each frame before being recharged to their final values ​​by the amplifier. Furthermore, the precharge transistor may deliver a specific bias current to bias the amplifier. The precharge gate may also be implemented as a constant current source configured to supply a fixed current.

[0036] In at least one further embodiment, the at least one photodiode comprises a first photodiode for generating a first charge signal in a high sensitivity mode, and further comprises a second photodiode for generating a second charge signal in a low sensitivity mode.

[0037] The first and second photodiodes can be different. For example, the first photodiode has a larger photoactive area than the second photodiode to generate more charge carriers than the second photodiode. Alternatively, the second photodiode can be provided with a filter to attenuate the second charge signal. The first and second photodiodes can share a common FD node, i.e., the same capacitance.

[0038] Thus, the two photodiodes can be assigned to two respective transfer gates, a first transfer gate being provided for transferring a first charge signal to the termination node of the capacitance, and a second transfer gate being provided for transferring a second charge signal to the termination node of the capacitance.

[0039] A first charge signal of the first photodiode results in a high sensitivity signal, and a second charge signal of the second photodiode results in a low sensitivity signal. Thus, by providing a first photodiode and a second photodiode different from the first photodiode, each charge signal can be used to obtain a high dynamic range.

[0040] In at least one further embodiment, the pixel array further comprises a sensitivity gate. The sensitivity gate is disposed between the reset gate and a termination node of the capacitance. In this embodiment, the pixel array further comprises a third capacitor comprising the termination node. The sensitivity gate is provided to short-circuit the termination node of the capacitance with the termination node of the third capacitor.

[0041] The sensitivity gate may be implemented as a gain switch. The sensitivity gate may be part of a sensitivity transistor having a first terminal electrically connected to the termination node of the capacitance and a second terminal electrically connected to the termination node of a third capacitor. By applying a gain signal to the sensitivity gate, the sensitivity transistor becomes conductive such that the FD node is shorted to the termination node of the third capacitor. The sensitivity transistor may be referred to as a dual conversion gain (DCG) transistor, and the sensitivity signal may be referred to as a DCG signal or a combined signal.

[0042] The third capacitor may be implemented as a MOS or MIM capacitor, and the termination node of the third capacitor is disposed between the reset gate and the sensitivity gate.

[0043] The third capacitor further comprises a further termination node which may be connected to ground.

[0044] By shorting the FD node with the terminal node of the third capacitor, the combined capacitance becomes larger than the magnitude of the FD capacitance. Keeping the charge constant, this leads to a reduced voltage signal. Therefore, by increasing the capacitance, the gain decreases. This means that if the capacitance and the third capacitor are shorted, the pixel array has a reduced gain. In other words, if the third capacitor is electrically disconnected from the capacitance by the sensitivity gate, the pixel array has an increased gain.

[0045] Generally, when the transfer gate is deactivated, the photodiode is separated from the capacitance by a potential barrier. Similarly, when the sensitivity gate is deactivated, the capacitance is separated from the third capacitor by a further potential barrier. This means that charge carriers are prevented from diffusing between the photodiode and the capacitance or between the capacitance and the third capacitor, respectively. However, in some embodiments, such charge overflow is permitted, particularly when the potential well of the photodiode or the potential well of the capacitance, respectively, becomes saturated. In this way, photo-induced charge carriers are not lost even during saturation, providing the pixel array with an increased dynamic range. In other words, the third capacitor stores excess charge carriers. Furthermore, the photodiode and / or the capacitance can be made smaller in size.

[0046] In at least one further embodiment, the first capacitor and the second capacitor are arranged in parallel. Both the first switch and the second switch are electrically connected directly to the output terminal of the amplifier. The terminal node of the first capacitor can be electrically connected to a further amplifier. The terminal node of the second capacitor can be electrically connected to a second further amplifier. The terminal node of the first capacitor and the terminal node of the second capacitor can also be connected to a common further amplifier. Advantageously, the first capacitor and the second capacitor can be independently controlled by the first and second switches.

[0047] In at least one further embodiment, the first capacitor and the second capacitor are arranged in a cascade connection. In this case, the second switch is electrically connected to the output terminal of the amplifier through the first switch. In other words, the second switch is arranged between the terminal node of the first capacitor and the terminal node of the second capacitor. Advantageously, fewer components are required than in the case of a parallel arrangement of the capacitors.

[0048] Furthermore, there is provided an image sensor comprising an array of pixels according to a pixel arrangement as described in one of the above embodiments, which means that all features disclosed for the pixel arrangement are also disclosed and applicable for the image sensor and vice versa.

[0049] Furthermore, an optoelectronic device is provided that comprises an image sensor, which means that all features disclosed for the image sensor are also disclosed and applicable to the optoelectronic device and vice versa.

[0050] Image sensors can be conveniently used in optoelectronic devices such as smartphones, tablet computers, laptops, or camera modules. For example, camera modules are configured to operate in the visible range for photography and / or video capture. Furthermore, pixel arrays are particularly suited to operating in global shutter mode because signals are stored in pixel-level memories, i.e., first and second capacitors. The global shutter mode is particularly suited for infrared applications, where the image sensor device further comprises a light source synchronized with the pixels. Therefore, optoelectronic devices equipped with such image sensors can also function in the infrared (IR) range, for example, for 3D imaging and / or identification purposes. Infrared-sensitive image sensors can be used in dark environments where a video feed is required. Such applications range from face unlocking of mobile phones to driving monitoring systems. Both can be equipped with illuminators in the shortwave infrared (SWIR) spectrum to prevent phone users / drivers from being blinded by the light shining on them.

[0051] Furthermore, methods are provided for operating a pixel array configured to convert electromagnetic radiation in a high-sensitivity mode and a low-sensitivity mode, respectively. The pixel arrays described above can be preferably used in the methods for operating a pixel array described herein. This means that all features disclosed for the pixel array and image sensor are also disclosed for the methods for operating a pixel array, and vice versa.

[0052] According to at least one embodiment of a method for operating a pixel array, the method includes converting electromagnetic radiation into a respective charge signal by at least one photodiode. The method further includes providing a reset signal to reset the capacitance. For example, the reset signal is applied to a reset gate electrically coupled to the capacitance. For example, applying the reset signal applies a pixel power supply voltage to a terminal node of the capacitance so that charge carriers accumulated in the capacitance are removed.

[0053] The method further includes providing a transfer signal to transfer each charge signal from the at least one photodiode to the capacitance, for example, the transfer signal being applied to a transfer gate between the photodiode and a termination node of the capacitance.

[0054] The method further includes generating a respective amplified signal based on the respective charge signals and the sensitivity mode. Each amplified signal is one of a low-sensitivity signal and a high-sensitivity signal. The low-sensitivity signal and the high-sensitivity signal are based on a common noise level. This may mean that the noise level of the low-sensitivity signal is correlated with the noise level of the high-sensitivity signal. For example, each amplified signal is generated by an amplifier electrically connected to a capacitance at an input terminal.

[0055] The method further includes providing a first switch signal to transfer each amplified signal to a first capacitor configured to store the high sensitivity signal, for example, the first switch signal being applied to a first switch between a termination node of the first capacitor and an output terminal of the amplifier.

[0056] The method further includes providing a second switch signal to transfer each amplified signal to a second capacitor configured to store the low sensitivity signal, for example, the second switch signal being applied to a second switch between a termination node of the second capacitor and an output terminal of the amplifier.

[0057] Advantageously, the two capacitors store two different signals: a high-sensitivity signal and a low-sensitivity signal. Therefore, the dynamic range of the pixel array can be expanded. Furthermore, since both signals are based on a common noise level, the low-sensitivity signal can be used as a reference level for the high-sensitivity signal. This means, for example, that the high-sensitivity signal can be accessed by the CDS so that thermal noise and reset noise can be effectively canceled out.

[0058] In at least one further embodiment of the method, the method further includes a first step during pixel exposure in which the pixel is operated in a low-sensitivity mode. In the low-sensitivity mode, a low-sensitivity signal is generated and stored in the second capacitor. In a second step during pixel exposure, the pixel is operated in a high-sensitivity mode such that a high-sensitivity signal is generated and stored in the first capacitor. Pixel exposure refers to the period of time during which the photodiode is exposed to light.

[0059] The low sensitivity signal is smaller than the high sensitivity signal. In particular, the high sensitivity signal is equal to the low sensitivity signal plus an additional video signal. Therefore, the low sensitivity signal is determined before the high sensitivity signal. Therefore, advantageously, the high sensitivity signal can be based on the low sensitivity signal.

[0060] In at least one further embodiment of the method, the first and second steps during pixel exposure are performed without resetting the capacitance between them. When the capacitance is reset, information about the low-sensitivity signal is removed from the FD node, so that the high-sensitivity signal is not based on the low-sensitivity signal. Advantageously, the capacitance stores information about the low-sensitivity signal so that it can be reused in the high-sensitivity mode. Advantageously, no additional noise is introduced.

[0061] In at least one further embodiment of the method, the low-sensitivity signal is read out in a first step during pixel readout. The high-sensitivity signal is read out in a second step during readout. Pixel readout refers to the time period during which the analog signal stored in the capacitor is further processed. For example, the analog signal is transferred via a column bus to a readout circuit and converted into a digital signal there. Advantageously, the low-sensitivity signal is read out before the high-sensitivity signal so that the low-sensitivity signal can be used as a reference level for the high-sensitivity signal.

[0062] Reading out a high-sensitivity signal can mean that the high-sensitivity signal is read out directly from the first capacitor. However, it can also mean that an attenuated version of the high-sensitivity signal is read out. If the first and second capacitors are arranged in cascade, the two capacitors are coupled to each other. For example, when reading out a high-sensitivity signal, the high-sensitivity signal can be redistributed in the first and second capacitors. This means that the charge in the first capacitor is mixed with the charge in the second capacitor. Therefore, the high-sensitivity signal in the first capacitor is attenuated by a factor of two, for example, if the first capacitor is equal to the second capacitor.

[0063] In at least one further embodiment of the method, in a third step during pixel readout, the capacitance is reset and a reset level is read out. Resetting the capacitance is performed by applying a reset signal. The reset level refers to the non-video signal of the pixel array, i.e., a signal without a charge signal from the photodiode. Resetting the capacitance, i.e., the FD node, introduces additional noise that is not correlated with the noise of the high-sensitivity or low-sensitivity signals. However, the reset level of the pixel array contains information about fixed pattern noise (FPN). Therefore, advantageously, the FPN of the pixel array can be determined in the third step during pixel readout.

[0064] In at least one further embodiment, the method further includes performing double delta sampling during pixel readout by using the reset level as a reference level for the low-sensitivity signal. The low-sensitivity signal is further processed in the case of high illumination. Since photon shot noise dominates at high illumination, thermal noise is less relevant here. Therefore, correlated double sampling is not necessary to remove noise from the video signal. However, it may be desirable to remove FPN from the video signal. By performing double delta sampling (DDS), i.e., by using the reset level as a reference level for the low-sensitivity signal, FPN can be removed.

[0065] In at least one further embodiment, the method further includes performing correlated double sampling by using the low-sensitivity signal as a reference level for the high-sensitivity signal during pixel readout. As described above, the low-sensitivity signal and the high-sensitivity signal are based on a common noise level. Therefore, by performing correlated double sampling, i.e., by using the low-sensitivity signal as a reference level for the high-sensitivity signal, noise can be effectively removed from the high-sensitivity signal. The removed noise includes both temporal noise and fixed pattern noise.

[0066] In at least one further embodiment, the method further includes, during pixel readout, determining whether to use a low-sensitivity signal or a high-sensitivity signal for further processing based on the respective amplitude levels. In the case of high illumination, the high-sensitivity signal may be saturated. Therefore, the low-sensitivity signal should be used for further processing. In the case of low illumination, the low-sensitivity signal may be weak and affected by noise. Therefore, the high-sensitivity signal should be used for further processing. The step of determining whether to use a low-sensitivity signal or a high-sensitivity signal for further processing based on the respective amplitude levels may include comparing the respective amplitude levels with a respective threshold. Advantageously, depending on the current illumination, either the low-sensitivity signal or the high-sensitivity signal can be used. Thus, the dynamic range is expanded.

[0067] In at least one further embodiment, the method further includes adjusting the conversion gain during pixel exposure in the low sensitivity mode by applying a gain signal to short-circuit the end node of the capacitance with the end node of a third capacitor. For example, the gain signal is applied to a sensitivity gate between the end node of the capacitance and the end node of the third capacitor. By shorting the respective end nodes for a given charge signal, the total capacitance is increased, which in turn reduces the voltage signal. Thus, the conversion gain for each charge signal is reduced. Thus, two different conversion gains can be provided.

[0068] In at least one further embodiment of the method, converting the electromagnetic radiation into respective charge signals includes generating a first charge signal in a high-sensitivity mode with a first photodiode and generating a second charge signal in a low-sensitivity mode with a second photodiode. In particular, the first and second photodiodes can be different to generate different charge signals at different illumination intensities. For example, a larger photodiode can be used in the high-sensitivity mode to generate an increased charge signal, and a smaller photodiode can be used in the low-sensitivity mode to generate a decreased charge signal and prevent saturation of the storage element in the pixel. By using two or at least two photodiodes, the dynamic range of the pixel array can be increased.

[0069] In at least one further embodiment of the method, converting the electromagnetic radiation into respective charge signals includes generating a first charge signal in a low-sensitivity mode with a reduced exposure time and generating a second charge signal in a high-sensitivity mode with an increased exposure time. The respective charge signals at a given illumination intensity can be varied by different exposure times. For example, a long exposure time can be used in the high-sensitivity mode to generate an increased charge signal, and a short exposure time can be used in the low-sensitivity mode to generate a decreased charge signal, thus preventing saturation. By using two or at least two exposure times, the dynamic range of the pixel array can be expanded.

[0070] Further embodiments of the method will be apparent to those skilled in the art from the pixel array embodiments described above, and vice versa.

[0071] Further, another method for operating a pixel array is provided. The pixel array configured to convert electromagnetic radiation in a high-sensitivity mode and a low-sensitivity mode as described above can also be used in this method of operation. This means that all features disclosed for the pixel array and the image sensor are also disclosed for the following method of operating a pixel array, and vice versa. Furthermore, aspects of the above method are also relevant to the following method. Thus, embodiments of the above method are also disclosed and applicable to the following method.

[0072] In at least one embodiment, a method includes accumulating charge carriers with a photodiode during a first integration period, the method further includes pulsing a transfer gate to a first voltage level at the end of the first integration period to transfer a portion of the accumulated charge carriers to a capacitance configured to drain to a power supply voltage.

[0073] The first integration period is a portion of the exposure period. This may mean that the exposure period is subdivided into several integration periods, for example, a first integration period, a second integration period, and a third integration period. The exposure period may be referred to as a pixel exposure period. As mentioned above, the capacitance may be a diffusion-mode (parasitic) capacitance. Therefore, in other words, the accumulated charge carriers are transferred to the diffusion node by applying a transfer signal to the transfer gate. The transfer gate may be implemented as part of the transfer transistor. The first voltage level may be a voltage level lower than the threshold voltage of the transfer transistor. This may mean that the first voltage level is a partial voltage level. For example, the first voltage level is 0.8 V. By applying the first voltage level to the transfer gate, the potential barrier between the photodiode and the diffusion node is lowered. Therefore, excess charge carriers may overcome the lowered potential barrier to be transferred from the photodiode to the diffusion node. These excess charge carriers are referred to as the portion of accumulated charge carriers. The portion is configured to drain to the power supply voltage. This can be achieved by resetting the diffusion node, which can be achieved by applying a reset signal to a reset transistor connected between the diffusion node and the pixel power terminal, as described above. Draining the portion can be performed, for example, during the exposure period, at the end of the exposure period, or after the exposure period.

[0074] In at least one embodiment, the method further includes continuing to accumulate charge carriers with the photodiode during a second integration period.

[0075] The second integration period is a portion of the exposure period. The second integration period is later than the first integration period. The second integration period may immediately follow the first integration period. The exposure period may include the first and second integration periods. The charge carriers accumulated in the photodiode after the second integration period include the charge carriers accumulated during the first and second integration periods minus the portion of the charge that is drained.

[0076] In at least one embodiment, at the end of the second integration period, the method further includes pulsing the transfer transistor to a first voltage level to transfer a first portion of the stored charge carriers to the capacitance, and storing a low-sensitivity signal representative of the first portion of the stored charge carriers in at least a second capacitor (80) of a pair of capacitors electrically coupled to the capacitance.

[0077] The step of storing the low-sensitivity signal may be performed during a storage period. The storage period may overlap with the exposure period. This may mean that the storage period begins during the exposure period. The storage period may be referred to as the pixel's frame storage period. Transferring the first portion of the accumulated charge carriers may be performed after resetting the diffusion node / capacitance to drain the portion of the accumulated charge carriers. The first portion of the accumulated charge carriers is different from the portion of the accumulated charge carriers. However, because the first voltage level is reapplied to the transfer gate, the potential barrier is lowered by the same amount. Therefore, the first portion of the accumulated charge carriers corresponds to the excess charge carriers accumulated during the second integration period. The first portion of the accumulated charge carriers is not drained but is stored in a pair of capacitors. The pair of capacitors is electrically coupled to the capacitance or the diffusion node, respectively. The pair of capacitors includes first and second capacitors as described above. The capacitors may be electrically coupled to the diffusion node via a source follower as described above. The capacitors may be arranged in parallel or cascaded as described above. When the capacitors are arranged in cascade, the low-sensitivity signal representing a first portion of the stored charge carriers can be distributed across both capacitors. When the capacitors are arranged in parallel, the low-sensitivity signal can instead be stored in one of the capacitors, for example, the second capacitor. Storing the low-sensitivity signal can be achieved by applying a switch signal to each switch assigned to the capacitor. For example, as described above, a first switch is assigned to the first capacitor and a second switch is assigned to the second capacitor.

[0078] In at least one embodiment, the method further includes continuing to accumulate charge carriers using the photodiode during a third integration period. The third integration period is part of the exposure period. The third integration period is after the second integration period. The third integration period may immediately follow the second integration period. The exposure period may include the first, second, and third integration periods. The charge carriers accumulated in the photodiode after the third integration period include the charge carriers accumulated during the first, second, and third integration periods minus the portion of the charge carriers drained and minus at least the first portion of the charge carriers stored in the second capacitor.

[0079] In at least one embodiment, at the end of the third integration period, the method further includes pulsing the transfer transistor to a second voltage level to transfer a remaining portion of the stored charge carriers to the capacitance, and storing a high sensitivity signal representative of the remaining portion of the stored charge carriers in a first capacitor of the pair of capacitors.

[0080] Pulsing the transfer transistor to a second voltage level is performed after pulsing the transfer transistor to the first voltage level. The second voltage level may be a full voltage level. The second voltage level may be a voltage level higher than the threshold voltage level of the transfer transistor. For example, the second voltage level is 2.8 V. Thus, by applying the second voltage level, the transfer transistor becomes conductive. Thus, by applying the second voltage level, the potential barrier between the photodiode and the diffusion node becomes lower than the potential barrier when the first voltage level is applied. In particular, the potential barrier may be completely eliminated. Thus, the remaining charge carriers accumulated in the photodiode are transferred to the diffusion node. The remaining portion of the accumulated charge carriers corresponds to the charge carriers accumulated during the first, second, and third integration periods minus the portion of the charge carriers drained and minus at least the first portion of the charge carriers stored in the second capacitor.

[0081] In at least one embodiment, during the readout period, the method further includes reading out the low sensitivity signal and the high sensitivity signal stored in the capacitor.

[0082] The step of reading out the respective signal may be performed by applying a select signal to the select transistor, as described above, which connects the capacitor on which the signal is stored to the column bus of the pixel, which may be electrically coupled to the column bus via a further source follower, as explained above.

[0083] The described method involves barrier modulation of the transfer gate. Through barrier modulation, the dynamic range of the pixel array can be expanded. In particular, the dynamic range of the pixel array is expanded by draining a portion of the accumulated charge carriers in high light conditions. The high-sensitivity signal (high conversion gain signal, HCG signal) includes a knee-point calibration value required during linearization of the pixel output signal. In particular, by knowing the respective durations of the first and second integration periods and the first voltage level, it is possible to reconstruct the linearized signal. The transfer transistor of each pixel is subject to variations and fluctuations in the manufacturing process. Therefore, the threshold voltage of the transfer transistor varies from pixel to pixel. This can mean that the barrier between the photodiode and the diffusion node varies from pixel to pixel when the first voltage level is applied. However, knowing the exact barrier level is relevant for eliminating fixed pattern noise (FPN). From the first voltage level and the pixel's HCG signal (corresponding to the remaining portion of the accumulated charge carriers after applying the first voltage level), information about the dependence of the output signal on the barrier can be derived. Furthermore, because the first voltage level applied during the exposure period is also applied during the storage period, the ratio of the first and second integration periods and the HCG signal can be used to determine how many charge carriers have drained to the supply voltage at the end of the first integration period. Given this amount and a low sensitivity signal (low conversion gain signal, LCG signal), the pixel output signal for use in high light conditions can be reconstructed.

[0084] Furthermore, since both signals are based on a common noise level and the diffusion nodes are not reset between storing the LCG signal and the HCG signal, the low-sensitivity signal (LCG signal) can serve as a reference level for the high-sensitivity signal (HCG signal). Therefore, CDS can be performed on the HCG signal used in low-light conditions (where the LCG signal contains only noise and no video information).

[0085] In at least one embodiment, a method for operating a pixel array includes accumulating charge carriers using a photodiode during a first integration period and pulsing a transfer gate to a first voltage level at the end of the first integration period to transfer a portion of the accumulated charge carriers to a capacitance, the portion being configured to drain to a power supply voltage. The method further includes continuing to accumulate charge carriers using the photodiode during a second integration period. The method further includes pulsing the transfer gate to a first voltage level at the end of the second integration period to transfer a first portion of the accumulated charge carriers to the capacitance and storing a low-sensitivity signal representative of the first portion of the accumulated charge carriers in at least a second capacitor of a pair of capacitors electrically coupled to the capacitance. The method further includes continuing to accumulate charge carriers using the photodiode during a third integration period (T3). The method further includes pulsing the transfer gate to a second voltage level at the end of the third integration period to transfer a remaining portion of the stored charge carriers to the capacitance, and storing a high sensitivity signal representative of the remaining portion of the stored charge carriers in a first capacitor of the pair of capacitors. The method further includes reading out the low sensitivity signal and the high sensitivity signal stored in the capacitors during a readout period.

[0086] In at least one embodiment, the high sensitivity signal indicates a calibration level based on the remaining fraction of stored charge carriers.

[0087] In at least one embodiment, the method further includes adjusting the pixel output signal based on the low sensitivity signal and the high sensitivity signal depending on a pixel-specific knee-point value determined based on the calibration level.

[0088] As mentioned above, the remaining portion of the accumulated charge carriers corresponds to the high-sensitivity signal, also known as the HCG signal. By knowing the first voltage level and the HCG signal, information about the transfer gate forming the barrier can be inferred. Therefore, the HCG signal can be used as a calibration level for the LCG signal. This means that the calibration level is the HCG signal. In other words, information about the drained portion of the accumulated charge carriers is not lost and can be reconstructed based on the first voltage level, the HCG signal, and the integration period. In this way, the drained charge carriers can be taken into account. Furthermore, a calibration level is needed in post-processing to remove FPN caused by fluctuations in the transfer gate.

[0089] The pixel output signal may be based on the LCG signal or the HCG signal, depending on the light conditions. In high light conditions, the LCG signal is further processed. Further processing of the LCG signal may mean that the LCG signal is adjusted according to the relationship between the calibration level and the first and second integration periods. Adjusting the pixel output signal is therefore sometimes referred to as pixel knee-point calibration. Pixel knee-point calibration may be performed individually for each pixel. Furthermore, because the barrier information is contained within the HCG signal, the pixel array is self-calibrated. Therefore, no additional readout is required.

[0090] Conditioning the LCG signal may further include a double delta sampling (DDS) routine to remove FPN.

[0091] In low light conditions, the HCG signal is further processed, which may mean that the HCG signal is adjusted by a correlated double sampling (CDS) routine.

[0092] In at least one embodiment, the first integration period is longer than the second integration period. This can mean that the duration of the first integration period is longer than the duration of the second integration period. For example, the first integration period is 1.5 to 3 times longer than the second integration period. For example, the first integration period is twice as long as the second integration period. In this way, saturation effects can be avoided.

[0093] In at least one embodiment, the second voltage level is higher than the first voltage level. This means that when the second voltage level is applied to the transfer gate, the barrier between the photodiode and the diffusion node is lower than when the first voltage level is applied to the transfer gate. Therefore, the first voltage level can be a partial voltage level, and the second voltage level can be a full voltage level. In other words, the first voltage level can be lower than the threshold voltage level, and the second voltage level can be higher than the threshold voltage level. The first voltage level can be lower than 1.0 V, for example, 0.8 V. For example, the second voltage level can be higher than 2.0 V, for example, 2.8 V. By applying a partial voltage level to the transfer gate, only a portion of the accumulated charge carriers can be transferred to the diffusion node. By applying a full voltage level to the transfer gate, the photodiode can be reset, and the remaining portion of the accumulated charge carriers can be transferred to the diffusion node.

[0094] The described method using barrier modulation can also be combined with aspects of the method described above.

[0095] In particular, in at least one embodiment, in a first step during pixel readout (readout period), a low sensitivity signal may be read out, in a second step during readout, a high sensitivity signal may be read out, and in a third step during pixel readout, the capacitance is reset and the reset level is read out.

[0096] In at least one further embodiment, the reset level can be used as a reference level for low sensitivity signals, which enables DDS.

[0097] In at least one further embodiment, correlated double sampling may be performed by using the less sensitive signal as a reference level for the more sensitive signal.

[0098] In at least one further embodiment, whether to use the low-sensitivity signal or the high-sensitivity signal for further processing can be determined based on their respective amplitude levels, thus allowing the pixel output signal to be adapted to lighting conditions and increasing the dynamic range.

[0099] In at least one further embodiment, the pixel array may include a dual conversion gain transistor as described above. Accordingly, the method may include adjusting the conversion gain by applying a gain signal to short a terminal node of the capacitance (corresponding to the diffusion node) with a terminal node of a third capacitor. Adjusting the conversion gain may be performed during the storage period.

[0100] The above-described method of operating a pixel array allows HDR in voltage-domain global shutter (VGS) pixels to be achieved without affecting pipeline mode, i.e., pipelining the signal to a storage capacitor. Furthermore, only two capacitors are required, which means that the pixel array can have a small area. The latter method utilizes self-calibrating barrier modulation, which means that the calibration value is included in one of the signals, specifically the HCG signal. Typically, the calibration value must be obtained by an additional readout.

[0101] Further embodiments of the method will be apparent to those skilled in the art from the pixel array embodiments described above, and vice versa. The pixel array may form a voltage-domain global shutter pixel. Alternatively, the pixel array forms a rolling shutter pixel.

[0102] The following description of the figures may further illustrate and explain aspects of pixel arrays and methods of operating such pixel arrays. Components and portions of pixel arrays that are functionally identical or have the same effect are indicated by the same reference numerals. Identical or substantially identical components and portions may be described only with respect to the figure in which they first appear. Their descriptions are not necessarily repeated in successive figures. [Brief explanation of the drawings]

[0103] [Figure 1] FIG. 1 illustrates the dynamic range of a pixel array. [Figure 2A] FIG. 1 illustrates an exemplary implementation of a pixel array. [Figure 2B] 2B shows exemplary signal timings for a pixel array according to FIG. 2A; [Figure 3] FIG. 10 illustrates another exemplary embodiment of a pixel array. [Figure 4A] FIG. 10 illustrates another exemplary embodiment of a pixel array. [Figure 4B] FIG. 4B illustrates exemplary signal timings for a pixel array according to FIG. 4A. [Figure 5] FIG. 10 illustrates another exemplary embodiment of a pixel array. [Figure 6] 1 is a schematic diagram of an optoelectronic device comprising an image sensor comprising an array of pixels; [Figure 7] FIG. 2B illustrates another exemplary signal timing for the pixel array according to FIG. 2A. [Figure 8] 2B illustrates exemplary operations performed by the pixel array according to FIG. 2A. [Figure 9]FIG. 2 illustrates exemplary characteristics of a pixel array. [Figure 10] FIG. 2B illustrates another exemplary signal timing for the pixel array according to FIG. 2A. DETAILED DESCRIPTION OF THE INVENTION

[0104] FIG. 1 shows the photo-induced charge signal Q of a pixel array 10 (not shown) plotted against illuminance I. It can be seen that a linear or nearly linear relationship exists between the charge signal Q and illuminance I. For small values ​​of the charge signal Q, the signal is dominated by a noise floor 998, making it difficult to obtain a usable video signal from the noisy charge signal Q. If the charge signal is sufficiently above the noise floor level 998, a usable video signal can be determined. However, for high charge signals Q, a saturation region 999 may be reached. This means that the photodiodes or memory elements in the pixel array 10 can only handle a certain number of photo-induced charge carriers because their respective potential wells are not large enough to store more charge. As a result, in a typical pixel array 10, it is not possible to obtain an appropriate video signal for very low light conditions and very high light conditions. The light conditions in between, i.e., the light conditions under which an appropriate video signal can be obtained, define the dynamic range DR of the pixel array 10. Increasing the dynamic range of the pixel array 10 is desirable.

[0105] 2A, an exemplary embodiment of a pixel array 10 is shown. The illustrated pixel array 10 is capable of being operated to achieve high dynamic range (HDR). The pixel array 10 is configured to convert electromagnetic radiation in high and low sensitivity modes, respectively.

[0106] The pixel array 10 includes at least one photodiode 20 configured to convert electromagnetic radiation into a respective charge signal. The photodiode 20 includes an anode terminal and a cathode terminal. The anode terminal of the photodiode 20 is connected to a negative pixel power supply voltage VSS, which may be ground (GND). The photodiode 20 may convert light of any wavelength, for example, visible light, infrared light, and / or ultraviolet light.

[0107] The pixel further comprises a transfer gate 30 between the photodiode 20 and the capacitance 40. In the embodiment shown in FIG. 1, the transfer gate 30 is implemented as part of a transfer transistor that functions as a switch. A first terminal of the transfer transistor is electrically connected to the cathode terminal of the photodiode 20. A second terminal of the transfer transistor is electrically connected to a termination node 42 of the capacitance 40. The termination node 42 is hereinafter referred to as a (floating) diffusion (FD) node 42. The capacitance 40 may be implemented as a capacitor and may be referred to as an FD capacitor. The transfer gate 30 of the transfer transistor is configured to receive a transfer signal TX for transferring the respective charge signals from the photodiode 20 to the capacitance 40. The capacitance 40 is configured to convert the respective charge signals into respective voltage signals. A further termination node 44 of the capacitance 40 may be connected to VSS.

[0108] The pixel array 10 further comprises a reset gate 50 electrically coupled to the capacitance 40 for resetting the capacitance 40. In the embodiment shown in FIG. 1 , the reset gate 50 is implemented as part of a reset transistor that functions as a switch. A first terminal of the reset transistor is electrically connected to a pixel power supply voltage VDD. A second terminal of the reset transistor is electrically connected to a termination node 42 of the capacitance 40. The reset gate 30 of the reset transistor is configured to receive a reset signal RTS for resetting the capacitance 40 by applying the pixel power supply voltage VDD, thus removing any redundant charge carriers.

[0109] The pixel array 10 further includes an amplifier 60 electrically connected to the capacitance 40 and configured to generate a respective amplified signal based on the respective charge signal and the sensitivity mode. Each amplified signal is a low-sensitivity signal or a high-sensitivity signal, respectively. The low-sensitivity signal and the high-sensitivity signal are based on a common noise level. The amplifier 60 may form a common-drain amplifier, known as a source follower, as shown in FIG. 2. A gate terminal 62 of the source follower is connected to the FD node 42 and serves as an input terminal 62 of the amplifier 60. The common terminal is connected to a power supply voltage VDD. Each amplified signal is generated at an output terminal 64 of the amplifier 60.

[0110] The pixel array 10 further comprises a first capacitor 70 configured to store a high-sensitivity signal and a second capacitor 80 configured to store a low-sensitivity signal. The first capacitor 70 comprises a termination node 72 and a further termination node 74. As shown in FIG. 1, the further termination node 74 may be connected to VSS. Furthermore, the second capacitor 80 comprises a termination node 82 and a further termination node 84. As shown in FIG. 2, the further termination node 84 may be connected to VSS.

[0111] The pixel array 10 further comprises a first switch 90 between the output terminal 64 of the amplifier 60 and the first capacitor 70. The first switch 90 is provided to transfer each amplified signal to the first capacitor 70. The first switch 90 may be formed by a first switching transistor. The first switching transistor has a gate terminal 90 configured to receive a first switch signal S1. A first terminal of the first switching transistor is connected to the output terminal 64 of the amplifier 60. A second terminal of the first switching transistor 90 is connected to a termination node 71 of the first capacitor 70.

[0112] The pixel array 10 further includes a second switch 100 disposed between the output terminal 64 of the amplifier 60 and the second capacitor 80. The second switch 100 is provided for transferring each amplified signal to the second capacitor 80. The second switch 100 may be formed by a second switching transistor. The second switching transistor may have a gate terminal 100 configured to receive a second switching signal S2. A first terminal of the second switching transistor is connected to the second terminal of the first switching transistor and to the termination node 72 of the first capacitor 70. A second terminal of the second switching transistor is connected to the termination node 82 of the second capacitor 80.

[0113] The pixel array 10 according to FIG. 2A can be operated as follows. During a first step during pixel exposure, the photodiode 20 is exposed to light for a first exposure time T1, such that a first charge signal is generated and converted into a low-sensitivity signal. By applying the respective switch signals S1 and S2, the low-sensitivity signal is transferred to and stored in the second capacitor 80. During a second step during pixel exposure, the photodiode 20 is exposed to light for a second exposure time T2, which is longer than the first exposure time T1, such that a second charge signal is generated and converted into a high-sensitivity signal. By applying the respective switch signals S1 and S2, the high-sensitivity signal is transferred to and stored in the first capacitor 70. The floating diffusion capacitance 40 does not need to be reset between the first and second steps. Therefore, the high-sensitivity signal is based on or includes the low-sensitivity signal. This means that both signals are based on a common noise level. Therefore, during pixel readout, the low sensitivity signal can be used as a reference level for the high sensitivity signal so that correlated double sampling (CDS) can be performed, and thus noise in the high sensitivity signal can be cancelled out.

[0114] In a further step during pixel readout, the reset level of the pixel array 10 is sampled by applying a reset signal RTS to the reset gate 50. The reset level can be used as a reference level for the low-sensitivity signal so that double delta sampling (DDS) can be performed. Thus, fixed pattern noise (FPN) in the low-sensitivity signal can be canceled out. During pixel readout, it can be determined whether to use the low-sensitivity signal by DDS or the high-sensitivity signal by CDS for further processing based on their respective amplitude levels.

[0115] The pixel array 10 shown in FIG. 2A includes additional components, which may be omitted in other embodiments. The pixel array 10 according to FIG. 2A further includes a precharge gate 160 electrically coupled to the output terminal 64 of the amplifier 60. The precharge gate 160 may be provided to precharge the first capacitor 70 and the second capacitor 80, which may specifically mean that the capacitors 70, 80 are discharged before a new signal is stored. As shown in FIG. 2A, the precharge gate 160 may be part of a precharge transistor having a first terminal connected to the output terminal 64 of the amplifier 60 and a second terminal connected to VSS. By applying a precharge signal PC to the precharge gate 160, the precharge transistor becomes conductive so that the first and second capacitors 70, 80 are discharged.

[0116] 2A further comprises a further amplifier 110, which has an input terminal 112 electrically connected to the second capacitor 80 and is configured to generate a pixel output signal at an output terminal 114 of the further amplifier 110. Similar to the amplifier 60, the further amplifier can be implemented as a source follower, with the gate 112 serving as the input terminal 112 and the common terminal connected to VDD.

[0117] The pixel array 10 further comprises a select gate 120 between the output terminal 114 of the further amplifier 110 and the column bus 130 for transferring the pixel output signal to the column bus 130. As shown, the select gate 120 may be part of a select transistor having a first terminal connected to the output terminal 114 of the further amplifier 110 and a second terminal connected to the column bus 130. By applying a select signal SEL to the select gate 120, the pixel output signal is transferred to the column bus 130.

[0118] In Figure 2B, operating the pixel array 10 according to Figure 2A is shown in more detail with respect to signal timing. However, it should be noted that the signal timing shown is an example and can be changed. Furthermore, the scaling of the time intervals should not be interpreted as an accurate indication.

[0119] Operating the pixel array 10 can be divided into two time intervals, the first time interval T ex is provided for pixel exposure and frame storage, and a second time interval T ro It can be seen that t is provided for pixel readout and t is provided for row readout, respectively. In this context, row readout can mean the readout of a single row. The rows can be read out sequentially, and all rows are read out at the same time interval T ro The pixel array 10 may be a global shutter pixel array, and the pixel exposure and frame store may be global operations, i.e., the pixel exposure and frame store may affect each pixel of the pixel array simultaneously. However, reading out a pixel may be a local operation, such that pixels or rows of the pixel array may be read out one after the other. Furthermore, in the pixel array 10 of the illustrated embodiment, the first time interval T ex is subdivided into a first (short) exposure time T1 and a second (long) exposure time T2 as explained above.

[0120] 2B shows the timing of the transfer signal TX, the reset signal RST, the first switch signal S1, the second switch signal S2, the precharge signal PC, and the select signal SEL. These signals can be in an activated state (high state) or an inactivated state (low state). Applying the respective signal can mean that the signal is switched to the activated state. In the following, the timing is explained in more detail using selected time points t1 to t8 shown in the figure.

[0121] At the end of the first exposure time T1, the transfer signal TX is applied at time t1 such that the respective charge signals are transferred from the photodiodes 20 to the capacitance 40. This in turn results in the low sensitivity signal being transferred to the second capacitor 80 since both switch signals S1, S2 controlling the first and second switches 90, 100 are in an activated state. By deactivating the second switch signal S2 at time t2, the low sensitivity signal is stored in the second capacitor 80.

[0122] At the end of the second exposure time T2, the transfer signal TX is applied again at time t3 to transfer the respective charge signals from the photodiodes 20 to the capacitance 40. This then results in the high-sensitivity signal being transferred to the first capacitor 70 because the switch signal S1 is still activated. By deactivating the first switch signal S1 at time t4, the high-sensitivity signal is stored in the first capacitor 70. Note that between times t1 and t3, the reset signal RST remains deactivated, meaning that the capacitance 40 is not reset so that the high-sensitivity and low-sensitivity signals are based on a common noise level. At time t5, the reset signal RST is activated to prevent imaging problems such as blooming. The reset signal RST is activated after the high-sensitivity signal is stored.

[0123] Pixel readout begins at time t6 by applying the select signal SEL. At this moment, the low-sensitivity signal stored in the second capacitor 80 is read out. The high-sensitivity signal stored in the first capacitor 70 is read out at time t7 by applying the second switch signal S2. From time t8, the reset level is read out by deactivating the reset signal RST. The first switch signal S1, the second switch signal S2, and the precharge signal PC are then activated so that a signal corresponding to the reset level is transferred to the readout circuit and the capacitors 70 and 80 are discharged. The pixel array 10 is then ready for the next frame.

[0124] FIG. 3 illustrates another embodiment of the pixel array 10. The embodiment according to FIG. 3 differs from the embodiment according to FIG. 2 in that the capacitors 70, 80 are not arranged in cascade, but in parallel. This means that the second switch 100 coupled to the second capacitor 80 is connected directly to the output terminal 64 of the amplifier 60, and not via the first switch 90 as in FIG. 2. It should be noted that the pre-charge gate 160 can also be implemented as a constant current source configured to provide a fixed current. Furthermore, the embodiment according to FIG. 3 further comprises a second further amplifier 110′ and a further select gate 120′ coupled to the second capacitor 80, while the further amplifier 110 and the select gate 120 are coupled to the first capacitor 70. However, it should be noted that the illustrated embodiment shows the parallel arrangement of the capacitors 70, 80 merely by way of example. Other arrangements are possible. For example, the parallel-arranged capacitors 70, 80 can share a common further amplifier 110 via an additional switch. At the expense of the need for additional components, the parallel arrangement has the advantage that the high-sensitivity signal and the low-sensitivity signal can be stored and read out independently. Those skilled in the art will understand how to implement the signal timing shown in FIG. 2B. However, because the first switch and the second switch can be operated independently, the signal timing may change slightly both during pixel exposure and pixel readout.

[0125] FIG. 4A shows another embodiment of the pixel array 10. The embodiment according to FIG. 4 differs from the embodiment according to FIG. 2 in that the pixel array further comprises a second photodiode 20′ connected to the FD node 42 via a second transfer gate 30′. This means that the first photodiode 20 and the second photodiode 20′ are arranged in parallel. The first photodiode 20 is configured to generate a first charge signal in a high-sensitivity mode, and the second photodiode 20′ is configured to generate a second charge signal in a low-sensitivity mode. The first and second photodiodes 20, 20′ can be different, which can mean that the respective charge signals are different at a given illumination intensity. The method of operating such a pixel array 10 can be similar to that in the embodiment of FIG. 2A, except that the exposure times of the respective photodiodes 20, 20′ can be equal.

[0126] In FIG. 4B, operating the pixel array 10 according to FIG. 4A is shown in more detail with respect to signal timing. Again, it should be noted that the illustrated signal timing is an example and can be modified. The scaling of the time intervals should not be interpreted as an accurate indication. The timing of the respective signals is similar to that of the example of FIG. 2B, except that the first transfer signal TX1 controls the first transfer gate 30, and the second transfer signal TX2 controls the second transfer gate 30′. Thus, at time t1, the respective charge signals are transferred from the second photodiode 20′ to the capacitance 40 by activating the second transfer signal TX2, while at time t3, the respective charge signals are transferred from the first photodiode 20 to the capacitance 40 by activating the first transfer signal TX1. For a further explanation of FIG. 4B, reference is made to the above description of FIG. 2B.

[0127] FIG. 5 illustrates another embodiment of the pixel array 10. The embodiment according to FIG. 5 differs from the embodiment according to FIG. 2A in that it further comprises a sensitivity gate 140 between the capacitance 40 and the reset gate 50. Thus, in this embodiment, the reset gate 50 is electrically coupled to the capacitance 40 via the sensitivity gate 140. The pixel array 10 further comprises a third capacitor 150. The third capacitor 150 comprises a termination node 152 and a further termination node 154. The further termination node 154 of the third capacitor 150 may be connected to VSS as shown. The sensitivity gate 140 may be part of a sensitivity transistor having a first terminal connected to the FD node 42 of the capacitance 40 and a second terminal connected to the termination node 152 of the third capacitor 150. By applying a gain signal to the sensitivity gate 140, the sensitivity transistor becomes conductive such that the FD node 42 is shorted to the termination node 152 of the third transistor 150. Therefore, the total capacitance can be increased and the conversion gain can be reduced.

[0128] The operating mode of this embodiment is similar to that of the embodiment according to FIG. 2A. However, here, the pixel 10 does not necessarily need to be exposed twice. The charge signal of the photodiode 20 is first converted with a low conversion gain by applying a gain signal to the sensitivity gate 140, resulting in a low sensitivity signal. The charge signal is then converted with a high conversion gain by deactivating the gain signal, resulting in a high sensitivity signal. As in the previous embodiment, the capacitance 40 is not reset between the generation of the high sensitivity signal and the generation of the low sensitivity signal. Those skilled in the art will understand how to implement the signal timing as shown in FIGS. 2B and 4B. However, the signal timing may vary slightly, at least during pixel exposure.

[0129] 6, an optoelectronic device 300 is shown schematically, including an image sensor 200 having a pixel array 10. The pixels 10 of the image sensor 200 may be arranged in a two-dimensional array, as shown in FIG. 6. The optoelectronic device 300 or the image sensor 200 may include other components, such as other circuit elements or a light source synchronized with the pixels 10. The pixel array 10 may be used, for example, in a voltage-domain global shutter pixel, or VGS pixel for short. The pixel array 10 may be implemented, for example, as a rolling shutter pixel.

[0130] FIG. 7 shows another exemplary timing diagram implemented by the pixel array 10 shown in FIG. 2A, for example. However, with minor modifications, the timing diagram can also be applied to the pixel array 10 according to FIG. 3 (omitting the first switch signal S1). The following signals are shown as a function of time: transfer signal TX, reset signal RST, first switch signal S1, and second switch signal S2. It should be noted that the illustrated signal timings are an example and can be modified. Furthermore, the scaling of the time intervals should not be interpreted as an accurate indication.

[0131] Figure 7 shows the reset period T rst and the exposure period T ex and (frame) storage period T FS The read period T ro is not shown. Readout period T ro is the storage period T FS Followed by the memory period T FS is the exposure period T ex Exposure period T ex is the reset period T rst Followed by:

[0132] Exposure period T ex The storage period T includes a first integration period T1, a second integration period T2, and a third integration period T3. The third integration period follows the second integration period T1. The second integration period T2 follows the first integration period T1. FSincludes a first storage stage FS1 and a second storage stage FS2, which follows the first storage stage FS1.

[0133] memory period T FS may be the global storage period for each pixel in the pixel array. ro can be performed individually for each row. Thus, the second storage phase FS2 and the readout period T ro There may be a time lag between

[0134] Reset period T rst During this time, the reset signal RST and transfer signal TX are applied. This can mean that the reset gate 50 and transfer transistor 30 are pulsed to remove any redundant charge carriers by connecting the photodiode 20 and diffusion node 42 to the pixel supply voltage VDD. The transfer gate can be pulsed to a full voltage level, i.e., the second voltage level V2. The reset signal RST can remain high until the second TX pulses to the first voltage level V1, as shown by the dashed line.

[0135] During the first integration period T1, charge carriers are accumulated by the photodiode 20. The amount of accumulated charge carriers depends on the duration of the first integration period T1. At the end of the first integration period T1, the transfer gate 30 is pulsed to a first voltage level V1. This leads to the transfer of a portion of the accumulated charge carriers to the capacitance 40 or the diffusion node 42, respectively. Said portion is configured to be drained to the pixel supply voltage VDD. This is done via a reset signal RST, which is used to connect the diffusion node 42 to the pixel supply voltage VDD.

[0136] After the pulse of transfer gate 30, charge carriers continue to be accumulated by photodiode 20 during a second integration period T2, which may be shorter than the first integration period T1. The amount of charge carriers accumulated during the second integration period T2 depends on the duration of the second integration period T2.

[0137] In the illustrated example, during the second integration period T2, a reset pulse RST is applied to the reset gate 50. This removes any redundant charge carriers from the diffusion node 42, and in particular the portion of the stored charge carriers that were transferred during the V1 pulse, so that said portion is drained to the pixel supply voltage VDD.

[0138] At the end of the second integration period T2, the transfer gate 30 is again pulsed to the first voltage level V1, which leads to the transfer of a first portion of the stored charge carriers to the diffusion node 42. A low sensitivity signal representative of the first portion of the stored charge carriers is configured to be stored in the capacitors (70, 80), as described below.

[0139] During the third integration period T3, charge carriers continue to be accumulated by the photodiode 20. The amount of accumulated charge carriers depends on the duration of the third integration period T3. At the end of the third integration period T3, the transfer gate 30 is pulsed to a second voltage level V2, which leads to the transfer of the remaining portion of the accumulated charge carriers to the diffusion node 42. A sensitive signal representative of the remaining portion of the accumulated charge carriers is configured to be stored in the capacitors (70, 80), as described below.

[0140] memory period T FSThe first storage stage FS1 employs a pulse to a first voltage level V1, which leads to the transfer of a first portion of the stored charge carriers to the capacitance 40 or the diffusion node 42, respectively. The first portion may correspond to the charge carriers accumulated during the second integration period T2. The first and second switches S1, S2 are then applied to store a low-sensitivity signal representing the first portion of the stored charge carriers in a pair of capacitors 70, 80 electrically coupled to the capacitance 40 via the source follower 60. The low-sensitivity signal may be redistributed in the first capacitor 70 and the second capacitor.

[0141] The second storage phase FS2 follows by using a pulse to a second voltage level V2, which leads to the transfer of the remaining portion of the accumulated charge carriers to the capacitance 40 and the diffusion node 42, respectively. The remaining portion may correspond to the charge carriers accumulated during the first through third integration periods T1 through T3 (the drained portion minus the first portion). The second voltage level V2 may be a full voltage level so that all remaining charge carriers are transferred. The first switch signal S1 is then applied to the first switch 90 to store the high-sensitivity signal representing the remaining portion of the accumulated charge carriers in the first capacitor 70. Alternatively, the first switch signal S1 may remain high from the first pulse to the second pulse, as indicated by the dashed line.

[0142] Figure 8 shows example operations performed by the pixel array 10 shown in Figure 2A, Figure 3, or Figure 5. In Figure 8, the operations are shown in blocks. A method for operating the pixel array 10 includes, for example, the following blocks, which may be named procedures or steps:

[0143] Block 350: Start of exposure: Electromagnetic radiation is converted into charge carriers by the photodiode 20. This means that the charge carriers are accumulated in the photodiode 20. This stage lasts for an exposure period T ex It is sometimes called the exposure period Tex may be subdivided into several subsequent integration periods T1 and T2. The number of integration periods may be two.

[0144] Block 351: The transfer barrier is modified based on a system input: A transfer signal TX provided to transfer transistor 30 controls the barrier between photodiode 20 and FD node 42. At the end of a first integration period T1, transfer gate 30 is pulsed to a first voltage level V1 of transfer signal TX. The first voltage level V1 of transfer signal TX is selected so that the barrier to charge carrier flow between photodiode 20 and FD node 42 is low. This means that some of the accumulated charge carriers are transferred to FD node 42. This is followed by second and third integration periods T2, T3 during which charge carriers continue to accumulate.

[0145] A portion of the stored charge carriers will be drained to the pixel supply voltage, which can be done by applying a reset signal RST (and coupling signal DCG, if applicable) so that the FD node 42 is electrically connected to the pixel supply voltage VDD.

[0146] Block 352: Transfer of a first portion of the charge carriers accumulated by the photodiode 20 to the FD node 42. At the end of the second integration period T2, the transfer gate 30 is again pulsed to the first voltage level V1 of the transfer signal TX. This means that the first portion of the accumulated charge carriers is transferred to the FD node 42. The first portion of the charge carriers corresponds to the charge carriers accumulated during the second integration period T2. The charge carriers at the FD node 42 generate a capacitive voltage at the input 62 of the amplifier 60.

[0147] Block 353: Storage period T FSIn the first stage FS1, a first portion of the charge carriers is stored in the first and second capacitors 70, 80: the first and second switching transistors 90, 100 are set to a conductive state to transfer the first portion of the charge carriers from the FD node 42 to the second capacitor 80. This may mean that an amplified capacitance voltage is applied to the first and second capacitors 70, 80. The second switch signal S2 may have a short pulse to equalize the voltages on the first and second capacitors 70, 80. This may mean that the signal is redistributed on the first and second capacitors 70, 80. The amplified capacitance voltage corresponds to a low conversion gain (LCG) signal.

[0148] Block 354: Read period T ro In the first stage of the readout of the second capacitor 80: the output voltage tapped at the second capacitor 80 is amplified by a further amplifier 110. The select transistor 120 is turned on during the readout period T ro When set to a conductive state in a first readout phase, the amplified output voltage is provided to the column line 130 for digitization. A first digitized value is generated, for example by an evaluation circuit, as a function of the first value of the output voltage. The first value of the output voltage corresponds to the LCG signal.

[0149] Block 355: Transfer remaining charge carriers to FD node 42: At the end of the third integration period T3, the transfer gate 30 is pulsed to the second voltage level V2 of the transfer signal TX, which means that the remaining portion of the stored charge carriers are transferred to the FD node 42. Therefore, the transfer gate 30 is pulsed to different voltage levels V1, V2 to change the barrier potential.

[0150] By pulsing to a second voltage level, the barrier between the photodiode 20 and the FD node 42 is minimized or eliminated. The first voltage level V1 of the transfer signal results in a higher barrier than the second voltage level V2. In one example, V1 <V2である。

[0151] Block 356: Storage period T FS In the second stage FS2, the remaining charge carriers accumulated by the photodiode 20 are stored in the first capacitor 70. This may mean that the capacitance voltage VC tapped at the FD node 42 is amplified by the amplifier 60. The amplified capacitance voltage is provided to the first capacitor 70 by providing a pulse of the first switch signal S1 to the first switching transistor 90. The amplified capacitance voltage corresponds to a high conversion gain (HCG) signal.

[0152] Block 357: Read period T ro Reading the first capacitor 70 in the second stage RO2 of the readout stage RO: After the output voltage at the second capacitor 80 is read out in the first readout stage RO1 in block 354, the second switching transistor 100 is set to a conductive state. Thus, the voltage at the first capacitor 70 and the voltage at the second capacitor 80 become equal. Since the capacitance voltage is still amplified by the amplifier 60, the output voltage at the second capacitor 80 is equal to the amplified capacitance voltage. The output voltage is amplified by the further amplifier 110. When the selection transistor 120 is set to a conductive state in the second readout stage RO2 of the readout stage RO, the amplified output voltage is provided to the column line 130 for digitization. A second digitized value is generated by the evaluation circuit as a function of the second value of the output voltage. The second value of the output voltage corresponds to the HCG signal.

[0153] Typically, the steps of blocks 352, 353, 355, and 356 are performed over a frame storage period T FS The steps of blocks 354 and 357 are performed during the read period T ro It is executed in

[0154] Block 358: Subtract the voltage of the second capacitor 80 or the digitized value of the voltage of the second capacitor 80 from the voltage of the first capacitor 70 or the digitized value of the voltage of the first capacitor 70: The output signal representing the illuminance IL of the photodiode 20 is a function of the first digitized value (resulting from block 353) and the second digitized value (resulting from block 357). In one example, the first digitized value (resulting from block 353) is subtracted from the second digitized value (resulting from block 357) by an evaluation circuit. Because the first (digitized) value and the second (digitized) value are based on a common noise level, including in particular thermal noise and reset noise, this operation allows the HCG signal to be accessed by correlated double sampling (CDS). This means that the LCG signal can be used as a reference level for the HCG signal. Because the HCG signal is used in low-light conditions, thermal noise is a relevant parameter. Therefore, thermal noise and reset noise can be effectively suppressed by CDS. In high light conditions, the LCG signal is further processed, where photon shot noise dominates and thermal noise is less relevant.

[0155] Block 359: Gain up the LCG signal. This may mean that the LCG signal is adjusted. In particular, the LCG signal may be amplified. Adjusting or amplifying the LCG signal may be performed by an evaluation circuit. This step may occur particularly if the pixel array 10 includes a dual conversion transistor 140 and a third capacitor 150. In that case, the LCG signal may be sampled at a lower gain to expand the dynamic range. To compensate for this gain adjustment, the LCG signal is gain-up in block 359. However, if the pixel array 10 does not include a dual conversion gain procedure, this step may be omitted. In addition, the LCG signal may be accessed using double delta sampling (DDS). The LCG signal is used in high-illumination situations, where photon shot noise is dominant and thermal noise is less relevant. Therefore, correlated double sampling is not necessary to remove noise from the video signal. However, it may be desirable to remove fixed pattern noise (FPN) from the video signal. By performing double delta sampling (DDS), FPN can be removed from the LCG signal. The DDS can be implemented by subtracting a reset level from the LCG signal, which is set after the second readout phase for the readout period T ro The data can be read out in the third step.

[0156] Block 360: Per-Pixel Knee-Point Calibration: The HCG signal includes a first calibration level required in post-processing to remove FPN caused by transfer transistor variations that affect the threshold voltage. Since the same first voltage level V1 applied for barrier modulation after the first integration period T1 is also applied during readout, the HCG signal includes the knee-point calibration value required during linearization and FPN correction. Knee-point calibration is performed for each pixel individually. Block 360 is optional.

[0157] Block 361: Linearization. It is possible to reconstruct linearized pixel output signals, i.e. pixel output signals that are linearly dependent on the illumination level. Reconstructing pixel output signals may depend on lighting conditions.

[0158] In low light conditions, any pulse to the first voltage level V1 does not affect the charge on the photodiode. Reconstruction can be achieved by reading out the HCG signal with a CDS.

[0159] In high light conditions, both pulses to the first voltage level V1 affect the charge on the photodiode. For reconstruction, the LCG signal is used in the DDS. For linearization, it is multiplied by the exposure ratio T0 / T1, where T0 is the total exposure time.

[0160] In medium light conditions, only the second pulse to the first voltage level V1 affects the charge on the photodiode. For reconstruction, the HCG signal (with CDS) and the LCG signal (with DDS) are summed in the digital domain.

[0161] The voltage level V1 of the pulse for barrier modulation of the transfer transistor 30 can optionally be used to reconstruct the pixel output signal.

[0162] 9 shows exemplary characteristics of pixel array 10, for example, as shown in FIG. 2A and operated according to the methods of FIGS. 7 and 8. The response signal SIG in the artificial unit is shown as a function of illumination I in the artificial unit. Signal SIG1 (dotted line) is the signal resulting from the first integration period T1. Pulsing transfer gate 30 to a first voltage level V1 causes excess charge carriers to drain into the pixel supply voltage VDD, resulting in saturation at higher exposure levels.

[0163] Signal SIG2 (dashed line) is the signal resulting from the second integration period T2. Because integration period T2 may be shorter than integration period T1, the slope of signal SIG2 is less steep than the slope of signal SIG1. Alternatively or additionally, the slope of signal SIG2 is less steep than the slope of signal SIG1 because both signals are acquired at different conversion gains. For example, signal SIG1 (up to the knee point) is acquired at a high conversion gain. For example, signal SIG2 is acquired at a low conversion gain. Therefore, the slope depends, for example, on the value of capacitance 40 and the capacitance value of third capacitor 150. The difference in slope depends on the gain ratio. If the size of photodiode 20 is too small, signal SIG2 may saturate for very high illumination levels.

[0164] The output signal SIG3 (solid line) is a signal obtained by combining the signals SIG1 and SIG2. Furthermore, the output signal SIG3 may be a function of the signals SIG1, SIG2, and a reset signal (not shown). By combining the signals SIG1 and SIG2, the dynamic range of the pixel array 10 can be expanded. Because the HCG signal corresponds to the remaining charge carriers after the pulse to the first voltage level V1, the exact saturation level of the signal SIG1 can be determined from the HCG signal.

[0165] 10 shows another exemplary timing diagram implemented by pixel array 10, such as that shown in FIG. 2A. The timing according to FIG. 10 differs from the timing according to FIG. 7 in that the exposure periods are defined differently. In particular, the exposure period T ex is the storage period T FS 7, the exposure may stop after the second integration period T2. This can mean that the exposure includes or consists of the first and second integration periods T1, T2. A reset pulse RST is applied at the end of the second integration period T2 to remove any redundant charge carriers from the diffusion node 42, particularly the portion of the accumulated charge carriers that were transferred during the V1 pulse.

[0166] In that embodiment, the method for operating the pixel array 10 comprises: ex During this integration, the method includes accumulating charge carriers using photodiode 20 during a first integration period T1, pulsing transfer gate 30 to a first voltage level V1 at the end of first integration period T1 to transfer a portion of the accumulated charge carriers to capacitance 40, the portion being configured to drain to power supply voltage VDD, and continuing to accumulate charge carriers using photodiode 20 during a second integration period T2.

[0167] During a storage period TFS, the transfer gate 30 is pulsed to a first voltage level V1 to transfer a first portion of the stored charge carriers to the capacitance 40, storing a low sensitivity signal representative of the first portion of the stored charge carriers in a pair of capacitors 70, 80 electrically coupled to the capacitance 40, and the transfer gate 30 is pulsed to a second voltage level V2 to transfer the remaining portion of the stored charge carriers to the capacitance 40, storing a high sensitivity signal representative of the remaining portion of the stored charge carriers in the first capacitor 70 of the pair of capacitors 70, 80. ro During this time, the low and high sensitivity signals stored in the capacitors 70, 80 are read out.

[0168] For further details, reference is made to the description of Figure 7. The features disclosed in connection with Figure 7 also apply to the embodiment according to Figure 10.

[0169] The embodiments of the pixel array 10 and methods of operating such a pixel array 10 disclosed herein have been discussed for the purpose of familiarizing the reader with the novel aspects of the ideas. While preferred embodiments have been shown and described, many variations, modifications, equivalents, and substitutions of the disclosed concepts may be made by those skilled in the art without unnecessarily departing from the scope of the claims.

[0170] It will be understood that the present disclosure is not limited to the disclosed embodiments and particularly shown and described above. Rather, features described in separate dependent claims or in the specification may be advantageously combined. Moreover, the scope of the present disclosure includes those variations and modifications that are obvious to those skilled in the art and that fall within the scope of the appended claims.

[0171] The term "comprises", when used in the claims or the description, does not exclude other elements or steps of the corresponding feature or procedure. When the words "a" or "an" are used in connection with a feature, they do not exclude a plurality of such features. Moreover, any reference signs in the claims should not be construed as limiting the scope.

[0172] Reference sign 10 pixel array 20 Photodiode 30 Transfer Gate 40 Capacitance 42 Capacitance termination node 44 Further termination nodes of capacitance 50 Reset Gate 60 Amplifier 62 Amplifier input terminal 64 Amplifier output terminal 70 First capacitor 72 First capacitor termination node 74 Further termination node of the first capacitor 80 Second capacitor 82 Second capacitor termination node 84 Further termination node of the second capacitor 90 First Switch 100 Second Switch 110 More Amplifiers 112 Further amplifier input terminal 114 Further amplifier output terminal 120 Selection Gate 130 row bus 140 Sensitivity Gate 150 Third Capacitor 152 Third capacitor termination node 154 Further termination node of the third capacitor 160 Precharge Gate 200 Image Sensor 300 Optoelectronic Devices Blocks 350-361 998 Noise Floor 999 Saturation region DR Dynamic Range FS1, FS2 memory stages Illuminance PC Precharge signal Q charge RST Reset signal S1, S2 switch signals SIG1~SIG3 signal SEL selection signal Time points t1 to t8 T1, T2, T3 integration period T ex Pixel exposure, exposure period T FS Memory period T ro Pixel readout, readout period T rst Reset Period TX, TX1, TX2 transmission signals V1, V2 voltage levels VSS Negative pixel supply voltage, GND VDD Pixel power supply voltage [Explanation of symbols]

[0173] 10 pixel array, pixels 20 Photodiode, first photodiode 20' Second Photodiode 30 Transfer gate, transfer transistor 30' Second Transfer Gate 40 capacitance, floating diffusion capacitance 42 Terminal nodes, (floating) diffusion (FD) nodes, FD nodes 44 more end nodes 50 Reset Gate 60 Amplifier, Source Follower 62 Gate terminal, input terminal 64 output terminals 70 First capacitor 71 End Nodes 72 End Nodes 74 more end nodes 80 Second capacitor 82 End Nodes 84 more end nodes 90 first switch, gate terminal, first switching transistor 100 second switch, gate terminal, second switching transistor 110 More Amplifiers 110' Second further amplifier 112 Input terminal, gate 114 Output terminal 120 Select gate, select transistor 120' Further Selection Gates 130 row bus, row line 140 sensitivity gate, dual conversion transistor 150 Third Capacitor 152 End Nodes 154 more end nodes 160 Precharge Gate 200 Image Sensor 300 Optoelectronic Devices 998 noise floor, noise floor level 999 Saturation region

Claims

1. A method for operating a pixel array (10), comprising: - storing charge carriers using the photodiode (20) during a first integration period (T1); - at the end of said first integration period (T1), pulsing the transfer gate (30) to a first voltage level (V1) to transfer a portion of said stored charge carriers to a capacitance (40); - draining said portion to a power supply voltage (VDD); - continuing to accumulate charge carriers using said photodiode (20) during a second integration period (T2); - at the end of the second integration period (T2), pulsing the transfer gate (30) to the first voltage level (V1) to transfer a first portion of the stored charge carriers to the capacitance (40) and storing a low sensitivity signal representative of the first portion of the stored charge carriers in at least a second capacitor (80) of a pair of capacitors (70, 80) electrically coupled to the capacitance (40); - continuing to accumulate charge carriers using said photodiode (20) during a third integration period (T3); - at the end of the third integration period (T3), pulsing the transfer gate (30) to a second voltage level (V2) to transfer a remaining portion of the stored charge carriers to the capacitance (40) and storing a sensitive signal representative of the remaining portion of the stored charge carriers in a first capacitor (70) of the pair of capacitors (70, 80); - read period (T ｒｏ ) reading out the low sensitivity signal and the high sensitivity signal stored in the capacitors (70, 80); Including, The method, wherein the second voltage level (V2) is higher than the first voltage level (V1).

2. 2. The method of claim 1 , wherein the high sensitivity signal indicates a calibration level based on the remaining portion of the stored charge carriers, the method further comprising adjusting a pixel output signal based on the low sensitivity signal and the high sensitivity signal in dependence on a pixel-specific knee-point value determined based on the calibration level.

3. 2. The method of claim 1, wherein the first integration period (T1) is longer than the second integration period (T2).

4. Pixel Readout (T ｒｏ In the first step during the process, the low sensitivity signal is read out and readout (T ｒｏ In a second step during the pixel readout (T ｒｏ 2. The method of claim 1, wherein in a third step during step (a), the capacitance (40) is reset and a reset level is read out.

5. The method of claim 4 , further comprising performing double delta sampling by using the reset level as a reference level for the low sensitivity signal.

6. The method of claim 1 , further comprising performing correlated double sampling by using the low sensitivity signal as a reference level for the high sensitivity signal.

7. The method of claim 1 , further comprising determining whether to use the low sensitivity signal or the high sensitivity signal for further processing based on their respective amplitude levels.

8. 2. The method of claim 1, further comprising adjusting a conversion gain by applying a gain signal to short a termination node (42) of the capacitance (40) with a termination node (152) of a third capacitor (150).

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