Semiconductor device and method for manufacturing the same

Abstract

According to the present invention, a p-type impurity concentration profile (41) in the depth direction of a p-type base region is controlled by means of ion implantation into the p-type base region in two or more stages. The ion implantation into the p-type base region in two or more stages are performed at different accelerating voltages, while setting the dose amount such that the higher the accelerating voltage is, the lower the dose amount is. With respect to the p-type impurity concentration profile (41) in the depth direction of the p-type base region, the impurity concentration asymmetrically decreases from a depth position (D1), at which the impurity concentration is highest, toward the n+ type source region side and toward the n+ type drain region side. With respect to the p-type impurity concentration profile (41), the impurity concentration decreases in stages at one or more different depth positions on the n+ type drain region side from the depth position (D1). Consequently, the present invention is able to ameliorate the trade-off relationship between increase of a gate threshold voltage and decrease of an on-resistance.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Conventionally, in MOSFETs (Metal Oxide Semiconductor Field Effect Transistors: MOS field effect transistors with an insulated gate consisting of a three-layer structure of metal-oxide-semiconductor), there is a trade-off relationship in which increasing the gate threshold voltage to suppress false turn-on due to noise increases the on-resistance.To improve this trade-off relationship, the cell (component of the element) structure has been optimized.

[0003] Generally, in a SiC-MOSFET with a trench gate structure that uses silicon carbide (SiC) as the semiconductor material, the trade-off between increasing the gate threshold voltage and reducing the on-resistance is improved by miniaturizing the cell size and optimizing the design of the JFET (Junction FET) portion while maintaining a predetermined gate threshold voltage.

[0004] Optimizing the design of the JFET portion means making the JFET portion less susceptible to depletion when switching from off to on by increasing the impurity concentration in the JFET portion or widening the width of the JFET portion, thereby suppressing an increase in JFET resistance. The JFET portion is an n-type region that exists adjacent to the channel portion near the bottom of the trench (gate trench) and serves as the current path for the main current.

[0005] Fig. 6 is a cross-sectional view showing the structure of a conventional semiconductor device. The conventional semiconductor device 110 shown in Fig. 6 is a vertical SiC-MOSFET having a trench gate structure on the front surface side of a semiconductor substrate 130 using SiC as a semiconductor material. The semiconductor substrate 130 is an n + The n-type drain region 101 + On the starting substrate 131, n -The epitaxial layers 132 and 133 that become the p-type drift region 102 and the p-type base region 103 are stacked in this order.

[0006] The semiconductor substrate 130 has a main surface on the p-type epitaxial layer 133 side as the front surface, and an n + The main surface on the side of the starting substrate 131 is referred to as the back surface. The p-type epitaxial layer 133 is doped with p-type impurities such as aluminum (Al). The trench gate structure is formed by a p-type base region 103, an n-type base region 104, and a n-type base region 106. + type source region 104, p ++ It is composed of a mold contact region 105, a trench 106, a gate insulating film 107 and a gate electrode 108.

[0007] n + type source region 104 and p ++ The n-type contact region 105 is a diffusion region formed inside the p-type epitaxial layer 133 by ion implantation into the p-type epitaxial layer 133 from the front surface of the semiconductor substrate 130. + type source region 104 and p ++ The contact regions 105 are selectively provided between the front surface of the semiconductor substrate 130 and the p-type base region 103 so as to be in contact with the p-type base region 103, respectively.

[0008] The p-type epitaxial layer 133 has n + type source region 104 and p ++ The portion excluding the p-type contact region 105 is the p-type base region 103. The trench 106 is formed in the n-type + through the p-type source region 104 and the p-type base region 103; - The trench 106 terminates inside the type epitaxial layer 132. A gate electrode 108 is provided inside the trench 106 with a gate insulating film 107 interposed therebetween.

[0009] When the MOSFET is turned on, a channel (n-type inversion layer) is formed in a portion 103a (hereinafter referred to as the channel portion: the portion surrounded by the dashed line) of p-type base region 103 along the sidewall of trench 106. In order to adjust the resistance value of channel portion 103a, p-type impurities such as aluminum (Al) are introduced into p-type base region 103 by one-stage (single-time) ion implantation from the front surface of semiconductor substrate 130.

[0010] The gate threshold voltage and on-resistance are determined by the acceleration voltage and dose of this one-stage ion implantation into the p-type base region 103. A p-type impurity concentration profile 141 (see FIG. 3 described later) in the depth direction of the p-type base region 103 shows a peak concentration at the depth position of the range of one-stage ion implantation into the p-type base region 103, and the depth position D101 of the peak concentration is + The source region 104 side and the n + The impurity concentration is a Gaussian distribution that decreases at approximately the same gradient toward the source and drain regions 101 .

[0011] p-type base region 103 and n - The n-type drift region 102 is located between the trench 106 and the n-type drift region 102. + At a deep position on the side of the p + p-type regions 121, 122 and n-type current diffusion region 123 are selectively provided. + The n-type regions 121 and 122 and the n-type current diffusion region 123 are formed by ion implantation. - Diffusion regions formed within the epitaxial layer 132.

[0012] p + The p-type regions 121 and 122 have the function of alleviating the electric field applied to the gate insulating film 107 at the bottom of the trench 106. + The area between the n-type regions 121 and 122 forms an n-type JFET portion that serves as a current path for a drift current (main current) that flows from the drain electrode 112 to the source electrode 111 within the semiconductor substrate 130 when the MOSFET is in an on-state.

[0013] As a conventional vertical SiC-MOSFET with a trench gate structure, a device has been proposed in which the p-type base region is formed only with a p-type epitaxial layer (see, for example, Patent Document 1 below). In Patent Document 1 below, p-type impurity ions are not implanted into the p-type base region. As a result, the impurity concentration in the p-type base region is uniform, and no concentration gradient occurs in the p-type impurity concentration profile in the depth direction of the p-type base region.

[0014] In addition, as a conventional vertical SiC-MOSFET with a planar gate structure, the shallow part of the p-type base region from the front surface of the semiconductor substrate is formed only with a p-type epitaxial layer, and the deep part from the front surface of the semiconductor substrate is formed by ion implantation of p-type impurities into the n-type epitaxial layer below the p-type epitaxial layer. - A device formed inside a silicon epitaxial layer has been proposed (see, for example, Patent Document 2 below).

[0015] In Patent Document 2 below, the impurity concentration in a shallow portion of a p-type base region from the front surface of a semiconductor substrate is made lower than the impurity concentration in a deep portion of the p-type base region from the front surface of the semiconductor substrate. By making the impurity concentration in the deep portion of the p-type base region from the front surface of the semiconductor substrate relatively high, punch-through is suppressed, and by making the impurity concentration in the shallow portion from the front surface of the semiconductor substrate relatively low, channel mobility is increased.

[0016] Furthermore, as another vertical SiC-MOSFET with a conventional trench gate structure, a device has been proposed in which p-type impurities are introduced into the p-type base region by two-stage ion implantation with different acceleration voltages to form a p-type high-concentration implantation region (see, for example, Patent Document 3 below). In Patent Document 3 below, by forming a high-concentration implantation region in the p-type base region, the on-resistance is reduced without changing the gate threshold voltage and the variation in the gate threshold voltage.

[0017] In Patent Document 3, the p-type impurity concentration profile in the depth direction of the high concentration implantation region shows peak concentrations according to each ion implantation profile at the depth position of each range of two stages of ion implantation with different acceleration voltages, and n + The impurity concentration decreases in a gradient that forms a valley-like concave curve (a curve that is convex in the direction in which the impurity concentration decreases) toward the side of the type drain region. [Prior art documents] [Patent documents]

[0018] [Patent Document 1] Japanese Patent Publication No. 2020-191420 [Patent Document 2] Japanese Patent Application Publication No. 2018-206873 [Patent Document 3] Patent No. 6115678 Summary of the Invention [Problem to be solved by the invention]

[0019] However, in the above-described conventional semiconductor device 110 (see FIG. 6), there is a limit to how much the cell size can be reduced due to limitations in the manufacturing process imposed by processing accuracy, and therefore there is a limit to how much the on-resistance can be reduced by reducing the cell size. + If the on-resistance is reduced by widening the gap between the gate-source regions 121 and 122, the saturation current value increases and the short-circuit capability decreases. Short-circuit capability is the capability to withstand short-circuit current. Short-circuit current is the drain-source current that flows when the load or arm is short-circuited, and it can be a large current that exceeds the rated current. The saturation current value is the saturation value of the drain-source current, which is determined depending on the gate-source voltage.

[0020] In order to solve the above-mentioned problems associated with the conventional technology, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can improve the trade-off relationship between increasing the gate threshold voltage and reducing the on-resistance. [Means for solving the problem]

[0021] In order to solve the above-mentioned problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features: A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate made of silicon carbide. A second semiconductor region of a second conductivity type is provided between a first main surface of the semiconductor substrate and the first semiconductor region. A third semiconductor region of a first conductivity type is selectively provided between the first main surface and the second semiconductor region. A trench passes through the third semiconductor region and the second semiconductor region and reaches the first semiconductor region. A gate electrode is provided inside the trench via a gate insulating film.

[0022] The first electrode is electrically connected to the second semiconductor region and the third semiconductor region. The second electrode is provided on a second main surface of the semiconductor substrate. The impurity concentration profile in the depth direction of the second semiconductor region has a first gradient such that the impurity concentration decreases from a first depth position where the impurity concentration is highest toward the first main surface, and the impurity concentration monotonically decreases from the first depth position toward the second main surface, forming steps at one or more different second depth positions that are deeper toward the second main surface than the first depth position. By The impurity concentration profile of a curve that is convex in a direction in which the impurity concentration increases toward the second main surface side, Gentler than the first gradient to Low impurity concentration has a second gradient of .

[0023] Further, in the semiconductor device according to the present invention, in the above-described invention, the impurity concentration profile of the second semiconductor region forms a curve that is convex in a direction in which the impurity concentration increases toward the second main surface side between a predetermined second depth position and the first depth position adjacent to the second depth position on the first main surface side or another second depth position. The second It is characterized by a gradient in the impurity concentration.

[0024] In addition, the semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the impurity concentration profile of the second semiconductor region is such that the distance between a predetermined second depth position and the first depth position or another second depth position adjacent to the second depth position on the first main surface side is in the range of 0.1 μm or more and 0.2 μm or less.

[0025] In addition, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the impurity concentration of the second semiconductor region is 1 / 10 or more of the impurity concentration at the first depth position in a portion from the first depth position to a third depth position that is 0.2 μm toward the second main surface.

[0026] Moreover, in the semiconductor device according to the present invention, in the above-mentioned invention, the first depth position is located closer to the first main surface than the center of the second semiconductor region in the depth direction.

[0027] In the semiconductor device according to the present invention, the impurity concentration at the first depth position of the second semiconductor region is 4.0×10 17 / cm 3 Over 8.0 x 10 17 / cm 3 It is characterized by being within the following range.

[0028] The semiconductor device according to the present invention is the above-described one, further comprising a first high concentration region of a second conductivity type and a second high concentration region of a second conductivity type. The first high concentration region is selectively provided inside the semiconductor substrate closer to the second main surface than the bottom surface of the trench, separated from the second semiconductor region, and faces the bottom surface of the trench in the depth direction. The first high concentration region has a higher impurity concentration than the second semiconductor region. The second high concentration region is selectively provided inside the semiconductor substrate closer to the second main surface than the bottom surface of the trench, in contact with the second semiconductor region, and separated from the trench and the first high concentration region. The second high concentration region has a higher impurity concentration than the second semiconductor region.

[0029] In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention has the following features: A silicon carbide layer is epitaxially formed on a starting substrate made of silicon carbide. growth a first step of forming a semiconductor substrate having a first semiconductor region of a first conductivity type inside the silicon carbide layer, with the silicon carbide layer side as a first main surface and the starting substrate side as a second main surface; a second step of forming a second semiconductor region of a second conductivity type inside the silicon carbide layer between the first main surface and the first semiconductor region; a third step of selectively forming a third semiconductor region of a first conductivity type between the first main surface and the second semiconductor region in a surface region of the silicon carbide layer; a fourth step of forming a trench that penetrates the third semiconductor region and the second semiconductor region and reaches the first semiconductor region; and a fifth step of forming a gate electrode provided inside the trench with a gate insulating film interposed therebetween.

[0030] A sixth step is performed in which a first electrode electrically connected to the second semiconductor region and the third semiconductor region is formed. A seventh step is performed in which a second electrode is formed on the second main surface. In the second step, a second conductivity type impurity is introduced from the first main surface into the silicon carbide layer by two or more stages of ion implantation at different acceleration voltages, with the interior of the second semiconductor region being set as a depth position of the range, and with a lower dose as the acceleration voltage increases. As a result of the ion implantation, the impurity concentration in the second semiconductor region decreases at a first gradient from a first depth position at which the impurity concentration is highest toward the first main surface, and the impurity concentration monotonically decreases from the first depth position toward the second main surface, forming a step at one or more different second depth positions deeper toward the second main surface than the first depth position. ,mosquito and from the first depth position to the second depth position a curve that is convex in the direction in which the impurity concentration increases toward the second main surface side, Gentler than the first gradient to Impurity concentration is reduced Has a second gradient An impurity concentration profile in the depth direction is formed.

[0031] Furthermore, the method for manufacturing a semiconductor device according to the present invention is characterized in that, in the second step, the acceleration voltage of the ion implantation is set within a range of 1.3 to 1.6 times the acceleration voltage of the ion implantation having the next lowest acceleration voltage after the ion implantation.

[0032] Furthermore, the method for manufacturing a semiconductor device according to the present invention is characterized in that, in the second step, the dose of the ion implantation is set within a range of 10% to 20% of the dose of the ion implantation having the next lowest acceleration voltage after the ion implantation.

[0033] Furthermore, in the method for manufacturing a semiconductor device according to the present invention, in the above-described invention, the first step sequentially deposits, as the silicon carbide layer, a first conductivity type silicon carbide layer that becomes the first semiconductor region and a second conductivity type silicon carbide layer, and the second step defines a portion of the second conductivity type silicon carbide layer excluding the third semiconductor region as the second semiconductor region, and adjusts the second semiconductor region to the impurity concentration profile by the ion implantation.

[0034] In addition, the method for manufacturing a semiconductor device according to the present invention is characterized in that in the first step, the silicon carbide layer of a first conductivity type is deposited, and in the second step, the ion implantation is performed in the silicon carbide layer with a depth position of a range between the third semiconductor region and the first semiconductor region, thereby forming the second semiconductor region having the impurity concentration profile.

[0035] According to the above-described invention, the internal resistance of the portion of the second semiconductor region on the second main surface side is reduced, so that even if the impurity concentration of the portion of the second semiconductor region on the second main surface side is increased to increase the gate threshold voltage, the on-resistance does not increase. Alternatively, the on-resistance can be reduced while maintaining the gate threshold voltage. [Effects of the Invention]

[0036] The semiconductor device and the method for manufacturing the semiconductor device according to the present invention have the advantage of being able to improve the trade-off between increasing the gate threshold voltage and reducing the on-resistance. [Brief explanation of the drawings]

[0037] [Figure 1] FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a cross-sectional view schematically showing the vicinity of the channel portion of FIG. [Figure 3] FIG. 3 is a characteristic diagram showing an impurity concentration profile along the cutting line AA' in FIG. [Figure 4] FIG. 4 is a characteristic diagram showing an ion implantation profile in the channel portion of FIG. [Figure 5] FIG. 5 is a characteristic diagram showing the relationship between the gate threshold voltage and the on-resistance in the first and second embodiments. [Figure 6] FIG. 6 is a cross-sectional view showing the structure of a conventional semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0038] Preferred embodiments of a semiconductor device and a method for manufacturing a semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - symbols attached to n or p indicate that the impurity concentration is higher or lower than that of layers or regions not prefixed with these symbols, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted.

[0039] (Embodiment) The structure of a semiconductor device according to an embodiment will be described. FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view schematically showing the vicinity of a channel portion of FIG. 1. FIG. 3 is a characteristic diagram showing an impurity concentration profile along the cutting line A-A' of FIG. 2. FIG. 4 is a characteristic diagram showing an ion implantation profile of the channel portion of FIG. 1. A semiconductor device 10 according to an embodiment shown in FIG. 1 is a vertical SiC-MOSFET having a trench gate structure on the front surface side of a semiconductor substrate (semiconductor chip) 30 using silicon carbide (SiC) as a semiconductor material.

[0040] The semiconductor substrate 30 is an n-type semiconductor substrate using SiC as a semiconductor material. + On the front surface of the starting mold substrate 31, n - The semiconductor substrate 30 is an epitaxial substrate formed by laminating, in this order, epitaxial layers (silicon carbide layers) 32, 33 that become the p-type drift region (first semiconductor region) 2 and the p-type base region (second semiconductor region) 3. The semiconductor substrate 30 has a main surface on the side of the p-type epitaxial layer (second conductivity type silicon carbide layer) 33 as the front surface (first main surface), and an n-type base region (second semiconductor region) 34 as the back surface (first main surface). + The main surface (n + The back surface of the starting substrate 31 is referred to as the back surface (second main surface). - The n-type epitaxial layer (first conductivity type silicon carbide layer) 32 is doped with an n-type impurity such as nitrogen (N), and the p-type epitaxial layer 33 is doped with a p-type impurity such as aluminum (Al).

[0041] n + The starting substrate 31 is n + The n-type drain region is - The n-type drift region 2 has a depth direction + The p-type base region 3 is adjacent to the front surface of the semiconductor substrate 30 and the n-type starting substrate 31. - The trench gate structure is formed between the p-type base region 3 and the n-type drift region 2. + p-type source region (third semiconductor region) 4 ++ The p-type base region 3 and the n-type contact region 5 are connected to the trench 6, the gate insulating film 7, and the gate electrode 8. -Between the n-type drift region 2 and the bottom surface of the trench 6, + At a deep position on the side of the drain region 1 (the back side of the semiconductor substrate 30), p + n-type regions (first and second heavily doped regions) 21 and 22 and an n-type current diffusion region 23 are selectively provided.

[0042] p + The n-type regions 21 and 22 and the n-type current diffusion region 23 are formed by ion implantation. - The p-type epitaxial layer 32 is a diffusion region formed inside the p-type epitaxial layer 32. + The p-type region 21 is provided apart from the p-type base region 3 and faces the bottom surface of the trench 6 in the depth direction. + The mold region 21 is p + The p-type region 22 is electrically connected to the source electrode 11 by being partially connected to the p-type region 22 or to another p-type region. + The mold region 21 may be in contact with the gate insulating film 7 at the bottom of the trench 6 or may be spaced apart from the bottom of the trench 6 .

[0043] p + The mold region 21 preferably faces the bottom corners (boundaries between the sidewalls and the bottom) of the trench 6 in the depth direction. This also reduces the electric field applied to the gate insulating film 7 at the bottom corners of the trench 6, enhancing the electric field reduction effect near the bottom of the trench 6. + The type region 22 is formed between the adjacent trenches 6 and the p + It is provided away from the mold area 21. + The type region 22 is n + The p-type source region 4 contacts the p-type base region 3 on its surface (the front surface side of the semiconductor substrate 30 ), and is electrically connected to the source electrode 11 via the p-type base region 3 .

[0044] p + The mold regions 21 and 22 are adjacent to each other in a direction parallel to the front surface of the semiconductor substrate 30. +Between the p-type regions 21 and 22 is an n-type JFET portion formed adjacent to a channel portion 3a (described later) in the current path of a drift current (main current) flowing from the drain electrode 12 to the source electrode 11 in the semiconductor substrate 30. + n in type regions 21 and 22 + The surface on the side of the mold drain region 1 is located at approximately the same depth. "Approximately the same depth" means that the depth is the same within a range including tolerances due to process variations.

[0045] The n-type current diffusion region 23 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. The n-type current diffusion region 23 is a p-type current diffusion layer between the adjacent trenches 6. + The n-type current diffusion region 23 is provided in contact with the n-type regions 21 and 22. + The surface of the n-type source region 4 contacts the p-type base region 3, and the n-type source region 4 contacts the p-type base region 3. + n-type drain region 1 - The insulating film 7 is in contact with the gate electrode 10 and the gate drift region 2. The insulating film 7 is in contact with the gate electrode 10 and the gate electrode 10. The insulating film 7 is in contact with the gate electrode 10. The insulating film 7 extends in a direction parallel to the front surface of the semiconductor substrate 30 and reaches the trench 6.

[0046] The n-type current diffusion region 23 may not be provided. When the n-type current diffusion region 23 is not provided, the n-type current diffusion region 23 may be replaced by - Type drift region 2 is n + The n-type drain region 1 extends between the adjacent trenches 6 to the p-type base region 3, and also extends in a direction parallel to the front surface of the semiconductor substrate 30 to the trenches 6 and contacts the gate insulating film 7. - The p-type epitaxial layer 32 + The portion excluding the n-type regions 21 and 22 and the n-type current diffusion region 23 is n - This is the type drift region 2.

[0047] n + Type source region 4 and p ++ The n-type contact region 5 is a diffusion region formed inside the p-type epitaxial layer 33 by ion implantation into the p-type epitaxial layer 33 from the front surface of the semiconductor substrate 30. +Type source region 4 and p ++ The n-type contact regions 5 are selectively provided between the front surface of the semiconductor substrate 30 and the p-type base region 3, in contact with the p-type base region 3. + Type source region 4 and p ++ The contact region 5 is in ohmic contact with the source electrode 11 on the front surface of the semiconductor substrate 30 .

[0048] n + The source region 4 is p ++ The gate insulating film 7 is provided closer to the trench 6 than the contact region 5 and is in contact with the sidewall of the trench 6. ++ The contact region 5 may not be provided. ++ When the contact region 5 is not provided, ++ Instead of the n-type contact region 5, the p-type base region 3 reaches the front surface of the semiconductor substrate 30 and contacts the source electrode 11. + Type source region 4 and p ++ The portion excluding the contact region 5 is the p-type base region 3 .

[0049] The trench 6 is formed in a depth direction from the front surface of the semiconductor substrate 30. + through the p-type source region 4 and the p-type base region 3, - The n-type epitaxial layer 32 terminates inside the n-type epitaxial layer 32. A gate insulating film 7 is provided along the inner wall of the trench 6. A gate electrode 8 is provided inside the trench 6 on the gate insulating film 7. The gate electrode 8 is connected to the n-type epitaxial layer 32 via the gate insulating film 7 on the side wall of the trench 6. + The p-type source region 4, the p-type base region 3, and the n-type current diffusion region 23 (or the n-type current diffusion region 23 if the n-type current diffusion region 23 is not provided) are - It faces the mold drift region 2).

[0050] When the MOSFET is turned on, a channel (n-type inversion layer) is formed in a portion 3a (channel portion: portion surrounded by a dashed line) of the p-type base region 3 along the sidewall of the trench 6. P-type impurities such as aluminum (Al) are introduced into the p-type base region 3 by two or more stages (two times) of ion implantation from the front surface of the semiconductor substrate 30. This two or more stages (for example, two stages in FIGS. 3 and 4 ) of ion implantation into the p-type base region 3 optimizes a p-type impurity concentration profile 41 in the depth direction of the p-type base region 3, thereby adjusting the resistance value of the channel portion 3a.

[0051] The two or more stages of ion implantation into the p-type base region 3 are set to different acceleration voltages, and the higher the acceleration voltage, the lower the dose amount is set. Therefore, the higher the acceleration voltage, the more the n + The impurity concentration peaks at a depth deep on the side of the n-type drain region 1, and the impurity concentration peaks at a depth deep on the side of the n-type drain region 1. + type source region 4 side and n + A Gaussian distribution of ion implantation profiles (corresponding to ion implantation profiles 61 and 62 in FIG. 4) is formed in which the impurity concentration decreases at approximately the same gradient toward the type / drain region 1 side.

[0052] The conditions for each of the two or more stages of ion implantation into the p-type base region 3 are, for example, set such that the acceleration voltage is in the range of about 1.3 times to 1.6 times the acceleration voltage and dose amount of the ion implantation with the next lowest acceleration voltage after the ion implantation for which the conditions are set, and the dose amount is in the range of about 10% to 20%. Specifically, for example, the acceleration voltage for the predetermined ion implantation is set to 600 keV, and the dose amount is set to 1.5×10 13 / cm 2 In the case of ion implantation with the next highest acceleration voltage, the acceleration voltage is set to be in the range of 780 keV to 960 keV, and the dose is set to 1.5 × 10 12 / cm 2 Over 3.0 x 10 12 / cm 2 It is sufficient to keep it within the following range.

[0053] The p-type impurity concentration profile 41 in the depth direction of the p-type base region 3 shows peak concentrations at the depth positions of the ranges of two or more stages of ion implantation with different acceleration voltages (corresponding to depth positions D1 and D2 in FIG. 3), and n + The peak concentration is relatively lower at a position deeper toward the p-type drain region 1. The depth position (first depth position: corresponding to depth position D1 in FIG. 3) of the peak concentration of the ion implantation profile of the ion implantation with the lowest acceleration voltage in two or more stages of ion implantation into the p-type base region 3 is the highest impurity concentration in the p-type base region 3, and is located at a position deeper than the center of the p-type base region 3 in the depth direction. + It is preferable that the source region 4 be located on the side of the source region 4 .

[0054] The p-type impurity concentration profile 41 in the depth direction of the p-type base region 3 is the peak concentration (the highest n + The peak concentration of the source region 4 is measured from the depth of + The impurity concentration decreases toward the p-type source region 4 side. + The depth position of the peak concentration on the n-type source region 4 side + The ion implantation profile on the side of the type source region 4 is at a depth position of the peak concentration of the ion implantation profile of the ion implantation with the lowest acceleration voltage. + 1 shows an ion implantation profile on the side of the source region 4.

[0055] In the p-type impurity concentration profile 41 in the depth direction of the p-type base region 3, + The depth position of the peak concentration on the side of the source region 4 (corresponding to the depth position D1 in FIG. 3) is n + The p-type impurity concentration profile on the side of the p-type drain region 1 is closer to the n-type epitaxial layer 33 than the peak concentration depth position of the impurity concentration profile of the p-type epitaxial layer 33 and the ion implantation profile of the ion implantation with the lowest acceleration voltage among the two or more stages of ion implantation into the p-type base region 3. +The impurity concentration profile of the p-type epitaxial layer 33 is uniform in the depth direction, so the p-type impurity concentration profile 41 in the depth direction of the p-type base region 3 is the most n-type impurity concentration profile. + The depth of the peak concentration on the source region 4 side is asymmetric.

[0056] The p-type impurity concentration profile 41 in the depth direction of the p-type base region 3 is + The depth position of the peak concentration on the side of the source region 4 is + The impurity concentration decreases stepwise at the depth position (second depth position) of each ion implantation range except for the ion implantation with the lowest acceleration voltage toward the n-type drain region 1 side. + The depth position of the peak concentration on the drain region 1 side is + The ion implantation profile on the side of the type drain region 1 is at a depth position of n 1 lower than the peak concentration of the ion implantation profile of the ion implantation with the highest acceleration voltage. + 1 shows the ion implantation profile on the side of the silicon-doped drain region 1.

[0057] Furthermore, the p-type impurity concentration profile 41 in the depth direction of the p-type base region 3 has a peak concentration difference of n between the peak concentrations of the ion implantation profiles adjacent to each other in the depth direction. + The impurity concentration decreases in a gradient that forms a mountain-like curve (a curve that is convex in the direction in which the impurity concentration increases) toward the p-type drain region 1, or the impurity concentration is uniform (flat without a gradient). That is, the p-type impurity concentration profile 41 in the depth direction of the p-type base region 3 does not have a valley-like depression (a depression that is convex in the direction in which the impurity concentration decreases) between the peak concentrations of ion implantation profiles that are adjacent to each other in the depth direction.

[0058] The most n-type impurity concentration profile 41 in the depth direction of the p-type base region 3 + The peak concentration on the side of the type source region 4 is, for example, 4.0×10 17 / cm 3 Over 8.0 x 10 17 / cm 3 The p-type impurity concentration profile 41 in the depth direction of the p-type base region 3 is within a range of about n or less. + The depth position of the peak concentration on the n-type source region 4 side is + n type source region 4 + That is, the p-type impurity concentration profile 41 in the depth direction of the p-type base region 3 is set at the n-type drain region 1 side. + The depth position D1 to n of the peak concentration on the source region 4 side + The distance w1 to the boundary 51 between the p-type source region 4 and the p-type base region 3 is greater than 0 μm.

[0059] The distance w1 is, for example, about 10% to 30% of the channel length L (10%≦w1 / L×100≦30%). The channel length L is the length of the channel portion 3a along the sidewall of the trench 6, and n + It is the distance from a boundary 51 between the n-type source region 4 and the p-type base region 3 to a boundary 52 between the p-type base region 3 and the n-type current diffusion region 23. The distance between the peak concentrations of ion implantation profiles adjacent to each other in the depth direction of the p-type impurity concentration profile 41 in the depth direction of the p-type base region 3 (corresponding to the distance w2 in FIG. 4) is within a range of approximately 0.1 μm or more and 0.2 μm or less for all of the distances between the peak concentrations.

[0060] The most n-type impurity concentration profile 41 in the depth direction of the p-type base region 3 + It is preferable that the distance (corresponding to the distance w3 in FIG. 4) from the depth position of the peak concentration on the side of the p-type drain region 1 to the boundary 52 between the p-type base region 3 and the n-type current diffusion region 23 is as wide as possible. + The closer the depth position of the peak concentration on the side of the p-type drain region 1 to the n-type current diffusion region 23, the greater the n concentration of the p-type base region 3. + The impurity concentration on the side of the p-type drain region 1 becomes higher, and the channel portion 3a and p +This is because the current path of the drift current becomes highly resistant as the distance between the first region and the second region becomes narrower.

[0061] Specifically, for example, as described above, in the conventional semiconductor device 110 (see FIG. 6: hereinafter referred to as the conventional example), a p-type impurity concentration profile 141 in the depth direction of the p-type base region 103 is adjusted by one-stage ion implantation into the p-type base region 103. This p-type impurity concentration profile 141 in the depth direction of the p-type base region 103 shows a peak concentration at the depth position of the range of one-stage ion implantation into the p-type base region 103, and the depth position D101 of the peak concentration is + The source region 104 side and the n + The impurity concentration is a Gaussian distribution in which the impurity concentration decreases at approximately the same gradient toward the source and drain regions 101 (see FIG. 3).

[0062] That is, the p-type impurity concentration profile 141 in the depth direction of the p-type base region 103 of the conventional example is symmetrical with respect to the depth position D101 of the peak concentration of one ion implantation profile formed by one stage of ion implantation. + The source region 104 side and the n + It is not possible to adjust only the p-type impurity concentration profile on one side of the p-type drain region 101. The conditions for one stage of ion implantation into the p-type base region 103 in the conventional example shown in FIG. 3 are an acceleration voltage of about 600 keV, an aluminum dopant, and a dose of 1.5×10 13 / cm 2 (In Figure 3, it is shown as "Al600keV").

[0063] On the other hand, in the semiconductor device 10 according to the embodiment (hereinafter referred to as Examples 1 and 2), the p-type impurity concentration profile 41 in the depth direction of the p-type base region 3 is n +Only the side (one side) of the p-type drain region 1 can be adjusted. For example, to make it easier to compare Examples 1 and 2 with the conventional example, the conditions for the ion implantation with the lowest acceleration voltage (hereinafter referred to as the first-stage ion implantation) of the two-stage ion implantation into the p-type base region 3 in Examples 1 and 2 are set to be the same as the conditions for the first-stage ion implantation in the conventional example (shown as "Al 600 keV" in FIG. 3).

[0064] The conditions for the remaining stage of ion implantation (hereinafter referred to as the second stage ion implantation) of the two stages of ion implantation into the p-type base region 3 in Example 1 are, for example, an acceleration voltage of about 900 keV, aluminum as the dopant, and a dose of 2.0×10 12 / cm 2 (Figure 3 shows "+Al900keV_2×10 12 / cm 2 The second stage ion implantation conditions in Example 2 are, for example, an acceleration voltage of about 900 keV, aluminum as the dopant, and a dose of 3.0×10 12 / cm 2 (Figure 3 shows "+Al900keV_3×10 12 / cm 2 "). Examples 1 and 2 were fabricated under the same conditions except that the dose of the second stage ion implantation into the p-type base region 3 was different.

[0065] In Examples 1 and 2, the p-type impurity concentration profile 41 (41a, 41b) in the depth direction of the p-type base region 3 shows a peak concentration at the same depth position D1 as the depth position D101 of the peak concentration of the p-type impurity concentration profile 141 of the conventional example, due to the ion implantation profile 61 of the first stage ion implantation performed under the same ion implantation conditions as the conventional example. In addition, the p-type impurity concentration profile 41 (41a, 41b) in the depth direction of the p-type base region 3 shows a peak concentration at the same depth position D1 as the depth position D101 of the peak concentration of the p-type impurity concentration profile 141 of the conventional example. + The depth position D1 of the peak concentration on the side of the n-type source region 4 + The peak concentration of the ion implantation profile 62 of the second stage ion implantation is reached at a depth position D2 on the side of the type drain region 1.

[0066] As a result, the p-type impurity concentration profile 41 (41a, 41b) in the depth direction of the p-type base region 3 is + The depth position D1 of the peak concentration on the n-type source region 4 side + The p-type impurity concentration on the side of the p-type drain region 1 is set to be lower than the depth position D101 of the peak concentration of the p-type impurity concentration profile 141 of the conventional example. + Type drain region 101 The p-type impurity concentration profile 41 (41b) in the depth direction of the p-type base region 3 becomes higher as the dose of the second stage ion implantation becomes higher. + The depth position D1 of the peak concentration on the side of the n-type source region 4 + The p-type impurity concentration on the drain region 1 side becomes higher.

[0067] 3, the p-type impurity concentration profile 41 in the depth direction of the p-type base region 3 is + The peak concentration on the side of the type source region 4 is, for example, 6.0×10 17 / cm 3 n + The intersection of the n-type impurity concentration profile 42 in the depth direction of the source region 4 and the p-type impurity concentration profile 41 in the depth direction of the p-type base region 3 is the n + The boundary 51 is between the p-type source region 4 and the p-type base region 3. The intersection of the p-type impurity concentration profile 41 (41a, 42b) in the depth direction of the p-type base region 3 and the n-type impurity concentration profile 43 in the depth direction of the n-type current diffusion region 23 is the boundary 52 (52a, 52b) between the p-type base region 3 and the n-type current diffusion region 23.

[0068] n + The n-type impurity concentration profile 42 in the depth direction of the n-type source region 4 shows a peak concentration at a depth position away from the front surface of the semiconductor substrate 30, and the depth position of the peak concentration is + The impurity concentration is approximately Gaussian, decreasing toward the n-type drain region 101. +The n-type impurity concentration profile 42 in the depth direction of the n-type source region 4 may have two or more locations where the peak concentration is approximately the same due to two or more stages of ion implantation with approximately the same dose but different acceleration voltages. + The n-type impurity concentration profile 42 in the depth direction of the source region 4 may have a valley-like depression between peak concentrations (a curve that is convex in the direction in which the impurity concentration decreases).

[0069] The n-type impurity concentration profile 43 in the depth direction of the n-type current diffusion region 23 is a box profile formed by multiple stages of ion implantation with approximately the same dose but different acceleration voltages, and has locations with approximately the same peak concentration due to the multiple stages of ion implantation, equal to the number of stages of ion implantation. The n-type impurity concentration profile 43 in the depth direction of the n-type current diffusion region 23 may have valley-like depressions between the peak concentrations. The terms "approximately the same (or approximately uniform) impurity concentration" and "approximately the same dose" mean that the impurity concentration and dose are the same within the range of tolerance due to process variations.

[0070] Specifically, the n-type impurity concentration profile 43 in the depth direction of the n-type current diffusion region 23 has peak concentrations at the depth positions of the range of the multiple stages of ion implantation, and the n + type source region 4 side and n + The ion implantation profile has a Gaussian distribution in which the impurity concentration decreases toward the n-type drain region 1 side, forming a continuous wave shape in the depth direction Z. The n-type impurity concentration profile 43 in the depth direction of the n-type current diffusion region 23 is + The depth position of the peak concentration on the side of the source region 4 is + The impurity concentration may decrease toward the source region 4 side.

[0071] n +The region from the boundary 51 between the source region 4 and the p-type base region 3 to the boundary 52 (52a, 52b) between the p-type base region 3 and the n-type current diffusion region 23 is the channel region 3a of the p-type base region 3. The p-type impurity concentration profile 40 in the depth direction of the p-type epitaxial layer 33 is, for example, 3.5×10 16 / cm 3 Only the channel portion 3 a of the p-type base region 3 may have the above-described p-type impurity concentration profile 41, and the portion of the p-type base region 3 excluding the channel portion 3 a may be formed only by the p-type epitaxial layer 33, thereby achieving a uniform p-type impurity concentration profile in the depth direction.

[0072] The most n-type impurity concentration profile 41 in the depth direction of the p-type base region 3 + The on-resistance is determined by the peak concentration on the side of the p-type source region 4. + The peak concentration on the p-type source region 4 side and the n-type base region 3 + The part on the side of the drain region 1 (the most n + The depth position of the peak concentration on the n-type source region 4 side + The gate threshold voltage is determined by the impurity concentration in the p-type base region 3. + The higher the impurity concentration in the portion on the side of the p-type drain region 1, the higher the gate threshold voltage becomes, improving noise immunity and suppressing false turn-on of the MOSFET. + Since the internal resistance of the portion on the side of the gate-drain region 1 is small, the on-resistance can be maintained even if the gate threshold voltage is increased.

[0073] The p-type impurity concentration profile 41 in the depth direction of the p-type base region 3 is set to the n-type + The depth position of the peak concentration on the side of the source region 4 is +By gradually decreasing the impurity concentration toward the p-type drain region 1 side, it is possible to maintain the variation in the gate threshold voltage relative to the target gate threshold voltage value even if the gate threshold voltage value is increased. + The depth position of the peak concentration on the side of the source region 4 is + The most n-type semiconductor layer is formed in a portion up to a depth position (third depth position) of, for example, about 0.2 μm on the side of the drain region 1. + It is preferable that the concentration be, for example, about 1 / 10 or more of the peak concentration on the type source region 4 side.

[0074] The interlayer insulating film 9 is provided on the entire front surface of the semiconductor substrate 30, and covers the gate electrode 8. Although only one MOSFET cell (a constituent unit of an element) is shown in FIG. 1, a plurality of cells of the same structure are arranged adjacent to each other on the semiconductor substrate 30. The contact holes in the interlayer insulating film 9 are provided with n + Type source region 4 and p ++ Type contact region 5(p ++ If the p-type contact region 5 is not provided, the p-type base region 3) is exposed.

[0075] The source electrode (first electrode) 11 is in ohmic contact with the front surface of the semiconductor substrate 30 through a contact hole in the interlayer insulating film 9, and + Type source region 4, p ++ The drain electrode 12 is electrically connected to the n-type contact region 5 and the p-type base region 3. The drain electrode 12 is provided on the entire back surface of the semiconductor substrate 30. The drain electrode (second electrode) 12 is an n-type + Type drain region 1(n + ohmic contact with the starting substrate 31) + The gate electrode is electrically connected to the drain region 1.

[0076] The operation of the semiconductor device 10 according to the embodiment will be described. While a voltage less than the gate threshold voltage is applied to the gate electrode 8 in a state where a positive voltage (forward voltage) with respect to the source electrode 11 is applied to the drain electrode 12, p +The p-type regions 21 and 22 and the p-type base region 3, and the n-type current diffusion region 23 and the n - The pn junction (main junction) between the SiC-type drift region 2 and the SiC-type drift region 2 is reverse biased, so that the SiC-MOSFET (semiconductor device 10) maintains an off state.

[0077] On the other hand, when a voltage equal to or greater than the gate threshold voltage is applied to the gate electrode 8 while a forward voltage is applied between the source and drain, a channel (n-type inversion layer) is formed in the channel portion 3a along the sidewall of the trench 6 in the p-type base region 3. + The n-type drain region 1 passes through the channel portion 3a. + A current (drift current) flows toward the type source region 4, and the SiC-MOSFET is turned on.

[0078] p-type base region 3 + The portion on the side of the p-type drain region 1 is the n-type impurity concentration profile 41 in the depth direction of the p-type base region 3. + The internal resistance is lower than that of the peak concentration portion on the side of the p-type source region 4. + The voltage is also borne by the p-type drain region 1 side, so the n + The impurity concentration in the portion on the side of the gate drain region 1 determines the gate threshold voltage.

[0079] p-type base region 3 + As the thickness of the portion on the p-type drain region 1 side (corresponding to the sum of distances w2 and w3 in FIG. 4) increases, the n + As a result, the voltage burden on the portion on the side of the p-type drain region 1 increases. + This reduces the voltage burden on the peak concentration portion on the side of the source region 4.

[0080] When the SiC-MOSFET is fully turned on, the n +The internal resistance of the portion on the side of the p-type drain region 1 hardly contributes, and the most n-type impurity concentration profile 41 in the depth direction of the p-type base region 3 + The voltage is borne only by the peak concentration portion on the side of the p-type source region 4. Therefore, the most n-type impurity concentration profile 41 in the depth direction of the p-type base region 3 + The peak concentration on the side of the source region 4 determines the on-resistance.

[0081] The p-type impurity concentration profile 41 in the depth direction of the p-type base region 3 is + The depth position of the peak concentration on the side of the source region 4 is + The n-type base region 3 is gradually decreased toward the p-type drain region 1 side. + Even if the gate threshold voltage is increased by increasing the impurity concentration in the portion on the side of the type drain region 1, the variation in the gate threshold voltage can be maintained relative to the target gate threshold voltage value.

[0082] Next, a method for manufacturing the semiconductor device 10 according to the embodiment will be described. First, a method for manufacturing an n-type semiconductor device using SiC as a semiconductor material will be described. + On the front surface of the starting substrate (starting wafer) 31, n - n type drift region 2 - The n-type epitaxial layer 32 is epitaxially grown (deposited). - The type epitaxial layer 32 is epitaxially grown to a thickness thinner than the predetermined thickness after the product (semiconductor device 10) is completed. - The impurity concentration of the epitaxial layer 32 is, for example, 1×10 16 / cm 3 That's about it.

[0083] Next, photolithography and ion implantation of p-type impurities create n - The p epitaxial layer 32 is provided with p + Type region 21 and p + The lower part of the mold region 22 (n +The n-type drain region 1 side is selectively formed by photolithography and ion implantation of n-type impurities. - In the surface region of the epitaxial layer 32, adjacent p + Type region 21 and p + Between the n-type region 22 and the n-type current diffusion region 23, a lower portion of the n-type current diffusion region 23 is formed.

[0084] Next, further epitaxial growth is performed to - The n-type epitaxial layer 32 is then grown to a predetermined thickness. Then, the n-type epitaxial layer 32 is grown by photolithography and ion implantation of p-type impurities. - The thickened portion of the epitaxial layer 32 is + The upper part of the mold region 22 (n + The n-type source region 4 side portion is selectively formed. Also, by photolithography and ion implantation of n-type impurities, - In the thickened portion of the epitaxial layer 32, adjacent p + Between the n-type regions 22, an upper portion of an n-type current spreading region 23 is formed.

[0085] p + The upper portion of the n-type region 22 and the upper portion of the n-type current diffusion region 23 are p + The n-type region 22 and the n-type current diffusion region 23 are provided at positions opposite to each other. - The p-type epitaxial layer 32 is formed to a depth that penetrates the thickened portion thereof. + The n-type region 22 and the n-type current diffusion region 23 are connected to each other. - The p-type epitaxial layer 32 + The n-type regions 21 and 22 and the n-type current diffusion region 23 + The part on the mold starting substrate 31 side is n - This becomes the type drift region 2.

[0086] Next, n - On the p-type epitaxial layer 32, a p-type epitaxial layer 33 that will become the p-type base region 3 is epitaxially grown (deposited) to a thickness of, for example, about 1 μm. +In the first step, a semiconductor substrate (semiconductor wafer) 30 is fabricated (manufactured) by sequentially stacking epitaxial layers 32 and 33 on the front surface of a p-type starting substrate 31. Next, n-type epitaxial layers 32 and 33 are implanted into the surface region of the p-type epitaxial layer 33 by photolithography and ion implantation. + Type source region 4 and p ++ The mold contact regions 5 are selectively formed (third step).

[0087] The p-type epitaxial layer 33 has n + Type source region 4 and p ++ n-type contact region 5 - The portion on the p-type epitaxial layer 32 side becomes the p-type base region 3. Next, a p-type impurity concentration profile 41 in the depth direction of the p-type base region 3 is adjusted by two or more stages of ion implantation from the front surface of the semiconductor substrate 30 into the p-type base region 3 (second step). The two or more stages of ion implantation into the p-type base region 3 are set to different acceleration voltages depending on the depth position of the range inside the p-type base region 3, and the higher the acceleration voltage, the lower the dose is set.

[0088] In the two or more stages of ion implantation into the p-type base region 3 (two stages in FIG. 4), the higher the acceleration voltage of the ion implantation, the greater the n + The depth positions of the range (depth positions D1 and D2 in FIG. 4) are set to positions deep on the side of the p-type drain region 1, and an ion implantation profile with a wide half-width (ion implantation profiles 61 and 62 in FIG. 4) is formed. Ion implantation profiles adjacent in the depth direction formed by two or more stages of ion implantation into the p-type base region 3 may be adjacent in the depth direction or may overlap each other in the depth direction.

[0089] Furthermore, it is preferable that the two or more stages of ion implantation into the p-type base region 3 are performed so as not to implant p-type impurities into the n-type current diffusion region 23 as much as possible. That is, it is preferable that the ion implantation profile by ion implantation into the p-type base region 3 does not reach the n-type current diffusion region 23, and it is preferable that the ion implantation profile by ion implantation into the p-type base region 3 with the highest acceleration voltage (corresponding to the ion implantation profile 62 in FIG. 4) does not reach the p-type epitaxial layer 33 and the n-type current diffusion region 23.- It is preferable that the gate electrode terminates at the boundary with the type epitaxial layer 32 .

[0090] As described above, the peak concentration of the ion implantation profile by the ion implantation into the p-type base region 3 with the lowest acceleration voltage (i.e., the lowest n concentration of the p-type impurity concentration profile 41 in the depth direction of the p-type base region 3) is + The on-resistance is determined by the peak concentration of the p-type impurity concentration profile 41 in the depth direction of the p-type base region 3. + The depth position of the peak concentration on the side of the source region 4 (corresponding to the depth position D1 in FIG. 4) is n + The impurity concentration in the portion on the side of the gate drain region 1 determines the gate threshold voltage.

[0091] The p-type impurity concentration profile 41 in the depth direction of the p-type base region 3 is + The depth position of the peak concentration on the side of the source region 4 is + As a result, the p-type impurity concentration profile 41 in the depth direction of the p-type base region 3 is gradually decreased toward the n-type drain region 1 side, compared with the p-type impurity concentration profile 141 in the depth direction of the p-type base region 103 of the conventional example (see FIG. 3). + The depth position of the peak concentration on the n-type source region 4 side + The impurity concentration on the side of the gate drain region 1 becomes higher.

[0092] The order of performing two or more stages of ion implantation into the p-type base region 3 can be changed as appropriate, but if ion implantation with a high acceleration voltage is performed after ion implantation with a low acceleration voltage, there is a risk that the impurities introduced by the ion implantation with a low acceleration voltage will be pushed deeper into the semiconductor substrate 30 by the subsequent ion implantation with a high acceleration voltage. For this reason, performing ion implantation with a high acceleration voltage first makes it easier to adjust the p-type impurity concentration profile 41 in the depth direction of the p-type base region 3 to the desired p-type impurity concentration profile.

[0093] Alternatively, the p-type base region 3 may have the p-type impurity concentration profile 41 in the depth direction. An n-type epitaxial layer may be deposited instead of the p-type epitaxial layer 33, and the p-type impurity may be introduced into the region of the n-type epitaxial layer where the p-type base region 3 is to be formed by two or more stages of ion implantation to form the p-type impurity concentration profile 41. In this case, the surface region of the n-type epitaxial layer may have an n-type impurity layer in contact with the p-type base region 3. + Type source region 4 and p ++ Mold contact regions 5 are selectively formed respectively.

[0094] The p-type impurity concentration profile 41 in the depth direction of the p-type base region 3 is adjusted (or formed), and the n + Formation of p-type source region 4 and ++ The order of steps 4 to 7, including the formation of the silicon-doped contact region 5, can be changed as appropriate. Next, a heat treatment is performed to activate all of the ion-implanted impurities. Next, trenches 6, gate insulating films 7, gate electrodes 8, interlayer insulating films 9, source electrodes 11, and drain electrodes 12 are formed by a general method (steps 4 to 7). Thereafter, the semiconductor wafer (semiconductor substrate 30) is diced (cut) into individual chips, thereby completing the semiconductor device 10 shown in FIG. 1.

[0095] As described above, according to the embodiment, the p-type impurity profile in the depth direction of the p-type base region is adjusted by two or more stages of ion implantation to obtain the most n-type impurity. + The depth of the peak concentration on the source region side is n + The n-type base region is gradually reduced toward the p-type drain region side by ion implantation at a high acceleration voltage. + The internal resistance of the p-type base region is reduced, + Even if the impurity concentration in the portion on the side of the gate-drain region is increased to increase the gate threshold voltage, the on-resistance does not increase. Alternatively, the on-resistance can be reduced while maintaining the gate threshold voltage. Therefore, the trade-off between increasing the gate threshold voltage and reducing the on-resistance can be improved.

[0096] (Example) The relationship between the gate threshold voltage and the on-resistance of the semiconductor device 10 according to the embodiment was examined. Fig. 5 is a characteristic diagram showing the relationship between the gate threshold voltage and the on-resistance of Examples 1 and 2. The horizontal axis of Fig. 5 represents the gate threshold voltage Vth [V], and the vertical axis represents the on-resistance RonA [mΩ cm 2 5 shows the relationship between the gate threshold voltage Vth and the on-resistance RonA for the above-described first and second embodiments and the conventional example.

[0097] From the results shown in FIG. 5, it was confirmed that in both Examples 1 and 2, when the on-resistance RonA was set to be the same as that of the conventional example, the gate threshold voltage Vth could be made higher than that of the conventional example. Also, When the gate threshold voltage Vth is set to the same value as in the conventional example, it was confirmed that the on-resistance RonA can be reduced compared to the conventional example while maintaining the variation in the gate threshold voltage Vth relative to the target gate threshold voltage value at the same level as in the conventional example.

[0098] From these findings, it was confirmed that the trade-off between increasing the gate threshold voltage Vth and reducing the on-resistance RonA can be improved by adjusting the p-type impurity concentration profile 41 in the depth direction of the p-type base region 3 (see FIG. 3), as described above. Therefore, a vertical SiC-MOSFET with a trench gate structure can be structured so that the on-resistance does not increase even if the gate threshold voltage Vth is increased.

[0099] The present invention can be modified in various ways, and in the above-described embodiments, for example, the dimensions of each part and the impurity concentration are variously set according to the required specifications, etc. Also, in the embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but the present invention is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0100] As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines. [Explanation of symbols]

[0101] 1n + Type drain region 2n - Type Drift Region 3 p-type base region 3a Channel part 4n + Type Source Area 5 p ++ Mold contact area 6. Trench 7 Gate insulating film 8 gate electrode 9 Interlayer insulating film 10 Semiconductor devices 11 Source electrode 12 Drain electrode 21,22 pages + type area 23 n-type current diffusion region 30 Semiconductor substrate 31n + Starting substrate 32n - Type epitaxial layer 33 p-type epitaxial layer 40, 41, 41a, 41b p-type impurity concentration profile 42,43 n-type impurity concentration profile 51n + The boundary between the p-type source region and the p-type base region 52 Boundary between p-type base region and n-type current diffusion region 61,62 Ion implantation profile D1, D2 Depth position of peak concentration of ion implantation profile L channel length

Claims

1. a semiconductor substrate made of silicon carbide; a first semiconductor region of a first conductivity type provided inside the semiconductor substrate; a second semiconductor region of a second conductivity type provided between the first main surface of the semiconductor substrate and the first semiconductor region; a third semiconductor region of the first conductivity type selectively provided between the first major surface and the second semiconductor region; a trench that penetrates the third semiconductor region and the second semiconductor region and reaches the first semiconductor region; a gate electrode provided inside the trench via a gate insulating film; a first electrode electrically connected to the second semiconductor region and the third semiconductor region; a second electrode provided on a second main surface of the semiconductor substrate; Equipped with The impurity concentration profile of the second semiconductor region in the depth direction is the impurity concentration decreases at a first gradient from a first depth position where the impurity concentration is highest toward the first main surface; the impurity concentration monotonically decreases from the first depth position toward the second main surface side, and a step is formed at one or more different second depth positions that are deeper toward the second main surface side than the first depth position; the impurity concentration profile from the first depth position to the second depth position forms a curve that is convex in the direction in which the impurity concentration increases toward the second main surface side, and has a second gradient in which the impurity concentration decreases more gradually than the first gradient.

2. 2. The semiconductor device according to claim 1, wherein the impurity concentration profile of the second semiconductor region, between a predetermined second depth position and the first depth position adjacent to the second depth position on the first main surface side or another second depth position, has a second gradient that forms a curve that is convex in the direction in which the impurity concentration increases as the impurity concentration decreases toward the second main surface side.

3. 2. The semiconductor device according to claim 1, wherein the impurity concentration profile of the second semiconductor region is such that the distance between a predetermined second depth position and the first depth position or another second depth position adjacent to the second depth position on the first main surface side is in the range of 0.1 μm or more and 0.2 μm or less.

4. 2. The semiconductor device according to claim 1, wherein the impurity concentration of the second semiconductor region is 1 / 10 or more of the impurity concentration at the first depth position in a portion from the first depth position to a third depth position 0.2 μm toward the second main surface.

5. 2. The semiconductor device according to claim 1, wherein the first depth position is closer to the first main surface than the center of the second semiconductor region in the depth direction.

6. The impurity concentration at the first depth position of the second semiconductor region is 4.0×10 17 / cm 3 Above 8.0 x 10 17 / cm 3 2. The semiconductor device according to claim 1, wherein the semiconductor device is within the following range.

7. a first high concentration region of a second conductivity type having an impurity concentration higher than that of the second semiconductor region, the first high concentration region being selectively provided within the semiconductor substrate closer to the second main surface than a bottom surface of the trench and spaced apart from the second semiconductor region and facing the bottom surface of the trench in a depth direction; a second high concentration region of a second conductivity type having an impurity concentration higher than that of the second semiconductor region, the second high concentration region being selectively provided inside the semiconductor substrate closer to the second main surface than the bottom surface of the trench, the second high concentration region being in contact with the second semiconductor region and being spaced apart from the trench and the first high concentration region; 2. The semiconductor device according to claim 1, further comprising:

8. a first step of epitaxially growing a silicon carbide layer on a starting substrate made of silicon carbide to produce a semiconductor substrate having a first main surface on the silicon carbide layer side and a second main surface on the starting substrate side, the semiconductor substrate having a first semiconductor region of a first conductivity type inside the silicon carbide layer; a second step of forming a second semiconductor region of a second conductivity type between the first main surface and the first semiconductor region within the silicon carbide layer; a third step of selectively forming a third semiconductor region of a first conductivity type between the first main surface and the second semiconductor region in a surface region of the silicon carbide layer; a fourth step of forming a trench that penetrates the third semiconductor region and the second semiconductor region and reaches the first semiconductor region; a fifth step of forming a gate electrode provided inside the trench with a gate insulating film interposed therebetween; a sixth step of forming a first electrode electrically connected to the second semiconductor region and the third semiconductor region; a seventh step of forming a second electrode on the second main surface; Including, In the second step, introducing a second conductivity type impurity into the silicon carbide layer from the first main surface by two or more stages of ion implantation at different acceleration voltages, with a dose being lowered as the acceleration voltage is higher, with the interior of the second semiconductor region being a depth position of the range; The ion implantation causes the second semiconductor region to the impurity concentration decreases at a first gradient from a first depth position where the impurity concentration is highest toward the first main surface; and forming an impurity concentration profile in the depth direction, wherein the impurity concentration monotonically decreases from the first depth position toward the second main surface side, forming a step at one or more different second depth positions that are deeper than the first depth position toward the second main surface side, and forming a second gradient from the first depth position to the second depth position that is convex in the direction in which the impurity concentration increases toward the second main surface side, and in which the impurity concentration decreases more gradually than the first gradient.

9. 9. The method for manufacturing a semiconductor device according to claim 8, wherein in the second step, the acceleration voltage of the ion implantation is set within a range of 1.3 to 1.6 times the acceleration voltage of the ion implantation having the next lowest acceleration voltage after the ion implantation.

10. 9. The method for manufacturing a semiconductor device according to claim 8, wherein in the second step, the dose of the ion implantation is set within a range of 10% to 20% of the dose of the ion implantation having the next lowest acceleration voltage.

11. In the first step, a first conductivity type silicon carbide layer that becomes the first semiconductor region and a second conductivity type silicon carbide layer are sequentially deposited as the silicon carbide layer; 9. The method for manufacturing a semiconductor device according to claim 8, wherein in the second step, a portion of the second conductivity type silicon carbide layer excluding the third semiconductor region is defined as the second semiconductor region, and the second semiconductor region is adjusted to the impurity concentration profile by the ion implantation.

12. In the first step, the silicon carbide layer of a first conductivity type is deposited; 9. The method for manufacturing a semiconductor device according to claim 8, wherein in the second step, the ion implantation is performed with a depth position of a range between the third semiconductor region and the first semiconductor region of the silicon carbide layer, thereby forming the second semiconductor region having the impurity concentration profile.

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