Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device with a vertical, the vertical element having drift region of a first conductivity type provided on a semiconductor substrate, a first injection portion provided below the drift region, and a second injection portion provided below the drift region and having a lower carrier injection efficiency than that of the first injection portion. The first injection portion is larger in area than the second injection portion on a back surface of the semiconductor substrate, and the vertical element has the first injection portion and the second injection portion provided alternately in a predetermined direction.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Patent Document 1 states that "the first low injection region 27 may be provided on the lower surface side of the semiconductor substrate 10 in the Y-axis direction, sandwiched between collector regions 22 provided on both ends of the transistor section 70." [Prior art document] [Patent documents] [Patent Document 1] JP 2019-161168 A [Patent Document 2] Japanese Patent Application Laid-Open No. 2005-333055 [Patent Document 3] General Disclosure of Japanese Patent Application Laid-Open No. 2000-4017

[0003] It is desirable to improve the tradeoff between on-state voltage Von and turn-off loss Eoff in a semiconductor device.

[0004] A first aspect of the present invention provides a semiconductor device including a vertical element, the vertical element having a drift region of a first conductivity type provided in a semiconductor substrate, a first injection portion provided below the drift region, and a second injection portion provided below the drift region and having a lower carrier injection efficiency than the first injection portion, the area of ​​the first injection portion being larger than the area of ​​the second injection portion on the back surface of the semiconductor substrate, and the vertical element having the first injection portion and the second injection portion arranged alternately in a predetermined direction.

[0005] In the semiconductor device, the vertical element may have the first implantation portion and the second implantation portion that are regularly arranged.

[0006] Any of the above semiconductor devices may include a plurality of trenches formed in the front surface of the semiconductor substrate, and the predetermined direction may be inclined at an angle of 0 to 90 degrees with respect to an extension direction of the plurality of trenches.

[0007] In any of the above semiconductor devices, the first implantation portion includes a first implantation region of a second conductivity type provided in the semiconductor substrate below the drift region, and a doping concentration of the first implantation region is 1E16 cm ―3 Above, 1E18cm ―3 It may be the following:

[0008] In any of the above semiconductor devices, the second implantation portion may include a second implantation region of a second conductivity type provided below the drift region in the semiconductor substrate, and the doping concentration of the second implantation region may be lower than the doping concentration of the first implantation region.

[0009] In any of the above semiconductor devices, the doping concentration of the second implantation region is 1E15 cm ―3 The doping concentration of the first implantation region may be equal to or greater than 0.5 times the doping concentration of the first implantation region.

[0010] Any of the above semiconductor devices may include an active region provided in the semiconductor substrate, an edge termination structure surrounding the active region in the semiconductor substrate, and a back surface low implantation region extending from below the edge termination structure to below the active region and adjacent to the first implantation region, the back surface low implantation region having a doping concentration lower than that of the first implantation region, wherein the boundary between the first implantation region and the back surface low implantation region may be located closer to the active region than the boundary between the active region and the edge termination structure.

[0011] In any of the above semiconductor devices, the doping concentration of the back surface low implantation region is 1E15 cm ―3 The doping concentration of the first implantation region may be equal to or greater than 0.5 times the doping concentration of the first implantation region.

[0012] In any of the above semiconductor devices, the doping concentration of the back surface low implantation region may be 0.01 to 0.5 times the doping concentration of the first implantation region.

[0013] Any of the above semiconductor devices may further include a gate pad portion provided above the semiconductor substrate outside the active region and electrically connected to the gate conductive portion of the vertical element, and the back surface low implantation region may be located below the gate pad portion.

[0014] Any of the above semiconductor devices may further include a gate runner that electrically connects the gate pad portion and the gate conductive portion, and the back surface low implantation region may be located below the gate runner.

[0015] In any of the above semiconductor devices, the proportion of the first implantation portion on the back surface of the vertical element may be 60% or more and 90% or less.

[0016] In any of the above semiconductor devices, the first implantation portion may have a first implantation region of a second conductivity type provided in the semiconductor substrate below the drift region, and the second implantation portion may have a second implantation region of the second conductivity type provided in the semiconductor substrate below the drift region. At the first implantation portion, the back surface of the semiconductor substrate may be in contact with a back surface electrode, and at the second implantation portion, the back surface of the semiconductor substrate may not be in contact with the back surface electrode.

[0017] In any of the above semiconductor devices, the second implantation portion may have an insulating film provided below the second implantation region, and the insulating film may be in contact with the rear surface of the semiconductor substrate.

[0018] In any of the above semiconductor devices, the second implantation portion may include a second implantation region of a second conductivity type provided below the drift region in the semiconductor substrate, an insulating film in contact with the second implantation region on the back surface of the semiconductor substrate, and a back surface electrode in contact with the insulating film below the insulating film.

[0019] In any of the above semiconductor devices, the proportion of the first implantation portion in the vertical element may be 75% or more and 99% or less.

[0020] In any of the above semiconductor devices, the first implantation portion may include a first implantation region of a second conductivity type provided in the semiconductor substrate below the drift region. The second implantation portion may include a second implantation region of the second conductivity type provided in the semiconductor substrate below the drift region. A lifetime in the second implantation region may be shorter than a lifetime in the first implantation region.

[0021] In any of the above semiconductor devices, the first implanter may include a first implantation region of a second conductivity type provided in the semiconductor substrate below the drift region. The second implanter may include a second implantation region of the second conductivity type provided in the semiconductor substrate below the drift region. The second implantation region may contain at least one element of Ar, Si, C, O, He, and H in a larger amount than the first implantation region.

[0022] In any of the above semiconductor devices, the vertical element may have a transistor portion, and the semiconductor device may be an RC-IGBT further including a diode portion.

[0023] In any of the above semiconductor devices, the back surface of the transistor section at the boundary between the transistor section and the diode section may be the first implantation section.

[0024] In any of the above semiconductor devices, the back surface of the transistor section at the boundary between the transistor section and the diode section may be the second implantation section.

[0025] Any of the above semiconductor devices may further include a lifetime control region extending from the diode portion to the transistor portion and including a lifetime killer, the lifetime control region being provided in the drift region.

[0026] In a second aspect of the present invention, there is provided a method for manufacturing a semiconductor device having a vertical element, the method comprising the steps of: forming a drift region of a first conductivity type in a semiconductor substrate; providing a first implantation portion in the semiconductor substrate below the drift region; and providing a second implantation portion in the semiconductor substrate below the drift region, the second implantation portion having a lower carrier injection efficiency than the first implantation portion, wherein, on a back surface of the semiconductor substrate, an area of ​​the first implantation portion is larger than an area of ​​the second implantation portion, and the first implantation portion and the second implantation portion are provided alternately in a predetermined direction.

[0027] In the above-described method for manufacturing a semiconductor device, the step of providing the first implanted portion may include the step of providing a first implanted region of a second conductivity type below the drift region in the semiconductor substrate. The step of providing the second implanted portion may include the step of providing a second implanted region of a second conductivity type below the drift region in the semiconductor substrate. The step of providing the first implanted region may include the step of irradiating with light. The step of providing the second implanted region may include the step of irradiating with light having higher energy than the light irradiation used in the step of providing the first implanted region.

[0028] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0029] [Figure 1A] FIG. 2 is a diagram showing an example of the top surface of the semiconductor device 100. [Figure 1B] FIG. 1B is a diagram showing an example of a cross section taken along aa' in FIG. 1A. [Figure 1C] 2 is a diagram showing an example of the bottom surface of the semiconductor device 100. FIG. [Figure 1D] 10 is a diagram showing an example of the bottom surface of a modified example of the semiconductor device 100. FIG. [Figure 1E] 10 is a diagram showing an example of the bottom surface of a modified example of the semiconductor device 100. FIG. [Figure 1F]10 is a diagram showing an example of the bottom surface of a modified example of the semiconductor device 100. FIG. [Figure 1G] 10 is a diagram showing an example of the bottom surface of a modified example of the semiconductor device 100. FIG. [Figure 2] FIG. 10 is a top view of a modified example of the semiconductor device 100. [Figure 3A] FIG. 3 is an enlarged view of the top surface of region A in FIG. [Figure 3B] FIG. 3B is a diagram showing an example of a cross section taken along the line cc' in FIG. 3A. [Figure 4] FIG. 3 is a diagram showing an example of a cross section taken along line bb' in FIG. 2. [Figure 5] FIG. 3 is an enlarged view of the top surface of region C in FIG. [Figure 6] 10 is a diagram showing the relationship between the area ratio of the first injection section 171 and Von-Eoff in the transistor section 70. FIG. [Figure 7A] 1 is a diagram showing an example of a cross section of a modified example of the semiconductor device 100. FIG. [Figure 7B] 1 is a diagram showing an example of a cross section of a modified example of the semiconductor device 100. FIG. [Figure 7C] 1 is a diagram showing an example of a cross section of a modified example of the semiconductor device 100. FIG. [Figure 7D] 1 is a diagram showing an example of a cross section of a modified example of the semiconductor device 100. FIG. [Figure 8] 10 is a diagram showing the relationship between the area ratio of the first injection section 171 and Von-Eoff in the transistor section 70. FIG. [Figure 9] 3 is a flowchart showing an example of a manufacturing process for the semiconductor device 100. DETAILED DESCRIPTION OF THE INVENTION

[0030] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0031] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "top" and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the top surface and the other surface is referred to as the bottom surface. The directions of "top," "bottom," "front," and "back" are not limited to the direction of gravity or the direction in which the semiconductor device is attached to a substrate or the like when mounted.

[0032] In this specification, technical matters may be explained using the Cartesian coordinate axes of the X-axis, Y-axis, and Z-axis. The Cartesian coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is written without specifying positive or negative, it means the direction parallel to the +Z-axis and -Z-axis.

[0033] In this specification, the plane parallel to the top surface of the semiconductor substrate is referred to as the XY plane, and the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis. The depth direction of the semiconductor substrate may be referred to as the Z-axis. In this specification, the view of the semiconductor substrate in the Z-axis direction is referred to as a planar view. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0034] In each embodiment, an example is shown in which the first conductivity type is N-type and the second conductivity type is P-type, but the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment will be opposite polarities.

[0035] In this specification, when we say "same" or "equal," it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0036] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting N-type conductivity or a semiconductor exhibiting P-type conductivity.

[0037] In this specification, doping concentration means the concentration of donors or acceptors at thermal equilibrium.

[0038] In this specification, when P+ type or N+ type is mentioned, it means that the doping concentration is higher than that of P type or N type, and when P- type or N- type is mentioned, it means that the doping concentration is lower than that of P type or N type.

[0039] FIG. 1A shows an example of the top surface of a semiconductor device 100. The semiconductor device 100 of this example is a semiconductor chip including at least a transistor section 70. The transistor section 70 is an example of a vertical element 700. That is, the vertical element 700 may include the transistor section 70. Hereinafter, the vertical element 700 may be described as the transistor section 70. Features described as features of the transistor section 70 may also be features of the vertical element 700. For example, the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT). As another example, the semiconductor device 100 may be an IGBT, a bipolar PIN diode, a MOSFET, or a Schottky barrier diode. However, the semiconductor device 100 is not limited to these. In this way, the vertical element 700 included in the semiconductor device 100 may have a PN junction in which a first conductivity type region and a second conductivity type region are in contact with each other.

[0040] The transistor section 70 is a region obtained by projecting a collector region 22 provided on the back surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The collector region 22 is an example of an implantation region 220. The collector region 22 and the implantation region 220 will be described later. The transistor section 70 includes a transistor such as an IGBT. The transistor section 70 may also include a transistor such as a MOSFET.

[0041] FIG. 1A shows the region around the chip edge, which is the edge side of semiconductor device 100, and omits other regions. For example, an edge termination structure may be provided in the region on the negative side of semiconductor device 100 in the Y-axis direction in this example. The edge termination structure reduces electric field concentration on the upper surface side of semiconductor substrate 10. The edge termination structure may have, for example, a guard ring, a field plate, a resurf, or a structure combining these. Note that, for convenience, this example describes the edge on the negative side of the Y-axis direction, but the same applies to other edges of semiconductor device 100. The edge termination structure may be provided to surround an active region including transistor portion 70.

[0042] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, etc. The semiconductor substrate 10 in this example is a silicon substrate.

[0043] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on a front surface 21 of a semiconductor substrate 10. The front surface 21 will be described later. The semiconductor device 100 of this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10.

[0044] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 17. The gate metal layer 50 is provided above the connection portion 25 and the well region 17.

[0045] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing metal. At least a portion of the emitter electrode 52 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 may have a barrier metal layer made of titanium or a titanium compound below the region made of aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0046] The emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 with an interlayer insulating film 38 sandwiched therebetween. The interlayer insulating film 38 is omitted in Fig. 1A. A contact hole 54, a contact hole 55, and a contact hole 56 are provided to penetrate the interlayer insulating film 38.

[0047] The contact hole 55 electrically connects the gate metal layer 50 and the gate conductive portion in the transistor portion 70 via the connection portion 25. A plug layer made of tungsten or the like may be formed inside the contact hole 55.

[0048] The contact hole 56 connects the emitter electrode 52 and the dummy conductive portion in the dummy trench portion 30. Inside the contact hole 56, a plug layer made of tungsten or the like may be formed.

[0049] The connection portion 25 is connected to a front surface side metal layer such as the emitter electrode 52 or the gate metal layer 50. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. In this example, the connection portion 25 is provided extending in the X-axis direction and electrically connected to the gate conductive portion. The connection portion 25 may also be provided between the emitter electrode 52 and the dummy conductive portion. In this example, the connection portion 25 is not provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is made of a conductive material such as polysilicon doped with impurities. In this example, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0050] The gate trench portion 40 is an example of a plurality of trench portions extending in a predetermined extension direction on the front surface 21 side of the semiconductor substrate 10. The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The gate trench portion 40 of this example may have two extension portions 41 extending in an extension direction (in this example, the Y-axis direction) that is parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connection portion 43 connecting the two extension portions 41.

[0051] It is preferable that at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extension portions 41 of the gate trench portion 40, it is possible to alleviate electric field concentration at the ends of the extension portions 41. At the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be electrically connected to the gate conductive portion via the connection portion 25.

[0052] The dummy trench portion 30 is an example of a plurality of trench portions extending in a predetermined extension direction on the front surface 21 side of the semiconductor substrate 10. The dummy trench portion 30 is a trench portion electrically connected to the emitter electrode 52. Like the gate trench portion 40, the dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The dummy trench portion 30 in this example has an I-shape on the front surface 21 of the semiconductor substrate 10, but like the gate trench portion 40, it may have a U-shape on the front surface 21 of the semiconductor substrate 10. That is, the dummy trench portion 30 may have two extension portions extending along the extension direction and a connection portion connecting the two extension portions.

[0053] The transistor section 70 of this example has a structure in which two gate trench sections 40 and two dummy trench sections 30 are repeatedly arranged. That is, the transistor section 70 of this example has gate trench sections 40 and dummy trench sections 30 in a 1:1 ratio. For example, the transistor section 70 has one dummy trench section 30 between two extension sections 41.

[0054] However, the ratio of the gate trench portions 40 to the dummy trench portions 30 is not limited to this example. The ratio of the gate trench portions 40 may be greater than the ratio of the dummy trench portions 30, or the ratio of the dummy trench portions 30 may be greater than the ratio of the gate trench portions 40. The ratio of the gate trench portions 40 to the dummy trench portions 30 may be 2:3 or 2:4. Furthermore, the transistor portion 70 may have all trench portions as gate trench portions 40 and no dummy trench portions 30.

[0055] The well region 17 is a second conductivity type region provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18, which will be described later. The well region 17 is an example of a well region provided on the peripheral side of the active region 120. The well region 17 is, for example, P+ type. The well region 17 is formed within a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. Part of the regions of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side are formed in the well region 17. The bottoms of the ends of the gate trench portion 40 and the dummy trench portion 30 in the extension direction may be covered by the well region 17.

[0056] The contact holes 54 are formed above the emitter region 12 and the contact region 15 in the transistor section 70. The contact holes 54 are not provided above the well regions 17 provided at both ends in the Y-axis direction. In this manner, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 may be provided extending in the extension direction.

[0057] The mesa portion 71 is a mesa portion provided adjacent to a trench portion in a plane parallel to the front surface 21 of the semiconductor substrate 10. The mesa portion is a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be a portion extending from the front surface 21 of the semiconductor substrate 10 to the deepest bottom of each trench portion. The extension portion of each trench portion may be considered as one trench portion. In other words, the region sandwiched between the two extension portions may be considered as a mesa portion.

[0058] The mesa portion 71 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface 21 of the semiconductor substrate 10. In the mesa portion 71, the emitter regions 12 and the contact regions 15 are provided alternately in the extension direction.

[0059] The base region 14 is a second conductivity type region provided on the front surface 21 side of the semiconductor substrate 10. The base region 14 is, for example, a P-type. The base region 14 may be provided on the front surface 21 of the semiconductor substrate 10 at both ends of the mesa portion 71 in the Y-axis direction. Note that FIG. 1A shows only one end of the base region 14 in the Y-axis direction.

[0060] The emitter region 12 is a region of the first conductivity type having a higher doping concentration than the drift region 18. In this example, the emitter region 12 is, for example, N+ type. An example of a dopant for the emitter region 12 is arsenic (As). The emitter region 12 is provided on the front surface 21 of the mesa portion 71 in contact with the gate trench portion 40. The emitter region 12 may be provided extending in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The emitter region 12 is also provided below the contact hole 54.

[0061] Furthermore, the emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30.

[0062] The contact region 15 is provided above the base region 14 and is a second conductivity type region having a higher doping concentration than the base region 14. In this example, the contact region 15 is, for example, P+ type. In this example, the contact region 15 is provided on the front surface 21 of the mesa portion 71. The contact region 15 may be provided in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The contact region 15 may or may not be in contact with the gate trench portion 40 or the dummy trench portion 30. In this example, the contact region 15 is in contact with the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also provided below the contact hole 54.

[0063] 1B shows an example of the a-a' cross section in FIG. 1A. The a-a' cross section is an XZ plane passing through the emitter region 12 in the transistor section 70. In the a-a' cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a backside electrode 24. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0064] The drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10. In this example, the drift region 18 is, for example, an N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein. That is, the doping concentration of the drift region 18 may be the same as the doping concentration of the semiconductor substrate 10.

[0065] The buffer region 20 is a region of a first conductivity type provided closer to the back surface 23 of the semiconductor substrate 10 than the drift region 18. In this example, the buffer region 20 is, for example, N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer spreading from the lower surface side of the base region 14 from reaching the first implantation region 221 and the second implantation region 222 of the second conductivity type. The buffer region 20 may be omitted.

[0066] In this example, the transistor section 70 has a first implantation section 171 and a second implantation section 172. The first implantation section 171 has a first implantation region 221 and a part of the back surface electrode 24. The second implantation section 172 has a second implantation region 222 and a part of the back surface electrode 24. However, as will be described later, the second implantation section 172 does not necessarily have the back surface electrode 24. The second implantation section 172 has a lower injection efficiency of carriers injected from the back surface electrode 24 than the first implantation section 171. On the back surface 23 of the semiconductor substrate 10, the area of ​​the first implantation section 171 may be larger than the area of ​​the second implantation section 172.

[0067] The first implantation portions 171 and the second implantation portions 172 may be provided alternately in the trench arrangement direction (the X-axis direction in this example). The first implantation portions 171 and the second implantation portions 172 may be provided at a constant repetition pitch. That is, the sum of the width of the first implantation portions 171 and the width of the second implantation portions 172 may be constant. The constant repetition pitch may be 20, 40, or 100 times the distance between each trench portion. The repetition pitch may be 20 μm or more and 100 μm or less.

[0068] The first injection portion 171 and the second injection portion 172 do not need to be repeated at a constant pitch as long as they are alternately arranged. Furthermore, the first injection portion 171 and the second injection portion 172 may be alternately arranged in the trench extension direction (the Y-axis direction in this example), or may be alternately arranged in a direction different from the trench extension direction. Details of how to arrange the first injection portion 171 and the second injection portion 172 will be described later. By providing the first injection portion 171 and the second injection portion 172 whose carrier injection efficiency is lower than that of the first injection portion 171, the carrier injection efficiency in the transistor portion 70 can be adjusted, and the Von-Eoff tradeoff can be improved.

[0069] The collector region 22 is provided below the buffer region 20 in the transistor section 70. The collector region 22 has a second conductivity type. The collector region 22 is an example of an injection region 220. The injection region 220 may be a region that contributes to carrier injection efficiency in the vertical element 700. As an example, if the vertical element 700 is a MOSFET, the injection region 220 may be a drain region. As another example, if the vertical element 700 is a bipolar PIN diode, the injection region 220 may be an anode region or a cathode region. Even if the vertical element 700 is another element, the injection region 220 may be a region that contributes to carrier injection efficiency. The collector region 22 in this example, which is the injection region 220, may include a first injection region 221 and a second injection region 222.

[0070] The first implantation region 221 is provided below the buffer region 20 in the first implantation section 171. The first implantation region 221 has a second conductivity type. In this example, the first implantation region 221 is, for example, a P-type. The conductivity type of the first implantation region 221 may be the same as the conductivity type of the implantation region 220. For example, if the implantation region 220 is of the first conductivity type, the conductivity type of the first implantation region 221 may also be the first conductivity type.

[0071] The second implantation region 222 is provided below the buffer region 20 in the second implantation section 172. The second implantation region 222 has a second conductivity type. In this example, the second implantation region 222 is, for example, a P-type. The conductivity type of the second implantation region 222 may be the same as the conductivity type of the implantation region 220. For example, if the implantation region 220 is of the first conductivity type, the conductivity type of the second implantation region 222 may also be the first conductivity type.

[0072] The doping concentration in the first implanted region 221 is 1E16 cm ―3 Above, 1E18cm ―3 In this specification, E represents a power of 10. For example, 1E16 is 1×10 16 This is what I mean.

[0073] The doping concentration in the second implanted region 222 may be lower than the doping concentration in the first implanted region 221. In one example, the doping concentration in the second implanted region 222 is 1E15 cm ―3 The doping concentration in the second implantation region 222 may be 0.5 times or less the doping concentration in the first implantation region 221. By ensuring this concentration, snapback can be suppressed.

[0074] The first implantation region 221 and the second implantation region 222 may be formed by implanting impurities from the front surface 21 or the back surface 23 of the semiconductor substrate 10. In one example, the second implantation region 222 may be formed by implanting impurities into the entire surface of the semiconductor substrate 10 from the back surface 23, and then the first implantation region 221 may be selectively formed by masking a portion of the back surface 23 of the semiconductor substrate 10 and implanting additional impurities. The mask may be any mask such as photoresist. The impurity for forming the first implantation region 221 and the second implantation region 222 may be, for example, boron (B).

[0075] The back surface electrode 24 is formed on the back surface 23 of the semiconductor substrate 10. The back surface electrode 24 is formed of a conductive material such as a metal. The material of the back surface electrode 24 may be the same as or different from the material of the emitter electrode 52.

[0076] The base region 14 is a region of the second conductivity type provided above the drift region 18. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may be provided in contact with the dummy trench portion 30.

[0077] The emitter region 12 is provided above the base region 14. The emitter region 12 is provided between the base region 14 and the front surface 21. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0078] The accumulation region 16 is a region of a first conductivity type that is provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18. In this example, the accumulation region 16 is, for example, an N+ type. However, the accumulation region 16 does not necessarily have to be provided. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage of the transistor section 70 can be reduced.

[0079] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the front surface 21. Each trench extends from the front surface 21 to the drift region 18. In regions where at least one of the emitter region 12, the base region 14, the contact region 15, and the accumulation region 16 is provided, each trench also penetrates these regions to reach the drift region 18. The trenches penetrating the doped regions do not necessarily mean that the trenches are formed after the doped regions are formed. The trenches penetrating the doped regions also include trenches formed after the trenches are formed.

[0080] The gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 formed on the front surface 21. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, further inward than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is made of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 with an interlayer insulating film 38.

[0081] The gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side, across the gate insulating film 42, in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0082] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 may be covered on the front surface 21 with an interlayer insulating film 38.

[0083] The interlayer insulating film 38 is provided above the semiconductor substrate 10. In this example, the interlayer insulating film 38 is provided in contact with the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. One or more contact holes 54 are provided in the interlayer insulating film 38 to electrically connect the emitter electrode 52 to the semiconductor substrate 10. Contact holes 55 and 56 may also be provided so as to penetrate the interlayer insulating film 38. The thickness of the interlayer insulating film 38 is, for example, 1.0 μm, but is not limited to this.

[0084] The interlayer insulating film 38 may be a silicon oxide film. The interlayer insulating film 38 may be a borophosphosilicate glass (BPSG) film, a borosilicate glass (BSG) film, or a phosphosilicate glass (PSG) film. The interlayer insulating film 38 may include a high-temperature silicon oxide (HTO) film.

[0085] 1C shows an example of the underside of the semiconductor device 100. Fig. 1C shows at least a partial region of the underside of the semiconductor device 100. That is, the region shown in Fig. 1C may be provided over the entire underside of the semiconductor device 100, the region shown in Fig. 1C may be provided on a portion of the underside of the semiconductor device 100, or the region shown in Fig. 1C may be repeatedly provided on the underside of the semiconductor device 100.

[0086] The vertical element 700 may have first injection portions 171 and second injection portions 172 arranged alternately in a predetermined direction. In this example, the first injection portions 171 and second injection portions 172 have short and long sides and are arranged to extend in the long side direction. In this example, the first injection portions 171 and second injection portions 172 are arranged alternately in a direction perpendicular to the extension direction of each injection portion.

[0087] The predetermined direction may have an inclination of 0 to 90 degrees relative to the trench extension direction. That is, the arrangement direction of the first implantation portions 171 and the second implantation portions 172 may have an inclination of 0 to 90 degrees relative to the trench extension direction (e.g., the Y axis). In FIG. 1C, only the Z axis is shown. That is, in FIG. 1C, the trench extension direction (e.g., the Y axis) may be any direction perpendicular to the Z axis.

[0088] The vertical element 700 may have regularly arranged first implanted portions 171 and second implanted portions 172. Regularly arranged first implanted portions 171 and second implanted portions 172 may mean that the first implanted portions 171 and second implanted portions 172 are alternately arranged at a constant repeat pitch. In this example, the first implanted portions 171 and second implanted portions 172 are alternately arranged at a constant repeat pitch in a direction perpendicular to the extension direction of each implanted portion.

[0089] Fig. 1D shows an example of the underside of a modified example of semiconductor device 100. Fig. 1D shows at least a partial region of the underside of semiconductor device 100. That is, the region shown in Fig. 1D may be provided over the entire underside of semiconductor device 100, the region shown in Fig. 1D may be provided on a portion of the underside of semiconductor device 100, or the region shown in Fig. 1D may be repeatedly provided on the underside of semiconductor device 100.

[0090] In this example, the first implantation portions 171 are repeatedly arranged in a first direction perpendicular to the depth direction of the semiconductor substrate 10 (the Z-axis in this example) and a second direction perpendicular to the first direction. The second implantation portions 172 are arranged to surround the first implantation portions 171. Therefore, the vertical element 700 in this example has the first implantation portions 171 and the second implantation portions 172 alternately arranged in a predetermined direction. The predetermined direction in this example may also have an inclination of 0 degrees or more and 90 degrees or less with respect to the trench extension direction. That is, in FIG. 1D , the trench extension direction (e.g., the Y-axis) may be any direction perpendicular to the Z-axis. Contrary to this example, the first implantation portions 171 may be arranged to surround the second implantation portions 172 repeatedly arranged in the first and second directions. In this case, the area of ​​the repeating unit of the second implantation portion 172, the repeat pitch, etc. may be adjusted so that the area of ​​the first implantation portion 171 is larger than the area of ​​the second implantation portion 172.

[0091] 1E shows an example of the underside of a modified example of semiconductor device 100. Fig. 1E shows at least a partial region of the underside of semiconductor device 100. That is, the region shown in Fig. 1E may be provided over the entire underside of semiconductor device 100, the region shown in Fig. 1E may be provided on a portion of the underside of semiconductor device 100, or the region shown in Fig. 1E may be repeatedly provided on the underside of semiconductor device 100.

[0092] In this example, the second implantation portions 172 are arranged point-symmetrically with respect to the center of the illustrated region. In this example, the first implantation portion 171 is arranged to surround the second implantation portion 172. Therefore, the vertical element 700 in this example has the first implantation portions 171 and the second implantation portions 172 arranged alternately in a predetermined direction. For example, the predetermined direction in this example may be any direction passing through the center of the point symmetry. The predetermined direction in this example may also have an inclination with respect to the trench extension direction of 0 degrees or more and 90 degrees or less. That is, in FIG. 1E, the trench extension direction (e.g., the Y-axis) may be any direction perpendicular to the Z-axis.

[0093] 1F shows an example of the underside of a modified example of the semiconductor device 100. Fig. 1F shows at least a partial region of the underside of the semiconductor device 100. That is, the region shown in Fig. 1F may be provided over the entire underside of the semiconductor device 100, the region shown in Fig. 1F may be provided on a portion of the underside of the semiconductor device 100, or the region shown in Fig. 1F may be repeatedly provided on the underside of the semiconductor device 100.

[0094] The first implantation portion 171 of this example is a rectangular shape and a rectangular ring shape concentric with the rectangular shape, which are repeatedly arranged in the radial direction from the center. The second implantation portion 172 of this example is a rectangular ring shape concentric with the first implantation portion 171, which are repeatedly arranged in the radial direction from the center in an area where the first implantation portion 171 is not provided. Therefore, the vertical element 700 of this example has the first implantation portion 171 and the second implantation portion 172 alternately arranged in a predetermined direction. The predetermined direction of this example may also have an inclination with respect to the trench extension direction of 0 degrees or more and 90 degrees or less. That is, in FIG. 1F, the trench extension direction (e.g., the Y axis) may be any direction perpendicular to the Z axis. Conversely to this example, a rectangular second implantation portion 172 may be arranged at the center, and rectangular ring-shaped first implantation portion 171 and second implantation portion 172 may be repeatedly arranged around the rectangular shape. In this case, the length of each part may be adjusted so that the area of ​​the first injection part 171 is larger than the area of ​​the second injection part 172.

[0095] 1G shows an example of the underside of a modified example of the semiconductor device 100. Fig. 1G shows at least a partial region of the underside of the semiconductor device 100. That is, the region shown in Fig. 1G may be provided over the entire underside of the semiconductor device 100, the region shown in Fig. 1G may be provided on a portion of the underside of the semiconductor device 100, or the region shown in Fig. 1G may be repeatedly provided on the underside of the semiconductor device 100.

[0096] The second implantation portions 172 in this example are arranged irregularly. The first implantation portions 171 in this example are provided in a region where the second implantation portions 172 are not provided, surrounding the second implantation portions 172. In this example, the vertical element 700 also has the first implantation portions 171 and the second implantation portions 172 arranged alternately in a predetermined direction. For example, the first implantation portions 171 and the second implantation portions 172 are arranged alternately in the direction connecting the center of the second implantation portion 172a and the center of the second implantation portion 172b. The predetermined direction in this example may also have an inclination of 0 degrees or more and 90 degrees or less with respect to the trench extension direction. That is, in FIG. 1G, the trench extension direction (e.g., the Y-axis) may be any direction perpendicular to the Z-axis.

[0097] As described above, the vertical element 700 of this example has the first injection parts 171 and the second injection parts 172 arranged alternately in a predetermined direction. By alternately arranging the first injection parts 171 and the second injection parts 172, which have a lower injection efficiency of carriers injected from the back surface electrode 24 than the first injection parts 171, it is possible to modulate the carrier distribution inside the vertical element 700. By modulating the carrier distribution in the vertical element 700, it is possible to improve the Von-Eoff tradeoff.

[0098] 2 shows a top view of a modified example of the semiconductor device 100. In this example, only some components of the semiconductor device 100 are shown, and some components are omitted. The semiconductor device 100 of this example includes a gate pad 112, a sense electrode 114, an anode pad 116, a cathode pad 118, and a temperature sensing unit 180.

[0099] The semiconductor substrate 10 has end sides 102 in top view. The semiconductor substrate 10 of this example has two pairs of end sides 102 that face each other in top view. In this example, the X-axis and the Y-axis are parallel to either of the end sides 102.

[0100] An active region 120 is provided in the semiconductor substrate 10. The active region 120 is a region through which a main current flows in the depth direction between the front surface 21 and the back surface 23 of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode 52 is provided above the active region 120, but is not shown in the figure.

[0101] The active region 120 is provided with at least one of a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as a free wheel diode (FWD). In the example of Fig. 2, the transistor sections 70 and the diode sections 80 are alternately arranged along a predetermined arrangement direction (the X-axis direction in this example) on the front surface 21 of the semiconductor substrate 10. In another example, the active region 120 may be provided with only one of the transistor section 70 and the diode section 80.

[0102] In this example, the region where the transistor section 70 is disposed is marked with the symbol "I," and the region where the diode section 80 is disposed is marked with the symbol "F." The transistor section 70 and the diode section 80 may each have a longitudinal direction in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than the width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section.

[0103] The diode section 80 is a region obtained by projecting a cathode region 82 provided on the back surface 23 side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The cathode region 82 will be described later. A first implantation region 221 or a second implantation region 222 may be provided in a region on the back surface 23 of the semiconductor substrate 10 other than the cathode region 82.

[0104] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 112, a sense electrode 114, an anode pad 116, and a cathode pad 118. Each pad is disposed near the edge 102. The vicinity of the edge 102 refers to the region between the edge 102 and the emitter electrode 52 in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0105] A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to the gate conductive portion 44 of the gate trench portion 40 in the active region 120. The semiconductor device 100 includes a gate wiring 130 that connects the gate pad 112 and the gate trench portion 40. Note that the gate wiring 130 is omitted in FIG. 2 .

[0106] The sense electrode 114 is electrically connected to a current sense unit 115 provided below the sense electrode 114. The sense electrode 114 detects the current flowing in the current sense unit 115. The current sense unit 115 detects the current flowing in the transistor unit 70. The current sense unit 115 has a structure corresponding to the transistor unit 70, and simulates the operation of the transistor unit 70, causing a current proportional to the current flowing in the transistor unit 70 to flow. By using the current sense unit 115, the current flowing in the transistor unit 70 can be monitored.

[0107] The temperature sensing unit 180 is provided on or inside the semiconductor substrate 10. In this example, it is provided on the well region 17 between the transistor units 70 in the center of the semiconductor device 100. The temperature sensing unit 180 detects the temperature of the active region 120. A detailed description of the configuration of the temperature sensing unit 180 will be omitted.

[0108] The anode pad 116 is electrically connected to the anode region of the temperature sensing section 180. The anode pad 116 is electrically connected to the anode region of the temperature sensing section 180 by an anode wiring 117.

[0109] The cathode pad 118 is electrically connected to the cathode region of the temperature sensing section 180. The cathode pad 118 is electrically connected to the cathode region of the temperature sensing section 180 by a cathode wiring 119.

[0110] The gate wiring 130 includes a gate metal layer 50 made of a metal such as aluminum, and a gate runner 48 made of a semiconductor such as polysilicon doped with impurities. The gate runner 48 will be described later. The gate wiring may be formed of either the gate metal layer 50 or the connection portion 25, or an appropriate combination of both.

[0111] The edge termination structure 140 is provided on the front surface 21 of the semiconductor substrate 10. The edge termination structure 140 is provided between the active region 120 and the edge 102 in a top view. The edge termination structure 140 relieves electric field concentration on the front surface 21 side of the semiconductor substrate 10. The edge termination structure 140 may include at least one of a guard ring, a field plate, and a resurf, which are provided in an annular shape surrounding the active region 120.

[0112] 3A shows a top view of a modified example of the semiconductor device 100. The semiconductor device 100 of this example includes a transistor section 70 and a diode section 80. This figure is an enlarged view of the top surface of region A in FIG.

[0113] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 provided inside the front surface 21 side of the semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion.

[0114] The dummy trench portion 30 of this example may have a U-shape on the front surface 21 of the semiconductor substrate 10, similar to the gate trench portion 40. That is, the dummy trench portion 30 may have two extension portions 31 extending along the extension direction and a connection portion 33 connecting the two extension portions 31.

[0115] The semiconductor device 100 of this example includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other. The transistor section 70 of this example includes a boundary section 90 located at the boundary between the transistor section 70 and the diode section 80. However, the semiconductor device 100 does not necessarily have to include the boundary section 90.

[0116] The boundary portion 90 is a region provided in the transistor portion 70 and adjacent to the diode portion 80. The boundary portion 90 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. The boundary portion 90 in this example does not have an emitter region 12. In one example, the trench portion of the boundary portion 90 is a dummy trench portion 30. The boundary portion 90 in this example is arranged so that both ends in the X-axis direction are dummy trench portions 30.

[0117] The contact holes 54 are provided above the base region 14 in the diode section 80. The contact holes 54 are provided above the contact regions 15 in the boundary section 90. None of the contact holes 54 are provided above the well regions 17 provided at both ends in the Y-axis direction.

[0118] The mesa portion 91 is provided in the boundary portion 90. The mesa portion 91 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. The mesa portion 91 of this example has a base region 14 and a well region 17 on the negative side in the Y-axis direction.

[0119] The mesa portion 81 is provided in a region of the diode portion 80 that is sandwiched between adjacent dummy trench portions 30. The mesa portion 81 has a base region 14 on the front surface 21 of the semiconductor substrate 10. The mesa portion 81 of this example has a well region 17 on the negative side in the Y-axis direction.

[0120] The emitter region 12 is provided in the mesa portion 71, but may not be provided in the mesa portion 81 or the mesa portion 91. The contact region 15 is provided in the mesa portion 71 and the mesa portion 91, but may not be provided in the mesa portion 81.

[0121] 3B shows an example of the c-c' cross section in FIG. 3A. The semiconductor device 100 of this example includes a front surface side lifetime control region 152. However, the semiconductor device 100 does not necessarily have to include the front surface side lifetime control region 152. The semiconductor device 100 of this example includes a first implantation region 221, a second implantation region 222, and a cathode region 82 on the back surface 23 side of the buffer region 20.

[0122] The contact region 15 is provided above the base region 14 in the mesa portion 91. The contact region 15 is provided in contact with the dummy trench portion 30 in the mesa portion 91. In other cross sections, the contact region 15 may be provided on the front surface 21 of the mesa portion 71.

[0123] The accumulation region 16 is provided in the transistor section 70 and the diode section 80. In this example, the accumulation region 16 is provided on the entire surface of the transistor section 70 and the diode section 80. However, the accumulation region 16 does not have to be provided in the diode section 80.

[0124] The cathode region 82 is provided below the buffer region 20 in the diode section 80. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80. That is, the collector region 22 is provided below the boundary section 90 in this example.

[0125] 3B, a second implantation region 222 is provided below the boundary 90. That is, in this example, a second implantation region 172 is provided below the boundary 90. However, a first implantation region 221 may also be provided below the boundary 90. That is, a first implantation region 171 may also be provided below the boundary 90.

[0126] As described above, the semiconductor device 100 including the vertical element 700 having the transistor portion 70 may further include a diode portion 80. The vertical element 700 may have a boundary portion 90 at the boundary with the diode portion 80. The boundary between the vertical element 700 and the diode portion 80 may be the boundary between the implantation region 220 and the cathode region 82. Below the boundary portion 90, a second implantation portion 172 may be provided, and a first implantation portion 171 may also be provided.

[0127] The front surface side lifetime control region 152 is provided closer to the front surface 21 than the center of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. In this example, the front surface side lifetime control region 152 is provided in the drift region 18. The front surface side lifetime control region 152 is provided in both the transistor section 70 and the diode section 80. The front surface side lifetime control region 152 is provided between the diode section 80 and the boundary section 90, and may not be provided in part of the transistor section 70. Below the front surface side lifetime control region 152, the back surface 23 of the semiconductor substrate 10 may have a first implantation region 221 and a second implantation region 222. The front surface side lifetime control region 152 can suppress hole injection from the diode section 80 and the transistor section 70, thereby reducing reverse recovery loss.

[0128] The front surface side lifetime control region 152 is provided extending from the diode section 80 to the transistor section 70. The front surface side lifetime control region 152 may be formed by irradiation from the front surface 21 of the semiconductor substrate 10. The front surface side lifetime control region 152 may be formed by irradiation from the back surface 23 side of the semiconductor substrate 10. In this example, the front surface side lifetime control region 152 is provided below the gate trench section 40. When a particle beam or the like for forming the front surface side lifetime control region 152 passes through the MOS gate structure of the semiconductor device 100, defects may occur at the interface between the gate oxide film and the semiconductor substrate.

[0129] The semiconductor device 100 may be a power semiconductor device for controlling power, etc. The semiconductor device 100 of this example may have a vertical semiconductor structure with a backside metal layer on the backside 23 side of the semiconductor substrate 10. However, the semiconductor device 100 may also have a lateral semiconductor structure without a metal layer on the backside 23 side.

[0130] In this example, an RC-IGBT with a trench gate structure is described as the semiconductor device 100. However, the semiconductor device 100 may be an IGBT with a planar gate structure or a reverse-blocking IGBT. The semiconductor device 100 may include an N-channel MOSFET or a P-channel MOSFET. As another example, the semiconductor device 100 may be a bipolar PIN diode or a Schottky barrier diode. However, the semiconductor device 100 is not limited to these.

[0131] Figure 4 shows an example of a cross section taken along the line bb' in Figure 2. Figure 4 shows the state near the boundary X2 between the active region 120 and the edge termination structure 140 of the semiconductor device 100 of this example. The edge termination structure 140 has a well region 17, multiple guard rings 92, multiple field plates 94, gate wiring 130, and a channel stopper 174.

[0132] The well region 17 is a P+ type region with a higher doping concentration than the base region 14. The well region 17 is provided from the front surface 21 of the semiconductor substrate 10 to a position deeper than the lower end of the trench portion. Providing the well region 17 makes it easier to separate the active region 120 and the edge termination structure 140. The region surrounded by the well region 17 in a top view may be the active region 120. One or more trench portions may be provided inside the well region 17. By providing the trench portion located at the farthest end of the multiple trench portions within the well region 17, electric field concentration in the trench portion can be alleviated.

[0133] A gate wiring 130 is provided above the well region 17. The gate wiring 130 in this example includes a gate metal layer 50 made of a metal such as aluminum, and a gate runner 48 made of a semiconductor such as polysilicon doped with impurities. The gate runner 48 is disposed above the well region 17, with an interlayer insulating film 38 sandwiched therebetween. The gate metal layer 50 is disposed above the gate runner 48, with the interlayer insulating film 38 sandwiched therebetween. The gate metal layer 50 and the gate runner 48 are connected by a through-hole provided in the interlayer insulating film 38. A back surface low-implantation region 223 may be provided below the gate runner 48 on the back surface 23 of the semiconductor substrate 10.

[0134] The back surface low implantation region 223 is a region of the second conductivity type that extends from below the edge termination structure 140 to below the active region 120. In one example, the back surface low implantation region 223 is P-type. The back surface low implantation region 223 may be provided on the back surface 23 of the semiconductor substrate 10 so as to have a boundary X1 that contacts the first implantation region 221. The back surface low implantation region 223 may also be provided on the back surface 23 of the semiconductor substrate 10 so as to have a boundary that contacts the second implantation region 222.

[0135] The doping concentration of the back surface low implanted region 223 may be lower than the doping concentration of the first implanted region 221. In one example, the doping concentration of the back surface low implanted region 223 is 1E15 cm ―3 It may be equal to or greater than the doping concentration of the first implantation region 221, and may be equal to or less than 0.5 times the doping concentration of the first implantation region 221.

[0136] The doping concentration of the backside low implanted region 223 may be the same as or lower than the doping concentration of the second implanted region 222. In one example, the doping concentration of the backside low implanted region 223 may be 0.01 times or more the doping concentration of the first implanted region 221 and may be 0.5 times or less the doping concentration of the first implanted region 221.

[0137] Boundary X1 between first implantation region 221 and back surface low implantation region 223 may be located closer to active region 120 than boundary X2 between active region 120 and edge termination structure 140. By providing back surface low implantation region 223, which has a lower doping concentration than first implantation region 221, below edge termination structure 140, hole injection from back surface 23 into edge termination structure 140 is suppressed, and the breakdown voltage of semiconductor device 100 can be improved.

[0138] Each guard ring 92 may be provided on the front surface 21 to surround the active region 120. The multiple guard rings 92 may have the function of spreading a depletion layer generated in the active region 120 outward from the semiconductor substrate 10. This makes it possible to prevent electric field concentration inside the semiconductor substrate 10, and improve the breakdown voltage of the semiconductor device 100.

[0139] The guard ring 92 of this example is a P+ type semiconductor region formed by ion irradiation near the front surface 21. The depth of the bottom of the guard ring 92 may be deeper than the depth of the bottom of the gate trench portion 40 and the dummy trench portion 30.

[0140] The upper surface of the guard ring 92 is covered with the interlayer insulating film 38. The field plate 94 is made of a conductive material such as metal or polysilicon. The field plate 94 may be made of the same material as the gate metal layer 50 or the emitter electrode 52. The field plate 94 is provided on the interlayer insulating film 38. The field plate 94 is connected to the guard ring 92 through a through-hole provided in the interlayer insulating film 38.

[0141] The channel stopper 174 is provided so as to be exposed on the front surface 21 and the side surface at the edge 102. The channel stopper 174 is an N-type region having a higher doping concentration than the drift region 18. The channel stopper 174 has the function of terminating the depletion layer generated in the active region 120 at the edge 102 of the semiconductor substrate 10.

[0142] 5 shows a top view of a modified example of the semiconductor device 100. This figure is an enlarged view of the top surface of region C in FIG.

[0143] 5 is an enlarged view of the vicinity of the boundary between the gate pad 112 and the transistor section 70 in a modified example of the semiconductor device 100. As indicated by the dotted line and arrow in FIG. 5 , the boundary between the collector region 22 and the back surface low injection region 223 is located closer to the transistor section 70 than the boundary between the transistor section 70 and the gate pad 112. That is, the back surface low injection region 223 may be provided below the gate pad 112. By providing the back surface low injection region 223, which has a lower doping concentration than the first injection region 221, below the gate pad 112, hole injection from the back surface 23 in the gate pad 112 is suppressed, and the breakdown voltage of the semiconductor device 100 can be improved.

[0144] FIG. 6 is a diagram showing the relationship between the area ratio of the first implantation portion 171 and Von-Eoff in the transistor portion 70 of the semiconductor device 100 of this example. As the ratio of the first implantation portion 171 decreases, the carrier injection efficiency of the semiconductor device 100 decreases, resulting in an increase in Von and a decrease in Eoff. The ratio of the first implantation portion to the back surface 23 of the transistor portion 70 may be 60% or more and 99% or less. The minimum dimension of one region of the second implantation portion 172 may be 0.1 μm to 40 μm, or 1 μm to 20 μm. By providing the second implantation portion 172, the conductivity modulation effect is optimized compared to conventional examples, suppressing an increase in Von while reducing Eoff, thereby improving the Von-Eoff tradeoff characteristics.

[0145] 7A is a diagram showing an example of a cross section of a modified example of the semiconductor device 100. This diagram shows an example of a cross section taken along line aa' of the modified example of the semiconductor device 100 shown in FIG. 1A. Differences from the cross section shown in FIG. 1B will be described below.

[0146] 7A, the second implanted region 222 is P-type instead of P-type, that is, the doping concentration in the first implanted region 221 and the second implanted region 222 may be the same in this example.

[0147] In this example, the back surface electrode 24 is in contact with the semiconductor substrate 10 on the back surface 23 of the semiconductor substrate 10 in the first implantation portion 171. On the other hand, the back surface electrode 24 is not in contact with the semiconductor substrate 10 on the back surface 23 of the semiconductor substrate 10 in the second implantation portion 172. That is, the back surface electrode 24 is not provided in the second implantation portion 172.

[0148] Since the second injection section 172 is not provided with the back surface electrode 24, the carrier injection efficiency in the second injection section 172 is lower than the carrier injection efficiency in the first injection section 171. As a result, in the drift region 18 of the second injection section 172, the total amount of carriers decreases during conductivity modulation, and the switching loss Eoff can be reduced.

[0149] Fig. 7B is a diagram showing an example of a cross section of semiconductor device 100 in a modified example different from that shown in Fig. 7A. Differences from the cross section shown in Fig. 7A will be described below.

[0150] 7B, the insulating film 26 contacts the semiconductor substrate 10 on the back surface 23 of the semiconductor substrate 10 at the second injection portion 172. This makes the carrier injection efficiency at the second injection portion 172 lower than the carrier injection efficiency at the first injection portion 171.

[0151] The insulating film 26 may be replaced with another structure as long as it is electrically insulating. For example, the insulating film 26 may be an oxide film such as SiO2, or a nitride film such as AlN. For example, the insulating film 26 may be an electrode of a Schottky junction. The electrode of the Schottky junction may be made of a metal such as Ni, Cu, or Au.

[0152] Fig. 7C is a diagram showing an example of a cross section of semiconductor device 100 in a modified example different from that shown in Fig. 7B. Differences from the cross section shown in Fig. 7B will be described below.

[0153] 7C , the back surface electrode 24 is provided below the insulating film 26 provided in the second injection section 172 in contact with the back surface 23 of the semiconductor substrate 10, so as to be in contact with the insulating film 26. This makes it possible to make the carrier injection efficiency in the second injection section 172 lower than the carrier injection efficiency in the first injection section 171, without thinning out a portion of the back surface electrode 24 from the semiconductor device 100.

[0154] Fig. 7D is a diagram showing an example of a cross section of semiconductor device 100 in a modified example different from that shown in Fig. 7C. Differences from the cross section shown in Fig. 7C will be described below.

[0155] In the modification shown in FIG. 7D , a back surface electrode 24 is provided so as to contact the back surface 23 of the semiconductor substrate 10 at the second implantation portion 172. That is, similar to the example of FIG. 1B , the back surface electrode 24 is provided on the entire back surface 23 of the semiconductor substrate 10. On the other hand, in the modification shown in FIG. 7D , the second implantation region 222 has crystal defects 153. The lifetime of the second implantation region 222 may be shorter than the lifetime of the first implantation region 221. This allows the carrier injection efficiency of the second implantation portion 172 to be lower than the carrier injection efficiency of the first implantation portion 171 without thinning out a portion of the back surface electrode 24 from the semiconductor device 100.

[0156] The crystal defects 153 may be formed by ion implanting an element with a low activation rate, such as Ar, Si, C, O, He, or H, into the second implantation region 222. That is, the second implantation region 222 may contain at least one element of Ar, Si, C, O, He, or H in a larger amount than the first implantation region 221. The crystal defects 153 may be formed by irradiating the second implantation region 222 with light.

[0157] 8 is a diagram showing the relationship between the area ratio of the first implantation portion 171 and Von-Eoff in the transistor portion 70 of the semiconductor device 100 of the modified example. When the ratio of the first implantation portion 171 is reduced, Von can be reduced with almost no effect on the value of Eoff. On the back surface 23 of the transistor portion 70, the ratio of the first implantation portion may be 75% or more and may be 90% or less. By providing the second implantation portion 172, the Von-Eoff trade-off characteristics are improved.

[0158] 9 is a flowchart showing an example of a manufacturing process for the semiconductor device 100. In step S100, a first conductivity type drift region 18 is formed in the semiconductor substrate 10. Step S100 of forming the drift region 18 does not have to be an independent step. That is, the drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein, and the step of forming the other regions may be step S100 of forming the drift region 18.

[0159] In step S110, a first implantation portion 171 is provided below the drift region 18. Step S110 of providing the first implantation portion 171 may include step S112 of providing a first implantation region 221 of the second conductivity type below the drift region 18 in the semiconductor substrate 10. Step S112 of providing the first implantation region 221 may include a step of irradiating with light.

[0160] In step S120, a second implantation portion 172 having a lower carrier injection efficiency than the first implantation portion 171 is provided below the drift region 18. The step of providing the second implantation portion 172 may include step S122 of providing a second implantation region 222 of the second conductivity type below the drift region 18 in the semiconductor substrate 10. Step S122 of providing the second implantation region 222 may include the step of irradiating the semiconductor substrate 10 with light having a higher energy than the light irradiation performed in step S112 of providing the first implantation region 221. By irradiating the semiconductor substrate 10 with light having a higher energy than the light irradiation performed in step S112 of providing the first implantation region 221, crystal defects 153 can be formed in the second implantation region 222. This allows the carrier injection efficiency of the second implantation portion 172 to be lower than the carrier injection efficiency of the first implantation portion 171.

[0161] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0162] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0163] 10 semiconductor substrate, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 17 well region, 18 drift region, 20 buffer region, 21 front surface, 22 collector region, 23 rear surface, 24 rear surface electrode, 25 connection portion, 26 insulating film, 30 dummy trench portion, 31 extension portion, 32 dummy insulating film, 33 Connection portion, 34 dummy conductive portion, 38 interlayer insulating film, 40 gate trench portion, 41 extension portion, 42 gate insulating film, 43 connection portion, 44 gate conductive portion, 48 gate runner, 50 gate metal layer, 52 emitter electrode, 54 contact hole, 55 contact hole, 56 contact hole, 70 transistor portion, 71 mesa portion , 80...diode portion, 81...mesa portion, 82...cathode region, 90...boundary portion, 91...mesa portion, 92...guard ring, 94...field plate, 100...semiconductor device, 102...edge, 112...gate pad, 114...sense electrode, 115...current sense portion, 116...anode pad, 117...anode wiring, 118...cathode pad, 119...cathode 1. Gate wiring, 120...active region, 130...gate wiring, 140...edge termination structure, 152...front surface side lifetime control region, 153...crystal defects, 171...first implantation region, 172...second implantation region, 174...channel stopper, 180...temperature sensing section, 220...implantation region, 221...first implantation region, 222...second implantation region, 223...back surface low implantation region, 700...vertical element

Claims

1. A semiconductor device including a vertical element, The vertical element is a first conductivity type drift region provided in a semiconductor substrate; a first injection portion provided below the drift region; a second injection section provided below the drift region and having a carrier injection efficiency lower than that of the first injection section; and an area of ​​the first implantation portion on the rear surface of the semiconductor substrate being larger than an area of ​​the second implantation portion; the vertical element has the first implantation portions and the second implantation portions alternately provided in a predetermined direction; the first implantation portion includes a first implantation region of a second conductivity type provided in the semiconductor substrate below the drift region; the doping concentration of the first implantation region is 1E16 cm −3 or more and 1E18 cm −3 or less; the second implantation portion includes a second implantation region of a second conductivity type provided in the semiconductor substrate below the drift region; the doping concentration of the second implanted region is lower than the doping concentration of the first implanted region; The ratio of the first injection portion to the rear surface of the vertical element is 60% or more and 99% or less. Semiconductor device.

2. 2. The semiconductor device according to claim 1, wherein said vertical element has said first implanted portion and said second implanted portion which are regularly provided.

3. a plurality of trenches provided on a front surface of the semiconductor substrate; 2. The semiconductor device according to claim 1, wherein the predetermined direction has an inclination of 0 degrees or more and 90 degrees or less with respect to the extending direction of the plurality of trench portions.

4. The doping concentration of the second implanted region is 1E15 cm ―３ 2. The semiconductor device according to claim 1, wherein the doping concentration of said first implantation region is equal to or greater than 0.5 times the doping concentration of said first implantation region.

5. an active region provided in the semiconductor substrate; an edge termination structure in the semiconductor substrate surrounding the active region; a back surface low implanted region extending from below the edge termination structure to below the active region and adjacent to the first implanted region, the back surface low implanted region having a doping concentration lower than that of the first implanted region; Equipped with 2. The semiconductor device according to claim 1, wherein a boundary between said first implantation region and said back surface low implantation region is located closer to said active region than a boundary between said active region and said edge termination structure.

6. The doping concentration of the back surface low implantation region is 1E15 cm ―３ 6. The semiconductor device according to claim 5, wherein the doping concentration of said first implantation region is equal to or greater than 0.5 times the doping concentration of said first implantation region.

7. 6. The semiconductor device according to claim 5, wherein the doping concentration of said back surface low implantation region is 0.01 to 0.5 times the doping concentration of said first implantation region.

8. a gate pad portion provided above the semiconductor substrate outside the active region and electrically connected to a gate conductive portion of the vertical element; 6. The semiconductor device according to claim 5, wherein the back surface low implantation region is located below the gate pad portion.

9. a gate runner electrically connecting the gate pad portion and the gate conductive portion; The semiconductor device of claim 8 , wherein the backside low-implant region is below the gate runner.

10. A semiconductor device comprising a vertical element, The vertical element is a first conductivity type drift region provided in a semiconductor substrate; a first injection portion provided below the drift region; a second injection section provided below the drift region and having a carrier injection efficiency lower than that of the first injection section; and an area of ​​the first implantation portion on the rear surface of the semiconductor substrate being larger than an area of ​​the second implantation portion; the vertical element has the first implantation portions and the second implantation portions alternately provided in a predetermined direction; the first implantation portion includes a first implantation region of a second conductivity type provided in the semiconductor substrate below the drift region; the second implantation portion includes a second implantation region of a second conductivity type provided in the semiconductor substrate below the drift region; the doping concentration of the second implanted region is lower than the doping concentration of the first implanted region; The semiconductor device includes: an active region provided in the semiconductor substrate; an edge termination structure in the semiconductor substrate surrounding the active region; a back surface low implanted region extending from below the edge termination structure to below the active region and adjacent to the first implanted region, the back surface low implanted region having a doping concentration lower than that of the first implanted region; Equipped with The doping concentration of the back surface low implantation region is the same as the doping concentration of the second implantation region. Semiconductor device.

11. A semiconductor device comprising a vertical element, The vertical element is a first conductivity type drift region provided in a semiconductor substrate; a first injection portion provided below the drift region; a second injection section provided below the drift region and having a carrier injection efficiency lower than that of the first injection section; and an area of ​​the first implantation portion on the rear surface of the semiconductor substrate being larger than an area of ​​the second implantation portion; the vertical element has the first implantation portions and the second implantation portions alternately provided in a predetermined direction; the first implantation portion has a first implantation region of a second conductivity type provided in the semiconductor substrate below the drift region; the second implantation portion has a second implantation region of a second conductivity type provided in the semiconductor substrate below the drift region, In the first implantation portion, the rear surface of the semiconductor substrate and the rear surface electrode are in contact with each other, and in the second implantation portion, the rear surface of the semiconductor substrate and the rear surface electrode are not in contact with each other. Semiconductor device.

12. 12. The semiconductor device according to claim 11, wherein the second implantation portion has an insulating film provided below the second implantation region, the insulating film being in contact with the back surface of the semiconductor substrate.

13. 12. The semiconductor device according to claim 11, wherein the proportion of said first implantation portion in said vertical element is 75% or more and 90% or less.

14. A semiconductor device comprising a vertical element, The vertical element is a first conductivity type drift region provided in a semiconductor substrate; a first injection portion provided below the drift region; a second injection section provided below the drift region and having a carrier injection efficiency lower than that of the first injection section; and an area of ​​the first implantation portion on the rear surface of the semiconductor substrate being larger than an area of ​​the second implantation portion; the vertical element has the first implantation portions and the second implantation portions alternately provided in a predetermined direction; The second injection section is a second implantation region of a second conductivity type provided in the semiconductor substrate below the drift region; an insulating film in contact with the second implantation region on the rear surface of the semiconductor substrate; a back electrode that is in contact with the insulating film below the insulating film; have Semiconductor device.

15. A semiconductor device comprising a vertical element, The vertical element is a first conductivity type drift region provided in a semiconductor substrate; a first injection portion provided below the drift region; a second injection section provided below the drift region and having a carrier injection efficiency lower than that of the first injection section; and an area of ​​the first implantation portion on the rear surface of the semiconductor substrate being larger than an area of ​​the second implantation portion; the vertical element has the first implantation portions and the second implantation portions alternately provided in a predetermined direction; the first implantation portion has a first implantation region of a second conductivity type provided in the semiconductor substrate below the drift region; the second implantation portion has a second implantation region of a second conductivity type provided in the semiconductor substrate below the drift region, The second implantation region contains at least one element selected from the group consisting of Ar, Si, C, O, He, and H in a larger amount than the first implantation region. Semiconductor device.

16. the vertical element has a transistor portion, The semiconductor device is an RC-IGBT further including a diode portion. The semiconductor device according to claim 1 .

17. 17. The semiconductor device according to claim 16, wherein the back surface of the transistor portion is the first implantation portion at the boundary between the transistor portion and the diode portion.

18. 17. The semiconductor device according to claim 16, wherein the back surface of the transistor portion is the second implantation portion at the boundary between the transistor portion and the diode portion.

19. a lifetime control region extending from the diode portion to the transistor portion and including a lifetime killer provided in the drift region; The semiconductor device according to claim 16.

20. A method for manufacturing a semiconductor device including a vertical element, comprising: forming a drift region of a first conductivity type in a semiconductor substrate; providing a first implant in the semiconductor substrate below the drift region; providing a second injection portion, the second injection portion having a carrier injection efficiency lower than that of the first injection portion, below the drift region in the semiconductor substrate; Equipped with an area of ​​the first implantation portion on the rear surface of the semiconductor substrate being larger than an area of ​​the second implantation portion; the first injection portions and the second injection portions are alternately provided in a predetermined direction, providing the first implantation region includes providing a first implantation region of a second conductivity type in the semiconductor substrate below the drift region; providing the second implanted portion includes providing a second implanted region of a second conductivity type in the semiconductor substrate below the drift region; providing the first implanted region includes irradiating with light; The step of providing the second implantation region includes a step of irradiating the first implantation region with light having higher energy than the light irradiation in the step of providing the first implantation region. A method for manufacturing a semiconductor device.

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