Semiconductor memory device and method for manufacturing the same

Abstract

To provide a semiconductor memory device capable of obtaining a sufficient margin for operation, and a manufacturing method of the semiconductor memory device.SOLUTION: A semiconductor memory device includes: a field effect transistor provided on a semiconductor substrate; an interlayer insulating film provided on the semiconductor substrate; a contact that passes through the interlayer insulating film and is electrically connected to a drain of the field effect transistor; a first wiring layer provided on the contact; a first insulating layer provided on the interlayer insulating film so as to embed the first wiring layer; an opening provided in the first insulating layer and the interlayer insulating film from a layer above the first wiring layer; and a ferroelectric capacitor that is provided in an inside of the opening and is electrically connected to a source of the field effect transistor.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor memory device and a method for manufacturing a semiconductor memory device. [Background technology]

[0002] Complementary MOS (CMOS) circuits, which consist of n-type field-effect transistors (nMOSFETs) and p-type field-effect transistors (pMOSFETs) mounted on the same substrate, are known for their low power consumption, high-speed operation, and ease of miniaturization and high integration.

[0003] For this reason, CMOS circuits are used in many LSI (Large Scale Integration) devices. In recent years, such LSI devices have been commercialized as SoCs (System on a Chip), which combine analog circuits, memory, logic circuits, and other components on a single chip.

[0004] The memory mounted on an LSI device is, for example, a static random access memory (SRAM), etc. In recent years, in order to further reduce the cost and power consumption of LSI devices, the use of dynamic RAM (DRAM), magnetic RAM (MRAM), ferroelectric RAM (FeRAM), etc. instead of SRAM has been considered.

[0005] Here, FeRAM is a semiconductor memory device that stores information using the direction of remanent polarization of a ferroelectric. An example of the structure of FeRAM is a structure in which a ferroelectric capacitor is formed inside a contact hole under a wiring or inside a damascene structure (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-7304 Summary of the Invention [Problem to be solved by the invention]

[0007] In such FeRAM, it is desirable to obtain a sufficient margin for operation by further increasing the capacitance of the ferroelectric capacitor. Specifically, in order to increase the capacitance of the ferroelectric capacitor, a ferroelectric capacitor structure and a ferroelectric capacitor formation method that enable a larger area are desired.

[0008] Therefore, it is desirable to provide a semiconductor memory device that can provide a sufficient margin for operation, and a method for manufacturing the semiconductor memory device. [Means for solving the problem]

[0009] A semiconductor memory device according to one embodiment of the present disclosure includes a field effect transistor provided on a semiconductor substrate, an interlayer insulating film provided on the semiconductor substrate, a contact penetrating the interlayer insulating film and electrically connecting to the drain of the field effect transistor, a first wiring layer provided on the contact, a first insulating layer provided on the interlayer insulating film and burying the first wiring layer, an opening provided in the first insulating layer and the interlayer insulating film from above the first wiring layer, and a ferroelectric capacitor provided inside the opening and electrically connecting to the source of the field effect transistor.

[0010] A semiconductor memory device according to one embodiment of the present disclosure includes a field effect transistor provided on a semiconductor substrate, an interlayer insulating film provided on the semiconductor substrate, an opening including a first opening formed in the interlayer insulating film and a second opening having a smaller opening diameter than the first opening and formed inside the first opening, and a ferroelectric capacitor provided inside the opening and electrically connected to a source of the field effect transistor.

[0011] A semiconductor memory device according to one embodiment of the present disclosure includes a field effect transistor provided on a semiconductor substrate, an interlayer insulating film provided on the semiconductor substrate, a contact that penetrates the interlayer insulating film and is electrically connected to the drain of the field effect transistor, and a ferroelectric capacitor that is provided at a height different from that of the contact inside an opening that penetrates at least the interlayer insulating film and is electrically connected to the source of the field effect transistor.

[0012] A method for manufacturing a semiconductor memory device according to one embodiment of the present disclosure includes forming a field effect transistor on a semiconductor substrate, forming an interlayer insulating film on the semiconductor substrate, forming a contact that penetrates the interlayer insulating film and is electrically connected to the drain of the field effect transistor, forming a first wiring layer on the contact, forming a first insulating layer on the interlayer insulating film to embed the first wiring layer, forming an opening in the first insulating layer and the interlayer insulating film from above the first wiring layer, and forming a ferroelectric capacitor inside the opening that is electrically connected to the source of the field effect transistor.

[0013] A method for manufacturing a semiconductor memory device according to one embodiment of the present disclosure includes forming a field effect transistor on a semiconductor substrate, forming an interlayer insulating film on the semiconductor substrate, forming a first opening in the interlayer insulating film, forming a second opening inside the first opening, the second opening having a smaller opening diameter than the first opening, and forming a ferroelectric capacitor electrically connected to a source of the field effect transistor inside an opening including the first opening and the second opening.

[0014] According to a semiconductor memory device and a method for manufacturing the semiconductor memory device according to an embodiment of the present disclosure, a capacitor included in the semiconductor memory device is formed in a memory cell in a three-dimensional structure that can secure a larger area. As a result, for example, the semiconductor memory device can increase the area of ​​the capacitor without increasing the area of ​​the memory cell, thereby further increasing the capacitance of the capacitor. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a circuit diagram showing an equivalent circuit of a semiconductor memory device according to a first embodiment of the present disclosure. [Figure 2] 2A and 2B are schematic diagrams showing a planar configuration and a cross-sectional configuration of the semiconductor memory device according to the same embodiment. [Figure 3A] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 3B] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 3C] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 3D] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 3E] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 3F] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 3G] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 3H] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 4] FIG. 2 is a cross-sectional view schematically showing a cross section of the semiconductor memory device according to the same embodiment taken along an active region. [Figure 5] 5A and 5B are schematic diagrams showing a planar configuration and a cross-sectional configuration of a semiconductor memory device according to a second embodiment of the present disclosure. [Figure 6A] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 6B] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 6C] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 6D] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 6E] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 6F] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 6G] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 7] FIG. 10 is a schematic diagram showing a cross-sectional configuration of a semiconductor memory device according to a third embodiment of the present disclosure. [Figure 8] FIG. 2 is a schematic diagram showing a planar layout of the semiconductor memory device according to the same embodiment. [Figure 9A] 10 is a cross-sectional view illustrating one step of a manufacturing method of the semiconductor memory device according to the embodiment. [Figure 9B] 10 is a cross-sectional view illustrating one step of a manufacturing method of the semiconductor memory device according to the embodiment. [Figure 9C] 10 is a cross-sectional view illustrating one step of a manufacturing method of the semiconductor memory device according to the embodiment. [Figure 9D] 10 is a cross-sectional view illustrating one step of a manufacturing method of the semiconductor memory device according to the embodiment. [Figure 9E] 10 is a cross-sectional view illustrating one step of a manufacturing method of the semiconductor memory device according to the embodiment. [Figure 9F] 10 is a cross-sectional view illustrating one step of a manufacturing method of the semiconductor memory device according to the embodiment. [Figure 9G] 10 is a cross-sectional view illustrating one step of a manufacturing method of the semiconductor memory device according to the embodiment. [Figure 9H] 10 is a cross-sectional view illustrating one step of a manufacturing method of the semiconductor memory device according to the embodiment. [Figure 9I] 10 is a cross-sectional view illustrating one step of a manufacturing method of the semiconductor memory device according to the embodiment. [Figure 10] FIG. 10 is a schematic diagram showing a cross-sectional configuration of a semiconductor memory device according to a first modified example of the embodiment. [Figure 11A] 10A and 10B are cross-sectional views illustrating a step in a manufacturing method of the semiconductor memory device according to the modified example. [Figure 11B] 10A and 10B are cross-sectional views illustrating a step in a manufacturing method of the semiconductor memory device according to the modified example. [Figure 11C] 10A and 10B are cross-sectional views illustrating a step in a manufacturing method of the semiconductor memory device according to the modified example. [Figure 11D] 10A and 10B are cross-sectional views illustrating a step in a manufacturing method of the semiconductor memory device according to the modified example. [Figure 11E] 10A and 10B are cross-sectional views illustrating a step in a manufacturing method of the semiconductor memory device according to the modified example. [Figure 11F] 10A and 10B are cross-sectional views illustrating a step in a manufacturing method of the semiconductor memory device according to the modified example. [Figure 12] FIG. 10 is a schematic diagram showing a cross-sectional configuration of a semiconductor memory device according to a second modification of the embodiment. [Figure 13] FIG. 10 is a schematic diagram showing a cross-sectional configuration of a semiconductor memory device according to a third modification of the embodiment. [Figure 14] 10A and 10B are schematic diagrams showing a planar configuration and a cross-sectional configuration of a semiconductor memory device according to a fourth embodiment of the present disclosure. [Figure 15A] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 15B] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 15C] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 15D] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 15E] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 15F] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 15G] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 15H] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 15I] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 16] FIG. 2 is a cross-sectional view schematically showing a cross section of the semiconductor memory device according to the same embodiment taken along an active region. [Figure 17] 10A and 10B are schematic diagrams showing a planar configuration and a cross-sectional configuration of a semiconductor memory device according to a fifth embodiment of the present disclosure. [Figure 18A] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 18B] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 18C] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 19] 10A and 10B are schematic diagrams showing a planar configuration and a cross-sectional configuration of a semiconductor memory device according to a sixth embodiment of the present disclosure. [Figure 20A] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 20B] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 21] 13A and 13B are schematic diagrams showing a planar configuration and a cross-sectional configuration of a semiconductor memory device according to a seventh embodiment of the present disclosure. [Figure 22A] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 22B] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 22C] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. [Figure 22D] 10A and 10B are schematic diagrams illustrating a step in the manufacturing method of the semiconductor memory device according to the same embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The embodiment described below is a specific example of the present disclosure, and the technology according to the present disclosure is not limited to the following aspects. Furthermore, the arrangement, dimensions, dimensional ratios, etc. of each component of the present disclosure are not limited to the aspects shown in the drawings.

[0017] The explanation will be given in the following order. 1. First embodiment Overview 1.2.Configuration Example 1.3. Manufacturing method 1.4. Example of operation 2. Second embodiment 2.1.Configuration Example 2.2. Manufacturing method 3. Third embodiment 3.1.Configuration Example 3.2. Manufacturing method 3.3. Variations 4. Fourth Embodiment 4.1.Configuration Example 4.2. Manufacturing method 4.3. Example of operation 5. Fifth Embodiment 5.1.Configuration Example 5.2. Manufacturing method 6. Sixth Embodiment 6.1.Configuration Example 6.2. Manufacturing method 7. Seventh Embodiment 7.1.Configuration Example 7.2. Manufacturing method

[0018] <1. First embodiment> (1.1. Overview) First, an overview of a semiconductor memory device according to a first embodiment of the present disclosure will be described with reference to Fig. 1. Fig. 1 is a circuit diagram showing an equivalent circuit of the semiconductor memory device according to this embodiment.

[0019] As shown in FIG. 1, a semiconductor memory device 10 according to this embodiment includes a capacitor 11 that stores information, and a transistor 21 that controls whether the capacitor 11 is selected or not.

[0020] The capacitor 11 is a ferroelectric capacitor including a pair of electrodes and a ferroelectric film sandwiched between the pair of electrodes. The capacitor 11 can store one bit of information depending on the direction of remanent polarization of the ferroelectric film. The capacitor 11 is electrically connected to the source line SL at one of the pair of electrodes and to the source of the transistor 21 at the other of the pair of electrodes.

[0021] The transistor 21 is a field effect transistor that controls the application of voltage to the capacitor 11. The source of the transistor 21 is electrically connected to the other electrode of the capacitor 11, and the drain is electrically connected to the bit line BL. The gate of the transistor 21 is electrically connected to the word line WL, and the state of the channel can be controlled by the voltage applied from the word line WL.

[0022] When writing information to the capacitor 11, in the semiconductor memory device 10, first, a voltage is applied to the word line WL, causing the channel of the transistor 21 to transition to an ON state. Then, a potential is applied to each of the source line SL and the bit line BL, and an electric field corresponding to the information to be written is applied to the ferroelectric film of the capacitor 11. In this way, the semiconductor memory device 10 can write information to the capacitor 11 by controlling the direction of the remanent polarization of the ferroelectric film of the capacitor 11 using an external electric field.

[0023] On the other hand, when reading information from the capacitor 11, in the semiconductor memory device 10, first, a voltage is applied to the word line WL, causing the channel of the transistor 21 to transition to an ON state. Then, a predetermined potential is applied to each of the source line SL and the bit line BL, causing the polarization direction of the ferroelectric film of the capacitor 11 to transition to a predetermined direction. At this time, the magnitude of the current flowing into the capacitor 11 during the transition varies depending on the polarization direction of the ferroelectric film before the transition. Therefore, the semiconductor memory device 10 can read the information stored in the capacitor 11 by measuring the magnitude of the current flowing into the capacitor 11.

[0024] Therefore, the semiconductor memory device 10 according to this embodiment can operate as an FeRAM (Ferroelectric Random Access Memory) that stores information in the capacitor 11 including a ferroelectric film.

[0025] In the semiconductor memory device 10 according to this embodiment, the capacitor 11 is provided inside a deeper opening. Specifically, in the semiconductor memory device 10, an opening is formed above a first wiring layer provided on an interlayer insulating film in which the transistor 21 is embedded, and the capacitor 11 is provided inside the opening. This allows the capacitance of the capacitor 11 to be increased further, and therefore the semiconductor memory device 10 can obtain a signal with a sufficient margin for operation.

[0026] (1.2. Configuration example) Next, a specific configuration example of the semiconductor memory device 10 according to this embodiment will be described with reference to Fig. 2. Fig. 2 is a schematic diagram showing the planar configuration and cross-sectional configuration of the semiconductor memory device 10 according to this embodiment.

[0027] In order to clarify the arrangement of each component, the planarization film 200 and the first insulating layer 300 formed over the entire surface of the semiconductor substrate 100 are omitted from the plan view in the upper left of Fig. 2. Each cross-sectional view in Fig. 2 shows a cross section taken along line AA, line BB, or line CC shown in the plan view in the upper left.

[0028] In the following, the term "first conductivity type" refers to either the "p type" or the "n type," and the term "second conductivity type" refers to the other of the "p type" or the "n type" that is different from the "first conductivity type."

[0029] 2, the semiconductor memory device 10 is provided on a semiconductor substrate 100. The semiconductor memory device 10 is a semiconductor memory that has a large number of memory cells arranged on the semiconductor substrate 100, and is capable of storing a large amount of information.

[0030] The capacitor 11 is provided inside an opening 110 formed on the source or drain region 151 by penetrating the planarization film 200 and the first insulating layer 300. Specifically, the capacitor 11 includes a lower electrode 111 provided along the inside of the opening 110, a ferroelectric film 113 provided on the lower electrode 111 along the opening 110, and an upper electrode 115 provided on the ferroelectric film 113 so as to fill the opening 110. The lower electrode 111 is electrically connected to the source or drain region 151 (e.g., the source) of the transistor 21, and the upper electrode 115 is electrically connected to a second wiring layer (not shown) that functions as a source line SL.

[0031] The transistor 21 includes a gate insulating film 140 provided on the semiconductor substrate 100, a gate electrode 130 provided on the gate insulating film 140, and a source or drain region 151 provided in an active region 150 of the semiconductor substrate 100. One of the source or drain regions 151 (for example, the source) is connected to the lower electrode 111 and thereby electrically connected to the capacitor 11, and the other of the source or drain region 151 (for example, the drain) is electrically connected via a contact 210 to a first wiring layer 310 functioning as a bit line BL. The gate electrode 130 is provided across the element isolation layer 105 and across multiple active regions 150, and thereby functions as a word line WL.

[0032] In the semiconductor memory device 10, the first wiring layer 310 is provided to extend in a first direction in the plane of the semiconductor substrate 100, and the gate electrode 130 is provided to extend in a second direction perpendicular to the first direction. The active region 150 is provided to extend in a strip shape in a third direction obliquely intersecting both the first and second directions. This allows the semiconductor memory device 10 to efficiently arrange the capacitors 11 and the transistors 21, thereby suppressing an increase in the area occupied by the semiconductor memory device 10.

[0033] Here, a stacked cylindrical dynamic random access memory (DRAM) can be cited as an example of a structure in which a capacitor is formed by embedding a dielectric and an electrode in an opening provided in the planarization film 200 or the semiconductor substrate 100. However, in a DRAM that stores information using charges accumulated in a capacitor, a capacitor capacitance of about 20 fF is required, for example, for a bit line capacitance of 100 fF in order to read the stored information with sufficient accuracy.

[0034] For example, if the dielectric constant of the dielectric used in the capacitor is 25, and the width of the dielectric film is 60 nm and the film thickness is 5 nm, the depth of the opening to form a capacitor with a capacitance of 20 fF will be approximately 8 μm. Since processing an opening of this depth is extremely difficult, it makes it difficult to miniaturize and increase the integration density of DRAM.

[0035] The semiconductor memory device 10 according to this embodiment functions as an FeRAM that stores information using the remanent polarization of a ferroelectric material. Since the FeRAM operates on a different principle from DRAM, even if the capacitance of the bit line is 100 fF, for example, the remanent polarization of the ferroelectric material may be 25 μC / cm 2 If the depth is about 200 nm, forming the capacitor 11 in an opening with a depth of about 200 nm makes it possible to read information with sufficient accuracy. Therefore, the semiconductor memory device 10 according to this embodiment can be more easily miniaturized and highly integrated.

[0036] Each component of the semiconductor memory device 10 will be described in more detail below.

[0037] The semiconductor substrate 100 is made of a semiconductor material and is a substrate on which the capacitor 11 and the transistor 21 are formed. The semiconductor substrate 100 may be a silicon substrate, or may be an SOI (Silicon On Insulator) substrate in which an insulating film such as SiO2 is sandwiched between a silicon substrate. The semiconductor substrate 100 may also be a substrate formed of other element semiconductors such as germanium, or may be a substrate formed of a compound semiconductor such as gallium arsenide (GaAs), gallium nitride (GaN), or silicon carbide (SiC).

[0038] The element isolation layer 105 is made of an insulating material and electrically isolates the transistors 21 provided on the semiconductor substrate 100 from each other. The element isolation layers 105 are provided in strip-shaped regions spaced apart from each other and extending in a third direction (e.g., a direction from the upper left to the lower right when viewed from the front of FIG. 2). The third direction is a direction obliquely intersecting both the first direction in which the first wiring layer 310 extends (e.g., a horizontal direction when viewed from the front of FIG. 2) and the second direction in which the gate electrode 130 extends (e.g., a vertical direction when viewed from the front of FIG. 2). For example, the element isolation layer 105 may be made of an insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON).

[0039] For example, the element isolation layer 105 is formed by using an STI (Shallow Trench Isolation) method to remove a part of the semiconductor substrate 100 in a predetermined region by etching or the like, and then filling the opening formed by etching or the like with silicon oxide (SiO x Alternatively, the element isolation layer 105 may be formed by thermally oxidizing a predetermined region of the semiconductor substrate 100 using a LOCOS (LOCal Oxidation of Silicon) method.

[0040] The strip-shaped regions separated from each other by the element isolation layer 105 function as active regions 150 in which the transistors 21 are provided. In the active regions 150, for example, a first conductivity type impurity (for example, a p-type impurity such as boron (B) or aluminum (Al)) is introduced.

[0041] 2, the element isolation layer 105 and the active region 150 may be provided in a strip shape extending in the third direction. This allows the capacitors 11 and the transistors 21 to be efficiently arranged in the semiconductor memory device 10, thereby preventing an increase in the area occupied by the semiconductor memory device 10.

[0042] The gate insulating film 140 is made of an insulating material and is provided on the active region 150 of the semiconductor substrate 100. The gate insulating film 140 may be made of an insulating material known as a gate insulating film for a field effect transistor. For example, the gate insulating film 140 may be made of silicon oxide (SiO x ) or other oxides.

[0043] The gate electrode 130 is made of a conductive material and is provided on the gate insulating film 140. Specifically, a plurality of the gate electrodes 130 are provided at predetermined intervals in a second direction perpendicular to a first direction in which the first wiring layer 310 extends, and extend in the first direction obliquely intersecting a third direction in which the element isolation layer 105 extends. The gate electrodes 130 are provided so as to extend beyond the element isolation layer 105 into a plurality of active regions 150, and thereby function as word lines WL that electrically connect the gates of the transistors 21 of each memory cell.

[0044] For example, the gate electrode 130 may be formed of polysilicon or the like, or may be formed of a metal, an alloy, a metal compound, or an alloy of a metal (such as Ni) and polysilicon (so-called silicide). Specifically, the gate electrode 130 may be formed of a laminated structure of a metal layer made of TiN or TaN and a polysilicon layer provided on the gate insulating film 140. Such a laminated structure allows the gate electrode 130 to have a lower wiring resistance than when it is formed of only a polysilicon layer.

[0045] The source or drain region 151 is a region of the second conductivity type formed in the semiconductor substrate 100. Specifically, the source or drain region 151 is provided in the active region 150 extending in the third direction, with the gate electrode 130 sandwiched therebetween. The source side of the source or drain region 151 is electrically connected to the lower electrode 111, and the drain side of the source or drain region 151 is electrically connected via the contact 210 to the first wiring layer 310, which is the bit line BL.

[0046] For example, the source or drain region 151 can be formed by introducing a second conductivity type impurity (e.g., an n-type impurity such as phosphorus (P) or arsenic (As)) into the semiconductor substrate 100 in the active region 150. Note that an LDD (Lightly-Doped Drain) region having a lower concentration of the second conductivity type impurity than the source or drain region 151 may be formed in the semiconductor substrate 100 between the source or drain region 151 and the gate electrode 130.

[0047] The sidewall insulating film 132 is made of an insulating material and is provided as a sidewall on the side surface of the gate electrode 130. The sidewall insulating film 132 can be formed by uniformly depositing an insulating film in a region including the gate electrode 130 and then vertically anisotropically etching the insulating film. For example, the sidewall insulating film 132 can be made of silicon oxide (SiO x ), silicon nitride (SiN x ), or an insulating oxynitride such as silicon oxynitride (SiON), in a single layer or multiple layers.

[0048] The sidewall insulating film 132 can control the positional relationship between the gate electrode 130 and the source or drain region 151 in a self-aligned manner by blocking the second-conductivity-type impurities when the second-conductivity-type impurities are introduced into the semiconductor substrate 100. Furthermore, the sidewall insulating film 132 can control the introduction of the second-conductivity-type impurities into the semiconductor substrate 100 in a stepwise manner, so that the above-mentioned LDD region can also be formed in a self-aligned manner between the source or drain region 151 and the gate electrode 130.

[0049] The cap layer 131 is provided on the gate electrode 130 and functions as a word line WL that electrically connects the gate electrodes 130 of each memory cell. For example, the cap layer 131 may be formed of a metal or a metal compound. Furthermore, as described above in the description of the gate electrode 130, the cap layer 131 may be formed of a metal, alloy, metal compound, or alloy (so-called silicide) of a metal (such as Ni) and polysilicon provided on polysilicon. That is, the gate electrode 130 and the cap layer 131 may be formed of a stacked structure of a metal layer made of TiN or TaN provided on the gate insulating film 140, a polysilicon layer (gate electrode 130), and a metal layer (cap layer 131) made of TiN or TaN. Such a stacked structure allows the semiconductor memory device 10 to further reduce wiring resistance.

[0050] The contact region 152 is provided on the surface of the semiconductor substrate 100 of the source or drain region 151, and can reduce the contact resistance between the source or drain region 151 and the lower electrode 111 or the contact 210. Specifically, the contact region 152 may be made of an alloy (so-called silicide) of silicon and a metal such as Ni.

[0051] The planarization film 200 is made of an insulating material, and is provided so as to bury the transistor 21 and to extend over the entire surface of the semiconductor substrate 100. For example, the planarization film 200 may be made of silicon oxide (SiO x ), silicon nitride (SiNx ), or an insulating oxynitride such as silicon oxynitride (SiON).

[0052] Although not shown in FIG. 2 , a liner layer made of an insulating material may be provided over the entire surfaces of the semiconductor substrate 100, the sidewall insulating film 132, and the cap layer 131. The liner layer can provide a high etching selectivity between the liner layer and the planarization film 200 in the step of forming an opening in the planarization film 200 for providing the capacitor 11 or the contact 210. This allows the liner layer to prevent etching from progressing to the semiconductor substrate 100 in the etching step. The liner layer may be made of an insulating oxynitride such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON). For example, when the planarization film 200 is made of silicon oxide (SiOx), the liner layer may be made of silicon nitride (SiNx).

[0053] The liner layer may also be configured as a layer that applies compressive stress or tensile stress to the semiconductor substrate 100 below the gate insulating film 140. In such a case, the liner layer can control the carrier mobility of a channel formed in the semiconductor substrate 100 by the stress effect.

[0054] The opening 110 is provided from an upper layer than the first wiring layer 310, penetrating the planarization film 200 and the first insulating layer 300, so as to expose the source or drain region 151. By providing the opening 110 from an upper layer, the semiconductor memory device 10 can further increase the area of ​​the cylindrical capacitor 11 provided inside the opening 110. Therefore, the semiconductor memory device 10 can further increase the capacitance of the capacitor 11 provided inside the opening 110.

[0055] The lower electrode 111 is made of a conductive material and is provided along the inside of an opening 110 formed in the planarization film 200 and the first insulating layer 300. Specifically, the opening 110 is provided so as to expose one of the source or drain regions 151, and the lower electrode 111 is provided on one of the source or drain regions 151 exposed by the opening 110. This allows the lower electrode 111 to be electrically connected to the source side of the source or drain region 151. Furthermore, the lower electrode 111 is provided recessed from the opening surface of the opening 110 provided in the first insulating layer 300. This prevents the lower electrode 111 from being short-circuited with the upper electrode 115, etc., in the capacitor 11.

[0056] For example, the lower electrode 111 may be made of a metal such as titanium (Ti) or tungsten (W), or may be made of a metal compound such as titanium nitride (TiN) or tantalum nitride (TaN). The lower electrode 111 may also be made of ruthenium (Ru) or ruthenium oxide (RuO2). The lower electrode 111 can be formed by using ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition), or sputtering using IMP (Ionized Metal Plasma), or the like.

[0057] The ferroelectric film 113 is made of a ferroelectric material and is provided on the lower electrode 111 along the inside of the opening 110 provided in the planarizing film 200 and the first insulating layer 300. The ferroelectric film 113 is made of a ferroelectric material that is spontaneously polarized and whose direction of remanent polarization can be controlled by an external electric field.

[0058] For example, the ferroelectric film 113 may be formed of a ferroelectric material with a perevskite structure, such as lead zirconate titanate (Pb(Zr,Ti)O: PZT) or strontium bismuthate tantalate (SrBi2Ta2O9: SBT). x , ZrO x or HfZrO xThe ferroelectric film 113 may be a ferroelectric film obtained by altering a film made of a high-dielectric material such as HfO by heat treatment or the like, or may be a ferroelectric film obtained by altering a film made of the above-mentioned high-dielectric material by introducing atoms such as lanthanum (La), silicon (Si) or gadolinium (Gd). Furthermore, the ferroelectric film 113 may be formed as a single layer or as multiple layers. For example, the ferroelectric film 113 may be formed as a single layer or as a multi-layer. x Alternatively, the ferroelectric film 113 may be a single layer film made of a ferroelectric material such as the above. The ferroelectric film 113 can be formed by using ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition), or the like.

[0059] The upper electrode 115 is made of a conductive material and is provided on the ferroelectric film 113 so as to fill the openings 110 provided in the planarization film 200 and the first insulating layer 300. For example, the upper electrode 115 may be made of a metal such as titanium (Ti) or tungsten (W), or may be made of a metal compound such as titanium nitride (TiN) or tantalum nitride (TaN). The upper electrode 115 may also be made of ruthenium (Ru) or ruthenium oxide (RuO2). The upper electrode 115 can be formed by using ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition), or the like.

[0060] The capacitor 11 is configured by sandwiching the above-mentioned ferroelectric film 113 between a lower electrode 111 and an upper electrode 115. This allows the semiconductor memory device 10 to store information based on the polarization direction of the ferroelectric film 113 of the capacitor 11.

[0061] The contact 210 is made of a conductive material and is provided so as to penetrate the planarization film 200. Specifically, the contact 210 is provided on the other of the source or drain regions 151, and electrically connects the drain side of the source or drain region 151 to the first wiring layer 310, which is the bit line BL.

[0062] For example, the contact 210 may be made of a metal such as titanium (Ti) or tungsten (W), or may be made of a metal compound such as titanium nitride (TiN) or tantalum nitride (TaN). The contact 210 may be formed of a single layer or a multi-layer stack. For example, the contact 210 may be formed of a stack of Ti or TiN and W.

[0063] The first wiring layer 310 is made of a conductive material and provided on the planarization film 200. Specifically, the first wiring layer 310 is provided on the contact 210 as wiring extending in a first direction perpendicular to a second direction in which the gate electrode 130 (word line WL) extends. The first wiring layer 310 functions as a bit line BL by being electrically connected to the drain side of the source or drain region 151 via the contact 210. The first wiring layer 310 may be made of a metal material such as aluminum (Al), or may be configured with a copper (Cu) damascene structure or a dual damascene structure.

[0064] The first insulating layer 300 buries the first wiring layer 310 and is provided on the planarization film 200 so as to extend over the entire surface of the semiconductor substrate 100. The first insulating layer 300 may be made of an insulating oxynitride such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON).

[0065] The via contact 311 is made of a conductive material and provided on the first wiring layer 310. Specifically, the via contact 311 is provided to penetrate the first insulating layer 300 and electrically connects the lower first wiring layer 310 with the upper wiring layer 312. The via contact 311 may be made of a metal material such as aluminum (Al), or may be configured with a copper (Cu) damascene structure.

[0066] The upper wiring layer 312 is made of a conductive material and is provided on the via contact 311. The upper wiring layer 312 may be made of a metal material such as aluminum (Al), or may have a copper (Cu) damascene structure. The upper wiring layer 312 is formed in the logic region. The wiring may be formed simultaneously with or shared with other circuits provided in the other circuits.

[0067] The upper electrode 115 of the capacitor 11 is electrically connected to a second wiring layer (not shown). The second wiring layer is made of a conductive material and is provided above the first insulating layer 300 and the upper wiring layer 312. Specifically, the second wiring layer is provided on the upper electrode 115 of the capacitor 11 as a wiring extending in the first direction, similar to the first wiring layer 310. The second wiring layer functions as a source line SL by being electrically connected to the upper electrode 115. The second wiring layer may be made of a metal material such as aluminum (Al), or may be configured with a copper (Cu) damascene structure or a dual damascene structure.

[0068] According to the above structure, in the semiconductor memory device 10, the capacitor 11, which is a ferroelectric capacitor, is provided inside the opening 110 that penetrates the planarization film 200 and the first insulating layer 300. This allows the semiconductor memory device 10 to expand the area of ​​the capacitor 11, thereby increasing the capacitance of the capacitor 11. Therefore, the semiconductor memory device 10 can obtain a signal with a sufficient margin for operation.

[0069] Furthermore, the semiconductor memory device 10 can more efficiently arrange the transistors 21 and capacitors 11 by defining the extending directions of the active region 150, the word lines WL, the source lines SL, and the bit lines BL, thereby preventing the semiconductor memory device 10 from increasing the area occupied by the memory cells.

[0070] (1.3. Manufacturing method) Next, a method for manufacturing the semiconductor memory device 10 according to this embodiment will be described with reference to Figures 3A to 3H. Figures 3A to 3H are schematic views illustrating one step in the method for manufacturing the semiconductor memory device 10 according to this embodiment.

[0071] 3A to 3H, layers provided over the entire surface of semiconductor substrate 100 are omitted, as in Fig. 2. Each of the cross-sectional views in Fig. 3A to 3H shows a cross section taken along line AA, line BB, or line CC shown in the top left plan view.

[0072] First, as shown in FIG. 3A, an element isolation layer 105 is formed on a semiconductor substrate 100, and an active region 150 in which a transistor 21 will be formed in a later step is formed.

[0073] Specifically, an SiO2 film is formed on a semiconductor substrate 100 made of Si by dry oxidation or the like, and then an Si3N4 film is formed by low-pressure CVD or the like. Next, a patterned resist layer is formed on the Si3N4 film so as to protect the region where the active region 150 will be provided, and then the SiO2 film, Si3N4 film, and semiconductor substrate 100 are etched to a depth of 350 nm to 400 nm. Next, SiO2 is deposited to a thickness of 650 nm to 700 nm to fill the openings formed by the etching, thereby forming the element isolation layer 105. For example, high-density plasma CVD may be used to deposit SiO2, which has good step coverage and can form a dense SiO2 film.

[0074] Subsequently, the excess SiO2 film is removed by CMP (Chemical Mechanical Polishing) or the like to planarize the surface of the semiconductor substrate 100. The SiO2 film may be removed by CMP until the Si3N4 film is exposed, for example.

[0075] Furthermore, the Si3N4 film is removed using hot phosphoric acid or the like. It is possible to anneal the semiconductor substrate 100 in an N2, O2, or H2 / O2 environment before removing the Si3N4 film in order to make the SiO2 film of the element isolation layer 105 a denser film or to round the corners of the active region 150. Next, the surface of the semiconductor substrate 100 in the region corresponding to the active region 150 is oxidized to a depth of about 10 nm to form an oxide film 100A, and then a first conductivity type impurity (e.g., boron (B)) is ion-implanted to convert the semiconductor substrate 100 in the active region 150 into a first conductivity type well.

[0076] Next, as shown in FIG. 3B, after depositing the gate insulating film 140, the gate electrode 130 is formed on the gate insulating film 140.

[0077] Specifically, first, the oxide film 100A covering the surface of the semiconductor substrate 100 is removed using a hydrofluoric acid solution or the like. Then, a gate insulating film 140 made of SiO2 is formed on the semiconductor substrate 100 to a thickness of 1.5 nm to 10 nm by dry oxidation using O2 at 700°C or by RTA (Rapid Thermal Anneal) processing. Note that, in addition to O2, a mixed gas of H2 / O2, N2O, or NO may also be used as the gas used for dry oxidation. Furthermore, when forming the gate insulating film 140, nitrogen doping into the SiO2 film is also possible by using plasma nitridation.

[0078] Next, polysilicon is deposited to a thickness of 50 nm to 150 nm using low-pressure CVD with SiH4 gas as the source gas and a deposition temperature of 580°C to 620°C. Thereafter, the deposited polysilicon is anisotropically etched using a patterned resist as a mask to form the gate electrode 130. For example, an HBr-based gas or a Cl-based gas can be used for the anisotropic etching. For example, for a 40 nm node, the gate electrode 130 may be formed with a gate width of approximately 40 nm to 50 nm.

[0079] The gate electrode 130 functions as a word line WL. The gate electrode 130 may be formed simultaneously with or shared with the gate electrodes of other transistors provided in the logic region or the like.

[0080] Next, as shown in FIG. 3C, sidewall insulating films 132 are formed on both side surfaces of the gate electrode 130, and a source or drain region 151 is formed in the active region 150 of the semiconductor substrate 100.

[0081] Specifically, arsenic (As), which is a second conductivity type impurity, is implanted on both sides of the gate electrode 130 at 5 keV to 20 keV, with a dose of 5 to 20×10 13 pieces / cm 2 The LDD region is formed by implanting ions at a concentration of 1000 . The formation of the LDD region can suppress the short channel effect, thereby suppressing the variation in characteristics of the transistor 21. Note that phosphorus (P) can also be used as the second conductivity type impurity.

[0082] Next, SiO2 is deposited to a thickness of 10 nm to 30 nm by plasma CVD, and then Si3N4 is deposited to a thickness of 30 nm to 50 nm by plasma CVD to form a sidewall insulating film. Thereafter, the sidewall insulating film is anisotropically etched to form sidewall insulating films 132 on both side surfaces of the gate electrode 130.

[0083] Then, arsenic (As), a second conductivity type impurity, is introduced at 20 keV to 50 keV, and 1 to 2 × 10 15 pieces / cm 2The second conductivity type impurity is introduced into both sides of the gate electrode 130 by ion implantation at a concentration of 1000°C. As a result, source or drain regions 151 are formed in the active region 150 on both sides of the gate electrode 130. Furthermore, the ion-implanted impurity is activated by RTA (Rapid Thermal Annealing) at 1000°C for 5 seconds, thereby forming the transistor 21. Note that in order to promote activation of the introduced impurity and suppress diffusion of the impurity, it is also possible to activate the impurity by spike RTA.

[0084] Furthermore, Ni is deposited to a thickness of 6 nm to 8 nm on the entire surface of the semiconductor substrate 100 by sputtering or the like, and then RTA is performed at 300°C to 450°C for 10 to 60 seconds to convert the Ni on the Si into silicide (NiSi). Unreacted Ni on the SiO2 is removed using H2SO4 / H2O2, thereby forming a cap layer 131 and contact region 152 made of low-resistance NiSi on the gate electrode 130 and the source or drain region 151. Note that Co or NiPt may be deposited instead of Ni to form the cap layer 131 and contact region 152 of CoSi2 or NiPtSi. The RTA temperature when Co or NiPt is deposited may be set appropriately.

[0085] Subsequently, as shown in FIG. 3D, a planarization film 200 is formed over the entire surface of the semiconductor substrate 100 so as to bury the transistor 21 therein.

[0086] Specifically, SiO 2 is deposited on the semiconductor substrate 100 to a thickness of 100 nm to 500 nm using CVD or the like, and then planarized by CMP, thereby forming the planarization film 200.

[0087] Although not shown, before forming the planarization film 200, a SiN x Alternatively, a liner layer made of SiN may be formed on the entire surface of the semiconductor substrate 100. For example, the liner layer may be formed by plasma CVD using SiN xThe liner layer may be formed to a thickness of 10 nm to 50 nm. The liner layer may also be formed as a layer that applies compressive stress or tensile stress to the semiconductor substrate 100. By forming the liner layer, the planarization film 200 can be etched in a later step under conditions that increase the etching selectivity between the planarization film 200 and the liner layer, allowing etching to be performed with higher controllability.

[0088] Next, as shown in FIG. 3E, contacts 210 are formed to electrically connect to the other of the source or drain regions 151 and the gate electrode 130, and then a first wiring layer 310 is formed on the contacts 210.

[0089] Specifically, an opening is formed on the other of the source or drain regions 151 by etching the planarization film 200. Subsequently, Ti and TiN are deposited in the formed opening by CVD or the like, and then W is deposited, and then planarization is performed by CMP, thereby forming the contact 210 on the other of the source or drain regions 151. Note that Ti and TiN may be deposited by sputtering or the like using IMP (Ion Metal Plasma). Planarization may also be performed by full surface etch-back instead of CMP.

[0090] It is possible to form contacts electrically connected to the gate electrode 130 in a similar process. Furthermore, these contacts 210 may be formed simultaneously with contacts of other transistors provided in the logic region or the like.

[0091] Thereafter, a first wiring layer 310 is formed on the planarization film 200 using Al or the like as a wiring material. The first wiring layer 310 functions as a bit line BL by extending in a first direction on the contact 210. Note that the first wiring layer 310 may be formed using a damascene structure using Cu as a wiring material.

[0092] Next, as shown in FIG. 3F, a first insulating layer 300 is formed to bury the first wiring layer 310, and then an opening 110 is formed that penetrates the planarization film 200 and the first insulating layer 300 and exposes the source or drain region 151.

[0093] Specifically, SiO2 is deposited on the planarization film 200 to a thickness of 100 nm to 500 nm using CVD or the like so as to bury the first wiring layer 310, and then planarization is performed by CMP to form the first insulating layer 300. The first insulating layer 300 may be formed of a low-dielectric-constant material (e.g., SiOC containing carbon) having a lower dielectric constant than SiO2. Although not shown, before forming the first insulating layer 300, a SiN x For example, the liner layer may be formed by using plasma CVD. x It can be formed by depositing it to a film thickness of 10 nm to 50 nm.

[0094] Next, an opening 110 is formed in the planarization film 200 and the first insulating layer 300 on the other of the source or drain regions 151 by anisotropic etching using a resist patterned by lithography as a mask. The opening 110 can be formed to a width of, for example, 60 nm. In this case, if the aspect ratio of the opening 110 is approximately 20 or less, the etching to form the opening 110 and the subsequent filling of the opening 110 by deposition can be performed without any problems. The anisotropic etching can be performed using, for example, a fluorocarbon-based gas. Furthermore, the use of the above-mentioned liner layer allows the etching to be stopped with good control.

[0095] Next, as shown in FIG. 3G, the capacitor 11 is formed inside the opening 110.

[0096] Specifically, first, TiN is deposited to a thickness of 5 nm to 10 nm on the source or drain region 151 along the internal shape of the opening 110 using sputtering by ALD, CVD, or IMP, to form the lower electrode 111. Thereafter, a resist is applied onto the deposited lower electrode 111, and then etch-back is performed under conditions that give the resist and the lower electrode 111 approximately the same selectivity, thereby recessing the lower electrode 111 from the opening surface of the opening 110. This leaves the lower electrode 111 on the bottom and side surfaces of the opening 110, and the shoulders of the lower electrode 111 are recessed, forming a recess.

[0097] Next, hafnium oxide (HfO ), which is a high dielectric material, is deposited on the lower electrode 111 along the inner shape of the opening 110. x ) is deposited to a thickness of 3 nm to 10 nm by CVD or ALD to form a ferroelectric film 113. Note that hafnium oxide (HfO x ) is subsequently converted into a ferroelectric material by annealing.

[0098] In addition, instead of hafnium oxide, zirconium oxide (ZrO x ) or hafnium zirconium oxide (HfZrO x It is also possible to use high-dielectric materials such as lanthanum (La), silicon (Si), or gadolinium (Gd) to convert these high-dielectric materials into ferroelectric materials.

[0099] Thereafter, TiN is deposited on the ferroelectric film 113 by CVD, ALD, sputtering, or the like to a thickness of 5 nm to 20 nm so as to fill the opening 110, thereby forming the upper electrode 115. Note that TaN or the like can also be used as the material for forming the upper electrode 115. Next, HfO, which constitutes the ferroelectric film 113, is deposited. x The HfO is then subjected to crystallization annealing to convert it into a ferroelectric material. xThe crystallization annealing for converting the first insulating layer 300 into a ferroelectric material may be performed in this process or in another process. The temperature of the crystallization annealing can be changed as desired, as long as it is within the range of 500°C or less and within the heat resistance range of other components such as the transistor 21, NiSi, and wiring. After that, CMP or the like is performed to remove excess ferroelectric film 113 and upper electrode 115 deposited on the first insulating layer 300. This forms the capacitor 11.

[0100] 3H, via contacts 311 and upper wiring layer 312 are formed on first wiring layer 310. Specifically, the via contacts 311 and upper wiring layer 312 can be formed by using a damascene structure using Cu or the like as a wiring material. Note that the via contacts 311 and upper wiring layer 312 may also be formed of Al or the like.

[0101] According to the above steps, the semiconductor memory device 10 according to this embodiment can be formed.

[0102] (1.4. Example of operation) Next, a description will be given of the write and read operations of the semiconductor memory device 10 according to this embodiment. Figure 4 is a cross-sectional view schematically showing a cross section of the semiconductor memory device 10 according to this embodiment taken along the active region 150.

[0103] 4, the semiconductor memory device 10 includes a transistor 21 and a capacitor 11 connected to the source side of a source or drain region 151 of the transistor 21. The semiconductor memory device 10 is driven by a word line WL connected to a gate electrode 130 of the transistor 21, a bit line BL connected to the drain side of the source or drain region 151 of the transistor 21 via a contact 210, and a source line SL connected to the capacitor 11.

[0104] Table 1 below shows an example of voltages (unit: V) applied to SWL, SBL, SSL, Well, UWL, UBL, and USL shown in FIG. 4 during write and read operations of the semiconductor memory device 10.

[0105] In Table 1, Vth is the threshold voltage for turning on the channel of transistor 21, and Vw is the voltage capable of reversing the polarization state of capacitor 11. SWL, SBL, and SSL respectively indicate the word line WL, bit line BL, and source line SL of a selected memory cell, and UWL, UBL, and USL respectively indicate the word line WL, bit line BL, and source line SL of an unselected memory cell. Well indicates the active region 150 of the semiconductor substrate 100.

[0106] [Table 1]

[0107] For example, when writing information "1" into a memory cell, Vw+Vth is applied to the word line WL connected to the selected memory cell of the semiconductor memory device 10, Vw is applied to the bit line BL, 0 V is applied to the source line SL, and 0 V is applied to the active region 150 of the semiconductor substrate 100. In addition, the word line WL, bit line BL, and source line SL connected to the unselected memory cells of the semiconductor memory device 10 are all set to 0 V.

[0108] According to this, in the selected memory cell, when Vw is applied to the bit line BL, the potential of the other of the source or drain region 151 of the transistor 21 becomes Vw, and therefore the potential of the lower electrode 111 of the capacitor 11 becomes Vw. On the other hand, since the potential of the source line SL is 0V, the potential of the upper electrode 115 becomes 0V. Therefore, an electric field of Vw is applied to the ferroelectric film 113 of the capacitor 11, which makes the lower electrode 111 side have a higher potential, and therefore the polarization state of the ferroelectric film 113 is controlled. By the above operation, for example, information "1" can be written to the memory cell.

[0109] At this time, the potential of the source or drain region 151 of the transistor 21 of the selected memory cell becomes Vw, but in the transistors 21 of the unselected memory cells, the word line WL and the gate electrode 130 are at 0 V. Therefore, in the adjacent unselected memory cells, no potential is applied to the lower electrode 111, and no electric field is applied to the ferroelectric film 113 of the capacitor 11.

[0110] Furthermore, when writing information "0" into a memory cell, Vw+Vth is applied to the word line WL connected to a selected memory cell of the semiconductor memory device 10, and Vw is applied to the source line SL. The bit line BL is set to 0V, and the active region 150 of the semiconductor substrate 100 is set to 0V. Furthermore, the word line WL, bit line BL, and source line SL connected to unselected memory cells of the semiconductor memory device 10 are each set to 0V.

[0111] According to this, in the selected memory cell, since the bit line BL is 0V, the potential of the other of the source or drain region 151 of the transistor 21 is 0V, and the potential of the lower electrode 111 of the capacitor 11 is 0V. On the other hand, since the potential of the source line SL is Vw, the potential of the upper electrode 115 is Vw. Therefore, a potential difference of Vw, which makes the upper electrode 115 side have a higher potential, is applied to the ferroelectric film 113 of the capacitor 11, and the polarization state of the ferroelectric film 113 is controlled. By the above operation, information such as "0" can be written to the memory cell.

[0112] At this time, the potential of the source line SL of the selected memory cell becomes Vw, but in the transistors 21 of the unselected memory cells, the word lines WL and the gate electrodes 130 are at 0 V. Therefore, in the adjacent unselected memory cells, no potential is applied to the lower electrodes 111, and no electric field is applied to the ferroelectric film 113 of the capacitors 11.

[0113] In addition, reading information from a memory cell of the semiconductor memory device 10 is performed, for example, by utilizing the change in displacement current that occurs when writing predetermined information (e.g., "1") to a memory cell based on the information ("0" or "1") stored before writing.

[0114] For example, Table 1 shows the voltages applied to the SWL, SBL, SSL, Well, UWL, UBL, and USL when writing "1" to a memory cell and reading information from the memory cell. In this case, if the information stored in the memory cell is "1," the amount of displacement current is small, and if the information stored in the memory cell is "0," the amount of displacement current is large. This allows the semiconductor memory device 10 to determine whether the information stored in the memory cell is "0" or "1."

[0115] However, when information is read from a memory cell by the above-described read operation, the information stored in the memory cell is overwritten with the predetermined information written during the read operation. That is, in the semiconductor memory device 10, reading information from a memory cell is a destructive read. Therefore, in the semiconductor memory device 10, after the read operation, a rewrite operation is performed to restore the information destroyed by the read operation.

[0116] 2. Second embodiment (2.1. Configuration example) Next, a semiconductor memory device according to a second embodiment of the present disclosure will be described with reference to Fig. 5. Fig. 5 is a schematic diagram showing the planar configuration and cross-sectional configuration of a semiconductor memory device 10A according to this embodiment.

[0117] 5, the planarization film 200 formed over the entire surface of the semiconductor substrate 100 is omitted in order to clarify the arrangement of each component. The cross sections are shown along the lines AA, BB, and CC shown in the plan view above.

[0118] As shown in FIG. 5, the semiconductor memory device 10A according to the second embodiment differs from the semiconductor memory device 10 according to the first embodiment in that a capacitor 11 is provided inside an opening 110 including a first opening 110A and a second opening 110B having different opening diameters.

[0119] Specifically, the first opening 110A is formed in the planarization film 200 with a larger diameter than the second opening 110B. The diameter of the first opening 110A may be, for example, such that it does not come into contact with the first opening 110A of an adjacent memory cell in the first direction and does not overlap with the gate electrode 130 in the second direction. The depth of the first opening 110A may also be such that it does not come into contact with the gate electrode 130, the sidewall insulating film 132, and the cap layer 131.

[0120] The second opening 110B has a smaller diameter than the first opening 110A and is formed in the planarization film 200 inside (i.e., at the bottom) of the first opening 110A. The size of the second opening 110B may be, for example, approximately the same as the size of the source or drain region 151. The depth of the second opening 110B may be such that the source or drain region 151 is exposed from the bottom of the first opening 110A.

[0121] Therefore, the opening 110 including the first opening 110A and the second opening 110B is provided in a shape in which the opening diameter widens on the upper side opposite to the lower side where the semiconductor substrate 100 is provided. By providing the capacitor 11 inside the opening 110 including the first opening 110A and the second opening 110B, the semiconductor memory device 10A can further increase the area of ​​the capacitor 11 while suppressing short circuits between the capacitor 11 and the gate electrode 130. Therefore, the semiconductor memory device 10A can obtain a signal with a sufficient margin for operation while improving the reliability of the device.

[0122] In the semiconductor memory device 10A of the second embodiment, the opening 110 may be provided so as to penetrate only the planarization film 200, or, as in the semiconductor memory device 10 of the first embodiment, may be provided so as to penetrate the planarization film 200 and the first insulating layer 300 from a layer above the first wiring layer 310.

[0123] (2.2. Manufacturing method) Next, a method for manufacturing the semiconductor memory device 10A according to this embodiment will be described with reference to Figures 6A to 6G. Figures 6A to 6G are schematic views illustrating one step in the method for manufacturing the semiconductor memory device 10A according to this embodiment.

[0124] 6A to 6G, similarly to Fig. 5, layers provided over the entire surface of semiconductor substrate 100 are omitted. Each of the cross-sectional views in Fig. 6A to 6G shows a cross section taken along line AA, line BB, or line CC shown in the top left plan view.

[0125] First, as shown in FIG. 6A, the transistor 21, the planarization film 200, and the contact 210 are formed by the same steps as those shown in FIGS. 3A to 3E of the first embodiment.

[0126] 6B, a first opening 110A is formed in the planarization film 200 on the other of the source and drain regions 151 by anisotropic etching using a resist patterned by lithography as a mask. The first opening 110A can be formed to have a width of 90 nm and a depth of 100 nm, for example.

[0127] Next, as shown in FIG. 6C, spacers 117 are formed on the inner surface of first opening 110A. Specifically, amorphous silicon (a-Si) is deposited to a thickness of 15 nm on planarization film 200 including first opening 110A, and then the a-Si is anisotropically etched to form spacers 117 only on the inner surface of first opening 110A. Spacers 117 can be formed from a material that will serve as a mask during etching to form second opening 110B in a subsequent step, and can be formed from, for example, silicon nitride (SiNx), silicon oxynitride (SiON), silicon carbide (SiC), or the like. The deposition temperature of a-Si is selected taking into consideration the effect on the underlying transistor 21, etc.

[0128] Next, as shown in FIG. 6D, a second opening 110B is formed at the bottom of the first opening 110A, and then a lower electrode 111 is formed along the inner shapes of the first opening 110A and the second opening 110B.

[0129] Specifically, the second opening 110B can be formed by etching the planarization film 200 using the spacer 117 as a mask. For example, the second opening 110B can be formed with good control by stopping the etching at the liner layer using high SiO2 / SiN etching conditions and then etching down to the contact region 152 above the source or drain region 151. The second opening 110B can be formed with a width (e.g., 60 nm) smaller than that of the first opening 110A. This increases the distance between the gate electrode 130 and the second opening 110B, thereby preventing a short circuit between the gate electrode 130 and the capacitor 11. At this time, the spacer 117 can also be removed. Specifically, by using chemical dry etching (CDE) to increase the etching selectivity between Si and SiO2, only the spacer 117 can be removed with good control.

[0130] Thereafter, TiN is deposited by ALD or CVD on the source or drain region 151 along the internal shapes of the first opening 110A and the second opening 110B to a thickness of 5 nm to 10 nm, thereby forming the lower electrode 111. Note that TaN or the like can also be used as the material for forming the lower electrode 111.

[0131] 6E, a resist is applied onto the deposited lower electrode 111, and then etch-back is performed under conditions that provide approximately the same selectivity between the resist and the lower electrode 111, thereby causing the lower electrode 111 to retreat from the opening surface of the first opening 110A. As a result, the shoulder of the lower electrode 111 can be retreated, forming a recess, while leaving the lower electrode 111 on the bottom and side surfaces of the first opening 110A and the second opening 110B.

[0132] Next, as shown in FIG. 6F, a ferroelectric film 113 and an upper electrode 115 are deposited on the lower electrode 111 to form the capacitor 11.

[0133] Specifically, first, hafnium oxide (HfOx), which is a high dielectric material, is deposited by CVD or ALD to a thickness of 3 nm to 10 nm on the lower electrode 111 along the internal shape of the opening 110 to form the ferroelectric film 113. Note that the high dielectric material hafnium oxide (HfOx) is converted into a ferroelectric material by annealing in a later stage.

[0134] Instead of hafnium oxide, it is also possible to use high-dielectric materials such as zirconium oxide (ZrOx) or hafnium zirconium oxide (HfZrOx).In addition, it is also possible to convert these high-dielectric materials into ferroelectric materials by doping them with lanthanum (La), silicon (Si), gadolinium (Gd), or the like.

[0135] Thereafter, TiN is deposited on the ferroelectric film 113 by CVD, ALD, sputtering, or the like to a thickness of 5 nm to 20 nm so as to fill the first opening 110A and the second opening 110B, thereby forming the upper electrode 115. Note that TaN, or the like, can also be used as a material for forming the upper electrode 115. Subsequently, crystallization annealing is performed to convert HfOx constituting the ferroelectric film 113 into a ferroelectric material. Note that the crystallization annealing to convert HfOx into a ferroelectric material may be performed in this process or in another process. The temperature of the crystallization annealing can be arbitrarily changed as long as it is within the range of, for example, 500°C or less and within the heat resistance range of other components such as the transistor 21, NiSi, and wiring. Thereafter, CMP or the like is performed to remove excess ferroelectric film 113 and upper electrode 115 deposited on the planarization film 200. This completes the formation of the capacitor 11.

[0136] Subsequently, as shown in FIG. 6G, a first wiring layer 310 is formed on the contact 210, and a second wiring layer 320 is formed on the upper electrode 115 of the capacitor 11.

[0137] Specifically, by using a damascene structure using Cu as the wiring material, a first wiring layer 310 can be formed on the contact 210. The first wiring layer 310 functions as a bit line BL by extending in a first direction on the contact 210. Similarly, by using a damascene structure using Cu or the like as the wiring material, a second wiring layer 320 can be formed on the upper electrode 115. The second wiring layer 320 functions as a source line SL by extending in a first direction on the upper electrode 115 of the capacitor 11. The first wiring layer 310 and the second wiring layer 320 may be formed of Al or the like.

[0138] According to the above steps, the semiconductor memory device 10A according to this embodiment can be formed.

[0139] 3. Third Embodiment (3.1. Configuration example) Next, a semiconductor memory device according to a third embodiment of the present disclosure will be described with reference to Figures 7 and 8. Figure 7 is a schematic diagram showing a cross-sectional configuration of a semiconductor memory device 10B according to this embodiment. Figure 8 is a schematic diagram showing a planar layout of the semiconductor memory device 10B according to this embodiment.

[0140] As shown in FIG. 7, the semiconductor memory device 10B according to the third embodiment is an FeRAM that includes a capacitor 11 for storing information and a transistor 21 for controlling the selection and non-selection of the capacitor 11, similar to the semiconductor memory device 10 according to the first embodiment and the semiconductor memory device 10A according to the second embodiment.

[0141] Specifically, the transistor 21 is composed of a source or drain region 151 provided in a semiconductor substrate 100, and a gate electrode 130 provided on the semiconductor substrate 100. The drain side of the source or drain region 151 is electrically connected to a contact 210, and the source side of the source or drain region 151 is electrically connected to a capacitor 11 having a three-dimensional structure.

[0142] A cap layer 131 made of silicide, which is an alloy of cobalt (Co) or nickel (Ni) and silicon (Si), is provided on the surface of the gate electrode 130. Similarly, a contact region 152 made of silicide, which is an alloy of cobalt (Co) or nickel (Ni) and silicon (Si), is provided on the surface of the source or drain region 151.

[0143] The contact 210 is formed by embedding a barrier metal layer 210B and a conductive layer 210A inside an opening provided in a planarization film 200 made of, for example, silicon oxide (SiOx). The conductive layer 210A is made of tungsten (W), polysilicon (poly-Si), or the like, and electrically connects the contact region 152 and the first wiring layer 310. The barrier metal layer 210B is made of, for example, Ti, TiN, or Ru, and covers the surface of the conductive layer 210A to suppress interaction between the conductive layer 210A and the planarization film 200. Note that the contact 210 may be formed of any structure and material as long as it can form an ohmic electrical connection with the contact region 152 and the source or drain region 151.

[0144] The capacitor 11 is provided inside an opening provided in the planarization film 200 and the interlayer insulating film 201. In the semiconductor memory device 10B according to this embodiment, the capacitor 11 is provided at a different height from the contact 210. For example, the capacitor 11 may be provided so as to be higher than the contact 210 by the height of the interlayer insulating film 201.

[0145] The interlayer insulating film 201 is made of, for example, silicon oxide (SiOx) or silicon nitride (SiNx) and is formed on the planarizing film 200. The interlayer insulating film 201 is provided to prevent the contacts 210 from being exposed to cleaning solutions or the like and being damaged in a later step of forming the capacitors 11.

[0146] The capacitor 11 is formed by sequentially stacking a lower electrode 111 made of Ti or TiN or the like, a ferroelectric film 113, and an upper electrode 115 made of Ti or TiN or the like. The capacitor 11 is an embedded capacitor in which the lower electrode 111 and the upper electrode 115 are insulated via the ferroelectric film 113. In the capacitor 11, the area where the lower electrode 111 and the upper electrode 115 face each other in parallel, and the fringe components from the electrode ends of the lower electrode 111 and the upper electrode 115 form the area effective as capacitance.

[0147] The ferroelectric film 113 may be made of a high-dielectric material such as hafnium oxide (HfOx), zirconium oxide (ZrOx), or hafnium zirconium oxide (HfZrOx).The ferroelectric film 113 may also be made of a ferroelectric material converted by doping the above high-dielectric material with lanthanum (La), silicon (Si), gadolinium (Gd), or the like.

[0148] A first insulating layer 300 is provided on the interlayer insulating film 201. A first wiring layer 310 electrically connected to the contact 210 and a second wiring layer 320 electrically connected to the upper electrode 115 of the capacitor 11 are provided on the first insulating layer 300. The lower end of the second wiring layer 320 is provided so as to cover the ferroelectric film 113 and the upper electrode 115 of the capacitor 11 and not to come into contact with the lower electrode 111.

[0149] As shown in FIG. 8, the semiconductor memory device 10B includes an active region 150 provided on a semiconductor substrate 100, a gate electrode 130 functioning as a word line WL, a contact 210, a capacitor 11, a first wiring layer 310 functioning as a bit line BL, and a second wiring layer 320 functioning as a source line SL.

[0150] A first wiring layer 310 functioning as a bit line BL and a second wiring layer 320 functioning as a source line SL are provided extending in a first direction within the plane of the semiconductor substrate 100. Furthermore, a gate electrode 130 functioning as a word line WL is provided extending in a second direction perpendicular to the first direction. An active region 150 is a region where a transistor 21 is provided, and is provided extending in a third direction obliquely intersecting both the first and second directions. Furthermore, a contact 210 is provided at an intersection of the active region 150 and the first wiring layer 310, and a capacitor 11 is provided at an intersection of the active region 150 and the second wiring layer 320.

[0151] (3.2. Manufacturing method) Next, a method for manufacturing the semiconductor memory device 10B according to this embodiment will be described with reference to Figures 9A to 9I. Figures 9A to 9I are cross-sectional views illustrating a step in the method for manufacturing the semiconductor memory device 10B according to this embodiment.

[0152] First, as shown in FIG. 9A, a transistor 21 is formed on a semiconductor substrate 100 through known processes (for example, the processes shown in FIGS. 3A to 3D), and a planarization film 200 is deposited on the semiconductor substrate 100 so as to bury the transistor 21.

[0153] Subsequently, as shown in FIG. 9B, an opening is formed in the planarization film 200 in a region corresponding to one of the source and drain regions 151, and a contact 210 is formed inside the formed opening.

[0154] Next, as shown in FIG. 9C, an interlayer insulating film 201 is formed on the planarizing film 200. The interlayer insulating film 201 is made of, for example, silicon oxide (SiO x ) or silicon nitride (SiN x The interlayer insulating film 201 is provided to prevent the contact 210 from being exposed to cleaning liquid or the like and being damaged in the subsequent process of forming the capacitor 11.

[0155] Subsequently, as shown in FIG. 9D, an opening 110 for forming the capacitor 11 is formed in the planarization film 200 in a region corresponding to the other of the source or drain regions 151.

[0156] Here, it is desirable to clean the bottom of the opening 110 with a cleaning solution containing sulfuric acid or a cleaning solution containing ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2) in order to improve the contact resistance and the variation in contact resistance between the capacitor 11 and the transistor 21. The cleaning solution may damage the contact 210, but in the semiconductor memory device 10B according to this embodiment, the interlayer insulating film 201 is provided on the contact 210, so that damage to the contact 210 by the cleaning solution can be prevented.

[0157] Thereafter, as shown in FIG. 9E, a conductive material is deposited inside the opening 110 and on the interlayer insulating film 201 to form a lower electrode layer 111A.

[0158] 9F, a resist is applied onto the deposited lower electrode layer 111A, and then etched back under conditions that provide approximately the same selectivity between the resist and the lower electrode layer 111A, thereby recessing the lower electrode layer 111A from the opening surface of the opening 110. This leaves the lower electrode 111 on the bottom and side surfaces of the opening 110, and the shoulder of the lower electrode 111 is recessed to form a recess. As a result, the lower electrode 111 is formed so that its upper end is lower than the opening surface of the opening 110 in order to prevent a short circuit with the second wiring layer 320, which will be formed later.

[0159] Next, as shown in FIG. 9G, a ferroelectric film layer 113A and an upper electrode layer 115A are deposited on the lower electrode 111.

[0160] Subsequently, as shown in FIG. 9H, the ferroelectric film layer 113A and the upper electrode layer 115A other than those inside the opening 110 are removed by dry etching, polishing, or the like, thereby forming the ferroelectric film 113 and the upper electrode 115.

[0161] Then, as shown in FIG. 9I, a first insulating layer 300 is deposited on the interlayer insulating film 201, and then a first wiring layer 310 and a second wiring layer 320 are formed using a damascene structure or the like using copper (Cu) as the wiring material.

[0162] According to the above steps, the semiconductor memory device 10B according to this embodiment can be formed.

[0163] (3.3. Variations) (First Modification) Next, a first modification of the semiconductor memory device 10B according to this embodiment will be described with reference to Figures 10 to 11F. Figure 10 is a schematic diagram showing a cross-sectional configuration of the semiconductor memory device 10B according to the first modification.

[0164] 10, the semiconductor memory device 10B according to the first modification differs from the structure shown in FIG. 7 in that the ferroelectric film 113 and the upper electrode 115 are patterned and deposited on the interlayer insulating film 201. The upper electrode 115 is patterned into a wiring shape on the interlayer insulating film 201, so that it can function as a second wiring layer 320. Therefore, the semiconductor memory device 10B according to the first modification does not need to include the second wiring layer 320. In the semiconductor memory device 10B according to the first modification, not including the second wiring layer 320 makes it possible to prevent a short circuit between the lower electrode 111 and the second wiring layer 320.

[0165] A method for manufacturing semiconductor memory device 10B according to this modification will now be described with reference to Figures 11A to 11F. Figures 11A to 11F are cross-sectional views illustrating a step in the method for manufacturing semiconductor memory device 10B according to this modification.

[0166] First, as shown in FIG. 11A, a transistor 21 and a contact 210 are formed on a semiconductor substrate 100 in the same steps as those shown in FIGS. 9A to 9D, and an opening 110 is formed in a planarizing film 200 and an interlayer insulating film 201.

[0167] Subsequently, as shown in FIG. 11B, a conductive material is deposited inside the opening 110 and on the interlayer insulating film 201 to form a lower electrode layer 111A.

[0168] 11C, a resist is applied onto the deposited lower electrode layer 111A, and then etched back under conditions that provide approximately the same selectivity between the resist and the lower electrode layer 111A, thereby recessing the lower electrode layer 111A from the opening surface of the opening 110. This leaves the lower electrode 111 on the bottom and side surfaces of the opening 110, and recesses the shoulders of the lower electrode 111, forming a recess. In this modification, the lower electrode 111 may be formed so that its upper end is higher than the opening surface of the opening 110.

[0169] Subsequently, as shown in FIG. 11D, a ferroelectric film layer 113A and an upper electrode layer 115A are deposited on the lower electrode 111.

[0170] Subsequently, as shown in FIG. 11E, the ferroelectric film layer 113A and the upper electrode layer 115A on the interlayer insulating film 201 are patterned into wiring shapes, thereby forming the ferroelectric film 113 and the upper electrode 115.

[0171] Thereafter, as shown in FIG. 11F, a first insulating layer 300 is deposited on the interlayer insulating film 201, and then a first wiring layer 310 is formed using a damascene structure or the like using copper (Cu) as the wiring material.

[0172] According to the above steps, the semiconductor memory device 10B according to this modification can be formed.

[0173] (Second Modification) A second modification of the semiconductor memory device 10B according to this embodiment will now be described with reference to Fig. 12. Fig. 12 is a schematic diagram showing a cross-sectional configuration of the semiconductor memory device 10B according to the second modification.

[0174] 12, the semiconductor memory device 10B according to the second modification differs from the structure shown in FIG. 7 in that the lower electrode 111, the ferroelectric film 113, and the upper electrode 115 are deposited on an interlayer insulating film 201. The lower electrode 111, the ferroelectric film 113, and the upper electrode 115 on the interlayer insulating film 201 are patterned, and a second wiring layer 320 is provided on the upper electrode 115. The semiconductor memory device 10B according to the second modification can be formed by simultaneously etching the lower electrode 111, the ferroelectric film 113, and the upper electrode 115 deposited on the interlayer insulating film 201.

[0175] (Third Modification) A third modification of the semiconductor memory device 10B according to this embodiment will now be described with reference to Fig. 13. Fig. 13 is a schematic diagram showing a cross-sectional configuration of the semiconductor memory device 10B according to the third modification.

[0176] As shown in FIG. 13, the semiconductor memory device 10B according to the third modification differs from the structure shown in FIG. 7 in that the contact region 152 is not provided in the source or drain region 151 electrically connected to the capacitor 11. The semiconductor memory device 10B according to the third modification does not have a contact region 152 formed in the source or drain region 151 electrically connected to the capacitor 11. x ) film or the like, and selectively silicidating it.

[0177] 4. Fourth Embodiment (4.1. Configuration example) Next, a semiconductor memory device according to a fourth embodiment of the present disclosure will be described with reference to Fig. 14. Fig. 14 is a schematic diagram showing the planar configuration and cross-sectional configuration of a semiconductor memory device 10C according to this embodiment.

[0178] In the plan view at the upper left of FIG. 14, the planarization film 200 formed over the entire surface of the semiconductor substrate 100 and the first to third insulating layers 300, 400, and 600 are omitted to clarify the arrangement of each component. Each cross-sectional view in FIG. 14 shows a cross section taken along line BB, line CC, or line DD shown in the plan view at the upper left. Line BB and line CC represent the cross-sectional configuration of a memory cell 10CC in the semiconductor memory device 10C, while line DD represents the cross-sectional configuration of a peripheral region of the semiconductor memory device 10C. The memory cell 10CC here refers to a region in which a capacitor 51, which will be described later, is provided. The peripheral region refers to a region surrounding a memory cell region in which a plurality of memory cells 10CC are provided. The peripheral region of the semiconductor memory device 10C may include, for example, a logic circuit.

[0179] 14, the semiconductor memory device 10C according to the fourth embodiment differs from the semiconductor memory device 10 according to the first embodiment in that it has a capacitor 51 instead of the capacitor 11 (see FIG. 1) of the first embodiment. Hereinafter, the same reference numerals will be used for components that are substantially the same as those of the semiconductor memory device 10 according to the first embodiment, and descriptions thereof will be omitted as appropriate.

[0180] The semiconductor memory device 10C is an FeRAM including a capacitor 51 that stores information and a transistor 21 that controls selection and non-selection of the capacitor 51. In addition to the capacitor 51 and the transistor 21, the semiconductor memory device 10C includes a semiconductor substrate 100, a planarization film 200, a contact 210, a first wiring layer 310, a first insulating layer 300, a second insulating layer 400, and a third insulating layer 600. The semiconductor substrate 100 has a main surface 100S.

[0181] The planarization film 200 serving as an interlayer insulating film is provided so as to cover the transistor 21 and the main surface 100S of the semiconductor substrate 100.

[0182] The transistor 21 is composed of a source or drain region 151 provided in the semiconductor substrate 100, and a gate electrode 130 provided on the semiconductor substrate 100. The drain side of the source or drain region 151 is electrically connected to a contact 210, and the source side of the source or drain region 151 is electrically connected to a capacitor 51 having a three-dimensional structure via the contact 210 and a first wiring layer 310.

[0183] The contact 210 is made of a conductive material and is provided so as to penetrate the planarization film 200. Specifically, the contact 210 is provided on the other of the source or drain regions 151, and electrically connects the drain side of the source or drain region 151 to the first wiring layer 310, which is the bit line BL.

[0184] The first wiring layer 310 is provided on the opposite side of the contact 210 from the transistor 21. The first wiring layer 310 is electrically connected to the contact 210. The first wiring layer 310 is made of a conductive material and provided on the planarization film 200. Specifically, the first wiring layer 310 is provided on the contact 210 as a wiring extending in a first direction perpendicular to a second direction in which the gate electrode 130 (word line WL) extends. The first wiring layer 310 functions as a bit line BL by being electrically connected to the drain side of the source or drain region 151 via the contact 210. In addition, a capacitor 51 is provided on the first wiring layer 310, i.e., on the opposite side of the contact 210 from the first wiring layer 310.

[0185] The first insulating layer 300 embeds the capacitor 51 and the first wiring layer 310. The first insulating layer 300 is provided on the planarization film 200, spreading over the entire surface of the semiconductor substrate 100. A via contact 311 and an upper wiring layer 312 are stacked on the first wiring layer 310. The via contact 311 and the upper wiring layer 312 are also embedded in the first insulating layer 300. However, the upper wiring layer 312 is exposed on the upper surface of the first insulating layer 300.

[0186] The via contact 311 is made of a conductive material and is in contact with the first wiring layer 310. The via contact 311 electrically connects the first wiring layer 310 and the upper wiring layer 312. The via contact 311 may be made of a metal material such as aluminum (Al), or may be made of a copper (Cu) damascene structure.

[0187] The upper wiring layer 312 is made of a conductive material and is provided on the via contact 311. The upper wiring layer 312 may be made of a metal material such as aluminum (Al), or may have a copper (Cu) damascene structure. The upper wiring layer 312 may be formed simultaneously with or shared with wiring for other circuits provided in the logic region or the like.

[0188] The first wiring layer 310 , the via contact 311 and the upper wiring layer 312 are provided so as to penetrate the first insulating layer 300 .

[0189] The second insulating layer 400 extends along the main surface 100S so as to entirely cover the first insulating layer 300. The second insulating layer 400 may be formed of an insulating oxynitride such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON). A via contact 411 and an upper wiring layer 412 are embedded in the second insulating layer 400. The via contact 411 and the upper wiring layer 412 are stacked in this order on the upper wiring layer 312. The upper wiring layer 412 is exposed on the upper surface of the second insulating layer 400.

[0190] The via contact 411 is made of a conductive material and is in contact with the upper wiring layer 312. The material of the via contact 411 can be, for example, the same as the material of the via contact 311. The upper wiring layer 412 is made of a conductive material and is provided on the via contact 411. The material of the upper wiring layer 412 can be, for example, the same as the material of the upper wiring layer 312. The upper wiring layer 412 may be formed simultaneously with or shared with wiring of other circuits provided in the logic region or the like.

[0191] The first insulating layer 300 and the second insulating layer 400 have openings 410 at positions corresponding to the first wiring layer 310 in the stacking direction perpendicular to the main surface 100S. The openings 410 are recesses that reach the first wiring layer 310 in the stacking direction. The openings 410 have a structure in which a lower portion 410L located above the first wiring layer 310 communicates with an upper portion 410U located above the lower portion 410L. For example, the area occupied by the lower portion 410L along the main surface 100S is smaller than the area occupied by the upper portion 410U along the main surface 100S. The first insulating layer 300 and the second insulating layer 400 extend to the peripheral region of the semiconductor memory device 10C. The first insulating layer 300 and the second insulating layer 400 also extend to a circuit region including a logic circuit provided in the peripheral region of the semiconductor memory device 10C. The capacitor 51 is embedded in the first insulating layer 300 and the second insulating layer 400 which also extend into the circuit region.

[0192] The capacitor 51 is provided to fill the opening 410. The capacitor 51 is located above the contact 210 and the first wiring layer 310. The capacitor 51 includes a lower electrode 511 provided along the inner surface of the opening 410, a ferroelectric film 513 provided on the lower electrode 511 along the opening 410, and an upper electrode 515 provided on the ferroelectric film 513. The lower electrode 511 is electrically connected to a source or drain region 151 (e.g., a source) of the transistor 21 via the first wiring layer 310 or the like. The upper electrode 515 is electrically connected to a second wiring layer 612 (described later) serving as a source line SL. Here, the area of ​​the upper electrode 515 along the main surface 100S is larger than the area of ​​a connection portion between the lower electrode 511 and the first wiring layer 310 along the main surface 100S.

[0193] The third insulating layer 600 extends along the main surface 100S so as to entirely cover the second insulating layer 400. The third insulating layer 600 may be formed of an insulating oxynitride such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON). A via contact 611 and a second wiring layer 612 are embedded in the third insulating layer 600. The via contact 611 and the second wiring layer 612 are stacked in this order on the upper electrode 515 and the upper wiring layer 412, respectively. The second wiring layer 612 is exposed on the upper surface of the third insulating layer 600.

[0194] The via contact 611 is made of a conductive material and is in contact with the upper wiring layer 412. The material of the via contact 611 can be, for example, the same as the material of the via contact 311. The second wiring layer 612 is made of a conductive material and is provided on the via contact 611.

[0195] The second wiring layer 612 is electrically connected to the upper electrode 515 of the capacitor 51 through the via contact 611. The second wiring layer 612 is provided on the upper electrode 515 of the capacitor 51 as a wiring extending in the first direction similar to the first wiring layer 310. The second wiring layer 612 functions as a source line SL by being electrically connected to the upper electrode 515. The second wiring layer 612 may be made of a metal material such as aluminum (Al), or may be made of a copper (Cu) damascene structure or a dual damascene structure.

[0196] In the semiconductor memory device 10C having the above structure, the capacitor 51 is provided above the first wiring layer 310, i.e., on the opposite side of the transistor 21 from the first wiring layer 310. This allows the area and thickness of the capacitor 51 to be larger than when, for example, a capacitor is provided in the gap between the first wiring layers 310. In other words, the capacitance of the capacitor 51 can be increased. Therefore, the semiconductor memory device 10C can ensure a signal with a sufficient margin for its operation. Furthermore, the degree of freedom in designing the planar shape of the capacitor 51 is improved.

[0197] (4.2. Manufacturing method) Next, a method for manufacturing the semiconductor memory device 10C according to this embodiment will be described with reference to Figures 15A to 15I. Figures 15A to 15I are schematic views illustrating one step in the method for manufacturing the semiconductor memory device 10C.

[0198] 15A to 15I also omit illustration of layers provided over the entire surface of semiconductor substrate 100, as in Fig. 14. Each of the cross-sectional views in Fig. 15A to 15I shows a cross section taken along line AA, line BB, line CC, or line DD shown in the top left plan view.

[0199] First, as shown in FIG. 15A, an element isolation layer 105 is formed on a semiconductor substrate 100 in the same manner as in the first embodiment, and an active region 150 in which a transistor 21 will be formed in a later step is formed.

[0200] Next, as shown in FIG. 15B, after depositing the gate insulating film 140 in the same manner as in the first embodiment, the gate electrode 130 is formed on the gate insulating film 140.

[0201] Next, as shown in FIG. 15C, sidewall insulating films 132 are formed on both side surfaces of the gate electrode 130, and source or drain regions 151 are formed in the active region 150 of the semiconductor substrate 100, in the same manner as in the first embodiment.

[0202] Subsequently, as shown in FIG. 15D, a planarization film 200 is formed over the entire surface of the semiconductor substrate 100 so as to bury the transistor 21, in the same manner as in the first embodiment.

[0203] Next, as shown in FIG. 15E, contacts 210 are formed to electrically connect to the other of the source or drain regions 151 and the gate electrode 130. After that, a first wiring layer 310 is formed on the contacts 210. The first wiring layer 310 can become bit lines BL by extending in a first direction on the contacts 210. The first wiring layer 310 can also be used as wiring that constitutes a logic circuit in the peripheral region. Furthermore, the first wiring layer 310 provided in the memory cell region electrically connects the contacts 210 and the lower electrodes 511 of the capacitors 51 on the BB lines.

[0204] Next, as shown in FIG. 15F, a first insulating layer 300 is formed to cover the planarizing film 200 and the first wiring layer 310.

[0205] Specifically, the first insulating layer 300 is formed by depositing an SiO2 film to a thickness of 100 nm to 500 nm on the planarization film 200 using CVD or the like so as to bury the first wiring layer 310. When forming the first insulating layer 300, the deposited SiO2 film may be planarized by, for example, CMP. The first insulating layer 300 may be formed of a low-dielectric-constant material (e.g., SiOC containing carbon) having a dielectric constant lower than that of SiO2. Note that, before forming the first insulating layer 300, a liner layer made of SiNx may be formed on the planarization film 200. For example, the liner layer may be formed by depositing SiNx to a thickness of 10 nm to 50 nm using plasma CVD.

[0206] After forming the first insulating layer 300, a via contact 311 and an upper wiring layer 312 are formed on the first wiring layer 310. Specifically, the via contact 311 and the upper wiring layer 312 can be formed by using a damascene structure using Cu or the like as a wiring material. The via contact 311 and the upper wiring layer 312 may also be formed of Al or the like.

[0207] Next, as shown in FIG. 15G, a second insulating layer 400 is formed to cover the first insulating layer 300.

[0208] Specifically, a SiO2 film is deposited on the first insulating layer 300 using CVD or the like to a thickness of 100 nm to 500 nm to form the second insulating layer 400. When forming the second insulating layer 400, the deposited SiO2 film may be planarized by, for example, CMP. The second insulating layer 400 may be formed of a low-dielectric-constant material (e.g., SiOC containing carbon) having a dielectric constant lower than that of SiO2. Note that, before forming the second insulating layer 400, a liner layer made of SiNx may be formed on the first insulating layer 300. For example, the liner layer may be formed by depositing SiNx to a thickness of 10 nm to 50 nm using plasma CVD.

[0209] After forming the second insulating layer 400, the via contact 411 and the upper wiring layer 412 are formed on the upper wiring layer 312. Specifically, the via contact 411 and the upper wiring layer 412 can be formed by using a damascene structure using Cu or the like as the wiring material. The via contact 411 and the upper wiring layer 412 may also be formed of Al or the like.

[0210] Next, as shown in FIG. 15H, an opening 410 is formed to expose the first wiring layer 310 in the memory cell region.

[0211] Specifically, the opening 410 is formed by selectively digging down the first insulating layer 300 and the second insulating layer 400 using anisotropic etching with a lithographically patterned resist as a mask. First, the lower portion 410L of the opening 410 is formed narrower than the upper portion 410U of the opening 410, e.g., 60 nm wide. After the lower portion 410L is formed, the upper portion 410U is formed in the same manner as the lower portion 410L. The width of the upper portion 410U is wider than the width of the lower portion 410L, e.g., 100 nm to 150 nm wide. If the aspect ratios of the lower portion 410L and the upper portion 410U are both approximately 20 or less, the etching to form the lower portion 410L and the upper portion 410U and the subsequent deposition to fill the opening 410 can be performed without any problems. The anisotropic etching can be performed using, for example, a fluorocarbon-based gas. Furthermore, the use of the liner layer described above allows for the etching to be stopped with good control.

[0212] Next, as shown in FIG. 15I, capacitor 51 is formed inside opening 410.

[0213] Specifically, first, TiN is deposited on the exposed first wiring layer 310 along the inner shape of the opening 410 to a thickness of 5 nm to 10 nm using sputtering by ALD, CVD, or IMP, thereby forming the lower electrode 511.

[0214] Next, hafnium oxide (HfOx), a high dielectric material, is deposited on the lower electrode 511 along the inner shape of the opening 410 to a thickness of 3 nm to 10 nm by CVD or ALD to form a ferroelectric film 513. Note that hafnium oxide (HfOx), a high dielectric material, is converted into a ferroelectric material by annealing in a later stage.

[0215] Instead of hafnium oxide, it is also possible to use high-dielectric materials such as zirconium oxide (ZrOx) or hafnium zirconium oxide (HfZrOx).In addition, it is also possible to convert these high-dielectric materials into ferroelectric materials by doping them with lanthanum (La), silicon (Si), gadolinium (Gd), or the like.

[0216] Thereafter, TiN is deposited on the ferroelectric film 513 by CVD, ALD, sputtering, or the like to a thickness of 5 nm to 20 nm so as to fill the opening 410, thereby forming the upper electrode 515. Note that TaN, or the like, can also be used as a material for forming the upper electrode 515. Subsequently, crystallization annealing is performed to convert HfOx, which constitutes the ferroelectric film 513, into a ferroelectric material. Note that the crystallization annealing to convert HfOx into a ferroelectric material may be performed in this process or in another process. The temperature of the crystallization annealing can be arbitrarily changed, for example, within a range of 500°C or less and within the heat resistance range of other components such as the transistor 21, NiSi, and wiring. Thereafter, CMP or the like is performed to remove excess ferroelectric film 513 and upper electrode 515 deposited on the second insulating layer 400. This completes the formation of the capacitor 51.

[0217] Subsequently, as shown in FIG. 14, a third insulating layer 600 is formed to cover the second insulating layer 400.

[0218] Specifically, a SiO2 film is deposited on the second insulating layer 400 using CVD or the like to a thickness of 100 nm to 500 nm to form the third insulating layer 600. When forming the third insulating layer 600, the deposited SiO2 film may be planarized by, for example, CMP. The third insulating layer 600 may be formed of a low-dielectric-constant material (e.g., SiOC containing carbon) having a dielectric constant lower than that of SiO2. Note that, before forming the third insulating layer 600, a liner layer made of SiNx may be formed on the second insulating layer 400. For example, the liner layer may be formed by depositing SiNx to a thickness of 10 nm to 50 nm using plasma CVD.

[0219] After forming the third insulating layer 600, a via contact 611 and a second wiring layer 612 are formed on the upper electrode 515 and the upper wiring layer 412, respectively. Specifically, the via contact 611 and the second wiring layer 612 can be formed by using a damascene structure using Cu or the like as a wiring material. The via contact 611 and the second wiring layer 612 may also be formed of Al or the like. Furthermore, the second wiring layer 612 can become a source line SL by extending, for example, in a first direction. The second wiring layer 612 can also be used as wiring that constitutes a logic circuit in the peripheral region.

[0220] According to the above steps, the semiconductor memory device 10C according to this embodiment can be formed.

[0221] (4.3. Example of operation) Next, the write and read operations of the semiconductor memory device 10C according to this embodiment will be described. Figure 16 is a cross-sectional view schematically showing a cross section of the semiconductor memory device 10C according to this embodiment taken along the active region 150.

[0222] 16, the semiconductor memory device 10C includes a transistor 21 and a capacitor 51 connected to the source side of a source or drain region 151 of the transistor 21. The semiconductor memory device 10C is driven by a word line WL connected to the gate electrode 130 of the transistor 21, a bit line BL connected to the drain side of the source or drain region 151 of the transistor 21 via a contact 210, and a source line SL connected to the capacitor 51.

[0223] The write and read operations of the semiconductor memory device 10C are performed in the same manner as the write and read operations of the semiconductor memory device 10 of the first embodiment. Therefore, the voltages shown in Table 1 above are applied to SWL, SBL, SSL, Well, UWL, UBL, and USL shown in FIG.

[0224] Note that Vth in Table 1 is the threshold voltage for turning on the channel of transistor 21. Similarly, Vw in Table 1 is the voltage capable of reversing the polarization state of capacitor 51. Also, SWL, SBL, and SSL in Table 1 represent the word line WL, bit line BL, and source line SL of a selected memory cell, respectively. Furthermore, UWL, UBL, and USL in Table 1 represent the word line WL, bit line BL, and source line SL of an unselected memory cell, respectively. Well in Table 1 represents the active region 150 of the semiconductor substrate 100.

[0225] When writing information of, for example, "1" to a selected memory cell 10CC of the semiconductor memory device 10C, Vw+Vth is applied to the word line WL connected to the selected memory cell 10CC, Vw is applied to the bit line BL, 0 V is applied to the source line SL, and 0 V is applied to the active region 150 of the semiconductor substrate 100. In addition, the word line WL, bit line BL, and source line SL connected to unselected memory cells 10CC of the semiconductor memory device 10C are each set to 0 V.

[0226] Furthermore, when writing information "0" to a selected memory cell 10CC of the semiconductor memory device 10C, Vw+Vth is applied to the word line WL connected to the selected memory cell 10CC, and Vw is applied to the source line SL. The bit line BL is set to 0V, and the active region 150 of the semiconductor substrate 100 is set to 0V. The word line WL, bit line BL, and source line SL connected to unselected memory cells 10CC of the semiconductor memory device 10C are each set to 0V.

[0227] Reading information from the memory cell 10CC of the semiconductor memory device 10C is performed by utilizing the fact that the displacement current that occurs when writing predetermined information (e.g., "1") to the memory cell 10CC changes based on the information ("0" or "1") stored before writing. The details are the same as for reading information from the memory cell of the semiconductor memory device 10.

[0228] <5. Fifth Embodiment> (5.1. Configuration example) Next, a semiconductor memory device according to a fifth embodiment of the present disclosure will be described with reference to Fig. 17. Fig. 17 is a schematic diagram showing the planar configuration and cross-sectional configuration of a semiconductor memory device 10D according to this embodiment.

[0229] In the plan view at the upper left of FIG. 17, the planarization film 200 formed over the entire surface of the semiconductor substrate 100 and the first to third insulating layers 300, 400, and 600 are omitted to clarify the arrangement of each component. Each cross-sectional view in FIG. 17 shows a cross section taken along line BB, line CC, or line DD shown in the plan view at the upper left. Line BB and line CC represent the cross-sectional configuration of a memory cell 10DD in the semiconductor memory device 10D, while line DD represents the cross-sectional configuration of a peripheral region of the semiconductor memory device 10D. The memory cell 10DD here refers to the region in which a capacitor 71, described below, is provided. The peripheral region refers to the region surrounding the memory cell region in which a plurality of memory cells 10DD are provided. The peripheral region of the semiconductor memory device 10D may include, for example, a logic circuit.

[0230] 17, the semiconductor memory device 10D according to the fifth embodiment differs from the semiconductor memory device 10C according to the fourth embodiment in that it has a capacitor 71 instead of the capacitor 51. Hereinafter, the same reference numerals will be used for components that are substantially the same as those in the semiconductor memory device 10C according to the fourth embodiment, and descriptions thereof will be omitted as appropriate.

[0231] The semiconductor memory device 10D is an FeRAM including a capacitor 71 for storing information and a transistor 21 for controlling selection and non-selection of the capacitor 71.

[0232] Similar to the capacitor 51, the capacitor 71 is provided so as to fill the opening 410. The capacitor 71 includes a lower electrode 711 provided along the inner surface of the opening 410, a ferroelectric film 713 provided on the lower electrode 711 along the opening 410, and an upper electrode 715 provided on the ferroelectric film 713. The lower electrode 711 is electrically connected to the source or drain region 151 (e.g., the source) of the transistor 21 via the first wiring layer 310 or the like. The upper electrode 715 is electrically connected to the second wiring layer 612 serving as the source line SL.

[0233] In the semiconductor memory device 10C of the third embodiment, the upper end of the lower electrode 511 reaches the upper surface of the second insulating layer 400, i.e., the surface opposite the semiconductor substrate 100. In contrast, in the semiconductor memory device 10D of the present embodiment, the upper end of the lower electrode 711 is located below the upper surface of the second insulating layer 400. Also, in the semiconductor memory device 10C of the third embodiment, the outer edge of the upper electrode 515 along the main surface 100S is located in a position recessed inward from the inner edge of the opening 410. Therefore, the area of ​​the upper electrode 515 along the main surface 100S is smaller than the area of ​​the opening 410 along the main surface 100S. In contrast, in the semiconductor memory device 10D of the present embodiment, the outer edge of the upper electrode 715 extends in the in-plane direction along the main surface 100S of the semiconductor substrate 100 until it contacts the inner edge of the opening 410. That is, in the in-plane direction along the main surface 100S of the semiconductor substrate 100, the shape and area of ​​the upper electrode 715 are substantially the same as the shape and area of ​​the opening 410. Therefore, the area of ​​the upper electrode 715 along the main surface 100S is substantially equal to the area of ​​the lower electrode 711 along the main surface 100S.

[0234] In the semiconductor memory device 10D having the above structure, similar to the semiconductor memory device 10C, the capacitor 71 is provided on the opposite side of the first wiring layer 310 from the transistor 21. This allows the area and thickness of the capacitor 71 to be larger than when, for example, a capacitor is provided in the gap between the first wiring layers 310. In other words, the capacitance of the capacitor 71 can be increased. Therefore, the semiconductor memory device 10D can ensure a signal with a sufficient margin for its operation. Furthermore, the degree of freedom in designing the planar shape of the capacitor 71 is improved.

[0235] Furthermore, in the semiconductor memory device 10D, the area of ​​the upper electrode 715 along the main surface 100S is made substantially equal to the area of ​​the lower electrode 711 along the main surface 100S. Therefore, compared to the semiconductor memory device 10C, for example, in the manufacturing process, when forming the via contact 611 connected to the upper electrode 715, it is easier to align the upper electrode 715 with the via contact 611. This can improve the manufacturing yield.

[0236] (5.2. Manufacturing method) Next, a method for manufacturing the semiconductor memory device 10D according to this embodiment will be described with reference to Figures 18A to 18C. Figures 18A to 18C are schematic views illustrating one step in the method for manufacturing the semiconductor memory device 10D.

[0237] 18A to 18C, similarly to Fig. 17, layers provided over the entire surface of semiconductor substrate 100 are omitted. Each of the cross-sectional views in Fig. 18A to 18C shows a cross section taken along line BB, line CC, or line DD shown in the top left plan view.

[0238] First, the opening 410 is formed in the same manner as in the process shown in Figures 15A to 15H of the fourth embodiment. Next, as shown in Figure 18A, a lower electrode film 711Z is formed inside the opening 410. Specifically, the lower electrode film 711Z is formed by depositing TiN to a thickness of 5 nm to 10 nm on the exposed first wiring layer 310 along the internal shape of the opening 410 using sputtering by ALD, CVD, or IMP.

[0239] Thereafter, as shown in FIG. 18B, the lower electrode 711 is formed. Specifically, a resist is applied onto the deposited lower electrode film 711Z, and etch-back is performed under conditions that provide approximately the same selectivity between the resist and the lower electrode film 711Z. By doing so, the upper end of the lower electrode film 711Z is recessed from the upper surface of the second insulating layer 400. This results in a lower electrode 711 that covers the bottom and side surfaces of the opening 410 and whose upper end is recessed from the upper surface of the second insulating layer 400.

[0240] 18C, hafnium oxide (HfOx), a high dielectric material, is deposited on the lower electrode 711 along the inner shape of the opening 410 to a thickness of 3 nm to 10 nm by CVD or ALD to form a ferroelectric film 713. Note that hafnium oxide (HfOx), a high dielectric material, is converted into a ferroelectric material by annealing in a later stage.

[0241] Instead of hafnium oxide, it is also possible to use high-dielectric materials such as zirconium oxide (ZrOx) or hafnium zirconium oxide (HfZrOx).In addition, it is also possible to convert these high-dielectric materials into ferroelectric materials by doping them with lanthanum (La), silicon (Si), gadolinium (Gd), or the like.

[0242] Thereafter, TiN is deposited on the ferroelectric film 713 by CVD, ALD, sputtering, or the like to a thickness of 5 nm to 20 nm so as to fill the opening 410, thereby forming the upper electrode 715. Note that TaN, or the like, can also be used as a material for forming the upper electrode 715. Subsequently, crystallization annealing is performed to convert HfOx, which constitutes the ferroelectric film 713, into a ferroelectric material. Note that the crystallization annealing to convert HfOx into a ferroelectric material may be performed in this process or in another process. The temperature of the crystallization annealing can be arbitrarily changed, for example, within a range of 500°C or less and within the heat resistance range of other components such as the transistor 21, NiSi, and wiring. Thereafter, CMP or the like is performed to remove excess ferroelectric film 713 and upper electrode 715 deposited on the second insulating layer 400. This completes the formation of the capacitor 71.

[0243] Subsequently, as shown in FIG. 17, a third insulating layer 600 is formed to cover the second insulating layer 400.

[0244] After forming the third insulating layer 600, a via contact 611 and a second wiring layer 612 are formed on the upper electrode 715 and the upper wiring layer 412. Specifically, the via contact 611 and the second wiring layer 612 can be formed by using a damascene structure using Cu or the like as a wiring material. The via contact 611 and the second wiring layer 612 may also be formed of Al or the like. Furthermore, the second wiring layer 612 can become a source line SL by extending, for example, in a first direction. The second wiring layer 612 can also be used as wiring that constitutes a logic circuit in the peripheral region.

[0245] According to the above steps, the semiconductor memory device 10D according to this embodiment can be formed.

[0246] 6. Sixth Embodiment (6.1. Configuration example) Next, a semiconductor memory device according to a sixth embodiment of the present disclosure will be described with reference to Fig. 19. Fig. 19 is a schematic diagram showing the planar configuration and cross-sectional configuration of a semiconductor memory device 10E according to this embodiment.

[0247] In the plan view at the upper left of FIG. 19, the planarization film 200 formed over the entire surface of the semiconductor substrate 100 and the first to third insulating layers 300, 400, and 600 are omitted to clarify the arrangement of each component. Each cross-sectional view in FIG. 19 shows a cross section taken along line BB, line CC, or line DD shown in the plan view at the upper left. Line BB and line CC represent the cross-sectional configuration of a memory cell 10EE in the semiconductor memory device 10E, and line DD represents the cross-sectional configuration of a peripheral region in the semiconductor memory device 10E. The memory cell 10EE here refers to a region in which a capacitor 81, which will be described later, is provided. The peripheral region refers to a region surrounding a memory cell region in which a plurality of memory cells 10EE are provided. The peripheral region of the semiconductor memory device 10E may include, for example, a logic circuit.

[0248] 19, the semiconductor memory device 10E according to the sixth embodiment differs from the semiconductor memory device 10D according to the fourth embodiment in that it has a capacitor 81 instead of the capacitor 71. Hereinafter, the same reference numerals will be used for components that are substantially the same as those in the semiconductor memory device 10D according to the fourth embodiment, and descriptions thereof will be omitted as appropriate.

[0249] The semiconductor memory device 10E is an FeRAM including a capacitor 81 for storing information and a transistor 21 for controlling selection and non-selection of the capacitor 81.

[0250] Similar to the capacitor 71, the capacitor 81 is provided so as to fill the opening 410. The capacitor 81 includes a lower electrode 811 provided along the inner surface of the opening 410, a ferroelectric film 813 provided on the lower electrode 811 along the opening 410, and an upper electrode 815 provided on the ferroelectric film 813. The lower electrode 811 is electrically connected to the source or drain region 151 (e.g., the source) of the transistor 21 via the first wiring layer 310 or the like. The upper electrode 815 is electrically connected to the second wiring layer 612 serving as the source line SL.

[0251] In the semiconductor memory device 10D of the fourth embodiment, the upper surface of the upper electrode 715 is substantially flush with the upper surface of the second insulating layer 400. In contrast, in the semiconductor memory device 10E of the present embodiment, the upper electrode 815 protrudes above the upper surface of the second insulating layer 400, that is, toward the opposite side from the semiconductor substrate 100. This increases the options for the formation method of the capacitor 81. Therefore, by selecting an appropriate formation method, it is possible to improve the manufacturing yield.

[0252] In the semiconductor memory device 10E having the above structure, the capacitance of the capacitor 81 can be made larger than the capacitance of the capacitor 71 in the semiconductor memory device 10D. Therefore, the semiconductor memory device 10E can ensure a signal with a sufficient margin for its operation. While the semiconductor memory device 10E in FIG. 19 illustrates a case where the area of ​​the upper electrode 815 along the main surface 100S is substantially equal to the area of ​​the lower electrode 811 along the main surface 100S, the area of ​​the upper electrode 815 along the main surface 100S can also be made larger than the area of ​​the lower electrode 811 along the main surface 100S.

[0253] (6.2. Manufacturing method) Next, a method for manufacturing the semiconductor memory device 10E according to this embodiment will be described with reference to Figures 20A and 20B. Figures 20A and 20B are schematic views illustrating one step in the method for manufacturing the semiconductor memory device 10E.

[0254] 20A and 20B, layers provided over the entire surface of semiconductor substrate 100 are omitted, as in Fig. 19. The cross-sectional views in Fig. 20A and 20B show cross sections taken along line BB, line CC, or line DD shown in the top left plan view.

[0255] First, the opening 410 is formed in the same manner as in the steps shown in FIGS. 15A to 15H of the fourth embodiment.

[0256] 20A, a lower electrode film 811Z is formed so as to entirely cover the inside of the opening 410 and the upper surface of the second insulating layer 400. Specifically, the lower electrode film 811Z is formed by depositing TiN to a thickness of 5 nm to 10 nm on the exposed first wiring layer 310 along the internal shape of the opening 410 using sputtering by ALD, CVD, or IMP. The lower electrode film 811Z is formed uniformly so as to also cover the upper surface of the second insulating layer 400.

[0257] Subsequently, hafnium oxide (HfOx), a high dielectric material, is deposited on the lower electrode film 811Z along the inner shape of the opening 410 to a thickness of 3 nm to 10 nm by CVD or ALD to form a ferroelectric film 813Z. Note that the high dielectric material hafnium oxide (HfOx) is converted into a ferroelectric material by annealing in a later stage. The ferroelectric film 813Z is formed uniformly so as to also cover the lower electrode film 811Z that covers the upper surface of the second insulating layer 400.

[0258] Thereafter, TiN is deposited on the ferroelectric film 813Z by CVD, ALD, sputtering, or the like to a thickness of 5 nm to 20 nm so as to fill the opening 410, thereby forming an upper electrode film 815Z. Note that TaN, or the like, can also be used as a material for forming the upper electrode film 815Z. Subsequently, crystallization annealing is performed to convert HfOx constituting the ferroelectric film 813Z into a ferroelectric material. Note that the crystallization annealing to convert HfOx into a ferroelectric material may be performed in this process or in another process. The temperature of the crystallization annealing can be changed arbitrarily, for example, within a range of 500°C or less and within the heat resistance range of other components such as the transistor 21, NiSi, and wiring.

[0259] Thereafter, using a resist patterned by lithography as a mask, anisotropic etching is performed on the upper electrode film 815Z, the ferroelectric film 813Z, and the lower electrode film 811Z in this order. As a result, as shown in Fig. 20B, for example, a plurality of capacitors 81 each having an upper electrode 815, a ferroelectric film 813, and a lower electrode 811 are formed. Either dry etching or wet etching can be used as the anisotropic etching.

[0260] 7. Seventh Embodiment (7.1. Configuration example) Next, a semiconductor memory device according to a seventh embodiment of the present disclosure will be described with reference to Fig. 21. Fig. 21 is a schematic diagram showing the planar configuration and cross-sectional configuration of a semiconductor memory device 10F according to this embodiment.

[0261] In the plan view at the upper left of FIG. 21, the planarization film 200 formed over the entire surface of the semiconductor substrate 100 and the first to third insulating layers 300, 400, and 600 are omitted to clarify the arrangement of each component. Each cross-sectional view in FIG. 21 shows a cross section taken along line BB, line CC, or line DD shown in the plan view at the upper left. Line BB and line CC represent the cross-sectional configuration of a memory cell 10FF in the semiconductor memory device 10F, while line DD represents the cross-sectional configuration of a peripheral region of the semiconductor memory device 10F. The memory cell 10FF here refers to a region in which a capacitor 91, which will be described later, is provided. The peripheral region refers to a region surrounding a memory cell region in which a plurality of memory cells 10FF are provided. The peripheral region of the semiconductor memory device 10F may include, for example, a logic circuit.

[0262] 21, the semiconductor memory device 10F according to the seventh embodiment differs from the semiconductor memory device 10C according to the fourth embodiment in that it has a capacitor 91 instead of the capacitor 51. Hereinafter, the same reference numerals will be used for components that are substantially the same as those in the semiconductor memory device 10C according to the fourth embodiment, and descriptions thereof will be omitted as appropriate.

[0263] The semiconductor memory device 10F is an FeRAM including a capacitor 91 for storing information and a transistor 21 for controlling selection and non-selection of the capacitor 91.

[0264] The capacitor 91 is provided to fill the opening 420. However, unlike the opening 410, the opening 420 is provided to penetrate only the second insulating layer 400. The capacitor 91 includes a lower electrode 911 provided along the inner surface of the opening 420, a ferroelectric film 913 provided on the lower electrode 911 along the opening 420, and an upper electrode 915 provided on the ferroelectric film 913. An upper wiring layer 313 is provided below the lower electrode 911. The upper wiring layer 313 is exposed on the upper surface of the first insulating layer 300 and is electrically connected to the lower surface of the lower electrode 911. The area of ​​the upper wiring layer 313 along the main surface 100S is, for example, equal to or greater than the area of ​​the lower electrode 911 along the main surface 100S. A via contact 311 is provided below the upper wiring layer 313. The via contact 311 electrically connects the upper wiring layer 313 and the first wiring layer 310. Therefore, the lower electrode 911 is electrically connected to the source or drain region 151 (for example, the source) of the transistor 21 via the first wiring layer 310 etc. The upper electrode 915 is electrically connected to the second wiring layer 612 as the source line SL.

[0265] In the semiconductor memory device 10F of this embodiment, the lower electrode 911 is electrically connected to the source or drain region 151 (e.g., the source) of the transistor 21 via the upper wiring layer 313, which has an area larger than that of the first wiring layer 310. This facilitates alignment of the lower electrode 911 with the first wiring layer 310. This improves manufacturing yield. Furthermore, since the capacitor 91 is provided so as to fill only the opening 420 that penetrates only the second insulating layer 400, the manufacturing process can be simplified compared to forming an opening 410 that includes a lower portion 410L having a relatively small area and an upper portion 410U having a relatively large area. Furthermore, the lower electrode 911 of the capacitor 91 is not directly connected to the first wiring layer 310 serving as a bit line, but is in contact with the upper wiring layer 313, which is an upper layer above the first wiring layer 310. If the lower electrode 911 of the capacitor 91 were to be in direct contact with the first wiring layer 310, which has many layout restrictions, then two photolithography steps would be required to form the capacitor 91. However, if the lower electrode 911 is formed so that it is in contact with the upper wiring layer 313, then the capacitor 91 can be formed with one photolithography step. This is because there are fewer layout restrictions on the upper wiring layer 313 than on the first wiring layer 310. This simplifies the manufacturing process.

[0266] (7.2. Manufacturing method) Next, a method for manufacturing the semiconductor memory device 10F according to this embodiment will be described with reference to Figures 22A to 22D. Figures 22A to 22D are schematic views illustrating a step in the method for manufacturing the semiconductor memory device 10F.

[0267] 22A to 22D, similarly to Fig. 21, layers provided over the entire surface of semiconductor substrate 100 are omitted. Also, each of the cross-sectional views in Fig. 22A to 22D shows a cross section taken along line BB, line CC, or line DD shown in the top left plan view.

[0268] First, a first insulating layer 300 is formed in the same manner as in the process shown in FIGS. 15A to 15F of the fourth embodiment. After the first insulating layer 300 is formed, as shown in FIG. 22A, a via contact 311 and an upper wiring layer 312 are sequentially formed on the first wiring layer 310 in the peripheral region. Furthermore, a via contact 311 and an upper wiring layer 313 are sequentially formed on the first wiring layer 310 in the memory cell region. Specifically, the via contact 311 and the upper wiring layers 312 and 313 can be formed by using a damascene structure using Cu or the like as the wiring material. The via contact 311 and the upper wiring layers 312 and 313 may also be formed of Al or the like.

[0269] 22B, a second insulating layer 400 is formed to cover the first insulating layer 300 in the same manner as in the fourth embodiment. After the second insulating layer 400 is formed, a via contact 411 and an upper wiring layer 412 are formed on the upper wiring layer 312 in the same manner as in the fourth embodiment.

[0270] Next, as shown in FIG. 22C, an opening 420 is formed to expose the upper wiring layer 313 in the memory cell region. Specifically, the opening 420 is formed by selectively digging down the second insulating layer 400 using anisotropic etching with a lithographically patterned resist as a mask. The opening 420 is formed to a width of, for example, 60 nm to 150 nm. If the aspect ratio of the opening 420 is approximately 20 or less, the etching to form the opening 420 and the subsequent filling of the opening 420 by deposition can be performed without any problems. The anisotropic etching can be performed using, for example, a fluorocarbon-based gas. Furthermore, the use of the liner layer described above allows the etching to be stopped with good control.

[0271] Next, as shown in FIG. 22D, a capacitor 91 is formed inside the opening 420.

[0272] Specifically, first, the lower electrode 911 is formed by depositing TiN to a thickness of 5 nm to 10 nm on the exposed upper wiring layer 313 along the inner shape of the opening 420 using sputtering by ALD, CVD, or IMP.

[0273] Next, hafnium oxide (HfOx), a high dielectric material, is deposited on the lower electrode 911 along the inner shape of the opening 420 to a thickness of 3 nm to 10 nm by CVD or ALD to form a ferroelectric film 513. Note that hafnium oxide (HfOx), a high dielectric material, is converted into a ferroelectric material by annealing in a later stage.

[0274] Instead of hafnium oxide, it is also possible to use high-dielectric materials such as zirconium oxide (ZrOx) or hafnium zirconium oxide (HfZrOx).In addition, it is also possible to convert these high-dielectric materials into ferroelectric materials by doping them with lanthanum (La), silicon (Si), gadolinium (Gd), or the like.

[0275] Thereafter, TiN is deposited on the ferroelectric film 913 by CVD, ALD, sputtering, or the like to a thickness of 5 nm to 20 nm so as to fill the opening 420, thereby forming the upper electrode 915. Note that TaN, or the like, can also be used as a material for forming the upper electrode 915. Subsequently, crystallization annealing is performed to convert HfOx, which constitutes the ferroelectric film 913, into a ferroelectric material. Note that the crystallization annealing to convert HfOx into a ferroelectric material may be performed in this process or in another process. The temperature of the crystallization annealing can be arbitrarily changed, for example, within a range of 500°C or less and within the heat resistance range of other components such as the transistor 21, NiSi, and wiring. Thereafter, CMP or the like is performed to remove excess ferroelectric film 913 and upper electrode 915 deposited on the second insulating layer 400. This completes the formation of the capacitor 91.

[0276] Subsequently, in the same manner as in the fourth embodiment, the third insulating layer 600 is formed, the via contact 611 is formed, and the second wiring layer 612 is formed.

[0277] According to the above steps, the semiconductor memory device 10F according to this embodiment can be formed.

[0278] The technology according to the present disclosure has been described above using the first to seventh embodiments and modifications thereof. However, the technology according to the present disclosure is not limited to the above-described embodiments, and various modifications are possible.

[0279] Furthermore, not all of the configurations and operations described in each embodiment are necessarily essential to the configurations and operations of the present disclosure. For example, among the components in each embodiment, any component not recited in an independent claim showing the highest concept of the present disclosure should be understood as an optional component.

[0280] Terms used throughout this specification and the appended claims should be interpreted as "open-ended" terms. For example, the terms "including" or "including" should be interpreted as "not limited to the manner described as including." The term "having" should be interpreted as "not limited to the manner described as having."

[0281] The terms used in this specification include terms that are used merely for the convenience of description and are not intended to limit the configuration or operation. For example, terms such as "right," "left," "upper," and "lower" merely indicate directions in the drawings to which reference is made. Furthermore, the terms "inner" and "outer" merely indicate directions toward and away from the center of a focused element, respectively. The same applies to similar terms and terms of a similar meaning.

[0282] The technology according to the present disclosure may also have the following configuration. According to the technology according to the present disclosure having the following configuration, the semiconductor memory device can increase the area of ​​the capacitor without increasing the area of ​​the memory cell, thereby further increasing the capacitance of the capacitor. This allows the semiconductor memory device to obtain a sufficient margin for operation. The effects achieved by the technology according to the present disclosure are not necessarily limited to the effects described herein, and may be any of the effects described in the present disclosure. (1) a field effect transistor provided on a semiconductor substrate; an interlayer insulating film provided on the semiconductor substrate; a contact that penetrates the interlayer insulating film and electrically connects to the drain of the field effect transistor; a first wiring layer provided on the contact; a first insulating layer provided on the interlayer insulating film and burying the first wiring layer; an opening provided in the first insulating layer and the interlayer insulating film from above the first wiring layer; a ferroelectric capacitor provided inside the opening and electrically connected to the source of the field effect transistor; A semiconductor memory device comprising: (2) The semiconductor memory device described in (1) above, wherein the ferroelectric capacitor includes a lower electrode provided along the internal shape of the opening, a ferroelectric film provided on the lower electrode, and an upper electrode provided on the ferroelectric film so as to fill the opening. (3) the lower electrode is electrically connected to the source of the field effect transistor; The semiconductor memory device according to (2) above, wherein the upper electrode is electrically connected to a second wiring layer provided on the first insulating layer. (4) The semiconductor memory device according to (3) above, wherein the second wiring layer is provided extending in the same direction as the first wiring layer. (5) The semiconductor memory device according to (3) or (4) above, wherein the first wiring layer is a bit line, and the second wiring layer is a source line. (6) the first wiring layer is provided extending in a first direction within a surface of the semiconductor substrate, The semiconductor memory device according to any one of (1) to (5) above, wherein the gate electrode of the field effect transistor is provided extending in a second direction perpendicular to the first direction. (7) the field effect transistor is provided in an active region of the semiconductor substrate; The semiconductor memory device according to (6) above, wherein the activation region is provided extending in a third direction obliquely intersecting the first direction and the second direction. (8) a field effect transistor provided on a semiconductor substrate; an interlayer insulating film provided on the semiconductor substrate; an opening including a first opening formed in the interlayer insulating film and a second opening having a smaller diameter than the first opening and formed inside the first opening; a ferroelectric capacitor provided inside the opening and electrically connected to the source of the field effect transistor; A semiconductor memory device comprising: (9) a field effect transistor provided on a semiconductor substrate; an interlayer insulating film provided on the semiconductor substrate; a contact that penetrates the interlayer insulating film and electrically connects to the drain of the field effect transistor; a ferroelectric capacitor provided at a height different from that of the contact inside an opening provided through at least the interlayer insulating film, the ferroelectric capacitor being electrically connected to the source of the field effect transistor; A semiconductor memory device comprising: (10) forming a field effect transistor in a semiconductor substrate; forming an interlayer insulating film on the semiconductor substrate; forming a contact that penetrates the interlayer insulating film and electrically connects to the drain of the field effect transistor; forming a first wiring layer on the contact; forming a first insulating layer on the interlayer insulating film to embed the first wiring layer; forming an opening in the first insulating layer and the interlayer insulating film from a layer above the first wiring layer; forming a ferroelectric capacitor inside the opening and electrically connecting to the source of the field effect transistor; A method for manufacturing a semiconductor memory device, comprising: (11) forming a field effect transistor in a semiconductor substrate; forming an interlayer insulating film on the semiconductor substrate; forming a first opening in the interlayer insulating film; forming a second opening inside the first opening, the second opening having a smaller opening diameter than the first opening; forming a ferroelectric capacitor electrically connected to a source of the field effect transistor within an opening including the first opening and the second opening; A method for manufacturing a semiconductor memory device, comprising: (12) a semiconductor substrate having a main surface; a field effect transistor having a drain and a source provided on the semiconductor substrate; an interlayer insulating film provided on the semiconductor substrate; a contact that penetrates the interlayer insulating film and is electrically connected to the drain of the field effect transistor; a first wiring layer provided on the opposite side of the contact from the field effect transistor and electrically connected to the contact; a first insulating layer provided on the interlayer insulating film and burying the first wiring layer; a ferroelectric capacitor provided on the opposite side of the field effect transistor as viewed from the first wiring layer, the ferroelectric capacitor being electrically connected to the source of the field effect transistor; Equipped with Semiconductor memory device. (13) a second insulating layer provided on the opposite side of the semiconductor substrate from the first wiring layer and extending to a circuit region including a logic circuit; The ferroelectric capacitor is provided on the first insulating layer and the second insulating layer. The semiconductor memory device according to (12) above. (14) Further comprising a second wiring layer, the ferroelectric capacitor has a lower electrode, an upper electrode, and a ferroelectric film sandwiched between the lower electrode and the upper electrode; the lower electrode is electrically connected to the source; The upper electrode is electrically connected to the second wiring layer. The semiconductor memory device according to (12) or (13) above. (15) The second wiring layer is provided on the opposite side of the first wiring layer from the semiconductor substrate. The semiconductor memory device according to (14) above. (16) The first wiring layer and the second wiring layer are both provided to extend in a first direction along the main surface. The semiconductor memory device according to (14) or (15) above. (17) the first wiring layer is a bit line, The second wiring layer is a source line. The semiconductor memory device according to any one of (14) to (16) above. (18) the first wiring layer extends in a first direction along the main surface, The field effect transistor further includes a gate electrode extending in a second direction substantially perpendicular to the first direction. The semiconductor memory device according to any one of (12) to (17) above. (19) the semiconductor substrate has an activation region that extends in a third direction along the main surface and that is oblique to both the first direction and the second direction, The field effect transistor is provided in the active region. The semiconductor memory device according to (18) above. (20) A first area of ​​the upper electrode along the major surface is larger than a second area of ​​a connection portion between the lower electrode and the source along the major surface. The semiconductor memory device according to (14) above. (twenty one) A third area of ​​the upper electrode along the main surface is equal to or greater than a fourth area of ​​the lower electrode along the main surface. The semiconductor memory device according to (14) above. (twenty two) a third wiring layer provided in a layer between the ferroelectric capacitor and the first wiring layer; The ferroelectric capacitor is electrically connected to the first wiring layer via the third wiring layer. (12) The semiconductor memory device according to (12). [Explanation of symbols]

[0283] 10, 10A, 10B...semiconductor memory device, 11...capacitor, 21...transistor, 100...semiconductor substrate, 105...element isolation layer, 110...opening, 110A...first opening, 110B...second opening, 111...lower electrode, 113...ferroelectric film, 115...upper electrode, 130...gate electrode, 131...cap layer, 132...sidewall insulating film, 140...gate insulating film, 150...active region, 151...source or drain region, 152...contact region, 200...planarization film, 201...interlayer insulating film, 210...contact, 210A...conductive layer, 210B...barrier metal layer, 300...first insulating layer, 310...first wiring layer, 311...via contact, 312...upper wiring layer, 320...second wiring layer

Claims

1. A semiconductor substrate having a main surface; a field effect transistor having a drain and a source provided on the semiconductor substrate; an interlayer insulating film provided on the semiconductor substrate; a contact that penetrates the interlayer insulating film and is electrically connected to the drain of the field effect transistor; a first wiring layer provided on the opposite side of the semiconductor substrate from the contact and electrically connected to the contact; a first insulating layer provided on the interlayer insulating film and burying the first wiring layer; a ferroelectric capacitor provided on the opposite side of the semiconductor substrate from the first wiring layer, the ferroelectric capacitor having a lower electrode electrically connected to the source of the field effect transistor, an upper electrode, and a ferroelectric film sandwiched between the lower electrode and the upper electrode; a second wiring layer provided on the opposite side of the semiconductor substrate as viewed from the ferroelectric capacitor, the second wiring layer being electrically connected to the upper electrode; a second insulating layer provided on the opposite side of the semiconductor substrate from the first wiring layer and extending to a circuit region including a logic circuit; Equipped with a first area of ​​the upper electrode along the main surface is larger than a second area of ​​a connection portion between the lower electrode and the source along the main surface; the field effect transistor, the first wiring layer, the ferroelectric capacitor, and the second wiring layer are provided in different layers in a stacking direction orthogonal to the main surface, The ferroelectric capacitor is provided in the first insulating layer and the second insulating layer. Semiconductor memory device.

2. The second wiring layer is provided on the opposite side of the first wiring layer from the semiconductor substrate.

2. The semiconductor memory device according to claim 1.

3. The first wiring layer and the second wiring layer are both provided to extend in a first direction along the main surface.

2. The semiconductor memory device according to claim 1.

4. the first wiring layer is a bit line, The second wiring layer is a source line.

2. The semiconductor memory device according to claim 1.

5. the first wiring layer extends in a first direction along the main surface, The field effect transistor further includes a gate electrode extending in a second direction substantially perpendicular to the first direction.

2. The semiconductor memory device according to claim 1.

6. the semiconductor substrate has an activation region that extends in a third direction obliquely intersecting both the first direction and the second direction and along the main surface; The field effect transistor is provided in the active region.

6. The semiconductor memory device according to claim 5.

7. A third area of ​​the upper electrode along the main surface is equal to or greater than a fourth area of ​​the lower electrode along the main surface.

2. The semiconductor memory device according to claim 1.

8. The lower electrode includes a bottom portion that extends along the main surface and faces the upper electrode in the stacking direction, and a wall portion that stands on the bottom portion so as to surround the periphery of the upper electrode along the main surface via the ferroelectric film.

2. The semiconductor memory device according to claim 1.

9. A semiconductor substrate having a main surface; a field effect transistor having a drain and a source provided on the semiconductor substrate; an interlayer insulating film provided on the semiconductor substrate; a contact that penetrates the interlayer insulating film and is electrically connected to the drain of the field effect transistor; a first wiring layer provided on the opposite side of the semiconductor substrate from the contact and electrically connected to the contact; a first insulating layer provided on the interlayer insulating film and burying the first wiring layer; a ferroelectric capacitor provided on the opposite side of the semiconductor substrate as viewed from the first wiring layer, the ferroelectric capacitor having a lower electrode electrically connected to the source of the field effect transistor, an upper electrode, and a ferroelectric film sandwiched between the lower electrode and the upper electrode; a second wiring layer provided on the opposite side of the semiconductor substrate as viewed from the ferroelectric capacitor and electrically connected to the upper electrode; Equipped with a first area of ​​the upper electrode along the main surface is larger than a second area of ​​a connection portion between the lower electrode and the source along the main surface; the field effect transistor, the first wiring layer, the ferroelectric capacitor, and the second wiring layer are provided in different layers in a stacking direction perpendicular to the main surface, The first wiring layer and the second wiring layer are both provided to extend in a first direction along the main surface. Semiconductor memory device.

10. A semiconductor substrate having a main surface; a field effect transistor having a drain and a source provided on the semiconductor substrate; an interlayer insulating film provided on the semiconductor substrate; a contact that penetrates the interlayer insulating film and is electrically connected to the drain of the field effect transistor; a first wiring layer provided on the opposite side of the semiconductor substrate from the contact and electrically connected to the contact; a first insulating layer provided on the interlayer insulating film and burying the first wiring layer; a ferroelectric capacitor provided on the opposite side of the semiconductor substrate as viewed from the first wiring layer, the ferroelectric capacitor having a lower electrode electrically connected to the source of the field effect transistor, an upper electrode, and a ferroelectric film sandwiched between the lower electrode and the upper electrode; a second wiring layer provided on the opposite side of the semiconductor substrate as viewed from the ferroelectric capacitor and electrically connected to the upper electrode; Equipped with a first area of ​​the upper electrode along the main surface is larger than a second area of ​​a connection portion between the lower electrode and the source along the main surface; the field effect transistor, the first wiring layer, the ferroelectric capacitor, and the second wiring layer are provided in different layers in a stacking direction perpendicular to the main surface, The lower electrode includes a bottom portion that extends along the main surface and faces the upper electrode in the stacking direction, and a wall portion that stands on the bottom portion so as to surround the periphery of the upper electrode along the main surface via the ferroelectric film. Semiconductor memory device.

Images