Semiconductor device and method for manufacturing a semiconductor device

Abstract

The semiconductor device (100) includes a semiconductor body (1) having an upper surface (10), a main electrode (2) on the upper surface, and a gate electrode (3). The semiconductor body includes a drift layer (11) of a first conductivity type, a first base region (12) of a second conductivity type, a second base region (13) of the first conductivity type, a first contact region (14) of the first conductivity type, and a second contact region (15) of the second conductivity type. The second base region has a higher doping concentration than the drift layer. The first contact region is adjacent to the first base region and the upper surface. The second contact region is adjacent to the second base region and the upper surface. The main electrode is in electrical contact with the first and second contact regions. In a first lateral direction, at least a part of the gate electrode is disposed between the first contact region and the second contact region.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates to semiconductor devices and methods for manufacturing semiconductor devices. [Background technology]

[0002] There is a need for improved semiconductor devices, for example, semiconductor devices that allow for efficient removal of charge carriers, such as holes, from a semiconductor body during a turn-off transient without compromising on-state losses. Additionally, there is a need for improved methods for fabricating such semiconductor devices. Summary of the Invention [Means for solving the problem]

[0003] SUMMARY OF THE INVENTION Embodiments of the present disclosure relate to improved semiconductor devices and improved methods for manufacturing semiconductor devices.

[0004] First, the semiconductor device is identified. According to one embodiment, a semiconductor device includes a semiconductor body having a top surface, a main electrode on the top surface, and a gate electrode. The semiconductor body includes a drift layer of a first conductivity type. The semiconductor body further includes a first base region of a second conductivity type vertically disposed between the drift layer and the top surface. The semiconductor body further includes a second base region of the first conductivity type vertically disposed between the drift layer and the top surface. The second base region has a higher doping concentration than the drift layer and is adjacent to the drift layer. The semiconductor body further includes a first contact region of the first conductivity type. The first contact region is adjacent to the first base region and the top surface. The semiconductor body further includes a second contact region of the second conductivity type. The second contact region is adjacent to the second base region and the top surface. The main electrode is in electrical contact with the first contact region and the second contact region. In the first lateral direction, at least a portion of the gate electrode is disposed between the first contact region and the second contact region and between the first base region and the second base region.

[0005] Bipolar semiconductor devices, such as IGBTs, are devices in which both electrons and holes participate in the conduction process. Injecting both electrons and holes creates a high-density plasma in the drift layer, lowering the resistance of this layer and consequently reducing losses during the on-state. However, during the off-state, the accumulated plasma needs to be removed quickly to minimize switching losses. Therefore, there is a trade-off between the on-state voltage drop (Vce-sat) and the turn-off switching losses (Eoff) of such devices.

[0006] In the present invention, a complementary transistor is introduced for controlled extraction of a second type of charge carrier, such as holes, through the second base region and second contact region. The complementary transistor provides an additional extraction path for the second type of charge carrier, which remains active only during the turn-off period of the primary transistor comprising the first base region and first contact region. Therefore, the switching losses of the semiconductor device are reduced without compromising its on-state. The functionality of the semiconductor device is not limited, for example, by trench spacing. Furthermore, because no additional gate connection is required, Miller capacitance Cgc is not adversely affected. This concept is applicable to MOS-based bipolar devices, such as IGBTs, reverse-conducting (RC)-IGBTs, bidirectional IGBTs (BIGTs), and MOS-controlled diodes, and can be translated to both trench and planar architectures.

[0007] The semiconductor body may be based on Si or SiC or GaN or any other semiconductor material. The lateral direction is defined herein as the direction parallel to the top surface of the semiconductor body. The vertical direction is defined herein as the direction perpendicular to the top surface.

[0008] The main electrode may be formed of a metal. The gate electrode may include or consist of a heavily doped metal or polysilicon. The gate electrode is insulated from the semiconductor body by an electrically isolating material, such as SiO2 or any other dielectric material, or a combination of two or more dielectric materials. Thus, the semiconductor device may be an insulated gate device. In particular, the gate electrode and the main electrode are electrically insulated from each other and can be set to different potentials for operation.

[0009] The drift layer may extend across the entire lateral extent of the semiconductor body. The drift layer is of a first conductivity type. The first conductivity type can be either electron-conducting or hole-conducting. The second conductivity type is different from the first conductivity type, i.e., either hole-conducting or electron-conducting. Regions or layers that are electron-conducting are n-doped, and regions or layers that are hole-conducting are p-doped. For example, the doping concentration in the drift layer is at least 10 8 cm -3 and at most 10 15 cm -3 is.

[0010] The first base region is disposed vertically between the drift layer and the top surface, i.e., disposed vertically between the drift layer and the top surface. For example, the doping concentration in the first base region is at least 10 15 cm -3 and / or at most 10 18 cm -3 The first base region may be adjacent to the drift layer and / or the top surface, i.e., may be in direct contact with the drift layer and / or may form part of the top surface.

[0011] The second base region is of the same conductivity type as the drift layer but has a higher doping concentration than the drift layer, for example, the doping concentration in the second base region is at least 10 times or at least 100 times higher than the drift layer. For example, the doping concentration in the second base region is at least 10 15 cm -3 and / or at most 10 18 cm -3 is.

[0012] The second base region is adjacent to, i.e., in direct contact with, the drift layer. In particular, there is no region of the second conductivity type vertically disposed between the drift layer and the second base region. Furthermore, the second base region may be adjacent to, i.e., form part of, the top surface.

[0013] Here, when comparing the doping concentrations of layers or regions, the average doping concentration or the maximum doping concentration of these layers or regions is compared. When defining the upper and lower limits of the doping concentration of a layer or region, it means that the maximum doping concentration of the respective layer / region does not exceed the upper limit, and the minimum doping concentration of the respective layer / region does not fall below the lower limit.

[0014] The first contact region is adjacent to the first base region and the top surface, i.e., directly contacts the first base region and forms part of the top surface. For example, the first contact region is disposed vertically between the first base region and the top surface and vertically adjacent to the first base region. Additionally or alternatively, the first contact region may be adjacent to the first base region in the first lateral direction.

[0015] The first contact region may be at least partially embedded in the first base region. In particular, the first contact region may be at least partially laterally surrounded by the first base region. The doping concentration in the first contact region may be, for example, higher than the doping concentration in the first base region, for example, at least 10 times or at least 100 times higher. For example, the doping concentration in the first contact region may be at least 10 times higher. 17 cm -3 or at least 10 18 cm -3 or at least 10 19 cm -3 is.

[0016] The second contact region is adjacent to the second base region and the top surface, i.e., directly contacts the second base region and forms part of the top surface. For example, the second contact region is disposed vertically between the second base region and the top surface and vertically adjacent to the second base region. Additionally or alternatively, the second contact region may be adjacent to the second base region in the first lateral direction.

[0017] The second contact region may be at least partially embedded in the second base region. In particular, the second contact region may be at least partially laterally surrounded by the second base region. The doping concentration in the second contact region may be, for example, higher than the doping concentration in the second base region, for example, at least 10 times or at least 100 times higher. For example, the doping concentration in the second contact region may be at least 10 times higher. 17 cm -3 or at least 10 18 cm -3 or at least 10 19 cm -3 is.

[0018] The contact region is also known as the source region. The thickness of the first and second base regions, measured in the vertical direction, may be at least 1 μm and / or at most 8 μm. The thickness of the first and second contact regions may in each case be at least 50 nm and / or at most 1 μm. The lateral extent of the first and second contact regions in the first lateral direction may in each case be at least 50 nm and / or at most 5 μm. The lateral extent of the first and second base regions in the first lateral direction may in each case be at least 500 nm and / or at most 5 μm.

[0019] The main electrode is in direct electrical contact with the first and second contact regions. For example, the main electrode is adjacent to the first and second contact regions at the top surface. For example, the main electrode is not in direct electrical contact with the second base region. An ohmic contact may be formed between the main electrode and the contact regions.

[0020] In the first lateral direction, at least a portion of the gate electrode, e.g., a majority or the entire gate electrode, is laterally disposed between the first contact region and the second contact region and between the first base region and the second base region. For example, in the first lateral direction, only one gate electrode is disposed between the first contact region and the second contact region and between the first base region and the second base region. As an example, the distance between the first contact region and the second contact region measured in the first lateral direction is at most 2 times or at most 1.5 times the lateral extent of the gate electrode in the first lateral direction. For example, the distance between the first contact region and the second contact region in the first lateral direction is at most 10 μm.

[0021] According to a further embodiment, the semiconductor device is configured such that by setting the potential of the gate electrode, a zone of the first base region is inverted by the gate electrode, i.e., the conductivity type is inverted in this zone, thus enabling a current flow of first type charge carriers between the drift layer and the first contact region through this zone. The inversion zone is the zone of the first base region facing the gate electrode, i.e., closest to the gate electrode.

[0022] Alternatively, a zone of the second base region is inverted by the gate electrode, thus allowing current flow of the second type of charge carriers between the drift layer and the second contact region through this zone. Again, the inversion zone is the zone of the second base region facing the gate electrode, i.e., closest to the gate electrode.

[0023] Thus, the drift layer, the first base region, and the first contact region form part of a first transistor (primary transistor), and the drift layer, the second base region, and the second contact region form part of a second transistor (complementary transistor).

[0024] If the first conductivity type is electron conduction, the charge carriers of the first type are electrons. Therefore, if the second conductivity type is hole conduction, the charge carriers of the second type are holes.

[0025] For example, in a first case, when the zone in the first base region is inverted, charge carriers of a first type can flow from the main electrode through the first contact region, the inversion zone in the first base region, and into the drift layer. For example, in a second case, when the zone in the second base region is inverted, charge carriers of a second type can flow from the drift layer through the inversion zone in the second base region and the second contact region and into the main electrode.

[0026] According to a further embodiment, the semiconductor device is a planar device, i.e., has a planar architecture, and the gate electrode is disposed on the top surface. For example, in a first lateral direction, the gate electrode is at least partially aligned with the first and second contact regions and / or the first and second base regions. This allows the gate electrode to be isolated from the contact regions by an electrical isolation layer. For example, in a plan view on the top surface, the gate electrode at least partially overlaps the first and second contact regions and the first and second base regions.

[0027] According to a further embodiment, the semiconductor device is a trench device, i.e., a trench architecture, and the gate electrode is disposed within the active trench. The active trench extends vertically from the top surface into the semiconductor body. For example, the first and second contact regions and / or the first and second base regions are at least partially aligned with the gate electrode in the vertical direction. That is, in a side view along the first lateral direction, the active trench and the gate electrode therein partially or completely overlap the first and second contact regions and / or the first and second base regions. For example, the active trench extends deeper into the semiconductor body than the first and second contact regions and / or the first and second base regions. For example, the active trench and the gate electrode extend vertically into the semiconductor body by at least 2 μm, at least 4 μm, and / or at most 10 μm.

[0028] According to a further embodiment, the semiconductor device comprises a dummy trench positioned next to and spaced apart from the active trench in the first lateral direction.

[0029] A trench having a gate electrode therein is referred to herein as an "active trench." A trench not having a gate electrode therein is referred to herein as a "dummy trench." For example, the second base region and the second contact region may be disposed between the active trench and the dummy trench in the first lateral direction. The second base region may be adjacent to the active trench and the dummy trench in the first lateral direction.

[0030] According to a further embodiment, the dummy trenches are filled with a conductive material, such as highly doped polysilicon, that is electrically isolated from the semiconductor body by, for example, an isolation material, for example, the conductive material in the dummy trenches is electrically connected to the main electrode.

[0031] The trenches in a semiconductor device, whether active or dummy, may all have the same dimensions within the limits of manufacturing tolerances, or the dummy trenches may be deeper or shallower than the active trenches.

[0032] For example, exactly one active trench is disposed between the first contact region and the second contact region and between the first base region and the second base region. The first and second contact regions may be adjacent to the active trench on different sides in the first lateral direction. Similarly, the first and second base regions may be adjacent to the active trench on different sides in the first lateral direction.

[0033] According to a further embodiment, an enhancement region of a first conductivity type is vertically disposed between the first base region and the drift layer. For example, the enhancement region extends laterally across the entire lateral extent of the first base region. Thus, the enhancement layer is disposed between the drift layer and the first base region across the entire lateral extent of the first base region. The enhancement region may be adjacent to the first base region and / or the drift layer. In this specification, this enhancement region is also referred to as a "first enhancement region."

[0034] According to further embodiments, the enhancement region has a doping concentration higher than the drift layer. For example, the doping concentration in the first enhancement region is at least 10 times or at least 100 times higher than the doping concentration in the drift layer. For example, the doping concentration in the enhancement region is at least 10 15 cm -3 and / or at most 10 19 cm -3 The enhancement region may have a thickness, measured vertically, of, for example, at least 1 μm and / or at most 3 μm.

[0035] The enhancement region is a blocking region for the second type of charge carriers, e.g., holes, and may therefore be referred to as a "hole blocking region" or "hole blocking layer," respectively.

[0036] According to a further embodiment, the semiconductor device comprises a third base region of the second conductivity type. The third base region is arranged next to the second base region in the first lateral direction such that the second base region is arranged between the first and third base regions in the first lateral direction. The second and third base regions may be spaced apart from each other in the first lateral direction by a trench, for example, by exactly one trench. The trench may be an active trench or a dummy trench.

[0037] The third base region is also disposed vertically between the top surface and the drift layer. It may be adjacent to the top surface and / or the drift layer. The doping concentration in the third base region may be the same as or different from the doping concentration in the first base region. The thickness of the third base region, measured vertically, is, for example, at least 1 μm greater than the thickness of the first base region.

[0038] According to a further embodiment, the third base region extends from the top surface into the semiconductor body. For example, the third base region extends deeper into the semiconductor body than the active trench or trenches. For example, the third base region extends at least 1 μm deeper into the semiconductor body than the trenches. The third base region is, for example, a so-called p-well.

[0039] According to further embodiments, the thickness of the insulating material between the first contact region and / or the first base region and the gate electrode is greater than the thickness of the insulating material between the second contact region and / or the second base region and the gate electrode, for example, the thickness between the first contact region / first base region and the gate electrode is at least 1.5 times or at least 2 times the thickness between the second contact region / second base region and the gate electrode.

[0040] According to a further embodiment, the main electrode is not in direct electrical contact with the second base region. This means that charge carriers cannot flow directly from the main electrode to the second base region or vice versa. Rather, charge carrier exchange must always occur via the second contact region.

[0041] According to a further embodiment, the semiconductor device comprises a further gate electrode. The further gate electrode is spaced apart from the gate electrode in the first lateral direction. For example, the further gate electrode is at the same potential as the gate electrode. In other words, the gate electrode and the further gate electrode may be short-circuited.

[0042] Additionally, a further gate electrode may be disposed in an active trench extending from the top surface into the semiconductor body.

[0043] According to a further embodiment, the second base region is arranged between the gate electrode and the further gate electrode in the first lateral direction. For example, no further gate electrode is arranged between the gate electrode and the further gate electrode in the first lateral direction. The second base region may be adjacent to two active trenches comprising the gate electrode and the further gate electrode in the first lateral direction.

[0044] According to a further embodiment, the semiconductor device is configured such that a zone of the second base region is inverted by the further gate electrode by setting the potential of the further gate electrode, the zone being located on a side of the second base region opposite the side of the second base region where the zone of the second base region is inverted by the gate electrode. The further gate electrode thus provides a current path on this opposite side. "Opposite" here refers to the first lateral direction. In other words, the gate electrode and the further gate electrode are arranged on opposite sides, inverting a zone of the second base region that is spaced apart, for example, in the first lateral direction.

[0045] In other words, the gate electrode and the further gate electrode establish two channels for the transport of charge carriers, for example hole channels.

[0046] According to further embodiments, the first and / or second contact regions are elongated regions extending in a second transverse direction oblique to the first transverse direction, e.g., perpendicular to the first transverse direction. This means that the lateral extent of the first and / or second contact regions is in each case greater in the second transverse direction than in the first transverse direction. For example, the lateral extent in the second transverse direction is in each case at least two times or at least five times greater than in the first transverse direction. The first and second contact regions may adjoin the top surface over their entire lateral extent in the first and / or second transverse direction.

[0047] Similarly, the first and second base regions may be elongated and extend in the second lateral direction, and the trench may be elongated and extend in the second lateral direction.

[0048] According to a further embodiment, the semiconductor device comprises several first contact regions adjacent to the top surface and the first base region and electrically contacting the main electrode. These first contact regions are separated and spaced apart from one another in the second lateral direction. For example, each first contact region has a lateral extent in the second lateral direction of at least 500 nm or at least 1 μm. The distance between each two adjacent first contact regions in the second lateral direction may in each case be at least 500 nm or at least 1 μm. All features disclosed so far for one first contact region, particularly with regard to doping concentration and conductivity type, are also disclosed for all other first contact regions.

[0049] According to a further embodiment, the semiconductor device comprises several second contact regions adjacent to the top surface and the second base region and electrically contacting the main electrode. These second contact regions are separated and spaced apart from one another in the second lateral direction. For example, each second contact region has a lateral extent in the second lateral direction of at least 500 nm or at least 1 μm. The distance between each two adjacent second contact regions in the second lateral direction may in each case be at least 500 nm or at least 1 μm. All features disclosed so far for one second contact region, particularly with regard to doping concentration and conductivity type, are also disclosed for all other second contact regions.

[0050] According to a further embodiment, the semiconductor device is a power semiconductor device, for example configured to handle a current of at least 1 A and / or a voltage of at least 100 V. The semiconductor device is, for example, a so-called vertical semiconductor device.

[0051] According to a further embodiment, the semiconductor device is a vertical device, i.e. a vertical architecture, in which case the cathode and the anode are arranged on opposite sides of the semiconductor body.

[0052] According to a further embodiment, the semiconductor device is a bipolar semiconductor device in which both electrons and holes contribute to the current during operation.

[0053] According to a further embodiment, the semiconductor device is an insulated gate bipolar transistor, IGBT for short, or a MOS-controlled diode, for example a reverse conducting (RC)-IGBT or a bidirectional IGBT (BIGT).

[0054] According to a further embodiment, the semiconductor device comprises a further main electrode applied to a back surface of the semiconductor body opposite to the top surface, and the semiconductor body may comprise a contact layer (anode layer) and / or a buffer layer between the drift layer and the further main electrode.

[0055] Next, a method for manufacturing a semiconductor device is identified. The method is particularly suitable for manufacturing a semiconductor device according to any one of the embodiments described herein. Accordingly, all features disclosed for the semiconductor device are also disclosed for the method, and vice versa.

[0056] According to one embodiment of a method for manufacturing a semiconductor device, the method includes providing a semiconductor body having a top surface and a drift layer of a first conductivity type. In a further step, a first base region, a second base region, a first contact region, and a second contact region are fabricated. The first base region is of a second conductivity type and is fabricated such that the first base region is vertically located between the drift layer and the top surface. The second base region is of the first conductivity type and is fabricated such that the second base region is vertically located between the drift layer and the top surface, the second base region having a higher doping concentration than the drift layer and adjacent to the drift layer. The first contact region is of the first conductivity type and is fabricated such that the first contact region is adjacent to the first base region and the top surface. The second contact region is of the second conductivity type and is fabricated such that the second contact region is adjacent to the second base region and the top surface. In a further step, a main electrode is applied to the top surface and electrical contact is established between the main electrode and the first contact region and between the main electrode and the second contact region. In a further step, a gate electrode is finally formed such that at least a portion of the gate electrode is located between the first and second contact regions and between the first and second base regions in a first lateral direction.

[0057] Before forming the first and second base regions and the first and second contact regions, the drift layer may reach a top surface, for example, forming the top surface. Fabricating the base regions and / or the contact regions may include, for example, implanting dopants through the top surface. For example, a mask is used to define areas where dopants for different regions will be implanted.

[0058] Hereinafter, with reference to the drawings, a semiconductor device and a method for manufacturing a semiconductor will be described in more detail based on exemplary embodiments. The accompanying drawings are included to provide a further understanding. In the drawings, elements of the same structure and / or function may be referred to by the same reference numerals. It should be understood that the embodiments shown in the drawings are exemplary representations and are not necessarily drawn to scale. To the extent that elements or components correspond to each other in terms of their functions in different drawings, their description will not be repeated for each of the following drawings. For clarity, elements may not be labeled with corresponding reference numerals in all drawings. [Brief explanation of the drawings]

[0059] [Figure 1] 1A-1D illustrate different exemplary embodiments of a semiconductor device. [Figure 2] 1A-1D illustrate different exemplary embodiments of a semiconductor device. [Figure 3] 1A-1D illustrate different exemplary embodiments of a semiconductor device. [Figure 4] 1A-1D illustrate different exemplary embodiments of a semiconductor device. [Figure 5] 1A-1D illustrate different exemplary embodiments of a semiconductor device. [Figure 6] FIG. 1 illustrates a reference semiconductor device. [Figure 7] 1A-1C illustrate simulation results showing the behavior of exemplary embodiments of a semiconductor device and a reference semiconductor device. [Figure 8] 1A-1C illustrate simulation results showing the behavior of exemplary embodiments of a semiconductor device and a reference semiconductor device. [Figure 9] 1A-1D illustrate different exemplary embodiments of a semiconductor device. [Figure 10] FIG. 1 illustrates a reference semiconductor device. [Figure 11]1A-1C illustrate simulation results showing the behavior of exemplary embodiments of a semiconductor device and a reference semiconductor device. [Figure 12] 1A-1C illustrate simulation results showing the behavior of exemplary embodiments of a semiconductor device and a reference semiconductor device. [Figure 13] 1A-1C illustrate simulation results showing the behavior of exemplary embodiments of a semiconductor device and a reference semiconductor device. [Figure 14] 1A-1C illustrate simulation results showing the behavior of exemplary embodiments of a semiconductor device and a reference semiconductor device. [Figure 15] 1A-1C illustrate simulation results showing the behavior of exemplary embodiments of a semiconductor device and a reference semiconductor device. [Figure 16] 1A-1D illustrate different exemplary embodiments of a semiconductor device. [Figure 17] FIG. 1 illustrates an example of a semiconductor device. [Figure 18] 1A-1D illustrate different exemplary embodiments of a semiconductor device. [Figure 19] 1A-1D illustrate different exemplary embodiments of a semiconductor device. [Figure 20] 1A-1D illustrate different exemplary embodiments of a semiconductor device. [Figure 21] 1A-1D illustrate different exemplary embodiments of a semiconductor device. [Figure 22] 1A-1D illustrate different exemplary embodiments of a semiconductor device. [Figure 23] 1A-1D illustrate different exemplary embodiments of a semiconductor device. [Figure 24] 1A-1D illustrate different exemplary embodiments of a semiconductor device. [Figure 25] 1A-1D illustrate different exemplary embodiments of a semiconductor device. [Figure 26] 1A-1D illustrate different exemplary embodiments of a semiconductor device. [Figure 27] 1A-1D illustrate different exemplary embodiments of a semiconductor device. [Figure 28]1A-1D illustrate different exemplary embodiments of a semiconductor device. [Figure 29] 1A-1D illustrate different exemplary embodiments of a semiconductor device. [Figure 30] 1 is a flowchart of an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 31] 1A-1D illustrate different exemplary embodiments of a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0060] 1 shows in cross-section a section of a first exemplary embodiment of a semiconductor device 100. The semiconductor device 100 comprises a semiconductor body 1, for example of Si or SiC or GaN. A main electrode 2 is applied to a top surface 10 of the semiconductor body 1. The main electrode 2 is, for example, a metal electrode.

[0061] The semiconductor body 1 comprises a drift layer 11 of a first conductivity type. In the following, it is assumed that the first conductivity type is electron conduction, and the corresponding doping is n-doping. This means that the drift layer 11 is n-doped. However, the described embodiments also work if the first conductivity type is hole conduction.

[0062] The first base region 12 and the second base region 13 are each located vertically between the drift layer 11 and the top surface 10. In this specification, "vertically" refers to a vertical direction V that is perpendicular to the top surface 10. The first base region 12 and the second base region 13 are arranged next to each other in a first lateral direction L1 that is parallel to the top surface 10. The first base region 12 is of a second conductivity type different from the first conductivity type, i.e., p-doped in this case. The second base region 13 is of the first conductivity type, i.e., n-doped. Both base regions 12 and 13 are adjacent to the drift layer 11 and the top surface 10.

[0063] A first contact region 14 is embedded in the first base region 12. The first contact region 14 is of a first conductivity type, i.e., n-doped, and is adjacent to the first base region 12 and the top surface 10. At the top surface 10, the first contact region 14 is in direct mechanical and electrical contact with the main electrode 2. Also, the first base region 12 is in direct mechanical and electrical contact with the main electrode 2 at the top surface 10.

[0064] A second contact region 15 is embedded in the second base region 13. The second contact region 15 is of the second conductivity type, i.e., p-doped, and is adjacent to the second base region 13 and the top surface 10. At the top surface 10, the second contact region 15 is in direct mechanical and electrical contact with the main electrode 2. However, since the main electrode 2 is not in direct mechanical or electrical contact with the second base region 13, the exchange of charge carriers between the main electrode 2 and the second base region 13 must always occur via the second contact region 15.

[0065] Active trenches 4 extend laterally from the top surface 10 into the semiconductor body 1 between the base regions 12, 13 and the contact regions 14, 15 and open into the drift layer 11. The depth of the active trenches 4, measured in the vertical direction V, is greater than the thickness of the base regions 12, 13 and the contact regions 14, 15, also measured in the vertical direction V. A gate electrode 3 is disposed within the active trench 4. The gate electrode 3 is made of, for example, heavily doped polysilicon. The gate electrode 3 is electrically isolated from the semiconductor body 1, in particular the base regions 12, 13 and the contact regions 14, 15, by an electrical isolation material 5, for example, made of SiO2. The semiconductor device 100 of FIG. 1 is a so-called trench device.

[0066] The doping concentration of the drift layer 11 is, for example, 10 8 cm -3 Over 10 15 cm -3 The doping concentration of each base region 12, 13 is, for example, 10 15 cm -3 ~1018 cm -3 The doping concentration in the contact regions 14, 15 is in each case in the range of, for example, 10 18 cm -3 ~10 21 cm -3 is within the range.

[0067] In the on-state of the semiconductor device 100, the gate electrode 3 may be at a positive potential with respect to the semiconductor body 1. This forms an inversion zone on the side of the first base region 12 facing the active trench 4, said inversion zone extending along the active trench 4 from the first contact region 14 to the drift layer 11. This allows electrons to be injected from the main electrode 2 into the contact region 14 and from there move within the inversion zone into the drift layer 11.

[0068] In the off-state of the semiconductor device 100, the gate electrode 3 may be at a negative potential with respect to the semiconductor body 1. The potentials of the main electrode 2 and the further main electrode may be the same as in the on-state. This results in an inversion zone being formed on the side of the second base region 13 facing the active trench 4, said inversion zone extending along the active trench 4 from the second contact region 15 to the drift layer 11. This allows holes to exit the drift layer 11 through the inversion zone, migrate along the inversion zone, and then enter the main electrode 2 through the second contact region 15.

[0069] Particularly when the semiconductor device 100 is a bipolar device such as an IGBT, very efficient hole drainage is thus possible, resulting in reduced turn-off losses.

[0070] The transistor realized with the first base region 12 and the first contact region 14 is referred to herein as the "primary transistor," and the transistor realized with the second base region 13 and the second contact region 15 is referred to as the "complementary transistor." In the exemplary embodiment described herein, the primary transistor is an NMOS transistor and the complementary transistor is a PMOS transistor.

[0071] The exemplary embodiment of Figure 2 shows a so-called planar device that does not use trenches as shown in Figure 1. Instead, gate electrode 3 is disposed on top surface 10 and is electrically isolated from semiconductor body 1 by electrical isolation material 5. In a plan view onto top surface 10, gate electrode 3 partially covers, i.e., overlaps, first 14 and second 15 contact regions. While the inversion zones and associated current paths in Figure 1 are primarily oriented in a vertical direction V, the inversion zones and associated current paths in Figure 2 are primarily oriented in a first lateral direction L1.

[0072] The exemplary embodiment of Fig. 3 shows a semiconductor device 100, which is an insulated gate bipolar transistor, or IGBT for short. On the back side of the semiconductor body 1, opposite the top side 10, a further main electrode 6, e.g., metal, is applied. The semiconductor body 1 comprises a further layer 20 of a second conductivity type, i.e., p-doped, which forms the back side and is in direct electrical and mechanical contact with the further main electrode 6. The doping concentration of the further layer 20 is, for example, higher than that of the drift layer 11. Between the drift layer 11 and the layer 20, a layer 19 of the first conductivity type is applied. The layer 19 adjoins the layer 20 and the drift layer 11. The doping concentration of the layer 19 is, for example, higher than that of the drift layer 11. The layer 19 is a so-called buffer layer.

[0073] 3, the first base region 12 is adjacent to the active trenches 4 on both sides in the first lateral direction L1. Both active trenches 4 are connected to the gate electrode 3. Second base regions 13 are arranged on both sides of the first base region 12, also in the first lateral direction L1, and are each spaced apart from the first base region 12 by one of the active trenches 4.

[0074] Each second base region 13 is located between and adjacent to the two trenches 4, 40. In each case, only the trench closest to the first base region 12 is the active trench 4. The other trench 40 in each case is a dummy trench. The dummy trenches 40 are, for example, electrically connected to the main electrode 2 and are therefore filled with a conductive material that is at the same potential as the main electrode 2. The dummy trenches 40 serve to reduce the capacitance between the gate electrode 3 and the further main electrode 6, also called the Miller capacitance or gate-collector capacitance Cgc.

[0075] 3 and other figures may show only a portion of a semiconductor device. The structure shown in these figures, comprising base regions 12, 13 and contact regions 14, 15, may be repeated several times in the first lateral direction L1.

[0076] 4, the semiconductor body 1 is of the second conductivity type, i.e., p-doped, and comprises a third base region 18 adjacent to the dummy trench 40 on the side facing away from the second base region 13. The doping concentration in the third base region 18 may be in the same or a different range than the first base region 12. The third base region 18 constitutes a p-well that extends deeper into the semiconductor body 1 than the trenches 4, 40. The third base region 18 allows for an improved breakdown voltage to be obtained.

[0077] Figure 5 shows a detailed view of the exemplary embodiment of Figure 4, showing only the first base region 12, the adjacent second base region 13, and half of the third base region 18. Figure 5 illustrates the doping profile by using different hatching: the higher the hatching dot density, the higher the doping concentration.

[0078] 6 shows a reference semiconductor device 200, e.g., a reference IGBT. In contrast to the IGBT of FIG. 5, the second base region 13 and the second contact region 15 are ignored. Rather, the semiconductor body 1 adjacent to the top surface 10 in the lateral direction between the dummy trench 40 and the active trench 4 also consists of a semiconductor material of the second conductivity type, e.g., having the same doping concentration as the first base region 12. A main electrode 2 is in electrical and mechanical contact with the semiconductor body 1 in the region between the two trenches 4, 40 (dummy contact).

[0079] 7 and 8 show simulated output characteristics Ic vs. Vce (curve 100) of the IGBT according to FIG. 5 compared with those of the reference IGBT according to FIG. 6, i.e., without the second base region and second contact region (curve 200). FIG. 7 shows the range from 0 to 2 V, and FIG. 8 shows the range from 0 to 25 V. The IGBT according to FIG. 5 shows an improvement of approximately 130 mV in Vce-sat compared to the reference IGBT according to FIG. 6. In the reference IGBT, the extraction of holes injected between the dummy trench 40 and the active trench 4 in the on-state reduces the plasma density in the drift region (drift layer 11), resulting in increased on-state losses. In the IGBT of FIG. 5, this hole extraction between the dummy trench 40 and the active trench 4 in the on-state is significantly reduced (by approximately 50%, see also FIG. 9). This is a result of placing the second base region and second contact region (PMOS transistor) between the active trench 4 and the dummy trench 40. This PMOS transistor is off during the IGBT on-state (Vge>Vth), thereby substantially eliminating a hole extraction path in the region between the active trench 4 and the dummy trench 40. This explains the excellent Vce-sat of the IGBT, which in the area laterally on top between the dummy trench 40 and the active trench 4 (i.e., without dummy contacts) is very close to the Vce-sat of the IGBT without electrical contact of the semiconductor body to the main electrode.

[0080] In short, the electrical contact to the main electrode 2 in the region between the active trench 4 and the dummy trench 40 is effectively invisible during the IGBT on-state, as desired to maintain plasma density.

[0081] 9 shows simulated hole current flow lines during on-state operation of the IGBT according to FIG. 5, and FIG. 10 shows simulated hole current flow lines for the reference IGBT according to FIG. 6. The density of the contour lines is proportional to the hole current. In FIGS. 9 and 10, Vce is selected to be 3 V, and it can be seen that the IGBT according to FIGS. 5 and 9 significantly suppresses the flow of hole current between the active trench 4 and the dummy trench 40.

[0082] Figure 11 shows the simulated hole current in the second contact region versus voltage Vce during on-state operation of the IGBT according to Figure 5 (curve 100) and the reference IGBT (curve 200). It can be seen that for the IGBT according to Figure 5, a reduction of about 50% in the hole current can be achieved in the on-state.

[0083] Figure 12 shows a simulation of Ic vs. Vce for Vge = -15 V. It can be seen that the blocking capabilities of the IGBT according to Figure 5 (curve 100) and the reference IGBT according to Figure 6 (curve 200) are almost the same.

[0084] FIG. 13 shows simulated turn-off switching characteristics of the IGBT according to FIG. 5 (curve 100_i) and the reference IGBT according to FIG. 6 (curve 200_i). Curves 100_1 and 200_1 show Vce versus time T, curves 100_2 and 200_2 show Vge versus time T, and curves 100_3 and 200_3 show Ic versus time T. The turn-off switching loss Eoff of the IGBT according to FIG. 5 is very close to the turn-off switching loss Eoff of the reference IGBT according to FIG. 6. It should also be noted that Eoff of the IGBT according to FIG. 5 is lower than that of the reference IGBT, which has no electrical contact with the main electrodes in the region between the trenches (see table below). This means that the PMOS transistor, which prevents holes from leaving in the on-state, is now active in the IGBT off-state and is effective in extracting holes from the IGBT device, thereby reducing its switching loss. In other words, the contact to the main electrode in the region between the dummy trench and the active trench, which was effectively invisible during the IGBT on-state, is visible during the IGBT off-state as desired to simultaneously improve on-state and switching losses.

[0085] Figure 14 shows a simulation of the turn-on switching characteristics using the same naming convention as in Figure 13. The IGBT according to Figure 5 shows lower turn-on losses Eon due to lower gate-emitter capacitance Cge compared to the reference IGBT of Figure 6. However, the total losses E total , i.e., E rec +E on (where E rec is the diode reverse recovery loss) remains the same (see table below).

[0086] FIG. 15 shows the simulated technology curve (E) at 25°C of the IGBT according to FIG. 5 (curve 100) compared to the reference IGBT according to FIG. 6 (curve 200). off Against V ce-sat ) is shown. The IGBT according to Figure 5 has a superior technology curve compared to the reference IGBT. ce-sat For the same E, the IGBT according to Fig. 5 shows an Eoff that is 18% lower than that of the reference IGBT. off Regarding the V of the IGBT according to Figure 5, ce-sat is 5% lower than that of the reference IGBT.

[0087] The table below shows a summary of the simulation results for an IGBT according to FIG. 5 (row 100) compared to a reference IGBT according to FIG. 6 (row 200) and compared to an IGBT according to FIG. 6 but without electrical contact of the main electrode to the semiconductor body in the region between the active trench 4 and the dummy trench 40 (row 300), i.e. without dummy contacts.

[0088] [Table 1]

[0089] 16 shows a further exemplary embodiment of the semiconductor device 100 similar to that of FIG. 3. However, in contrast to the exemplary embodiment of FIG. 3, a first enhancement region 16 is disposed between the drift layer 11 and the first base region 12. The first enhancement region 16 is of the first conductivity type, i.e., n-doped, and has a higher doping concentration than the drift layer 11, for example at least 10 times higher. The enhancement region 16 improves on-state losses or Vce-sat by reducing hole leakage.

[0090] 17 shows an example of an IGBT similar to that of FIG. 16, but with second enhancement regions 17 of the second conductivity type, i.e., p-doped, vertically disposed between the second base region 13 and the drift layer 11. These enhancement regions 17 reduce electron leakage through the electrical contact to the second contact region 15 of the main electrode 2 and improve hole collection during turn-off.

[0091] FIG. 18 illustrates an exemplary embodiment similar to that of FIG. 4, but further comprising a first enhancement region 16 between the first base region 12 and the drift layer 11.

[0092] The exemplary embodiment of Figure 19 is similar to that of Figure 18, except that in the active trench 4, the electrical isolation layer 5 is thicker between the gate electrode 3 and the first contact region 14 than between the second contact region 15 and the gate electrode 3. This design can reduce the Vth of the PMOS transistor, allowing it to turn on earlier during the IGBT off-state, to further reduce switching losses. In turn, the doping concentration of the second base region 13 can be further increased to reduce hole leakage due to diffusion in the IGBT on-state.

[0093] 20 , the first contact region 14 extends in the first lateral direction L1 across the entire lateral extent of the first base region 12. In other words, the first contact region 14 extends in the first lateral direction L1 from one active trench 4 to the next active trench 4. This makes it possible to completely suppress the hole path from the drift layer 11 to the main electrode 2 via the first base region 12.

[0094] 21, the second contact region 15 has the same lateral extent in the first lateral direction L1 as the second base region 13. In other words, the second contact region 15 extends in the first lateral direction L1 from each active trench 4 to the next dummy trench 40.

[0095] The exemplary embodiment of Figure 22 is similar to that of Figure 21. However, here, the trenches on either side of the second base region 13 are active trenches 4. In this embodiment, PMOS transistors are formed in both active trenches 4 adjacent to each second base region 13.

[0096] 23 shows an example embodiment similar to that of FIG. 22, but with additional dummy trenches 40 sandwiching the four active trenches 4 in the first lateral direction L1. An additional second base region 13 is formed between the dummy trenches 40 and the active trenches 4. The addition of the dummy trenches 40 can further reduce the Miller capacitance Cgc.

[0097] 24, in contrast to FIG. 23, second contact regions 15 are formed in the further second base region 13. The main electrode 2 may also be in electrical contact with these second contact regions 15.

[0098] 25, the second base region 13 is formed only between the active trench 4 and the dummy trench 40. A third base region 18 of the second conductivity type is formed on the other side of the dummy trench 40. The dummy trench 40 and the active trench 4 extend deeper into the semiconductor body 1 than the base regions 12, 13, 18.

[0099] The exemplary embodiment of Figure 26 shows a planar IGBT 100 similar to that of Figure 2. Again, an enhancement region 16 of the first conductivity type is disposed between the first base region 12 and the drift layer 11.

[0100] FIG. 31 shows an exemplary embodiment of a planar IGBT 100 having a non-uniform thickness of the electrical isolation layer 5 to reduce gate capacitance.

[0101] 27 shows an exemplary embodiment of the semiconductor device 100 in a plan view of the top surface 10. As can be seen, the base regions 12, 13 and the contact regions 14, 15 are elongated and in each case have a main direction of extension parallel to a second lateral direction L2 that is perpendicular to the first lateral direction L1.

[0102] 28, multiple first contact regions 14 are embedded in the same first base region 12. These first contact regions 14 are arranged one after the other and spaced apart from each other in the second lateral direction L2.

[0103] 29, a plurality of second contact regions 15 are embedded in the second base region 13. The second contact regions 15 are arranged one after the other and spaced apart from each other in the second lateral direction L2. Unlike what is shown in FIG. 29, the first contact regions 14 do not need to be located exactly opposite the second contact regions 15, and may be arranged in a staggered configuration.

[0104] In contrast to what is shown in the exemplary embodiment, the thickness (depth) of the first base region 12 and the second base region 13 can be different from each other, and the spacing between the trenches 4, 40 can be different from each other.

[0105] FIG. 30 shows a flow chart of an exemplary embodiment of a method for manufacturing a semiconductor device.

[0106] In step S1, a semiconductor body is provided having a top surface and a drift layer of a first conductivity type. In further steps S2, S3, S4, and S5, a first base region, a second base region, a first contact region, and a second contact region are fabricated. The first base region is of a second conductivity type and is fabricated such that the first base region is located vertically between the drift layer and the top surface. The second base region is of the first conductivity type and is fabricated such that the second base region is located vertically between the drift layer and the top surface, the second base region having a higher doping concentration than the drift layer and adjacent to the drift layer. The first contact region is of the first conductivity type and is fabricated such that the first contact region is adjacent to the first base region and the top surface. The second contact region is of the second conductivity type and is fabricated such that the second contact region is adjacent to the second base region and the top surface. In a further step S6, a main electrode is applied to the top surface and electrical contact is established between the main electrode and the first contact region and between the main electrode and the second contact region. In a further step S7, a gate electrode is formed such that the gate electrode is finally located in a first lateral direction between the first and second contact regions and between the first and second base regions.

[0107] The embodiments shown in the above-described figures represent exemplary embodiments of the improved semiconductor devices and improved methods for manufacturing the semiconductor devices, and therefore, they do not constitute an exhaustive list of all embodiments of the improved semiconductor devices and improved methods. Actual semiconductor devices and methods may differ from the illustrated embodiments, for example, with respect to the arrangement and elements. [Explanation of symbols]

[0108] Reference sign 1. Semiconductor body 2 Main electrode 3. Gate electrode 4 Active Trench 5 Electrical isolation materials 6 Further main electrodes 10 Top side 11 Drift layer 12 First base region 13 Second base region 14 first contact region 15 Second contact area 16 First Enhancement Region 17 Second Enhancement Region 18 Third base region 19 layers 20 layers 40 Dummy Trench 100 Semiconductor Devices 200 Reference Semiconductor Devices Si method steps L1 First lateral direction L2 Second lateral V vertical direction 100_i curve label 200_i curve label

Claims

1. a semiconductor body (1) having a top surface (10) and a back surface; a main electrode (2) on said upper surface (10); a further main electrode (6) on the rear surface; Gate electrode (3) and A bipolar semiconductor device (100) comprising: The semiconductor body (1) a drift layer (11) of a first conductivity type; a first base region (12) of a second conductivity type vertically disposed between the drift layer (11) and the upper surface (10); a second base region (13) of the first conductivity type vertically disposed between the drift layer (11) and the upper surface (10), the second base region (13) having a doping concentration higher than that of the drift layer (11) and adjacent to the drift layer (11); a first contact region (14) of the first conductivity type adjacent to the first base region (12) and the top surface (10); a second contact region (15) of the second conductivity type adjacent to the second base region (13) and the top surface (10); Equipped with the main electrode (2) is in electrical contact with the first contact area (14) and the second contact area (15); In a first lateral direction (L1), at least a part of the gate electrode (3) is arranged between the first contact region (14) and the second contact region (15) and between the first base region (12) and the second base region (13); A semiconductor device (100), wherein a thickness of an insulating material (5) between the first contact region (14) and / or the first base region (12) and the gate electrode (3) is greater than a thickness of an insulating material (5) between the second contact region (15) and / or the second base region (13) and the gate electrode (3).

2. The semiconductor device (100) is configured such that, by setting the potential of the gate electrode (3), a zone of the first base region (12) is inverted by the gate electrode (3) and allows a current flow of a first type of charge carriers between the drift layer (11) and the first contact region (14) through this zone, or Alternatively, a zone of the second base region (13) is inverted by the gate electrode (3) and allows a current flow of second type charge carriers between the drift layer (11) and the second contact region (15) through this zone. The semiconductor device according to claim 1 , configured as follows:

3. The semiconductor device (100) of claim 1 or 2, wherein the semiconductor device (100) is a planar device and the gate electrode (3) is arranged on the top surface (10).

4. 3. The semiconductor device (100) according to claim 1 or 2, wherein the semiconductor device (100) is a trench device, and the gate electrode (3) is arranged in an active trench (4) extending vertically (V) from the top surface (10) into the semiconductor body (1).

5. Further comprising at least one dummy trench (40) arranged adjacent to the active trench (4) in the first lateral direction (L1) and spaced apart from the active trench (4); The semiconductor device (100) of claim 4, wherein the dummy trench (40) is filled with a conductive material electrically connected to the main electrode (2).

6. an enhancement region (16) of the first conductivity type vertically disposed between the first base region (12) and the drift layer (11); The semiconductor device (100) of claim 1 or 2, wherein the enhancement region (16) has a higher doping concentration than the drift layer (11).

7. 3. The semiconductor device (100) of claim 1, wherein a third base region (18) of the second conductivity type is arranged adjacent to the second base region (13) in the first lateral direction (L1) such that the second base region (13) is arranged between the first (12) and third (18) base regions in the first lateral direction (L1).

8. The semiconductor device (100) is a trench device, wherein the gate electrode (3) is disposed in an active trench (4) extending vertically (V) from the top surface (10) into the semiconductor body (1); 8. The semiconductor device (100) of claim 7, wherein the third base region (18) extends from the top surface (10) into the semiconductor body (1) deeper into the semiconductor body (1) than the active trench (4).

9. 3. The semiconductor device (100) of claim 1 or 2, wherein the main electrode (2) is not in direct electrical contact with the second base region (13).

10. further comprising a further gate electrode (3) spaced apart from the gate electrode (3) in the first lateral direction (L1); the second base region (13) is arranged between the gate electrode (3) and the further gate electrode (3) in the first lateral direction (L1), 3. The semiconductor device (100) of claim 2, wherein the semiconductor device (100) is configured such that by setting the potential of the further gate electrode (3), a zone of the second base region (13) is inverted by the further gate electrode (3), the zone being located on a side of the second base region (13) opposite to a side of the second base region (13) on which the zone of the second base region (13) is inverted by the gate electrode (3), thereby providing a current path on this opposite side.

11. 3. The semiconductor device (100) of claim 1 or 2, wherein the first (14) and / or second (15) contact regions are elongated regions extending in a second lateral direction (L2) that is oblique to the first lateral direction (L1).

12. a number of first contact regions (14) adjacent to said top surface (10) and said first base region (12) and in electrical contact with said main electrode (2), said first contact regions (14) being separated and spaced apart from one another in a second lateral direction (L2) oblique to said first lateral direction (L1); and / or 3. The semiconductor device (100) according to claim 1, further comprising a number of second contact regions (15) adjacent to the top surface (10) and the second base region (13) and in electrical contact with the main electrode (2), the second contact regions (15) being separated and spaced apart from one another in a second lateral direction (L2) oblique to the first lateral direction (L1).

13. The semiconductor device (100) of claim 1 or 2, wherein the semiconductor device (100) is an IGBT.

14. A method for manufacturing a bipolar semiconductor device (100), comprising: Providing a semiconductor body (1) having a top surface (10), a back surface and a drift layer (11) of a first conductivity type; a first base region (12) of a second conductivity type, the first base region (12) being positioned vertically between the drift layer (11) and the upper surface (10); a second base region (13) of the first conductivity type, the second base region (13) being positioned vertically between the drift layer (11) and the upper surface (10), the second base region (13) having a higher doping concentration than the drift layer (11), and adjacent to the drift layer (11); a first contact region (14) of the first conductivity type, the first contact region (14) adjacent to the first base region (12) and the top surface (10); a second contact region (15) of the second conductivity type, the second contact region (15) being adjacent to the second base region (13) and the top surface (10); and applying a main electrode (2) to said top surface (10) and establishing electrical contact between said main electrode (2) and said first contact area (14) and between said main electrode (2) and said second contact area (15); applying a further main electrode to said back surface; forming a gate electrode (3) so that at least a portion of the gate electrode (3) is ultimately located between the first contact region (14) and the second contact region (15) and between the first base region (12) and the second base region (13) in a first lateral direction (L1); Including, The method, wherein a thickness of an insulating material (5) between the first contact region (14) and / or the first base region (12) and the gate electrode (3) is greater than a thickness of an insulating material (5) between the second contact region (15) and / or the second base region (13) and the gate electrode (3).

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