Semiconductor Devices

Abstract

To provide a transistor with high yield, which has high electrical characteristics though having a fine structure; and achieve high performance, high reliability and high productivity in a semiconductor device including the transistor.SOLUTION: In a semiconductor device which has a transistor in which an oxide semiconductor film including a channel formation region and low-resistance regions sandwiching the channel formation region, a gate insulation film and a gate electrode layer with an insulation film including an aluminum oxide film which covers a top face and lateral faces are sequentially laminated, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor film and a top face and part of lateral faces of the insulation film including the aluminum oxide film.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] A transistor (thin film transistor) is made using a semiconductor thin film formed on a substrate with an insulating surface. The technology of constructing thin-film transistors (also called TFTs) is attracting attention. It is widely used in electronic devices such as ICs and image display devices. Silicon-based semiconductor materials are widely known as semiconductor thin films that can be applied to transistors. Another material that has attracted attention is oxide semiconductors.

[0004] For example, amorphous silicon containing indium (In), gallium (Ga), and zinc (Zn) A transistor using a semiconductor layer made of oxide (In-Ga-Zn-O amorphous oxide) A resistor is disclosed in Patent Document 1. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-181801 Summary of the Invention [Problem to be solved by the invention]

[0006] By the way, in order to achieve high speed operation of transistors, low power consumption of transistors, high integration, etc. To achieve this, miniaturization of transistors is essential.

[0007] To realize higher performance semiconductor devices, the on-characteristics of miniaturized transistors (e.g. By improving the on-state current and field effect mobility, we can realize high-speed response and high-speed operation of semiconductor devices. It is an object of the present invention to provide a structure and a manufacturing method thereof.

[0008] Furthermore, there is a concern that the yield in the manufacturing process will decrease as transistors become smaller.

[0009] Providing transistors with high electrical characteristics and reliability with a high yield even in microstructures One of the purposes of this project is to provide

[0010] Furthermore, semiconductor devices including the transistors also have improved performance, reliability, and productivity. One of the objectives is to achieve [Means for solving the problem]

[0011] An insulating film including an oxide semiconductor film, a gate insulating film, and an aluminum oxide film covering the top and side surfaces In a semiconductor device having a transistor in which gate electrode layers each having a film thereon are stacked in order, The source electrode layer and the drain electrode layer are formed of an insulating material including an oxide semiconductor film and an aluminum oxide film. The oxide semiconductor film is provided in contact with a top surface and a part of a side surface of the insulating film. Preferably, the channel forming region is sandwiched between low resistance regions.

[0012] The top and side surfaces of the gate electrode layer are covered with an insulating film containing an aluminum oxide film. Even if the source electrode layer and the drain electrode layer overlap with the top surface of the gate electrode layer, the aluminum oxide film The insulating film containing the insulating film prevents short-circuiting between the source electrode layer or the drain electrode layer and the gate electrode layer. Electrical defects can be prevented, and therefore the yield of transistors having fine structures can be improved. It can be produced more efficiently.

[0013] In addition, in the semiconductor device, oxygen is introduced into the oxide semiconductor film in a manufacturing process. The upper and side surfaces of the gate electrode layer are covered with an aluminum oxide film. By covering the gate electrode layer with an insulating film containing The insulating film may be formed by covering a part of the insulating film containing an aluminum oxide film. can be done.

[0014] The insulating film containing the aluminum oxide film is resistant to both impurities such as hydrogen and moisture, and oxygen. It has a high blocking effect that prevents substances from passing through the membrane.

[0015] Therefore, the insulating film including the aluminum oxide film is subject to fluctuations during and after the manufacturing process. The incorporation of impurities such as hydrogen and moisture into the oxide semiconductor film and the formation of the oxide semiconductor It functions as a protective film that prevents oxygen, which is a main component material, from being released from the oxide semiconductor film. This allows the transistor to have stable electrical characteristics.

[0016] The oxide semiconductor film is formed by adding oxygen (at least any of oxygen radicals, oxygen atoms, and oxygen ions). The oxygen is supplied to the film by introducing oxygen into the film. Ion doping method, plasma immersion ion implantation method, plasma treatment Theories, etc. can be used.

[0017] Further, a dopant is introduced into the oxide semiconductor film in a self-aligned manner using the gate electrode layer as a mask; In the oxide semiconductor film, the resistance between the channel formation region and the drain region is lower than that of the channel formation region. A low-resistance region containing a dopant is formed. The dopant changes the conductivity of the oxide semiconductor film. The dopant is introduced by ion implantation and ion doping. , plasma immersion ion implantation, etc. can be used.

[0018] The present invention provides a semiconductor device having an oxide semiconductor film including a low-resistance region sandwiching a channel formation region in a channel length direction. As a result, the transistor has high on-state characteristics (for example, on-state current and field-effect mobility), High-speed operation and high-speed response are possible.

[0019] One embodiment of the invention disclosed in this specification is a semiconductor device including an oxide semiconductor film provided over an oxide insulating film. a gate insulating film over the oxide semiconductor film; and a gate insulating film overlapping with the channel formation region. a gate electrode layer; and an insulating film including an aluminum oxide film covering an upper surface and a side surface of the gate electrode layer. , the oxide semiconductor film, and the insulating film including the aluminum oxide film. The semiconductor device has a wiring layer.

[0020] One embodiment of the invention disclosed in this specification is a channel forming insulating film provided on an oxide insulating film. an oxide semiconductor film including a low-resistance region and a channel formation region sandwiched therebetween; a gate insulating film on the channel forming region, a gate electrode layer on the gate insulating film overlapping the channel forming region, and a gate electrode layer on the gate insulating film overlapping the channel forming region. an insulating film including an aluminum oxide film covering the top and side surfaces of the gate electrode layer; a low resistance region; and and a wiring layer in contact with the upper surface and part of the side surface of the insulating film containing the aluminum oxide film. The resist region is a semiconductor device that contains dopants.

[0021] One embodiment of the invention disclosed in this specification is a semiconductor device including an oxide semiconductor film provided over an oxide insulating film. a gate insulating film over the oxide semiconductor film; and a gate insulating film overlapping with the channel formation region. a gate electrode layer; and an insulating film including an aluminum oxide film covering an upper surface and a side surface of the gate electrode layer. an insulating film including an oxide semiconductor film, a gate insulating film, a gate electrode layer, and an aluminum oxide film; An interlayer insulating layer having an opening reaching the oxide semiconductor film formed thereon, and an oxide semiconductor film formed in the opening. Wiring contacting a part of the top surface and side surface of an insulating film including a semiconductor film and an aluminum oxide film The semiconductor device has a layer.

[0022] One embodiment of the invention disclosed in this specification is a channel forming insulating film provided on an oxide insulating film. an oxide semiconductor film including a low-resistance region and a channel formation region sandwiched therebetween; a gate insulating film on the channel forming region, a gate electrode layer on the gate insulating film overlapping the channel forming region, and a gate electrode layer on the gate insulating film overlapping the channel forming region. an insulating film including an aluminum oxide film covering the top surface and side surfaces of a gate electrode layer; an oxide semiconductor film; A low resistance region is formed on an insulating film including a gate insulating film, a gate electrode layer, and an aluminum oxide film. an interlayer insulating layer having an opening extending to the insulating layer, a low resistance region formed in the opening, and an aluminum oxide film; and a wiring layer contacting a part of the upper surface and side surface of the insulating film including the aluminum film. The semiconductor device includes a power supply.

[0023] The oxide semiconductor film overlaps with the gate electrode layer and the insulating film including the aluminum oxide film. The region is higher than a region that does not overlap with the gate electrode layer and the insulating film including the aluminum oxide film. It may also be configured to have an oxygen concentration.

[0024] In one embodiment of the invention disclosed in this specification, an oxide insulating film is formed, and an oxide insulating film is formed on the oxide insulating film. a gate insulating film is formed on the oxide semiconductor film; and an oxide semiconductor film is formed on the gate insulating film. A gate electrode layer is formed on the oxide semiconductor film, and an oxide film is formed on the gate electrode layer to cover the top and side surfaces of the gate electrode layer. an insulating film including an aluminum film is formed, and This is a method for manufacturing a semiconductor device in which a wiring layer is formed in contact with the upper surface and part of the side surface of an insulating film.

[0025] In one embodiment of the invention disclosed in this specification, an oxide insulating film is formed, and an oxide insulating film is formed on the oxide insulating film. a gate insulating film is formed on the oxide semiconductor film; and an oxide semiconductor film is formed on the gate insulating film. A gate electrode layer is formed on the oxide semiconductor film, and the gate electrode layer is used as a mask to form a gate electrode layer on the oxide semiconductor film. A dopant is selectively introduced into the film to form a low resistance region, and the top and side surfaces of the gate electrode layer are forming an insulating film including an aluminum oxide film covering the low resistance region and the aluminum oxide film; a method for manufacturing a semiconductor device in which a wiring layer is formed in contact with a part of the upper surface and side surface of an insulating film including the insulating film; do.

[0026] In one embodiment of the invention disclosed in this specification, an oxide insulating film is formed, and an oxide insulating film is formed on the oxide insulating film. a gate insulating film is formed on the oxide semiconductor film; and an oxide semiconductor film is formed on the gate insulating film. A gate electrode layer is formed on the oxide semiconductor film, and the gate electrode layer is covered with an oxide film on the top and side surfaces. An insulating film including an aluminum film is formed, and an oxide semiconductor film, a gate insulating film, a gate electrode layer, and an interlayer insulating layer is formed on the insulating film including the oxide semiconductor film and the aluminum oxide film; and forming an opening that exposes a portion of the top surface and side surface of the insulating film including the aluminum oxide film. The opening is provided with an oxide semiconductor film and an insulating film including an aluminum oxide film. This is a method for manufacturing a semiconductor device in which a wiring layer is formed in contact with a part of the semiconductor device.

[0027] In one embodiment of the invention disclosed in this specification, an oxide insulating film is formed, and an oxide insulating film is formed on the oxide insulating film. a gate insulating film is formed on the oxide semiconductor film; and an oxide semiconductor film is formed on the gate insulating film. A gate electrode layer is formed on the oxide semiconductor film, and the gate electrode layer is used as a mask to form a gate electrode layer on the oxide semiconductor film. A dopant is selectively introduced into the film to form a low resistance region, and the top and side surfaces of the gate electrode layer are An insulating film including an aluminum oxide film is formed to cover the oxide semiconductor film, the gate insulating film, and the gate An interlayer insulating layer is formed on the electrode layer and the insulating film including the aluminum oxide film, and a low-temperature insulating film is formed on the interlayer insulating layer. An opening exposing a resistor region and a part of the top and side surfaces of an insulating film including an aluminum oxide film and forming a low resistance region and an upper surface and a side surface of the insulating film including the aluminum oxide film in the opening. The present invention relates to a method for manufacturing a semiconductor device, in which a wiring layer is formed in contact with a part of the semiconductor device.

[0028] In the above structure, the gate insulating film is etched using the gate electrode layer as a mask to oxidize the gate insulating film. An insulating film including an aluminum film may be in contact with the oxide semiconductor film. A gate insulating film may be provided between the insulating film containing a tungsten film and the oxide semiconductor film. .

[0029] In the above structure, a wiring layer (a source electrode layer or An electrode layer overlapping with the drain electrode layer may be provided. The electrode layer may be provided over the oxide insulating film. Alternatively, the insulating film may be embedded in an oxide insulating film.

[0030] Under the oxide semiconductor film, a wiring layer (source electrode layer or drain electrode layer) and the oxide semiconductor film By providing an electrode layer in the contact region, the source electrode layer and the drain electrode layer The contact resistance between the wiring layer, which functions as an insulating electrode layer, and the oxide semiconductor film can be reduced. Therefore, the on-state characteristics of the transistor can be improved.

[0031] In the above structure, the surface of the oxide insulating film on which the oxide semiconductor film is formed is flattened by planarization treatment. A thin oxide semiconductor film can be provided with good coverage. The process involves chemical mechanical polishing, etching, plasma treatment, etc., either alone or in combination. It can be used in combination.

[0032] Further, a heat treatment (dehydration or dehydrogenation treatment) for releasing hydrogen or moisture from the oxide semiconductor film may be performed. In addition, when a crystalline oxide semiconductor film is used as the oxide semiconductor film, Heat treatment for crystallization may be carried out.

[0033] One embodiment of the present invention is a transistor or a circuit including a transistor. For example, the present invention relates to a semiconductor device, a transistor in which a channel formation region is formed of an oxide semiconductor, The present invention relates to a semiconductor device having a circuit including a transistor. , LSI, CPU, power devices mounted on power supply circuits, memory, thyristors, converters, semiconductor integrated circuits including image sensors, and electronic devices such as liquid crystal display panels. The present invention relates to electronic equipment that incorporates, as a component, a light-emitting display device having an electro-optical device or a light-emitting element. [Effects of the Invention]

[0034] Providing transistors with high electrical characteristics and reliability with a high yield even in microstructures It can be provided.

[0035] Furthermore, semiconductor devices including the transistors also have improved performance, reliability, and productivity. This can be achieved. [Brief explanation of the drawings]

[0036] [Figure 1] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 2] 1A to 1C are cross-sectional views illustrating one embodiment of a method for manufacturing a semiconductor device. [Figure 3] 1A and 1B are cross-sectional views illustrating one embodiment of a semiconductor device. [Figure 4] 1A and 1B are cross-sectional views illustrating one embodiment of a semiconductor device. [Figure 5] 1A and 1B are a plan view and a cross-sectional view illustrating one embodiment of a semiconductor device. [Figure 6] 1A to 1C are a cross-sectional view, a plan view, and a circuit diagram illustrating one embodiment of a semiconductor device. [Figure 7] 1A and 1B are a circuit diagram and a perspective view illustrating one embodiment of a semiconductor device. [Figure 8] 1A and 1B are a cross-sectional view and a plan view illustrating one embodiment of a semiconductor device. [Figure 9] FIG. 1 is a circuit diagram illustrating one embodiment of a semiconductor device. [Figure 10] FIG. 1 is a block diagram illustrating one embodiment of a semiconductor device. [Figure 11] FIG. 1 is a block diagram illustrating one embodiment of a semiconductor device. [Figure 12] FIG. 1 is a block diagram illustrating one embodiment of a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0037] Hereinafter, embodiments of the invention disclosed in this specification will be described in detail with reference to the accompanying drawings. However, the invention disclosed in this specification is not limited to the following description, and various forms and details may be used. It will be readily understood by those skilled in the art that the invention disclosed in this specification can be modified in any manner. The present invention is not limited to the following embodiments. The ordinal numbers such as 2 are used for convenience and do not indicate the order of processes or stacking. Furthermore, in this specification, no specific name is given as a matter for identifying the invention. do not have.

[0038] (Embodiment 1) In this embodiment mode, one mode of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. In this embodiment, a transistor including an oxide semiconductor film is used as an example of a semiconductor device. Shows.

[0039] The transistor may have a single gate structure in which one channel formation region is formed, or two gate structures in which two channel formation regions are formed. The gate structure may be a double gate structure in which three gates are formed, or a triple gate structure in which three gates are formed. The semiconductor device has two gate electrode layers arranged above and below the channel forming region with a gate insulating film interposed therebetween. A dual gate type may also be used.

[0040] The transistor 440a shown in FIGS. 1A and 1B is a top-gate transistor. FIG. 1(A) is a plan view of the device taken along the dashed line X1-Y1 in FIG. 1(A). The cross section corresponds to FIG. 1(B). Note that the interlayer insulating film 415 is omitted in FIG. 1(A). are.

[0041] As shown in FIG. 1B, which is a cross-sectional view in the channel length direction, a semiconductor device including a transistor 440a The semiconductor device is formed by depositing a channel on a substrate 400 having an insulating surface provided with an oxide insulating film 436. a gate electrode forming region 409; an oxide semiconductor film 403 including low-resistance regions 404a and 404b; The insulating film 402, the gate electrode layer 401, and the aluminum oxide film covering the top and side surfaces of the gate electrode layer 401 are The insulating film 414 including a aluminum film, the interlayer insulating film 415, the source electrode layer 405a, the drain electrode It has a pole layer 405b.

[0042] The interlayer insulating film 415 is provided to flatten the unevenness caused by the transistor 440a. , low resistance regions 404a and 404b, an insulating film 414 including an aluminum oxide film, and a gate insulating film The low-resistance region 4 of the oxide semiconductor film 403 is exposed through the opening. 404a, 404b, the gate insulating film 402, and the insulating film 414 including the aluminum oxide film. A source electrode layer 405a and a drain electrode layer 405b are provided in contact with the top surface and part of the side surface of the semiconductor substrate. It is being used.

[0043] In this embodiment, an aluminum oxide film is used as the insulating film 414 containing an aluminum oxide film. The aluminum oxide film is made of high density (film density 3.2 g / cm 3 Above 3.6, preferably 3.6 g / cm 3 By setting the temperature to 1000 .mu.m or more, the transistor 440a can have stable electrical characteristics. The film density can be measured by Rutherford backscattering spectroscopy (RBS). Backscattering Spectrometry and X-ray reflectometry (X It can be measured by X-Ray Reflection (RR). The aluminum film has oxygen in the film (bulk) in an amount exceeding the stoichiometric ratio. For example, when an aluminum oxide film is used, AlO x (however, x>1.5).

[0044] The top and side surfaces of the gate electrode layer 401 are covered with an insulating film 414 containing an aluminum oxide film. Therefore, the source electrode layer 405a and the drain electrode layer 405b are formed on the gate electrode layer 401. The insulating film 414 including the aluminum oxide film prevents the source electrode layer 405a from overlapping the surface. Alternatively, an electrical defect such as a short circuit between the drain electrode layer 405b and the gate electrode layer 401 can be prevented. Therefore, the transistor 440a having a fine structure can be manufactured with high yield. It is possible.

[0045] The insulating film including the aluminum oxide film may have a structure that covers the top and side surfaces of the gate electrode layer. Alternatively, the gate insulating film may be formed over the gate insulating film as in the transistor 440a. For example, a transistor 410a shown in FIG. Then, the gate insulating film 402 is etched using the gate electrode layer 401 as a mask, and the gate electrode An aluminum oxide film is formed on the top and side surfaces of the stack of the layer 401 and the gate insulating film 402. The transistor 410a may have a structure in which the insulating film 414 containing an oxide is provided. The compound semiconductor film 403 and the insulating film 414 including the aluminum oxide film are in contact with each other.

[0046] The insulating film including the aluminum oxide film covering the top and side surfaces of the gate electrode layer is formed as shown in FIG. A continuous single membrane can be used as shown in Fig. 1. Alternatively, multiple membranes can be used, e.g. For example, as in a transistor 410b shown in FIG. 3B, The insulating films 414a and 414b including the aluminum oxide film and the upper surface of the gate electrode layer 401 Alternatively, a structure may be adopted in which a plurality of insulating films 414c including an aluminum oxide film covering the insulating film 414c are provided. .

[0047] In addition, in the manufacturing process of the semiconductor device, the oxide semiconductor film 403 is oxygen radicals, oxygen atoms, or oxygen ions) are introduced to supply oxygen into the film. The oxygen introduction method includes ion implantation, ion doping, plasma immersion, and The ion implantation method, plasma treatment, etc. can be used.

[0048] The oxide semiconductor film 403 provided in the transistor 440a is in a crystalline state. It is preferable that the film contains a region in which the oxygen content is excessive with respect to the stoichiometric composition in the film. In this case, the oxygen content is set to a level exceeding the stoichiometric ratio of the oxide semiconductor. Alternatively, the oxygen content is set to a level exceeding that in the case of a single crystal. Oxygen may be present between the atoms.

[0049] The upper surface and side surfaces of the gate electrode layer 401 are covered with an insulating film 414 including an aluminum oxide film. As a result, the channel formation region 4 of the oxide semiconductor film 403 overlapping with the gate electrode layer 401 is 09 and a part of the low resistance regions 404a and 404b are covered with an insulating film 41 containing an aluminum oxide film. 4 can be configured to cover it.

[0050] The insulating film 414 including the aluminum oxide film is resistant to both impurities such as hydrogen and moisture and oxygen. On the other hand, it has a high blocking effect that prevents it from passing through the membrane.

[0051] Therefore, the insulating film including the aluminum oxide film is subject to fluctuations during and after the manufacturing process. The incorporation of impurities such as hydrogen and moisture into the oxide semiconductor film and the formation of the oxide semiconductor It functions as a protective film that prevents oxygen, which is a main component material, from being released from the oxide semiconductor film. This allows the transistor 440a to have stable electrical characteristics.

[0052] Note that dopant is deposited on the oxide semiconductor film 403 in a self-aligned manner using the gate electrode layer 401 as a mask. The channel formation region 409 is sandwiched between the oxide semiconductor film 403 and the channel formation region 409. The resistivity of the dopant-containing low-resistance regions 404a and 404b is lower than that of the dopant-containing region 409. The dopant is an impurity that changes the conductivity of the oxide semiconductor film 403. The methods of introducing ions include ion implantation, ion doping, and plasma immersion ion implantation. For example, a ion implantation method can be used.

[0053] The channel formation region 409 is sandwiched between low resistance regions 404a and 404b in the channel length direction. By including the oxide semiconductor film 403, the transistor 440a has improved on-state characteristics (for example, , on-state current and field-effect mobility), enabling high-speed operation and high-speed response.

[0054] The oxide semiconductor used for the oxide semiconductor film 403 is at least indium (In). It is preferable that the material contains In or zinc (Zn). It is particularly preferable that the material contains In and Zn. and a stabilizer for reducing variations in electrical characteristics of a transistor using the oxide. It is preferable that the stabilizer further contains gallium (Ga). It is preferable to have tin (Sn) as a stabilizer. It is preferable to use aluminum (Al) as a stabilizer. It is preferable that the stabilizer contains zirconium (Zr). is preferred.

[0055] Other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Ru It may contain one or more of tetraethion (Te) and tetraethion (Tb).

[0056] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide are used. You can be there.

[0057] Here, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as its main components. The ratio of In, Ga, and Zn is not important. Metal elements other than a and Zn may be included.

[0058] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer) It is also possible to use a material represented by the formula: where M is selected from Ga, Fe, Mn, and Co. It refers to one or more metal elements. In addition, as an oxide semiconductor, In2SnO5 (ZnO) n A material expressed as (n>0 and n is an integer) may be used.

[0059] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3), In:Ga:Z n=2:2:1 (=2 / 5:2 / 5:1 / 5), or In:Ga:Zn=3:1:2 In-Ga-Zn oxides with atomic ratios of (=1 / 2:1 / 6:1 / 3) and their neighboring compositions Alternatively, an oxide of In:Sn:Zn=1:1:1 (=1 / 3: 1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or is In-Sn with an atomic ratio of In:Sn:Zn=2:1:5 (=1 / 4:1 / 8:5 / 8). It is preferable to use a -Zn-based oxide or an oxide having a composition close to that.

[0060] However, it is not limited to these, and the required semiconductor characteristics (mobility, threshold, variation, etc.) In addition, in order to obtain the required semiconductor characteristics, Carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. It is preferable to use an appropriate one.

[0061] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. Therefore, even in In-Ga-Zn oxides, the mobility can be increased by reducing the defect density in the bulk. It can be done.

[0062] For example, when the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of the oxide with c=1) is In:Ga:Zn=A:B:C (A+B+C = 1), the oxide composition is close to (aA) 2 +(bB) 2 + (cC) 2 ≦r 2 The value of r can be set to, for example, 0.05. The same applies to other oxides.

[0063] The oxide semiconductor film 403 may be single-crystalline, polycrystalline (also referred to as polycrystalline), or amorphous. Which state to take?

[0064] Preferably, the oxide semiconductor film is a CAAC-OS (C Axis Aligned Cr The film is a crystalline oxide semiconductor.

[0065] The CAAC-OS film is neither completely single crystalline nor completely amorphous. The oxide semiconductor film has a crystalline-amorphous mixed phase structure in which a crystalline portion is included in an amorphous phase. The crystal portion is often sized to fit within a cube with one side less than 100 nm. Transmission Electron Microscope (TEM) In the observation image using a microscope, the boundary between the amorphous and crystalline parts in the CAAC-OS film was The grain boundaries in the CAAC-OS film were not clearly observed by TEM. Therefore, the CAAC-OS film is not affected by electron transfer due to grain boundaries. The decrease in mobility is suppressed.

[0066] The crystal part included in the CAAC-OS film has a c-axis that is the normal vector of the surface on which the CAAC-OS film is formed. The triangle is aligned parallel to the normal vector of the hole or surface and perpendicular to the ab plane. The metal atoms are arranged in a layered or hexagonal shape when viewed perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. The orientation of the a and b axes may be different. The range of 5° to 95° is also included. This also includes the range of 10° to 5°.

[0067] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, The proportion of crystalline parts may be higher near the surface than near the growth surface. By adding impurities to the AC-OS film, the crystalline part in the impurity-doped region becomes amorphous. It may also be pawned.

[0068] The c-axis of the crystalline part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The CAAC-OS film shape (on which the film is formed) is Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface, they may face in different directions. The direction of the c-axis of the crystal is the normal vector of the surface on which the CAAC-OS film is formed. The direction of the crystal is parallel to the normal vector of the film or surface. is formed by carrying out a crystallization treatment such as a heat treatment after the film formation.

[0069] The electrical characteristics of a transistor using a CAAC-OS film change when irradiated with visible light or ultraviolet light. Therefore, the transistor has high reliability.

[0070] Note that part of oxygen contained in the oxide semiconductor film may be substituted with nitrogen.

[0071] In addition, in oxide semiconductors with crystalline parts such as CAAC-OS, defects in the bulk can be further reduced. By improving the surface flatness, the movement can be reduced more than that of an amorphous oxide semiconductor. To improve the surface flatness, it is necessary to deposit an oxide semiconductor on a flat surface. Specifically, it is preferable to form a surface having an average surface roughness (Ra) of 1 nm or less, preferably 0 It is preferable to form it on the surface with a thickness of 0.3 nm or less, more preferably 0.1 nm or less.

[0072] Ra is defined in JIS B 0601:2001 (ISO4287:1997). It is a three-dimensional extension of the arithmetic mean roughness that is currently used to measure curved surfaces. It can be expressed as "the average of the absolute values ​​of the deviations from the specified surface to the target surface" and is defined by the following formula.

[0073]

number

[0074] Here, the specified surface is the surface to be measured for roughness, and has coordinates (x1, y1, f(x1, y 1)),(x1,y2,f(x1,y2)),(x2,y1,f(x2,y1)),(x 2, y2, f(x2, y2)) and the specified surface is the xy plane. The area of ​​the projected rectangle is S0, and the height of the reference plane (average height of the specified plane) is Z0. was measured using an atomic force microscope (AFM). It is possible to determine.

[0075] The thickness of the oxide semiconductor film 403 is 1 nm to 30 nm (preferably 5 nm to 10 nm). m or less), and sputtering method, MBE (Molecular Beam Epita xy) method, CVD method, pulsed laser deposition method, ALD (Atomic Layer Deposition The oxide semiconductor film 403 can be formed by a spat Film deposition is performed with multiple substrate surfaces set approximately perpendicular to the target surface. Alternatively, the film may be formed using a sputtering apparatus that performs the above steps.

[0076] The CAAC-OS film can be formed by sputtering a polycrystalline oxide semiconductor target. The sputtering target is used to form a film by sputtering. Upon impact, the crystalline regions contained in the sputtering target cleave from the ab plane, forming a -b: Detached as flat or pellet-shaped sputtered particles with surfaces parallel to the plane In this case, the plate-like sputtered particles may be transferred to the substrate while maintaining their crystalline state. By reaching the plate, a CAAC-OS film can be formed.

[0077] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0078] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film formation chamber can be In addition, the impurity concentration in the deposition gas can be reduced. A deposition gas at a temperature of -80°C or lower, preferably -100°C or lower, is used.

[0079] In addition, by increasing the substrate heating temperature during film formation, the migration of sputtered particles after they reach the substrate is reduced. Specifically, the substrate heating temperature is set to 100°C or higher and 740°C or lower, preferably The film is formed at a temperature between 200°C and 500°C. When a plate-shaped sputtering particle reaches the substrate, migration occurs on the substrate, The flat surface of the sputtered particle adheres to the substrate.

[0080] In addition, increasing the oxygen ratio in the deposition gas and optimizing the power reduces plasma damage during deposition. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. The product is %.

[0081] As an example of a sputtering target, an In-Ga-Zn-O compound target is The following are the results:

[0082] InO X powder, GaO Y Powder and ZnO Z The powders are mixed in a specified number of moles and then pressurized. By heat treatment at a temperature between 1000℃ and 1500℃, polycrystalline In-Ga -Zn-O compound target, where X, Y, and Z are any positive numbers. , the predetermined molar ratio is, for example, InO X powder, GaO Y Powder and ZnO Z Powder, 2 :2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3 or 3:1:2. The type of powder and the molar ratio of the powder to be mixed depend on the sputtering target to be prepared. This can be changed as appropriate depending on the kit.

[0083] 2A to 2D show an example of a method for manufacturing a semiconductor device including a transistor 440a. vinegar.

[0084] First, an oxide insulating film 436 is formed over a substrate 400 having an insulating surface.

[0085] There is no significant limitation on the substrate that can be used for the substrate 400 having an insulating surface, but at least In either case, it is necessary to have heat resistance to the extent that it can withstand subsequent heat treatment. Glass substrates such as aluminoborosilicate glass and aluminoborosilicate glass, ceramic substrates, A quartz substrate, a sapphire substrate, etc. can be used. Also, silicon or silicon carbide substrates can be used. Any single crystal semiconductor substrate, polycrystalline semiconductor substrate, compound semiconductor substrate such as silicon germanium A substrate, an SOI substrate, or the like can also be used, and a semiconductor element is provided on such a substrate. may be used as the substrate 400.

[0086] Alternatively, a semiconductor device may be manufactured using a flexible substrate as the substrate 400. In order to manufacture such a semiconductor device, a transistor including an oxide semiconductor film 403 is formed over a flexible substrate. The transistor 440a may be directly formed, or the transistor including the oxide semiconductor film 403 may be formed on another substrate. The resistor 440a may be fabricated and then peeled off and transferred to a flexible substrate. In order to peel and transfer the transistor 4 including the oxide semiconductor film from the substrate to a flexible substrate, It is advisable to provide a release layer between the film 40a and the film 40b.

[0087] The oxide insulating film 436 is formed by a plasma CVD method, a sputtering method, or the like. Silicon, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide , gallium oxide, or a mixture of these materials.

[0088] The oxide insulating film 436 may be a single layer or a stacked layer. The In—Hf—Zn-based oxide film and the oxide semiconductor film 403 may be laminated in this order. 00, a silicon oxide film, and In-Zr-Zn with an atomic ratio of In:Zr:Zn=1:1:1 Alternatively, a silicon oxide film and an oxide semiconductor film 403 may be stacked in this order on the substrate 400. In-Gd-Zn oxide film with an atomic ratio of In:Gd:Zn=1:1:1, oxide The semiconductor films 403 may be stacked in order.

[0089] In this embodiment, the oxide insulating film 436 is formed by a silicon oxide film formed by a sputtering method. Use a con membrane.

[0090] Alternatively, a nitride insulating film may be provided between the oxide insulating film 436 and the substrate 400. The insulating film is made of silicon nitride or silicon oxynitride by plasma CVD or sputtering. It is formed using aluminum nitride, aluminum oxide nitride, or a mixture of these materials. It is possible.

[0091] Next, the oxide semiconductor film 403 is formed over the oxide insulating film 436.

[0092] The oxide insulating film 436 is in contact with the oxide semiconductor film 403 and therefore contains at least In both cases, the amount of oxygen contained in the oxide insulating film 43 preferably exceeds the stoichiometric ratio. When a silicon oxide film is used as 6, SiO 2+α (where α>0). By using such an oxide insulating film 436, oxygen can be supplied to the oxide semiconductor film 403. By supplying oxygen to the oxide semiconductor film 403, the characteristics can be improved. As a result, oxygen vacancies in the film can be compensated for.

[0093] For example, the oxide insulating film 436 containing a large amount (excessive amount) of oxygen, which serves as an oxygen supply source, is formed as an oxide semiconductor. By providing the oxide insulating film 436 in contact with the oxide semiconductor film 403, the oxide insulating film 436 3. By performing heat treatment in a state where the oxide semiconductor film 403 is at least partially in contact with the oxide semiconductor film 403, oxygen can be introduced into the oxide semiconductor film 403. Supply may be made.

[0094] In the step of forming the oxide semiconductor film 403, hydrogen or water is formed in the oxide semiconductor film 403. In order to prevent the inclusion of the oxide semiconductor film 403, a sputtering treatment was performed as a pretreatment for forming the oxide semiconductor film 403. The substrate on which the oxide insulating film 436 is formed is preheated in a preheating chamber of a plating apparatus. It is also preferable to desorb and exhaust impurities such as hydrogen and moisture adsorbed in the oxide insulating film 436. The exhaust means provided in the preheating chamber is preferably a cryopump.

[0095] A region of the oxide insulating film 436 which is in contact with the oxide semiconductor film 403 is subjected to planarization treatment. The planarization treatment is not particularly limited, but may be a polishing treatment (for example, a chemical polishing treatment). Mechanical polishing, dry etching, and plasma treatment can be used.

[0096] The plasma treatment may be, for example, a reverse plasma treatment in which argon gas is introduced to generate plasma. Reverse sputtering is a process in which RF is applied to the substrate side in an argon atmosphere. This method involves applying voltage using a power supply to generate plasma near the substrate, thereby modifying the surface. Instead of the argon atmosphere, nitrogen, helium, oxygen, etc. may be used. When the oxide insulating film 436 is subjected to the etching, powdery substances (particles, dust, etc.) attached to the surface of the oxide insulating film 436 are removed. (also called) can be removed.

[0097] As a planarization process, polishing, dry etching, and plasma treatment may be performed multiple times. In addition, when the steps are combined, there is no particular limitation on the order of the steps. The thickness is not limited to a specific value and may be set appropriately depending on the unevenness of the surface of the oxide insulating film 436.

[0098] The planarization treatment is performed by, for example, applying a chemical functional group to the surface of the silicon oxide film used as the oxide insulating film 436. The silicon oxide film surface is polished by mechanical polishing to an average surface roughness (Ra) of approximately 0 .15nm would be fine.

[0099] Note that the oxide semiconductor film 403 is formed under conditions in which a large amount of oxygen is contained (for example, under conditions in which oxygen (e.g., sputtering under a 100% oxygen atmosphere) (preferably, the oxide semiconductor has a stoichiometric composition in a crystalline state, and the content of oxygen is It is preferable to use a membrane containing regions in which the metal is in excess.

[0100] Note that in this embodiment, the oxide semiconductor film 403 is formed by a sputtering method. The target for this purpose is a gold alloy with a composition of In:Ga:Zn=3:1:2 [atomic ratio]. Using a metal oxide target, an In-Ga-Zn oxide film (IGZO film) is formed.

[0101] The relative density (filling rate) of the metal oxide target is preferably 90% or more and 100% or less. The relative density is 95% or more and 99.9% or less. Use a metal oxide target with a high relative density. As a result, the formed oxide semiconductor film can be a dense film.

[0102] The oxide semiconductor film 403 is formed using a sputtering gas containing hydrogen, water, a hydroxyl group, or It is preferable to use a high-purity gas from which impurities such as hydrides have been removed.

[0103] The substrate is held in a film-forming chamber that is kept in a reduced pressure state. Then, the remaining moisture in the film-forming chamber is removed. The sputtering gas from which hydrogen and moisture have been removed is introduced, and the substrate 40 is sputtered using the target. In order to remove residual moisture in the deposition chamber, an oxide semiconductor film 403 is formed on the substrate. type vacuum pumps, such as cryopumps, ion pumps, titanium sublimation pumps It is preferable to use a turbo molecular pump with a cold trap as the exhaust means. The deposition chamber evacuated using a cryopump may be, for example, Hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (preferably compounds containing carbon atoms) Since gases such as impurities are exhausted, the impurities contained in the oxide semiconductor film 403 formed in the deposition chamber are The concentration of substances can be reduced.

[0104] In addition, the oxide insulating film 436 and the oxide semiconductor film 403 are formed successively without exposure to the air. The oxide insulating film 436 and the oxide semiconductor film 403 are preferably connected without being exposed to air. When the oxide insulating film 436 is formed continuously, impurities such as hydrogen and moisture are adsorbed on the surface of the oxide insulating film 436. It can be prevented.

[0105] Next, oxygen (at least oxygen radicals, oxygen atoms, and oxygen ions) is added to the oxide semiconductor film 403. (including any one of the above) is introduced to supply oxygen to the oxide semiconductor film. These include ion implantation, ion doping, and plasma immersion ion implantation. The deposition method, plasma treatment, etc. can be used.

[0106] In the manufacturing process of the transistor 440a in this embodiment, the oxygen introduction step is performed by using an oxygen It is preferable to perform this process after the formation of the oxide semiconductor film 403 and before the formation of the gate electrode layer 401. Oxygen may be introduced into the oxide semiconductor film 403 multiple times.

[0107] In the step of introducing oxygen, oxygen may be introduced directly into the oxide semiconductor film 403 or into the gate insulating film 404. Oxygen may be introduced into the oxide semiconductor film 403 through another film such as a When introducing ions into 403 through other membranes, ion implantation, ion doping, plasma Although it is possible to use methods such as myosin ion implantation, In the case where the element is directly introduced into the oxide semiconductor film 403, plasma treatment or the like can be used.

[0108] In this embodiment, oxygen is implanted into the oxide semiconductor film 403 by an ion implantation method. By the implantation step, the oxide semiconductor film 403 is stoichiometrically oriented when the oxide semiconductor is in a crystalline state. The oxide semiconductor film 403 includes a region where the oxygen content is excessive relative to the composition.

[0109] For example, when the oxygen concentration in the oxide semiconductor film 403 introduced by the oxygen introduction step is 1 x1018 / cm 3 3x10 or more 21 / cm 3 It is preferable that the oxygen content is less than the above. The region may be present in part of the oxide semiconductor film 403 (including the interface). By introducing the element, the oxide insulating film 436, the oxide semiconductor film 403, and the gate insulating film In the stack of the oxide insulating film 436 and the oxide semiconductor film 402, At least in the semiconductor film 403 or at the interface between the oxide semiconductor film 403 and the gate insulating film 402 Also contains oxygen.

[0110] The oxide semiconductor film 403 has a stoichiometric composition in which the oxide semiconductor has a crystalline state, and oxygen In this case, the oxygen content is too high due to the chemical The oxygen content should exceed the stoichiometric ratio. Alternatively, the oxygen content should exceed the amount of oxygen in the case of a single crystal. Oxygen may exist between the lattices of oxide semiconductors. The conductor composition is InGaZn m O m+3x (x>1). For example, m=1 When the composition of the oxide semiconductor is InGaZnO 1+3x (x>1), resulting in excess oxygen If , 1 + 3x is greater than 4.

[0111] The supplied oxygen fills oxygen vacancies in the oxide semiconductor film 403. can.

[0112] In an oxide semiconductor, oxygen is one of the main components. The oxygen concentration in the conductive film was measured by SIMS (Secondary Ion Mass Spectroscopy) It is difficult to estimate accurately using methods such as oxide semiconductors. It is difficult to determine whether oxygen has been intentionally added to the conductive film.

[0113] By the way, oxygen has 17 O and 18 There are isotopes such as O, and their existence in nature The respective proportions of oxygen atoms are known to be approximately 0.037% and 0.204% of the total oxygen atoms. In other words, the concentrations of these isotopes in the oxide semiconductor film can be measured by a method such as SIMS. Therefore, by measuring these concentrations, it is possible to estimate the oxide semiconductor It may be possible to estimate the oxygen concentration in the conductive film more accurately. By measuring the oxygen concentration, it may be possible to determine whether oxygen has been intentionally added to the oxide semiconductor film. stomach.

[0114] In the case where oxygen is directly introduced into the oxide semiconductor film 403 as in this embodiment, The insulating films (oxide insulating film 436, gate insulating film 402, etc.) in contact with the body film 403 must be Although it is not necessary for the insulating film (oxide The insulating film 436, the gate insulating film 402, etc. are made to be a film containing a large amount of oxygen, and oxygen is further directly A plurality of oxygen supply methods may be used to introduce oxygen into the oxide semiconductor film 403.

[0115] Next, the oxide semiconductor film 403 is formed into an island-shaped oxide semiconductor film by a photolithography process. It is processed into a film 403 .

[0116] In addition, a resist mask for forming the island-shaped oxide semiconductor film 403 was formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask can be used. Therefore, the manufacturing cost can be reduced.

[0117] Note that the oxide semiconductor film 403 can be etched by either dry etching or wet etching. For example, when the oxide semiconductor film 403 is wet-etched, The etching solution used may be a mixture of phosphoric acid, acetic acid, and nitric acid. ITO-07N (manufactured by Kanto Chemical Co., Ltd.) may also be used. Inductively Coupled Plasma Etching Method Dry etching may also be used. For example, the IGZO film may be etched by ICP etching. Etching was performed by etching method (etching conditions: etching gas (BCl3:Cl2 = 6 0sccm:20sccm), power supply power 450W, bias power 100W, pressure 1.9P a) and can be processed into island shapes.

[0118] Further, excess hydrogen (including water and a hydroxyl group) is removed (dehydrated or The temperature for the heat treatment is 300°C or higher and 700°C or lower. The temperature should be below ℃ or below the distortion point of the substrate. The heat treatment should be carried out under reduced pressure or in a nitrogen atmosphere. For example, the substrate can be introduced into an electric furnace, which is one type of heat treatment apparatus, and an oxide semiconductor The film 403 is subjected to a heat treatment at 450° C. for 1 hour in a nitrogen atmosphere.

[0119] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device that heats the object to be treated by radiation may be used. For example, a GRTA (Gas Reactor Atomic Energy Analyzer) apid Thermal Anneal) equipment, LRTA (Lamp Rapid T RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, high-pressure mercury lamp It is a device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp or other lamp. The GRTA device is a device that uses high-temperature gas to perform heat treatment. Inert gases such as argon or nitrogen that do not react with the material to be treated by heat treatment An active gas is used.

[0120] For example, as a heat treatment, the substrate is placed in an inert gas heated to a high temperature of 650 to 700°C. After heating for several minutes, GRTA may be performed in which the substrate is taken out of the inert gas.

[0121] In the heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the nitrogen or hydrogen introduced into the heat treatment device is not contained. The purity of rare gases such as sodium, neon, and argon is preferably 6N (99.9999%) or higher. is 7N (99.99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 It is preferable to set the concentration to less than 1 ppm.

[0122] After the oxide semiconductor film 403 was heated by the heat treatment, high-purity oxygen gas and high-purity SiO 2 were added to the same furnace. nitrous oxide gas or ultra dry air (CRDS (cavity ring down laser separation) When measured using a dew point meter using the optical method, the moisture content is 20 ppm (-55°C in dew point equivalent). air, preferably 1 ppm or less, more preferably 10 ppb or less, may be introduced. It is preferable that the oxygen gas or nitrous oxide gas does not contain water, hydrogen, etc. Alternatively, the purity of the oxygen gas or nitrous oxide gas introduced into the heat treatment device is preferably 6N or more. or 7N or more (i.e., impurity concentration in oxygen gas or nitrous oxide gas is 1 ppm or less, Preferably, the concentration is 0.1 ppm or less. This action simultaneously reduces impurities through the removal process of dehydration or dehydrogenation treatment. By supplying oxygen, which is the main component material that makes up oxide semiconductors, The semiconductor film 403 can be highly purified and made into an I-type (intrinsic) semiconductor film.

[0123] Note that the timing of heat treatment for dehydration or dehydrogenation is determined based on the time when the oxide semiconductor film is heated. The step may be performed after the island-shaped oxide semiconductor film 403 is formed or after the island-shaped oxide semiconductor film 403 is formed.

[0124] The heat treatment for dehydration or dehydrogenation may be carried out multiple times, or may be carried out in combination with other heat treatments. You can sleep.

[0125] The heat treatment for dehydration or dehydrogenation is performed to form the oxide semiconductor film 403 into an island shape. If the oxide insulating film 436 is covered with the oxide semiconductor film 403, the oxide insulating film 436 is This prevents the oxygen contained in the insulating film 436 from being released by the heat treatment. preferable.

[0126] Furthermore, the dehydration or dehydrogenation treatment can remove oxygen, which is a main component material of the oxide semiconductor. In the oxide semiconductor film, oxygen is released and the amount of oxygen is reduced. Oxygen vacancies exist in the areas where the oxide has been removed, and these oxygen vacancies cause fluctuations in the electrical characteristics of the transistor. This results in the creation of donor levels.

[0127] Therefore, when dehydration or dehydrogenation treatment is performed, oxygen is supplied to the oxide semiconductor film 403. By supplying oxygen to the oxide semiconductor film 403, oxygen vacancies in the film are eliminated. can be compensated for.

[0128] Therefore, dehydration or dehydrogenation treatment is performed before the step of introducing oxygen into the oxide semiconductor film 403. It is preferable to keep

[0129] In addition, an oxide insulating film containing a large amount (excessive amount) of oxygen, which serves as an oxygen supply source, is used as the oxide semiconductor film 40. 3, oxygen can be supplied from the oxide insulating film to the oxide semiconductor film 403. In the above structure, a heat treatment is performed as the dehydration or dehydrogenation treatment. Heat treatment is performed in a state where the oxide semiconductor film 403 and the oxide insulating film are at least partly in contact with each other. In this way, oxygen may be supplied to the oxide semiconductor film.

[0130] Hydrogen or moisture is removed from the oxide semiconductor, and the semiconductor is highly purified to minimize the amount of impurities. By supplying oxygen to compensate for oxygen vacancies, an I-type (intrinsic) oxide semiconductor or an I-type By doing so, it is possible to obtain an oxide semiconductor that is as close to intrinsic as possible. Bringing the Fermi level (Ef) of a semiconductor to the same level as the intrinsic Fermi level (Ei) Therefore, by using the oxide semiconductor film in a transistor, the oxide semiconductor film can be effectively prevented from being generated due to oxygen vacancies. The variation in threshold voltage Vth of the transistor and the threshold voltage shift ΔVth are reduced. It is possible.

[0131] Next, a gate insulating film 442 is formed to cover the oxide semiconductor film 403 .

[0132] In order to improve coverage of the gate insulating film 442, a surface of the oxide semiconductor film 403 is also coated with a The above-mentioned planarization treatment may be performed. In this case, the oxide semiconductor film 403 preferably has a surface with good flatness.

[0133] The thickness of the gate insulating film 442 is set to 1 nm or more and 20 nm or less, and is formed by sputtering or MBE. The method, CVD method, pulsed laser deposition method, ALD method, etc. can be used as appropriate. The insulating film 442 is formed by forming a plurality of substrate surfaces approximately perpendicular to the sputtering target surface. The film may be formed using a sputtering device that forms a film in a set state.

[0134] The gate insulating film 442 may be a silicon oxide film, a gallium oxide film, an aluminum oxide film, Silicon nitride film, silicon oxynitride film, aluminum oxynitride film, or silicon nitride oxide film The gate insulating film 442 can be formed using an oxide semiconductor film. In particular, the gate insulating film 442 preferably contains oxygen in the film (bulk It is preferred that oxygen is present in an amount exceeding the stoichiometric ratio in the gas (e.g., in the gas). When a silicon oxide film is used as the gate insulating film 442, SiO 2+α (However, α In this embodiment, the gate insulating film 442 is made of SiO 2+α (however, A silicon oxide film with α>0 is used. This silicon oxide film is used as the gate insulating film 442. By using the oxide semiconductor film 403 as a cathode, oxygen can be supplied to the oxide semiconductor film 403, and the characteristics of the oxide semiconductor film 403 can be improved. Furthermore, the gate insulating film 442 can be formed depending on the size and gate It is preferable to form the insulating film 442 in consideration of its step coverage.

[0135] The gate insulating film 442 may be made of hafnium oxide, yttrium oxide, or hafnium. Silicate (HfSi x O y (x>0, y>0)), nitrogen-doped hafnium silicate HfSiO x N y (x>0, y>0)), hafnium aluminate (HfAl x O y (x>0, y>0)), and high-k materials such as lanthanum oxide can be used to Furthermore, the gate insulating film 442 may have a single-layer structure or a stacked structure. It may also be a structure.

[0136] Next, a conductive film is formed over the gate insulating film 442, and the conductive film is etched to form a gate electrode layer. Form 401.

[0137] The material of the gate electrode layer 401 is molybdenum, titanium, tantalum, tungsten, aluminum, or the like. Metallic materials such as aluminum, copper, chromium, neodymium, scandium, etc., or alloys containing these as their main components The gate electrode layer 401 can be formed using a gold material. Semiconductor films such as element-doped polycrystalline silicon films, nickel silicide, etc. The gate electrode layer 401 may have a single layer structure or a stacked layer structure. The structure may also be used.

[0138] The material of the gate electrode layer 401 includes indium oxide, tin oxide, and tungsten oxide. Indium oxide, indium zinc oxide with tungsten oxide, indium zinc oxide with titanium oxide Indium oxide, indium tin oxide with titanium oxide, indium oxide zinc oxide, oxide Conductive materials such as silicon-doped indium tin oxide can also be used. The conductive material and the metal material may be laminated together.

[0139] In addition, a layer of the gate electrode layer 401 in contact with the gate insulating film 442 is made of a metal oxide containing nitrogen. oxide films, specifically, nitrogen-containing In-Ga-Zn-O films and nitrogen-containing In-Sn-O films. film, In-Ga-O film containing nitrogen, In-Zn-O film containing nitrogen, Sn -O film, nitrogen-containing In-O film, or metal nitride film (InN, SnN, etc.) can be used. These films have a valence of 5 eV (electron volts), preferably 5.5 eV (electron volts) or more. When used as a gate electrode layer, the electrical characteristics of a transistor are improved by a threshold voltage of 100 V. The value voltage can be made positive, and a so-called normally-off switching element can be realized. .

[0140] Next, a dopant 421 is introduced into the oxide semiconductor film 403 using the gate electrode layer 401 as a mask. The low resistance regions 404a and 404b are formed (see FIG. 2(A)).

[0141] The dopant 421 is an impurity that changes the conductivity of the oxide semiconductor film 403. The 421st group of elements includes group 15 elements (typically phosphorus (P), arsenic (As), and antimony (Ant). Sb), boron (B), aluminum (Al), nitrogen (N), argon (Ar) , helium (He), neon (Ne), indium (In), fluorine (F), chlorine (Cl ), titanium (Ti), and zinc (Zn) may be used. can.

[0142] The dopant 421 passes through other films (for example, the gate insulating film 402) by an implantation method, The dopant 421 can also be introduced into the oxide semiconductor film 403. Ion implantation, ion doping, plasma immersion ion implantation In this case, the dopant 421 may be a single ion or a free ion. It is preferable to use fluoride or chloride ions.

[0143] The dopant 421 introduction process is performed by adjusting the injection conditions such as the acceleration voltage and the dose amount, and the film through which the dopant 421 passes. In this embodiment, phosphorus is used as the dopant 421. The phosphorus ions are implanted by ion implantation using the dopant 421. is 1 x 10 13 ions / cm 2 5x10 or more 16 ions / cm 2 The following would suffice.

[0144] The concentration of dopant 421 in the low resistance region is 5×10 18 / cm 3 More than 1×10 22 / cm 3 It is preferable that:

[0145] The dopant 421 may be introduced while the substrate 400 is heated.

[0146] Note that the treatment of introducing the dopant 421 into the oxide semiconductor film 403 may be performed multiple times. A plurality of types of dopants may be used.

[0147] After the introduction of the dopant 421, a heat treatment may be performed. The temperature is 300°C to 700°C, preferably 300°C to 450°C, for 1 hour in an oxygen atmosphere. It is preferable to carry out heating under nitrogen atmosphere, reduced pressure, or air (ultra-dry air). Processing may be performed.

[0148] In this embodiment, phosphorus (P) ions are implanted into the oxide semiconductor film 403 by an ion implantation method. The implantation conditions for phosphorus (P) ions are an acceleration voltage of 30 kV and a dose of 1.0 × 1 0 15 ions / cm 2 Let's say.

[0149] When the oxide semiconductor film 403 is a CAAC-OS film, the introduction of the dopant 421 In this case, a heat treatment is performed after the introduction of the dopant 421. This allows the crystallinity of the oxide semiconductor film 403 to be restored.

[0150] Therefore, the oxide film having the low resistance regions 404a and 404b sandwiching the channel forming region 409 is A compound semiconductor film 403 is formed.

[0151] Next, an insulating film including an aluminum oxide film is formed to cover the gate electrode layer 401. The insulating film containing the aluminum film is etched to form an insulating film 414 containing an aluminum oxide film. Furthermore, the gate electrode layer 401 and the insulating film 414 including the aluminum oxide film are masked. Then, the gate insulating film 442 is etched to form the gate insulating film 402 (FIG. 2(B) )reference).

[0152] The insulating film 414 containing an aluminum oxide film may be a single layer or a multilayer. Includes aluminum film.

[0153] The insulating film 414 including the aluminum oxide film is formed by a plasma CVD method, a sputtering method, or The film can be formed by vapor deposition or the like.

[0154] In addition to the aluminum oxide film, the insulating film 414 containing the aluminum oxide film is typically is a silicon oxide film, a silicon oxynitride film, an aluminum oxynitride film, or a gallium oxide film Inorganic insulating films such as hafnium oxide and magnesium oxide can also be used. a titanium film, a zirconium oxide film, a lanthanum oxide film, a barium oxide film, or a metal nitride film (e.g. For example, an aluminum nitride film can also be used.

[0155] In this embodiment, the insulating film 414 containing aluminum oxide is formed by a sputtering method. The insulating film 414 containing the aluminum oxide film is formed by sputtering. Film formation by the coating method is performed under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare The treatment can be carried out in a mixed atmosphere of gas and oxygen.

[0156] The insulating film 414 containing the aluminum oxide film is formed by applying a method that prevents impurities such as water and hydrogen from being mixed in. It is preferable to form it appropriately.

[0157] In the same manner as in the formation of the oxide semiconductor film, the insulating film 414 including the aluminum oxide film was formed in the deposition chamber. To remove residual moisture, use an adsorption type vacuum pump (such as a cryopump). It is preferable to use an aluminum oxide film formed in a film-forming chamber evacuated using a cryopump. The concentration of impurities contained in the insulating film 414 can be reduced. As an exhaust means for removing residual moisture in the film forming chamber of the insulating film 414, a turbo molecular pump was used. A cold trap may be added to the filter.

[0158] The insulating film 414 including the aluminum oxide film is formed using the following sputtering gas: It is preferable to use a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrides have been removed. It's nice.

[0159] The insulating film 414 including an aluminum oxide film is provided over the oxide semiconductor film 403. The aluminum oxide film allows both impurities such as hydrogen and moisture, and oxygen to pass through the film. It has a high blocking effect.

[0160] Therefore, the aluminum oxide film is free from hydrogen, which is a factor of fluctuation during and after the manufacturing process. The inclusion of impurities such as moisture in the oxide semiconductor film 403 and the inclusion of a main component constituting the oxide semiconductor The oxide semiconductor film 403 functions as a protective film for preventing oxygen, which is a material, from being released from the oxide semiconductor film 403. This allows the transistor 440a to have stable electrical characteristics.

[0161] an oxide semiconductor film 403, a gate insulating film 402, a gate electrode layer 401, and an aluminum oxide film An interlayer insulating film 415 is formed on the insulating film 414 containing the transistor. The thickness is preferably such that the unevenness caused by the resistor 440a can be flattened. A silicon oxynitride film is formed by the VD method.

[0162] The interlayer insulating film 415 is typically a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or a silicon nitride film. Aluminum oxide nitride film, silicon nitride film, aluminum nitride film, silicon oxide nitride film An inorganic insulating film such as an aluminum nitride oxide film or an aluminum oxide film can be used. The film 5 can be formed by plasma CVD, sputtering, or the like.

[0163] Furthermore, a planarizing insulating film may be formed to reduce surface irregularities caused by the transistors. The planarization insulating film may be made of organic materials such as polyimide, acrylic, or benzocyclobutene resin. In addition to the above organic materials, low-dielectric-constant materials (low-k materials) and the like can also be used. It should be noted that by stacking multiple insulating films made of these materials, A planarizing insulating film may be formed.

[0164] The interlayer insulating film 415 is covered with the oxide semiconductor film 403 (low-resistance regions 404a and 404b), the gate The insulating film 402 and the upper and side surfaces of the insulating film 414 including the aluminum oxide film are partially exposed. Openings 445a and 445b are formed (see FIG. 2(C)).

[0165] The openings 445a and 445b are formed by two etching processes using two masks. That's fine.

[0166] When the openings 445a and 445b are formed, the insulating film 414 including the aluminum oxide film is etched. Since the opening 4 functions as an opening stopper, the gate electrode layer 401 is not exposed. In the etching process for forming 45a and 45b, the interlayer insulating film 415 and the aluminum oxide The conditions for high selectivity with the insulating film 414 including the silicon film (etching conditions, interlayer insulating film 415 and and the material of the insulating film 414 including an aluminum oxide film).

[0167] The source electrode layer 405a and the drain electrode layer 405b are formed in the openings 445a and 445b. The source electrode layer 405a and the drain electrode layer 405b are used to connect to other transistors. A variety of circuits can be configured.

[0168] The source electrode layer 405a and the drain electrode layer 405b are formed using the same material as the gate electrode layer 401. It can be formed by using a method such as Al, Cr, Cu, Ta, Ti, Mo, W, etc. Metal films containing elements selected from the above, or metal nitride films (titanium nitride) containing the above elements as components. A film made of silicon, a film made of molybdenum nitride, a film made of tungsten nitride, etc. can be used. A high melting point metal film such as Ti, Mo, or W on either or both the top and bottom of a metal film such as Cu or metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) The source electrode layer 405a and the drain electrode layer 405b may be stacked. The conductive film used for the conductive layer may be formed of a conductive metal oxide. Examples include indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), and Indium tin oxide (In2O3-SnO2), indium zinc oxide (In2O3 -ZnO) or these metal oxide materials containing silicon oxide can be used. can.

[0169] For example, the source electrode layer 405a and the drain electrode layer 405b may be formed of a single layer of a molybdenum film. Lamination of tantalum nitride film and copper film, or lamination of tantalum nitride film and tungsten film, etc. You can be there.

[0170] Through the above steps, the transistor 440a of this embodiment is manufactured (see FIG. 2D).

[0171] 4A, a source electrode layer 405a, a drain electrode layer 405b, and a The electrode layer 405b is polished by chemical mechanical polishing to expose the interlayer insulating film 415. Parts of the source electrode layer 405a and the drain electrode layer 405b may be removed to form a transistor. In the transistor 440b, the source electrode layer 405a and the drain electrode layer 405b are formed as an interlayer insulating film. 415 does not protrude from the surface but is embedded in the surface. Wiring layers 435a and 435b can be provided in contact with the channel electrode layer 405b. The width of the wiring layer 435 is larger than the width of the source electrode layer 405a and the drain electrode layer 405b in the direction Since the width between the wiring layer 435a and the wiring layer 435b can be increased, the processing process becomes easier.

[0172] The wiring layer 435a and the wiring layer 435b are connected to the gate electrode layer 401, the source electrode layer 405a, or the drain electrode layer 405b. The layer 405b can be formed using the same material and method as the layer 405b. For example, Al Cr, Cu, Ta, Ti, Mo, W, or a metal film containing an element selected from the above elements. Metal nitride films containing titanium nitride as a component (titanium nitride film, molybdenum nitride film, tungsten nitride film) Also, one or both of the upper and lower sides of a metal film such as Al or Cu can be used. On the other hand, high melting point metal films such as Ti, Mo, W, etc. or their metal nitride films (titanium nitride film, nitride film) Alternatively, the wiring layer 4 may be a laminate of a molybdenum nitride film, a tungsten nitride film, or the like. The conductive film used for the wiring layer 435a and the wiring layer 435b may be formed of a conductive metal oxide. Conductive metal oxides include indium oxide (In2O3), tin oxide (SnO2), Zinc oxide (ZnO), indium oxide, tin oxide (In2O3-SnO2), indium oxide In2O3-ZnO or these metal oxide materials containing silicon oxide The above-mentioned material can be used.

[0173] The source electrode layer 405a and the drain electrode layer 405b can be removed by chemical mechanical polishing or other methods. Also, cutting (grinding, polishing) methods such as chemical mechanical polishing may be used. In addition to polishing, etching (dry etching, wet etching) and plasma treatment are also available. For example, after the removal process by chemical mechanical polishing, dry etching may be performed. Chipping and plasma treatment (reverse sputtering, etc.) are performed to improve the flatness of the treated surface. It is also possible to combine cutting (grinding, polishing) with etching, plasma treatment, etc. In this case, the order of the steps is not particularly limited. This may be appropriately set depending on the material, film thickness, and surface irregularities.

[0174] In addition, as in a transistor 440c shown in FIG. 4B, the interlayer insulating film 415 is not provided. It may also be constructed as such.

[0175] The transistors 440a, 440b, and 440c of this embodiment include a source electrode layer 405a, The drain electrode layer 405b is formed on the exposed top surface of the oxide semiconductor film 403 and the aluminum oxide. The insulating film 414 is provided in contact with the upper surface and part of the side surface of the insulating film 414 including the silicon film.

[0176] The upper surface and side surfaces of the gate electrode layer 401 are covered with an insulating film 414 containing an aluminum oxide film. Therefore, the source electrode layer 405a and the drain electrode layer 405b are formed on the gate electrode layer 401. The insulating film 414 including the aluminum oxide film prevents the source electrode layer 405a from overlapping the surface. Alternatively, an electrical defect such as a short circuit between the drain electrode layer 405b and the gate electrode layer 401 can be prevented. Therefore, the transistors 440a, 440b, and 440 c can be produced with high yield.

[0177] Furthermore, the source electrode layer 405a or the drain electrode layer 405b and the oxide semiconductor film 403 The distance between the contact region and the gate electrode layer 401 is determined by the thickness of the aluminum oxide film. This results in a width in the channel length direction of the insulating film 414 including the insulating film 414, which allows further miniaturization to be achieved. This allows for more consistent control.

[0178] Therefore, for example, as in a transistor 440d illustrated in FIG. 4C, Openings 445a and 445b are provided to form the source electrode layer 405a and the drain electrode layer 405b. Even if the position of the source electrode layer 405a or the drain electrode layer 5b is slightly shifted during the manufacturing process, A contact region between the gate electrode layer 405b and the oxide semiconductor film 403 and a gate electrode layer 405c are formed. Therefore, the distance between the transistor and the electrode layer 401 can be made the same. This can reduce defects and variations in the electrical characteristics of the resistor 440d.

[0179] In this manner, the source electrode layer 405a or the drain electrode layer 405b and the oxide semiconductor film 403 The distance between the contact region and the gate electrode layer 401 can be shortened. Therefore, the source electrode layer 405a or the drain electrode layer 405b and the oxide semiconductor film 403 The resistance between the contact region and the gate electrode layer 401 is reduced, and the transistor It is possible to improve the on-characteristics of the switches 440a, 440b, 440c, and 440d. .

[0180] As described above, in a semiconductor device, it is possible to provide an on-chip device having a fine structure with little variation in characteristics. and providing highly efficient transistors 440a, 440b, 440c, and 440d with a high yield. It is possible.

[0181] Therefore, a semiconductor device that realizes miniaturization and has high electrical characteristics, and a method for manufacturing the semiconductor device A method for fabricating the device can be provided.

[0182] (Embodiment 2) In this embodiment mode, another embodiment of a semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. The same parts as those in the above embodiment or parts and steps having similar functions are the same as those in the above embodiment. The same operations can be performed as in the first embodiment, and the repeated explanation will be omitted. The literal meaning is omitted.

[0183] The transistors 430a and 430b shown in FIGS. 5A to 5C are top-gate transistors. 5A is a plan view of the transistor 430a, and FIG. The cross section taken along the dashed line X2-Y2 in FIG. 5(B) corresponds to FIG. 5(A). In FIG. 5C, the interlayer insulating film 415 is omitted. FIG.

[0184] As shown in FIG. 5B and FIG. 5C, which are cross-sectional views in the channel length direction, transistor 4 The semiconductor device including the transistor 430a and the transistor 430b is provided with an insulating film 436. On a substrate 400 having an edge surface, electrode layers 465a, 465b, 465b, and includes the channel forming region 409 and the low resistance regions 404a and 404b. a gate insulating film 402; a gate electrode layer 401; An insulating film 414 including an aluminum oxide film covering the top and side surfaces, an interlayer insulating film 415, a source The transistor includes an electrode layer 405a and a drain electrode layer 405b.

[0185] The transistors 430a and 430b described in this embodiment each have a low resistance layer under the oxide semiconductor film 403. The source electrode layer 405a or the drain electrode layer 405b is in contact with the resistor regions 404a and 404b. In this example, electrode layers 465a and 465b are provided so as to overlap with each other.

[0186] The transistor 430a illustrated in FIGS. 5A and 5B includes an island-shaped electrode layer over an oxide insulating film 436. 465a and 465b are provided, and an oxide semiconductor is provided on and in contact with the electrode layers 465a and 465b. The electrode layers 465a and 465b are formed on the oxide semiconductor film 403. The source electrode layer 405a or the drain electrode layer 405b is in contact with the resistor regions 404a and 404b. The transistor 430a has a source electrode layer 405a and a drain electrode layer 5b. 405b, the surfaces of the source electrode layer 405a and the drain electrode layer 405b are polished. The height of the surface of the interlayer insulating film 415 (height from the surface of the substrate 400) is approximately the same as that of the surface of the interlayer insulating film 415.

[0187] The transistor 430b illustrated in FIG. 5C has a first insulating film 436 formed therein. Island-shaped electrode layers 465a and 465b are provided, and the electrode layers 465a and 465b are in contact with each other. The electrode layers 465a and 465b are formed of an oxide semiconductor film 403. The source electrode layer 405a and the drain electrode layer 405b are in contact with the low resistance regions 404a and 404b of the semiconductor substrate 403. It overlaps with the pole layer 405b.

[0188] The oxide semiconductor film 403 is provided under the source electrode layer 405a or the drain electrode layer 405b. Electrode layers 465a and 465b are provided in the contact region with the semiconductor film 403. As a result, the source electrode layer 405a, the drain electrode layer 405b, and the oxide semiconductor film 4 Since the contact resistance with the transistor 430a and the transistor 430b can be reduced, the transistors 430a and 430b can be turned on. The characteristics can be improved.

[0189] The electrode layer 465a can be used as the source terminals of the transistors 430a and 430b. The electrode layer 465b can also be used as the drain terminal of the transistors 430a and 430b. It can be used.

[0190] The electrode layers 465a and 465b may be made of molybdenum, titanium, tantalum, tungsten, or aluminum. Metallic materials such as aluminum, copper, chromium, neodymium, scandium, etc., or the above elements Metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) Alternatively, the electrode layers 465a and 465b may be formed using an oxide semiconductor. The above materials may be used in a single layer or a laminate.

[0191] Oxide semiconductors include In-Ga-Zn oxide (also written as IGZO), indium oxide, In2O3, tin oxide (SnO2), zinc oxide (ZnO), indic oxide Tin oxide (In2O3-SnO2), indium oxide zinc oxide (In2O3-ZnO) or For the insulating layer, any of these oxide semiconductor materials containing silicon oxide can be used.

[0192] When an oxide semiconductor material is used for the electrode layers 465a and 465b, the oxide semiconductor When processing the film 403 into an island shape, the electrode layers 465a and 465b are etched as little as possible. As shown in FIG. 1, at least the electrode layers 465a and 465b exposed from the oxide insulating film 436 and the oxide It is necessary to use a material that has a selectivity for etching with the semiconductor film 403. Depending on the etching conditions, the electrode layers 465a and 465b may have a partially etched shape. In addition, the electrode layers 465a and 465b may be doped with a dopant (impurity element). It is also possible to use conductive materials or semiconductor materials that have been made to have low resistance by using a method such as the above.

[0193] When an oxide semiconductor material is used for the electrode layers 465a and 465b, the oxide semiconductor film Depending on the material and film formation conditions, the interfaces between the electrode layers 465a and 465b and the oxide semiconductor film may be poor. In addition, when the interface is unclear, the electrode layers 465a and 465b and A region that can be called a mixed region or a mixed layer with the oxide semiconductor film may be formed. do.

[0194] At least a part of the electrode layers 465a and 465b is the source electrode layer 405a or the drain electrode layer 405b. The size and thickness of the layer 405b are not particularly limited as long as the layer 405b is located at a position where the layer 405b overlaps the layer 405b.

[0195] However, in the case of the transistor 430a, the oxide insulating film 436 is provided. In consideration of the coverage of the oxide semiconductor film 403 of the thin film to be formed, the electrode layers 465a and 465b It is preferable that the thickness of the film is not too large and that the end portion has a tapered angle.

[0196] On the other hand, like the transistor 430b, the surface of the transistor 430 is embedded in the oxide insulating film 436 and is not polished. When polishing is performed, increasing the film thickness of the electrode layers 465a and 465b results in lower resistance. Therefore, it is preferable.

[0197] The interlayer insulating film 415 is provided to flatten the irregularities caused by the transistors 430a and 430b. low resistance regions 404a and 404b, an insulating film 414 including an aluminum oxide film, The gate insulating film 402 is exposed through an opening. The resistor regions 404a and 404b, the gate insulating film 402, and the insulating film including the aluminum oxide film The source electrode layer 405a and the drain electrode layer 405b are in contact with the upper surface and part of the side surface of the insulating film 414. 05b is provided.

[0198] In this embodiment, an aluminum oxide film is used as the insulating film 414 containing an aluminum oxide film. Use.

[0199] The upper surface and side surfaces of the gate electrode layer 401 are covered with an insulating film 414 containing an aluminum oxide film. Therefore, the source electrode layer 405a and the drain electrode layer 405b are formed on the gate electrode layer 401. The insulating film 414 including the aluminum oxide film prevents the source electrode layer 405a from overlapping the surface. Alternatively, an electrical defect such as a short circuit between the drain electrode layer 405b and the gate electrode layer 401 can be prevented. Therefore, the yield of the transistors 430a and 430b having a fine structure can be improved. It can be produced more efficiently.

[0200] In addition, in the manufacturing process of the semiconductor device, the oxide semiconductor film 403 is oxygen radicals, oxygen atoms, or oxygen ions) are introduced to supply oxygen into the film. The oxygen introduction method includes ion implantation, ion doping, plasma immersion, and The ion implantation method, plasma treatment, etc. can be used.

[0201] The oxide semiconductor film 403 provided in the transistors 430a and 430b is made of an oxide semiconductor. A film containing regions with an excess of oxygen compared to the stoichiometric composition in the crystalline state. In this case, the oxygen content is preferably set to a level exceeding the stoichiometric ratio of the oxide semiconductor. Alternatively, the oxygen content is set to a level exceeding that of a single crystal. Oxygen may also exist between the lattices of semiconductors.

[0202] The upper surface and side surfaces of the gate electrode layer 401 are covered with an insulating film 414 including an aluminum oxide film. As a result, the channel formation region 4 of the oxide semiconductor film 403 overlapping with the gate electrode layer 401 is 09 and a part of the low resistance regions 404a and 404b are covered with an insulating film 41 containing an aluminum oxide film. 4 can be configured to cover it.

[0203] The insulating film containing the aluminum oxide film is resistant to both impurities such as hydrogen and moisture, and oxygen. It has a high blocking effect that prevents substances from passing through the membrane.

[0204] Therefore, the insulating film 414 containing the aluminum oxide film is not changed during and after the manufacturing process. The intrusion of impurities such as hydrogen and moisture into the oxide semiconductor film, which are the cause of the breakdown of the oxide semiconductor, The film functions as a protective film that prevents oxygen, the main component of the oxide semiconductor film, from being released from the film. Therefore, stable electrical characteristics can be provided to the transistors 430a and 430b. Cut.

[0205] Note that dopant is deposited on the oxide semiconductor film 403 in a self-aligned manner using the gate electrode layer 401 as a mask. The channel formation region 409 is sandwiched between the oxide semiconductor film 403 and the channel formation region 409. The resistivity of the dopant-containing low-resistance regions 404a and 404b is lower than that of the dopant-containing region 409. The dopant is an impurity that changes the conductivity of the oxide semiconductor film 403. The methods of introducing ions include ion implantation, ion doping, and plasma immersion ion implantation. For example, a ion implantation method can be used.

[0206] The channel formation region 409 is sandwiched between low resistance regions 404a and 404b in the channel length direction. By including the oxide semiconductor film 403, the transistors 430a and 430b have improved on-state characteristics. The device has high performance (for example, on-state current and field-effect mobility), and is capable of high-speed operation and high-speed response.

[0207] In a semiconductor device, a transistor having a fine structure with little variation in characteristics and high on-state characteristics is This allows the resistors 430a and 430b to be provided with a high yield.

[0208] Therefore, a semiconductor device that realizes miniaturization and has high electrical characteristics, and a method for manufacturing the semiconductor device A method for fabricating the device can be provided.

[0209] As described above, the configurations, methods, etc. shown in this embodiment are applicable to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0210] (Embodiment 3) In this embodiment, the transistor shown in this specification is used, and the transistor An example of a semiconductor device that can retain memory contents and has no limit on the number of times it can be written is shown in the drawing. This will be explained using:

[0211] 6A and 6B show an example of the configuration of a semiconductor device. FIG. 6A shows a cross-sectional view of the semiconductor device, and FIG. FIG. 6B is a plan view of the semiconductor device, and FIG. 6C is a circuit diagram of the semiconductor device. 6A corresponds to the cross sections taken along lines C1-C2 and D1-D2 in FIG. 6B.

[0212] The semiconductor device shown in FIGS. 6A and 6B has a transistor using a first semiconductor material in the lower part. a transistor 160 and a transistor 162 made of a second semiconductor material on top of it; The transistor 162 may be the transistor described in Embodiment 1 or 2. In this embodiment, the transistor 162 of the first embodiment can be applied. This is an example in which the structure of the transistor 440b shown in FIG.

[0213] Here, the first semiconductor material and the second semiconductor material may be materials having different forbidden band widths. For example, the first semiconductor material may be a semiconductor material other than an oxide semiconductor (such as silicon). The second semiconductor material can be an oxide semiconductor. The transistors used in this method can easily operate at high speed. The properties of the charge storage capacitor allow it to retain charge for a long period of time.

[0214] It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that p-channel transistors can also be used. In order to retain the capacitance, the transistor using an oxide semiconductor as described in Embodiment 1 is used. In addition to being used for resistor 162, materials used in semiconductor devices and the structure of semiconductor devices, etc. The specific configuration of the device is not necessarily limited to that shown here.

[0215] The transistor 160 in FIG. 6A includes a semiconductor material (e.g., silicon). A channel forming region 116 is provided on a substrate 185, and a an impurity region 120 provided in the semiconductor substrate; and an intermetallic compound region 124 in contact with the impurity region 120. , a gate insulating film 108 provided on the channel forming region 116; and a gate electrode 110 provided at the source electrode. However, for convenience, we refer to such a state as a transistor. In this case, the source is sometimes called the The source electrode and drain electrode are sometimes referred to as the source electrode and drain region. In this specification, the term "source electrode" may include a source region.

[0216] An element isolation insulating layer 106 is provided on the substrate 185 so as to surround the transistor 160. The insulating layer 128 and the insulating layer 130 are provided to cover the transistor 160. In the transistor 160, a sidewall insulating layer (sidewall) is formed on the side surface of the gate electrode 110. A wall insulating layer may be provided to form the impurity region 120 including regions with different impurity concentrations.

[0217] The transistor 160 using a single crystal semiconductor substrate can operate at high speed. By using this transistor as a readout transistor, it is possible to read out information at high speed. Two insulating layers are formed to cover the transistor 160. As a process before forming the capacitor 162 and the capacitor element 164, the two insulating film layers are subjected to CMP. Then, planarized insulating layers 128 and 130 are formed, and at the same time, the upper surface of the gate electrode 110 is Expose.

[0218] The insulating layer 128 and the insulating layer 130 are typically made of a silicon oxide film, a silicon oxynitride film, or an oxide Aluminum film, aluminum oxynitride film, silicon nitride film, aluminum nitride film, nitride An inorganic insulating film such as a silicon oxide film or an aluminum nitride oxide film can be used. The layer 128 and the insulating layer 130 are formed by using a plasma CVD method, a sputtering method, or the like. It is possible.

[0219] In addition, organic materials such as polyimide, acrylic resin, and benzocyclobutene resin can be used. In addition to the above organic materials, low-dielectric-constant materials (low-k materials) can also be used. When organic materials are used, the insulating layer can be formed by wet methods such as spin coating and printing. 128, an insulating layer 130 may be formed.

[0220] In this embodiment, the insulating layer 128 is a silicon nitride film, and the insulating layer 130 is a silicon nitride film. A silicon oxide film is used.

[0221] A planarization treatment is performed on the surface of the insulating layer 130 in a region where the oxide semiconductor film 144 is to be formed. In this embodiment, the surface is sufficiently planarized by a polishing process (for example, a CMP process). Preferably, the average surface roughness of the insulating layer 130 is 0.15 nm or less. A semiconductor film 144 is formed.

[0222] The transistor 162 illustrated in FIG. 6A is a transistor in which an oxide semiconductor is used for a channel formation region. Here, the oxide semiconductor film 144 included in the transistor 162 is a highly pure oxide semiconductor film. By using a highly purified oxide semiconductor, Therefore, the transistor 162 having excellent off-state characteristics can be obtained.

[0223] The transistor 162 has a small off-state current, and therefore, by using this transistor, it is possible to achieve long-term recording. It is possible to retain the memory contents, i.e., no refresh operation is required, or , it is possible to realize a semiconductor memory device in which the frequency of refresh operations is extremely low. Power consumption can be reduced sufficiently.

[0224] In this embodiment, the transistor 162 is provided over the interlayer insulating film 135 in the manufacturing process. The source electrode layer and the drain electrode layer are removed by a chemical mechanical polishing process. Electrode layers 142a and 142b are formed to function as conductive electrode layers. An electrode layer 142c electrically connected to the gate electrode 110 is formed in the same process as the layers 142a and 142b. Form.

[0225] In addition, the source wiring layer or In addition, wiring layers 138a and 138b are provided to function as drain wiring layers.

[0226] The transistor 162 is provided over the oxide semiconductor film 144 with a gate insulating film 146 interposed therebetween. The upper and side surfaces of the gate electrode 148 are covered with an insulating film 137 containing an aluminum oxide film. Therefore, even if the electrode layers 142a and 142b overlap the upper surface of the gate electrode 148, the aluminum oxide The insulating film 137 including the aluminum film separates the electrode layers 142a and 142b and the gate electrode 148. This prevents electrical defects such as short circuits between the Transistors having a fine structure can be manufactured with a high yield.

[0227] Therefore, the transistor 162 has an electrode layer that functions as a source electrode layer or a drain electrode layer. The contact regions 142a and 142b are in contact with the oxide semiconductor film 144, and the gate Since the distance to the electrode 148 can be shortened, the electrode layers 142a and 142b and the oxide semiconductor The resistance between the contact area with the conductive film 144 and the gate electrode 148 is reduced. As a result, the on-characteristics of the transistor 162 can be improved.

[0228] In addition, oxygen is introduced into the oxide semiconductor film 144 during the manufacturing process, and the oxide semiconductor film 144 contains a large amount of oxygen (excessive oxygen). The upper surface and side surfaces of the gate electrode 148 are covered with an insulating film 1 containing an aluminum oxide film. 37, the channel of the oxide semiconductor film 144 overlapping with the gate electrode 148 is The formation region and a part of the low resistance region are covered with an insulating film 137 including an aluminum oxide film. It is possible.

[0229] In this embodiment, an aluminum oxide film is used as the insulating film 137 containing an aluminum oxide film. The aluminum oxide film is made of high density (film density 3.2 g / cm 3 Above 3.6, preferably 3.6 g / cm 3 By setting the temperature to a value equal to or higher than the above, the transistor 162 can have stable electrical characteristics. It is possible.

[0230] An insulating film 150 is provided over the transistor 162 as a single layer or a stacked layer. In this embodiment, an aluminum oxide film is used as the insulating film 150.

[0231] The electrode layer 142 of the transistor 162 is connected via the interlayer insulating film 135 and the insulating film 150. A conductive layer 153 is provided in the area overlapping with the electrode layer 142c and the wiring layer 13a. 8a, the interlayer insulating film 135, the insulating film 150, and the conductive layer 153 form a capacitor element 16. That is, the electrode layer 142a of the transistor 162 is The conductive layer 153 functions as one electrode of the capacitor 164. If no capacitance is required, the capacitor 164 may be omitted. In addition, the capacitor 164 may be provided separately above the transistor 162 .

[0232] An insulating film 152 is provided over the transistor 162 and the capacitor 164. On the insulating film 152, a transistor 162 and a wiring for connecting other transistors are provided. Although not shown in FIG. 6A, the wiring 156 is formed on the insulating film 150, The wiring layer 138b and the electrode layer 138c are connected to each other through an electrode formed in an opening formed in the insulating film 152 or the like. 142b, where the electrode is electrically connected to the oxide of at least the transistor 162. It is preferable that the insulating film 144 is provided so as to overlap with a part of the nitride semiconductor film 144 .

[0233] In FIGS. 6A and 6B, the transistor 160 and the transistor 162 are The source region of the transistor 160 is provided so as to overlap at least a part of the The drain region is preferably provided so as to partially overlap the oxide semiconductor film 144. In addition, the transistor 162 and the capacitor 164 are at least For example, the conductive layer 153 of the capacitor 164 is provided so as to partially overlap with the At least a part of the gate electrode 110 of the transistor 160 is overlapped therewith. By adopting such a planar layout, it is possible to reduce the area occupied by the semiconductor device. This allows for high integration.

[0234] The electrical connection between the wiring layer 138b and the wiring 156 is This may be done by direct contact, or by providing an electrode on the insulating film between the wiring layer 138b and the wiring 156. The electrode may be disposed between the electrodes.

[0235] Next, an example of a circuit configuration corresponding to FIGS. 6(A) and 6(B) is shown in FIG. 6(C).

[0236] In FIG. 6C, the first wiring (1st Line) and the source voltage of the transistor 160 The electrode is electrically connected to the second wiring (2nd Line) and the gate of the transistor 160. The third line and the drain electrode are electrically connected. The fourth transistor 162 is electrically connected to one of the source electrode and the drain electrode of the fourth transistor 162. The wiring (4th Line) and the gate electrode of the transistor 162 are electrically connected. The gate electrode of the transistor 160 and the source voltage of the transistor 162 are connected to each other. The other of the electrode and drain electrode is electrically connected to one of the electrodes of the capacitor 164. The wiring (5th Line) and the other electrode of the capacitor element 164 are electrically connected. .

[0237] In the semiconductor device shown in FIG. 6C, the potential of the gate electrode of the transistor 160 can be maintained. By taking advantage of this feature, it is possible to write, store, and read information as follows.

[0238] The writing and retention of data will be explained. First, the potential of the fourth wiring is applied to the transistor The potential is set to a level at which the transistor 162 is turned on, thereby turning on the transistor 162. The potential of the third wiring is applied to the gate electrode of the transistor 160 and the capacitor 164. That is, a predetermined charge is applied to the gate electrode of the transistor 160 (write Here, charges that give two different potential levels (hereinafter referred to as low-level charges, H Then, the voltage of the fourth wiring is The potential is set to a potential at which the transistor 162 is turned off, and the transistor 162 is turned off. By doing so, the charge given to the gate electrode of the transistor 160 is retained (retained Hold).

[0239] Since the off-state current of the transistor 162 is extremely small, the gate electrode of the transistor 160 The charge is retained for a long time.

[0240] Next, we will explain how to read information. When a predetermined potential (constant potential) is applied to the first wiring, When an appropriate potential (read potential) is applied to the fifth wiring, the gate of the transistor 160 Depending on the amount of charge held in the electrode, the second wiring takes on a different potential. If the transistor 160 is an n-channel type, a high level voltage is applied to the gate electrode of the transistor 160. Apparent threshold V when a load is applied th_H is the gate of transistor 160 Apparent threshold voltage V when a low-level charge is applied to the electrode th_L Lower Here, the apparent threshold voltage is the voltage at which the transistor 160 is in the "on" state. Therefore, the potential of the fifth wiring is V th_H and V th_L By setting the potential V0 between For example, in writing, a high level charge is given, the potential of the fifth wire is V0 (>V th_H ) then, If a low level charge is applied, the fifth resistor 160 is in the "ON state." The potential of the wiring is V0( <V th_L ), transistor 160 is in the "off state" Therefore, the stored information can be read by checking the potential of the second wiring. It is possible.

[0241] When memory cells are arranged in an array, only the information in the desired memory cell can be read. In this way, if the information is not read out, the state of the gate electrode Regardless of the potential at which transistor 160 is in the "off state," i.e., V th_H Yo Alternatively, a potential smaller than the potential of the gate electrode may be applied to the fifth wiring. The potential at which the transistor 160 is in the "on state," i.e., V th_L A larger potential Just give it to the fifth wire.

[0242] In the semiconductor device described in this embodiment, an oxide semiconductor is used in the channel formation region. By using extremely small transistors, memory contents can be retained for an extremely long period of time. In other words, the refresh operation becomes unnecessary or the refresh operation is This allows the frequency of operations to be reduced significantly, resulting in a significant reduction in power consumption. In addition, when there is no power supply (however, it is desirable that the potential is fixed), However, it is possible to retain the stored contents for a long period of time.

[0243] Furthermore, the semiconductor device described in this embodiment mode does not require a high voltage for writing data. There is no problem of degradation of the capacitor. For example, unlike conventional non-volatile memory, the floating gate There is no need to inject electrons into the floating gate or extract electrons from the floating gate. The problem of deterioration of the gate insulating film does not occur at all. The device does not have the limit on the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and Furthermore, the on / off state of the transistor determines the amount of information Since writing is performed, high speed operation can be easily achieved.

[0244] As described above, semiconductor devices that have achieved miniaturization and high integration and are endowed with high electrical characteristics have been developed. It is possible to provide a semiconductor device and a method for manufacturing the semiconductor device.

[0245] As described above, the configurations, methods, etc. shown in this embodiment are applicable to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0246] (Fourth embodiment) In this embodiment, the transistors described in Embodiments 1 to 3 are used. A semiconductor device that can retain its memory contents even when the device is not connected to a power source, and has no limit on the number of times it can be written to. The configuration of the device, which differs from that shown in the third embodiment, will be explained with reference to FIGS. 7 and 8. Make it clear.

[0247] FIG. 7(A) shows an example of a circuit configuration of a semiconductor device, and FIG. 7(B) shows an example of the semiconductor device. First, the semiconductor device shown in FIG. 7(A) will be explained, followed by the semiconductor device shown in FIG. The semiconductor device shown in B) will be described below.

[0248] In the semiconductor device shown in FIG. 7A, the bit line BL and the source electrode of the transistor 162 The drain electrode is electrically connected to the word line WL, and the gate voltage of the transistor 162 is The electrode is electrically connected to the source electrode or drain electrode of the transistor 162 and the capacitor element The first terminal of 254 is electrically connected to the first terminal of 254 .

[0249] Next, data is written and stored in the semiconductor device (memory cell 250) shown in FIG. This section explains how to do this.

[0250] First, the potential of the word line WL is set to a potential at which the transistor 162 is turned on. The transistor 162 is turned on. As a result, the potential of the bit line BL is changed to the potential of the capacitor 254. The potential of the word line WL is then applied to the first terminal (write). By setting the potential at which the transistor 62 is turned off, the transistor 162 is turned off. The potential of the first terminal of the capacitance element 254 is held (held).

[0251] The transistor 162 including an oxide semiconductor has an extremely low off-state current. For this reason, when the transistor 162 is turned off, the first The potential of the terminal (or the charge stored in the capacitance element 254) is kept constant for an extremely long time. It is possible to retain it.

[0252] Next, the reading of information will be described. When the transistor 162 is turned on, the floating The bit line BL and the capacitance element 254 are electrically connected to each other. As a result, the potential of the bit line BL changes. The amount of change in potential is determined by the potential of the first terminal of the capacitance element 254 (or the potential stored in the capacitance element 254). It takes on different values ​​depending on the charge.

[0253] For example, the potential of the first terminal of the capacitance element 254 is V, the capacitance of the capacitance element 254 is C, and the bit line The capacitance component of BL (hereinafter also referred to as bit line capacitance) is CB, and the capacitance before charge redistribution is If the potential of the bit line BL is VB0, the potential of the bit line BL after the charge is redistributed is (CB*VB0+C*V) / (CB+C). Therefore, the state of memory cell 250 is Therefore, if the potential of the first terminal of the capacitance element 254 takes two states, V1 and V0 (V1>V0), Then, the potential of the bit line BL when the potential V1 is maintained is (=(CB*VB0+C*V1 ) / (CB+C)) is the potential of the bit line BL when the potential V0 is maintained (=(CB* VB0+C*V0) / (CB+C)).

[0254] Then, by comparing the potential of the bit line BL with a predetermined potential, information can be read out. do.

[0255] As described above, in the semiconductor device illustrated in FIG. 7A, the off-state current of the transistor 162 is extremely small. Therefore, the charge stored in the capacitance element 254 can be maintained for a long time. In other words, refresh operations are not required, or the frequency of refresh operations can be reduced. Since it is possible to make the power consumption extremely low, it is possible to reduce the power consumption sufficiently. Even if there is no power supply, the memory contents can be retained for a long period of time. do.

[0256] Next, the semiconductor device shown in FIG. 7B will be described.

[0257] The semiconductor device shown in FIG. 7B has the memory cell 2 shown in FIG. 7A as a memory circuit on the upper part. 50, and at the bottom, The peripheral circuits required to operate the array 251 (memory cell arrays 251a and 251b) The peripheral circuit 253 is electrically connected to the memory cell array 251. It is being done.

[0258] By using the configuration shown in FIG. 7B, the peripheral circuit 253 is connected to the memory cell array 251 ( Since it can be provided directly under the memory cell arrays 251a and 251b, It is possible to achieve miniaturization.

[0259] The transistors provided in the peripheral circuit 253 are made of a different semiconductor material from the transistor 162. It is more preferable to use silicon, germanium, silicon germanium, Silicon carbide, gallium arsenide, or the like can be used, and a single crystal semiconductor can also be used. Alternatively, organic semiconductor materials may be used. The transistor is capable of sufficiently high speed operation. It is possible to realize various circuits (logic circuits, drive circuits, etc.) that require operation. do.

[0260] In the semiconductor device shown in FIG. 7B, two memory cell arrays 251 (memory cell Although the configuration in which the memory cell array 251a and the memory cell array 251b are stacked has been illustrated, The number of memory cells is not limited to this. A configuration in which three or more memory cells are stacked can also be used. good.

[0261] Next, the specific configuration of the memory cell 250 shown in FIG. 7(A) will be described with reference to FIG. 8. conduct.

[0262] 8 shows an example of the configuration of the memory cell 250. FIG. 8A shows a cross section of the memory cell 250. 8(A) shows a diagram of the memory cell 250, and FIG. 8(B) shows a plan view of the memory cell 250. These correspond to cross sections taken along lines F1-F2 and G1-G2 in FIG. 8(B).

[0263] The transistor 162 illustrated in FIGS. 8A and 8B is the same as that described in any one of Embodiments 1 to 3. The configuration can be the same as that shown in FIG.

[0264] The insulating film 256 is a single layer or a stacked layer over the transistor 162 provided over the insulating layer 180. The electrode layer 142a of the transistor 162 is formed with the insulating film 256 interposed therebetween. A conductive layer 262 is provided in a region overlapping with the wiring layer 138a which is electrically connected to the , a wiring layer 138a electrically connected to the electrode layer 142a, an interlayer insulating film 135, and an insulating film 2 56 and the conductive layer 262 form a capacitance element 254. The electrode layer 142a of the capacitor 162 functions as one electrode of the capacitor 254, and the conductive layer 262 serves as the other electrode of the capacitor 254.

[0265] An insulating film 258 is provided over the transistor 162 and the capacitor 254. On the insulating film 258, a memory cell 250 is connected to an adjacent memory cell 250. Although not shown, the wiring 260 is formed by insulating film 256 and insulating film 260. 258, etc., and electrically connects to the electrode layer 142a of the transistor 162. However, if another conductive layer is provided in the opening, the other The wiring 260 and the wiring layer 138a electrically connected to the electrode layer 142a are connected to each other through the conductive layer. The wiring 260 may be electrically connected to the bit line B in the circuit diagram of FIG. Equivalent to L.

[0266] In FIGS. 8A and 8B, the electrode layer 142b of the transistor 162 is It can also function as the source electrode of a transistor included in the memory cell.

[0267] By adopting the planar layout shown in FIG. 8(A), the area occupied by the semiconductor device can be reduced. Therefore, high integration can be achieved.

[0268] As described above, the memory cells formed in multiple layers on the upper side are transistors using oxide semiconductors. The transistor using an oxide semiconductor has a low off-state current. Therefore, by using this, it is possible to retain the stored contents for a long period of time. This allows the frequency of refresh operations to be reduced significantly, resulting in sufficient power consumption. can be reduced to

[0269] In this way, transistors using materials other than oxide semiconductors (in other words, transistors with sufficiently high speed operation) The peripheral circuits are made up of transistors that can be operated with an oxide semiconductor. In a broader sense, it is a transistor with a sufficiently small off-state current. This makes it possible to realize a semiconductor device with unprecedented features. By forming the gate and memory circuits in a stacked structure, the integration of the semiconductor device can be increased.

[0270] As described above, semiconductor devices that have achieved miniaturization and high integration and are endowed with high electrical characteristics have been developed. It is possible to provide a semiconductor device and a method for manufacturing the semiconductor device.

[0271] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0272] (Embodiment 5) In this embodiment mode, the semiconductor device described in the above embodiment mode is applied to a mobile phone, a smartphone, an An example of application to a portable device such as a child book will be described with reference to FIGS.

[0273] In mobile devices such as mobile phones, smartphones, and e-books, image data is temporarily stored. SRAM or DRAM is used in the following: The reason is that flash memory has a slow response time and is not suitable for image processing. On the other hand, when SRAM or DRAM is used for temporary storage of image data, the following characteristics are observed: do.

[0274] In a normal SRAM, one memory cell is made up of transistors 801 to 808 as shown in FIG. It consists of six transistors, X decoder 807 and Y decoder 808. It is driven by transistor 808. 4 and transistor 806 form an inverter, enabling high speed operation. The memory cell is composed of six transistors, which has the disadvantage of requiring a large cell area. When the minimum dimension of the design rule is F, the area of ​​the SRAM memory cell is usually 100 ~150F 2 For this reason, SRAM has the highest cost per bit among all types of memory. stomach.

[0275] On the other hand, in a DRAM, the memory cell is made up of a transistor 811, a storage It is composed of a storage capacitor 812, which is driven by an X decoder 813 and a Y decoder 814. Each cell is composed of one transistor and one capacitor, and has a small area. The memory cell area of ​​RAM is usually 10F 2 However, DRAM is always refreshed. It requires a memory card and consumes power even when not being rewritten.

[0276] However, the memory cell area of ​​the semiconductor device described in the previous embodiment is 10F 2 Before and after , and frequent refresh is not required. Therefore, the memory cell area is reduced, and Power consumption can be reduced.

[0277] A block diagram of the portable device is shown in Fig. 10. The portable device shown in Fig. 10 includes an RF circuit 901, an analog a digital baseband circuit 902, a digital baseband circuit 903, a battery 904, and a power supply Circuit 905, application processor 906, flash memory 910, display A controller 911, a memory circuit 912, a display 913, a touch sensor 919, It is composed of an audio circuit 917, a keyboard 918, etc. The display 913 is The device is composed of a power supply 914, a source driver 915, and a gate driver 916. The application processor 906 includes a CPU 907, a DSP 908, and an interface 909. Generally, the memory circuit 912 is composed of an SRAM or a DRAM. By adopting the semiconductor device described in the previous embodiment in this portion, It is capable of writing and reading information at high speed, retaining data for a long period of time, and consuming little power. can be reduced to minutes.

[0278] FIG. 11 shows a display device in which the semiconductor device described in the previous embodiment is used in a memory circuit 950 of the display. The memory circuit 950 shown in FIG. It is composed of a switch 954, a switch 955 and a memory controller 951. The memory circuit receives image data (input image data) from a signal line and stores the image data in the memory 952. and reads out and controls the data (stored image data) stored in the memory 953. Display controller 956 and a signal from the display controller 956 A display 957 is connected to display the image.

[0279] First, certain image data is generated by an application processor (not shown). The input image data A is input to the memory 952 via the switch 954. The image data stored in the memory 952 (stored image data A) is then 955 and a display controller 956 to a display 957. , will be displayed.

[0280] If there is no change in the input image data A, the stored image data A usually has a frequency of about 30 to 60 Hz. The display controller 956 reads the data from the memory 952 via the switch 955. It is revealed.

[0281] Next, for example, when the user rewrites the screen (i.e., input image data A If there is a change in the input image data, the application processor The input image data B is stored in the memory 953 via the switch 954. During this time, the stored image data A is periodically read out from the memory 952 via the switch 955. When the new image data (stored image data B) has been stored in the memory 953, From the next frame of the display 957, the stored image data B is read out, and the switch 95 5, and the stored image data is displayed on the display 957 via the display controller 956. Data B is sent and displayed. This reading is then followed by the next new image data being stored in the memory. This continues until the data is stored in the memory 952.

[0282] In this way, the memory 952 and the memory 953 alternately write and read image data. By reading out the data, the display 957 displays the data. The memory 52 and the memory 953 are not limited to being separate memories, but may be divided into one memory. The semiconductor device described in the above embodiment may be used as the memory 952 and the memory 953. By adopting this technology, it is possible to write and read information at high speed and to retain data for a long period of time. This makes it possible to sufficiently reduce power consumption.

[0283] Figure 12 shows a block diagram of an electronic book. , microprocessor 1003, flash memory 1004, audio circuit 1005, keyboard a card 1006, a memory circuit 1007, a touch panel 1008, a display 1009, It is configured by a display controller 1010.

[0284] Here, the semiconductor device described in the previous embodiment is used for the memory circuit 1007 in FIG. The role of the memory circuit 1007 is to temporarily store the contents of the book. An example of a feature is when a user uses the highlight feature. When reading an e-book, you may want to mark a specific part. The highlighting function is called the highlight function, and it allows you to change the display color, underline, make the text bold, etc. The purpose is to differentiate the user from the surroundings by making the text smaller or changing the font. This is a function that stores and retains information from specified locations. If you want to store this information for a long period of time, It may be copied to the flash memory 1004. In this case, the same as in the previous embodiment By adopting the semiconductor device described above, writing and reading of information can be improved. This allows for high speed, long-term storage, and sufficient reduction in power consumption.

[0285] As described above, the portable device shown in this embodiment mode is equipped with the semiconductor device according to the above embodiment. This allows for high-speed readout, long-term memory retention, and low power consumption. A portable device with reduced noise is realized.

[0286] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

Claims

1. a first transistor having a first channel formation region including silicon, a second transistor having a second channel formation region including an oxide semiconductor, and a capacitor; a semiconductor device in which a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitance element are electrically connected to each other, a first insulating layer having a region located on a channel formation region of the first transistor; a first conductive layer having a region located above the first insulating layer and functioning as a gate electrode of the first transistor; a second insulating layer having a region in contact with a side surface of the first conductive layer; a third insulating layer having a region located above the second insulating layer; an oxide semiconductor layer having a region in contact with a top surface of the third insulating layer, the oxide semiconductor layer including a channel formation region of the second transistor and a pair of impurity regions sandwiching the channel formation region; a second conductive layer having a region located above the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a fourth insulating layer having a region located above the second conductive layer; a third conductive layer having a region in contact with an upper surface of the fourth insulating layer and electrically connected to one of the first conductive layer and the impurity region; a fourth conductive layer having a region in contact with an upper surface of the fourth insulating layer and electrically connected to the other of the impurity regions; a fifth insulating layer having a region located above the third conductive layer and a region located above the fourth conductive layer; a fifth conductive layer having a region located above the fifth insulating layer; a sixth conductive layer having a region overlapping with the first conductive layer and a region overlapping with the third conductive layer and having a function as the other electrode of the capacitor element; the fifth conductive layer overlaps with the first channel formation region and with the second channel formation region; a potential of the fifth conductive layer is supplied to a gate electrode of the first transistor through at least the other of the impurity regions, the second channel formation region, and the one of the impurity regions in this order; In a plan view, the second conductive layer has a region extending in a first direction, In a plan view, the sixth conductive layer has a region extending in the first direction.

2. a first transistor having a first channel formation region including silicon, a second transistor having a second channel formation region including an oxide semiconductor, and a capacitor; a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitor element are electrically connected to each other; a first insulating layer having a region located on a channel formation region of the first transistor; a first conductive layer having a region located above the first insulating layer and functioning as a gate electrode of the first transistor; a second insulating layer having a region in contact with a side surface of the first conductive layer; a third insulating layer having a region located above the second insulating layer; an oxide semiconductor layer having a region in contact with a top surface of the third insulating layer, the oxide semiconductor layer including a channel formation region of the second transistor and a pair of impurity regions sandwiching the channel formation region; a second conductive layer having a region located above the oxide semiconductor layer and functioning as a gate electrode of the second transistor; a fourth insulating layer having a region located above the second conductive layer; a third conductive layer having a region in contact with an upper surface of the fourth insulating layer and electrically connected to one of the first conductive layer and the impurity region; a fourth conductive layer having a region in contact with an upper surface of the fourth insulating layer and electrically connected to the other of the impurity regions; a fifth insulating layer having a region located above the third conductive layer and a region located above the fourth conductive layer; a fifth conductive layer having a region located above the fifth insulating layer; a sixth conductive layer having a region overlapping with the first conductive layer and a region overlapping with the third conductive layer and having a function as the other electrode of the capacitor element; the fifth conductive layer overlaps with the first channel formation region and with the second channel formation region; a potential of the fifth conductive layer is supplied to a gate electrode of the first transistor through at least the other of the impurity regions, the second channel formation region, and the one of the impurity regions in this order; In a plan view, the second conductive layer has a region extending in a first direction, the sixth conductive layer has a region extending in the first direction in a plan view, the second insulating layer comprises silicon nitride; The semiconductor device, wherein the third insulating layer comprises silicon oxide.

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