Imaging device

Abstract

To provide an imaging device of low consumption power.SOLUTION: A pixel circuit is configured to be able to detect differential data between a reference frame and a target frame in a pixel, and a peripheral circuit is configured to be able to perform efficient A-D conversion on the differential data so that the compression ratio gets higher. The differential data coded by the compression is written in a storage element and sequentially read out. At this time, the frequency of a clock signal can be reduced in accordance with the amount of data. The read data is extended and added to the reference frame and configures the image of the target frame.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to an imaging device and an operation method thereof.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the invention disclosed herein more specifically relates to The technical field of one aspect of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, device, power storage device, storage device, imaging device, operation method thereof, or manufacturing method thereof This can be cited as an example.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term generally refers to a semiconductor device. A transistor and a semiconductor circuit are examples of a semiconductor device. A display device, an imaging device, or an electronic device may include a semiconductor device. [Background technology]

[0004] Oxide semiconductors have been attracting attention as semiconductor materials that can be used in transistors. Transistors are made using zinc oxide or In-Ga-Zn oxide semiconductors as oxide semiconductors. Techniques for producing such a capacitor have been disclosed (see Patent Documents 1 and 2).

[0005] Furthermore, an imaging device in which a transistor including an oxide semiconductor is used in part of a pixel circuit is particularly It is disclosed in patent document 3.

[0006] In addition, the CMOS (Complem) sensor has 133 million pixels and is compatible with 8K / 4K imaging. (Central Metal Oxide Semiconductor) Image Sensor Such a technique is disclosed in Non-Patent Document 1. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Patent Document 3] Japanese Patent Application Laid-Open No. 2011-119711 [Non-patent literature]

[0008] [Non-Patent Document 1] R. Funatsu et al., “133Mpixel 60fps CMOS Image Sensor with 32-Column Shared High-Speed ​​Column-Parallel SAR ADCs”, IEEE ISSCC Dig.Tech.Papers, 2015. Summary of the Invention [Problem to be solved by the invention]

[0009] High-definition images such as 8K4K images have a huge amount of data, and it is difficult to compress the data. It is preferable to reduce the amount of data transmitted by this method.

[0010] On the other hand, although compressing the data acquired by the imaging device reduces the load on data transmission, The digital image processing required to compress the data consumes a huge amount of power.

[0011] Therefore, an object of one embodiment of the present invention is to provide an imaging device with low power consumption. Alternatively, an imaging device that acquires differential data between successive frames can be provided. Another object of the present invention is to provide an imaging device that can efficiently compress image data. One of the objectives is to provide an image with less noise. One of the objects is to provide an imaging device suitable for high-speed operation. Another object is to provide an imaging device with high resolution. Another object is to provide an imaging device with a high degree of integration. It is an object of the present invention to provide an imaging device capable of capturing images under low illumination conditions. One of the objects is to provide an imaging device with a wide dynamic range. It is an object of the present invention to provide an imaging device that can be used in a wide range of apertures. One of the objectives is to provide an imaging device with high image quality. One of the objects is to provide a novel imaging device. Another object is to provide a method for driving the imaging device. One of the objects is to provide a novel semiconductor device and the like.

[0012] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0013] One aspect of the present invention is a method for compressing imaging data by obtaining difference data between frames. The present invention relates to an imaging device that can

[0014] One aspect of the present invention is an imaging device having a pixel, a first circuit, a second circuit, and a third circuit. The pixel has a function of outputting a first potential held in a charge storage portion, and the pixel The second potential held in the charge storage unit is output, and the first potential is a first frame potential. The second potential corresponds to the difference data between the image data of the first frame and the image data of the second frame, and the second potential corresponds to the charge This corresponds to the data when the storage section is initialized, and the first circuit is the difference between the first potential and the second potential. It has the function of outputting a third potential obtained by adding or subtracting the absolute value to the reference potential, and The circuit converts the third potential into n-bit (n is a natural number equal to or greater than 1) first digital data. The second circuit has a function of detecting the magnitude relationship of the third potential with respect to the reference potential by a 1-bit second signal. The second circuit has a function of converting the first digital data into the second digital data. It has the function of outputting n+1 bit digital data by combining digital data. The circuit of 3 has a function of compressing and storing n+1-bit digital data. It is an imaging device.

[0015] The pixel includes first to fifth transistors, a first capacitor, a second capacitor, and a third capacitor. a first electrode of the photoelectric conversion element and a second electrode of the photoelectric conversion element; the source or drain of the first transistor, The other terminal of the first transistor is electrically connected to one of the source and drain of the second transistor. The other of the source and drain of the first transistor is electrically connected to one electrode of the first capacitor. The other of the source and drain of the first transistor is connected to the second capacitor element. The other electrode of the second capacitor is electrically connected to one electrode of the third transistor. The other electrode of the second capacitor element is electrically connected to one of the source and drain. the other electrode of the second capacitor is electrically connected to the gate electrode of the third transistor. the source or drain of the fourth transistor is electrically connected to one electrode of the capacitor element. One of the terminals of the first transistor and the second transistor is electrically connected to one of the source and drain of the fifth transistor. It can be configured as follows.

[0016] The first to third transistors have an oxide semiconductor in a region where a channel is formed. The oxide semiconductor may have a structure containing In, Zn, and M (M is Al, Ti, Ga, It is preferred that the alloy contains at least one of the following elements: Sn, Y, Zr, La, Ce, Nd, or Hf.

[0017] The first circuit includes a sixth transistor, a seventh transistor, a fourth capacitor, and a fifth a capacitance element, and one of the source and drain of the sixth transistor is connected to the seventh transistor. the source or drain of the sixth transistor; One of the source and drain of the seventh transistor is electrically connected to one electrode of the fourth capacitor element. The other of the source and drain of the transistor is electrically connected to one electrode of the fifth capacitor element. The other electrode of the fourth capacitor element may be electrically connected to the pixel. do.

[0018] The second circuit includes a first comparator circuit, a second comparator circuit, and an OR circuit. A first latch circuit, a second latch circuit, a counter circuit, a first wiring, and a second wiring a third wiring, and first to n+1th (n is a natural number of 1 or more) buffer circuits. The first comparator circuit has a first input terminal, a second input terminal and a first output terminal. the second comparator circuit has a third input terminal, a fourth input terminal, and a second output terminal the OR circuit has a fifth input terminal, a sixth input terminal and a third output terminal, The first latch circuit has a seventh input terminal, an eighth input terminal and a fourth output terminal, and the second The latch circuit has a ninth input terminal, a tenth input terminal and a fifth output terminal, and The circuit has an eleventh input terminal, a twelfth input terminal, and n sixth output terminals, and The wiring can provide a first reference potential, and the second wiring can provide a second reference potential. the third wiring can supply a clock signal; the first input terminal can supply a first The second input terminal is electrically connected to the first wiring, and the third input terminal is electrically connected to the first wiring. The terminal is electrically connected to the second wiring, and the fourth input terminal is electrically connected to the first circuit. , the first output terminal is electrically connected to the fifth input terminal, and the first output terminal is electrically connected to the seventh input terminal. the second output terminal is electrically connected to the sixth input terminal, and the eighth input terminal is electrically connected to the sixth input terminal. The fourth output terminal is electrically connected to the ninth input terminal. the tenth input terminal is electrically connected to the third output terminal, and the fifth output terminal is electrically connected to the nth The 11th input terminal is electrically connected to the input terminal of the +1 buffer circuit, and the 11th input terminal is the third output terminal The twelfth input terminal is electrically connected to the third wiring, and the n sixth The output terminals are electrically connected to the input terminals of the first to n-th buffer circuits, respectively. The configuration may be such that:

[0019] The third circuit is a memory element array, the fourth circuit, the fifth circuit, the sixth circuit, and the seventh circuit. circuit, the eighth circuit, the ninth circuit, the tenth circuit, the eleventh circuit, the twelfth circuit, The fourth circuit is a circuit for detecting the input data. The fifth circuit has a function of encoding the digital data, and the fifth circuit outputs the encoded digital data. The sixth circuit has a function of temporarily storing multi-bit digital data into a single-bit digital data. The seventh circuit functions as a row decoder for writing. The eighth circuit functions as a column decoder for writing, and the ninth circuit functions as a column decoder for reading. The tenth circuit functions as a row decoder for reading data. the eleventh circuit has a function of controlling the write address of the memory element array; The 12th circuit has the function of controlling the read address of the memory element array, and the 13th circuit Calculates the digital data corresponding to the difference between the addresses specified by the fourth and fifth circuits The 14th circuit has a function of converting digital data into analog data. The 15th circuit has the function of generating clock signals with different frequencies according to analog data. The configuration may include:

[0020] The digital data stored in the third circuit is run-length compressed or Huffman compressed. Preferably it is data.

[0021] The photoelectric conversion element may use selenium or a compound containing selenium in the photoelectric conversion layer. For example, the selenium may be amorphous or crystalline. [Effects of the Invention]

[0022] By using one embodiment of the present invention, an imaging device with low power consumption can be provided. Therefore, it is possible to provide an imaging device that acquires difference data between successive frames. Alternatively, it is possible to provide an imaging device that can efficiently compress image data. Alternatively, it is possible to provide an imaging device that can capture an image with less noise. Alternatively, it is possible to provide an imaging device suitable for high-speed operation. Alternatively, a highly integrated imaging device can be provided. Alternatively, it is possible to provide an imaging device that can capture images under low illumination. It is possible to provide an imaging device with a wide dynamic range. Alternatively, an imaging device with a high aperture ratio can be provided. It is possible to provide a highly reliable imaging device. It is possible to provide an imaging device or the like, or to provide a driving method for the imaging device. Alternatively, a novel semiconductor device or the like can be provided.

[0023] Note that the effects of one embodiment of the present invention are not limited to these. Depending on the circumstances, the effect may be different from those mentioned above. Alternatively, for example, one aspect of the present invention may be In some cases, these effects may not be present. [Brief explanation of the drawings]

[0024] [Figure 1] 1A and 1B are a perspective view and a top view illustrating an imaging apparatus. [Figure 2] 1A and 1B are diagrams illustrating a connection mode of a terminal. [Figure 3] FIG. 2 is a top view illustrating an imaging apparatus. [Figure 4] FIG. 2 is a top view illustrating a division form of a pixel array and peripheral circuits. [Figure 5] 1A and 1B are a circuit diagram illustrating a pixel of an imaging device and a timing chart illustrating the operation of the imaging device. [Figure 6] 1A and 1B are a circuit diagram illustrating a pixel of an imaging device and a timing chart illustrating the operation of the imaging device. [Figure 7] Circuit diagram of the CDS circuit and block diagram of the A / D conversion circuit. [Figure 8] 4 is a timing chart illustrating the operation of the comparator circuit. [Figure 9] FIG. 2 is a diagram illustrating the operation of an A / D conversion circuit. [Figure 10] FIG. 2 is a diagram illustrating the operation of an A / D conversion circuit. [Figure 11] FIG. 1 is a block diagram of a circuit having a function of storing digital data. [Figure 12] FIG. 2 is a diagram illustrating a pixel circuit. [Figure 13] FIG. 2 is a diagram illustrating a pixel circuit. [Figure 14] FIG. 2 is a diagram illustrating a pixel circuit. [Figure 15] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 16] 3A to 3C are diagrams illustrating the operation of the imaging apparatus. [Figure 17] FIG. 2 is a cross-sectional view illustrating the structure of a photoelectric conversion element. [Figure 18] FIG. 3 is a cross-sectional view illustrating a connection configuration of photoelectric conversion elements. [Figure 19] FIG. 3 is a cross-sectional view illustrating a connection configuration of photoelectric conversion elements. [Figure 20] FIG. 1 is a cross-sectional view illustrating an imaging device. [Figure 21]FIG. 3 is a cross-sectional view illustrating a connection configuration of photoelectric conversion elements. [Figure 22] FIG. 1 is a cross-sectional view illustrating an imaging device. [Figure 23] FIG. 1 is a cross-sectional view illustrating an imaging device. [Figure 24] 1A and 1B are a cross-sectional view and a circuit diagram illustrating an imaging device. [Figure 25] FIG. 1 is a cross-sectional view illustrating an imaging device. [Figure 26] FIG. 1 is a cross-sectional view illustrating an imaging device. [Figure 27] FIG. 1 is a cross-sectional view illustrating an imaging device. [Figure 28] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 29] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 30] FIG. 1 is a cross-sectional view illustrating a configuration of an imaging apparatus. [Figure 31] FIG. 1 is a diagram illustrating a curved imaging device. [Figure 32] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 33] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 34] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 35] 1A and 1B are cross-sectional views of a transistor in a channel length direction; [Figure 36] 1A and 1B are a top view and a cross-sectional view illustrating a semiconductor layer. [Figure 37] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 38] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 39] 1A and 1B are diagrams illustrating a cross section of a transistor in a channel width direction. [Figure 40] 1A and 1B are cross-sectional views of a transistor in a channel length direction; [Figure 41] 1A and 1B are a top view and a cross-sectional view illustrating a transistor. [Figure 42] FIG. 1 is a top view illustrating a transistor. [Figure 43]1A and 1B are diagrams illustrating structural analysis of a CAAC-OS and a single-crystal oxide semiconductor by XRD, and a selected-area electron diffraction pattern of a CAAC-OS. [Figure 44] Cross-sectional TEM image of CAAC-OS, as well as planar TEM image and its image analysis. [Figure 45] Electron diffraction pattern of nc-OS and cross-sectional TEM image of nc-OS. [Figure 46] Cross-sectional TEM image of a-like OS. [Figure 47] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. [Figure 48] 1A and 1B are a perspective view and a cross-sectional view of a package that houses an imaging device. [Figure 49] 1A and 1B are a perspective view and a cross-sectional view of a package that houses an imaging device. [Figure 50] 1A to 1C illustrate electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0025] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various forms and details without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-described embodiments. In the drawings, the same parts or parts having similar functions are designated by the same reference numerals. The same elements in the drawings are used interchangeably, and repeated explanations may be omitted. In some cases, the timing may be omitted or changed as appropriate between different drawings.

[0026] The ordinal numbers such as 1st and 2nd are used for convenience and do not represent the order of processes or stacking. Therefore, for example, "the first" should not be replaced with "the second" or "the third" In addition, ordinal numbers described in this specification and the like can be replaced with other numbers as appropriate. and the ordinal numbers used to identify an aspect of the present invention may not match.

[0027] For example, in this specification, when it is explicitly stated that X and Y are connected, In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected is also considered to be disclosed in this specification. Therefore, the present invention is not limited to the predetermined connection relationships, for example, the connection relationships shown in the drawings or text. Connections other than those shown in the drawings or text are also treated as if they were described in the drawings or text. do.

[0028] Here, X and Y are the object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.). , etc.).

[0029] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When no external device (such as a diode, display element, light-emitting element, or load) is connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0030] An example of an electrical connection between X and Y is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more devices (such as diodes, display elements, light-emitting elements, and loads) can be connected between X and Y. It is possible. The switch has a function to control on / off. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state), allowing current to flow. The switch has the function of controlling whether or not the current flows. When X and Y are electrically connected, This includes the case where Y is directly connected.

[0031] An example of a functional connection between X and Y is a function that allows the functional connection between X and Y. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (D / A conversion circuits, A / D conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (Power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.) voltage sources, current sources, switching circuits, amplifier circuits (which output large signal amplitudes or current amounts, etc.), (common circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal One or more circuits (generator, memory, control circuit, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the output from X If a signal is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there is a direct connection between X and Y and a direct connection between X and Y. and Y are electrically connected.

[0032] In addition, if it is explicitly stated that X and Y are electrically connected, are electrically connected (i.e., there is another element or circuit between X and Y) X and Y are functionally connected (i.e., X and Y are functionally connected) and (When there is a functional connection between them via another circuit) and when X and Y are directly connected (i.e., when X and Y are connected without any other element or circuit between them) is considered to be disclosed in the present specification. If it is explicitly stated that it is connected, The same content is considered to be disclosed in the present specification.

[0033] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or (not shown), electrically connected to X, and the drain (or second terminal, etc.) of the transistor is connected to Z 2 (or not), and is electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0034] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor" The terminals of the transistor (or the first terminal) are electrically connected to each other. 1 terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y. It can be expressed as "connected to the source (or the first The first terminal of the transistor is electrically connected to X, and the drain of the transistor is electrically connected to the second terminal of the transistor. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of the transistor. and the drain (or second terminal, etc.) are electrically connected to Y, and X, the source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this order of connection. By specifying the order of connections in the circuit configuration using a simple expression method, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined by the above.

[0035] Alternatively, for example, "the source (or first terminal, etc.) of a transistor" is electrically connected to X through at least a first connection path, and the first connection path is , and the second connection path is a transistor through a transistor. The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor The first connection path is a path via Z1, and the second connection path is a path between the first and second transistors. The drain (or second terminal, etc.) of the capacitor is electrically connected to Y through at least a third connection path. the third connection path does not have the second connection path, and the third connection path The connection path is the path via Z2. The source (or first terminal, etc.) of the resistor is connected to the resistor via Z1 by at least the first connection path. and electrically connected to X, and the first connection path does not have a second connection path; The second connection path has a connection path through a transistor, and (or the second terminal, etc.) is connected to Y via Z2 by at least a third connection path. The third connection path does not have the second connection path. Alternatively, the source (or first terminal, etc.) of the transistor may be at least The first electrical path is electrically connected to X through Z1. The primary path does not have a second electrical path, and the second electrical path is a From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor The drain (or second terminal, etc.) of the transistor is connected to at least a third The third electrical path is electrically connected to Y through Z2. , does not have a fourth electrical path, and the fourth electrical path is (or second terminal, etc.) to the source (or first terminal, etc.) of the transistor. Using the same expression as these examples, the circuit configuration By defining the connection path in Distinguishing between the first terminal (or the second terminal, etc.) and the drain (or the second terminal, etc.) to determine the technical scope. can be done.

[0036] These representation methods are merely examples, and the present invention is not limited to these representation methods. , Y, Z1, Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0037] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are different, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the electrode in this specification has the functions of both components. The term "electromagnetic connection" refers to a case where one conductive film has the functions of multiple components. This also falls within the scope of the above.

[0038] The words "film" and "layer" may be used interchangeably depending on the situation. For example, the term "conductive layer" can be replaced with "conductive film." ". Alternatively, for example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0039] Generally, potential (voltage) is relative, and the magnitude is relative to the reference potential. The size is determined by the thickness of the ground. Even if it is stated, it does not necessarily mean that the potential is 0 volts. For example, "ground" or "GND" may be defined based on the lowest potential in the circuit. Or, define "ground" or "GND" based on the midpoint of the circuit. In such cases, positive and negative potentials are defined based on that potential. This becomes the case.

[0040] (Embodiment 1) In this embodiment, an imaging device which is one embodiment of the present invention will be described with reference to drawings.

[0041] One aspect of the present invention is to detect difference data between a reference frame and a target frame in a pixel. and a pixel circuit configuration that can efficiently convert the differential data into analog signals so that the compression rate is high. The configuration of peripheral circuits that can be used to implement the compression-encoded differential signal and the method of operation thereof. The data is written to the memory element and read out sequentially. The frequency of the clock signal can be reduced. The read data is expanded by an external circuit. and then add it to the reference frame to construct the image.

[0042] Therefore, in the imaging device according to one embodiment of the present invention, image data is efficiently compressed and the clock frequency is reduced. The power consumption can be reduced by appropriately reducing the frequency. Equipped with a noise reduction circuit, it is possible to capture images with less noise even in low light conditions. can.

[0043] FIG. 1A is a perspective view of an appearance of an imaging device of one embodiment of the present invention. The imaging device has a stacked structure. 1B is a top view of layer 31, and FIG. 1C is a top view of layer 32. FIG. 3 is a top view of layer 32.

[0044] The layer 31 has a pixel array 21 in which a plurality of pixel circuits 20 are arranged in a matrix. A terminal T is provided at one end of the row wiring connected to the pixel circuit 20. A terminal Q is provided at one end of the column wiring connected to the line 20. In other words, the terminal T is The number of terminals T1 to T6 is shown in FIG. and Q1 to Q3 are shown.

[0045] Layer 32 drives pixel array 21, converts data, reads data, and stores data. The circuit has peripheral circuits 26 (circuits 22, 23, 24, 25, etc.) for storing data. The circuit 22 is provided with terminals T' equal to the number of rows, and the circuit 23 is provided with terminals T' equal to the number of columns. That is, the number of terminals Q' is the same as the number of columns. 6' and Q1' to Q3' are shown.

[0046] The layer 31 and the layer 32 are provided one on top of the other, and as shown in FIG. 2, the terminals T and T' are , terminal Q and terminal Q' are arranged to overlap each other and have electrical connections. By adopting such a configuration, the wiring length can be shortened, and the wiring resistance and parasitic capacitance can be reduced. This allows for high-speed operation and power saving because the effects of raw capacitance can be suppressed. Since the pixel circuit 20 and wiring can be provided on the circuit 26, the imaging device can be made smaller. It should be noted that a portion of the peripheral circuit 26 may be provided outside the layer 32.

[0047] The circuits 22 to 25 are silicon-based in order to achieve both high speed operation and a CMOS circuit configuration. It is preferable to fabricate the transistor using a silicon transistor (hereinafter referred to as a silicon transistor). For example, layer 32 may be a silicon substrate on which the circuitry is formed. The pixel array 21 includes transistors using an oxide semiconductor (hereinafter referred to as OS transistors). It is preferable to fabricate the circuits 22 to 25 using a transistor. The transistors may be provided on the same surface as the pixel array 21 .

[0048] 1A, 1B, and 1C show a case where the peripheral circuit 26 for driving the pixel array 21 is not divided. On the other hand, to drive a huge number of pixels such as 8K4K, the peripheral circuit 26 must be operated at high speed. It is preferable to divide the peripheral circuit 26 into multiple parts and operate them in parallel. It's nice.

[0049] For example, as shown in FIG. 3A, the entire pixel array is divided into pixel array 21a and pixel array 3B, the pixel array 21a is divided into two parts, 21b and 21c. The peripheral circuit 26a and the peripheral circuit 26b corresponding to the pixel array 21b are provided on the layer 32. The clock frequency is reduced by dividing the peripheral circuit 26 and operating them in parallel as shown in the figure. It is possible.

[0050] 3A and 3B, the pixel arrays 21a to 21b are arranged in a manner similar to that shown in FIG. 4A. Although the embodiment has been shown in which the peripheral circuits 21b and 26a to 26b are divided into two, The number is not limited to this. For example, as shown in FIG. 4B, pixel arrays 21a to 21b are 21d and peripheral circuits 26a to 26d. As shown in FIG. 1C, the pixel arrays 21a to 21h and the peripheral circuits 26a to 26h are Alternatively, the circuit 26h may be divided into eight parts. Alternatively, as shown in FIG. 4(D), Alternatively, the pixel array 21q and the peripheral circuits 26a to 26q may be divided into 16 sections. Alternatively, you can divide the image into any number of vertical pixels that are evenly divisible, such as 32. Alternatively, as shown in FIG. 4(E), the pixel array 21 and the peripheral circuit 26 can be arranged horizontally and vertically. It may be divided equally in the direction.

[0051] 5A is a circuit diagram of the pixel circuit 20. In the pixel circuit 20, One electrode is electrically connected to one of the source and drain of the transistor 41 . The other of the source or drain of the transistor 41 is connected to the source or drain of the transistor 42. The other of the source and drain of the transistor 41 is electrically connected to The source or drain of the transistor 41 is electrically connected to one electrode of the capacitor C1. The other end of the drain is electrically connected to one electrode of the capacitance element C2. The electrode of the capacitor is electrically connected to one of the source and drain of the transistor 43. The other electrode of the element C2 is electrically connected to the gate electrode of the transistor 44. The other electrode of the transistor C2 is electrically connected to one electrode of the capacitance element C3. One of the source or drain of transistor 44 is connected to one of the source or drain of transistor 45. and electrically connected to each other.

[0052] Here, the other of the source or drain of the transistor 41 and the source or drain of the transistor 42 One of the drains, one of the electrodes of the capacitance element C1 and one of the electrodes of the capacitance element C2 are connected. The node FD1 connected to the capacitor C2 is a first charge storage section. The source or drain of the transistor 43, the gate electrode of the transistor 44, and the capacitor A node FD2 to which one electrode of the element C3 is connected serves as a second charge storage section.

[0053] The other electrode of the photoelectric conversion element PD is electrically connected to a wiring 71 (VPD). The other of the source or the drain of the transistor 42 is electrically connected to a wiring 72 (VPR). The other electrode of the capacitor C1 is electrically connected to a wiring 73 (VSS). The other of the source and drain of 43 is electrically connected to a wiring 74 (VFR). The other electrode of the element C3 is electrically connected to the wiring 75 (VC). The other of the source and the drain is electrically connected to the wiring 76 (VO). The other of the source and drain of 45 is electrically connected to a wiring 91 (OUT1).

[0054] Wiring 71 (VPD), wiring 72 (VPR), wiring 73 (VSS), and wiring 74 (VF R), wiring 75 (VC) and wiring 76 (VO) can function as power supply lines. For example, the wiring 72 (VPR), the wiring 73 (VSS), the wiring 74 (VFR), and The wiring 75 (VC) can function as a low-potential power supply line. The wiring 76 (VO) can function as a high-potential power supply line.

[0055] The gate electrode of the transistor 41 is electrically connected to the wiring 61 (TX). The gate electrode of the transistor 42 is electrically connected to the wiring 62 (PR). The gate electrode of the transistor 45 is electrically connected to the wiring 63 (FR). , and is electrically connected to the wiring 64 (SE).

[0056] The wiring 61 (TX), the wiring 62 (PR), the wiring 63 (FR) and the wiring 64 (SE) are It can function as a signal line that controls the conduction of the transistor.

[0057] The transistor 41 controls the potential of the node FD1 in accordance with the output of the photoelectric conversion element PD. The transistor 42 can function as a transfer transistor for the node FD It can function as a reset transistor that initializes the potential of transistor 1. The transistor 43 functions as a reset transistor that initializes the potential of the node FD2. The transistor 44 is an amplifying transistor that outputs a signal according to the potential of the node FD2. The transistor 45 can function as a selection transistor for selecting the pixel circuit 20. It can function as a transistor.

[0058] The above-described configuration of the pixel circuit 20 is an example, and some of the transistors and some of the capacitance elements Or, some wiring may not be included. In some cases, transistors, capacitance elements, wiring, etc. are included. In addition, the connection form of some wiring may differ from the above. The configuration may differ from the one shown.

[0059] An example of the operation of the pixel circuit 20 shown in FIG. 5(A) will be explained using the timing chart shown in FIG. 5(B). The period A (times T1 to T6) corresponds to the period for acquiring the data of the reference frame. Period B (times T7 to T12) corresponds to the period for acquiring the difference data of the first frame. Period C (times T13 to T18) corresponds to the period for acquiring the difference data of the second frame. In addition, the wiring 71 (VPD) and the wiring 76 (VO) are set to a high potential ("H"), and the wiring 72 (V PR), wiring 73 (VSS), wiring 74 (VFR) and wiring 75 (VC) are set to a low potential (" L”).

[0060] First, the operation of acquiring image data of the reference frame in period A will be described. Then, the wiring 61 (TX) is set to "H", the wiring 62 (PR) is set to "H", and the wiring 63 (FR) is set to "H". Then, the node FD1 is reset to the potential of the wiring 72 (VPR), and the node FD2 is reset to the potential of the wiring 72 (VPR). It is reset to the potential of line 74 (VFR).

[0061] At time T2, when the wiring 62 (PR) is set to "L" and the wiring 63 (FR) is set to "L", The potential of node FD1 begins to rise in response to the illuminance. At this time, the potential change at node FD1 is multiplied by a and transmitted to node FD2. This shall be the case.

[0062] At time T3, when the wiring 61 (TX) is set to "L", the nodes FD1 and FD At this time, if the potential of node FD1 is x, the potential of node FD2 is The potential at node FD1 and node FD2 at each time is shown in Table 1. The potential at the time of reset is set to 0.

[0063] [Table 1]

[0064] At time T4, when the wiring 64 (SE) is set to "H", a signal corresponding to the potential of the node FD2 is generated. The signal (image signal) is output to a wiring 91 (OUT1).

[0065] At time T5, when the wiring 63 (FR) is set to "H", the node FD2 is connected to the wiring 74 (VF R), and a signal (reset signal) corresponding to the reset potential is sent to the wiring 91 (OUT1).

[0066] At times T4 and T5, the two signals output to the wiring 91 (OUT1) are The difference is extracted by the operation of the circuit 28. The difference is calculated by This corresponds to the net image signal that has been removed. do.

[0067] At time T5, the potential of the node FD2 is reset to the potential of the wiring 74 (VFR). When the potential at node FD1 is increased, the potential at node FD2 also decreases due to capacitive coupling. If the change is multiplied by b and transmitted to node FD1, the potential of node FD1 is (1-ab )x.

[0068] Next, the operation of acquiring the difference data of the first frame in period B will be described. This explains the case where the difference data for the first frame is 0, that is, the same image as the reference frame is acquired. At time T7, the wiring 61 (TX) is set to "H" and the wiring 62 (PR) is set to "H". Then, the potential of the node FD1 is reset to the potential of the wiring 72 (VPR), and the potential of the node FD2 is Due to capacitive coupling (a 2 ba)x.

[0069] At time T8, when the wiring 62 (PR) is set to "L", the potential of the node FD1 changes in response to the illuminance. The potential at node FD2 also begins to rise due to capacitive coupling.

[0070] At time T9, when the wiring 61 (TX) is set to "L", the nodes FD1 and FD At this time, if the potential of node FD1 is x, the potential of node FD2 is The place is A 2 It becomes bx.

[0071] At time T10, when the wiring 64 (SE) is set to "H", a voltage corresponding to the potential of the node FD2 is The signal (image signal) is output to a wiring 91 (OUT1).

[0072] At time T11, when the wiring 63 (FR) is set to "H", the node FD2 is connected to the wiring 74 (V FR), and a signal (reset signal) corresponding to the reset potential is sent to the wiring 9 The difference data for the first frame is acquired.

[0073] Next, the operation of acquiring the difference data of the second frame in the period C will be described. A case where the difference data of the second frame is 0 will be described. At time T13, the wiring 61 ( TX) is set to "H" and the wiring 62 (PR) is set to "H", the node FD1 is connected to the wiring 72 (VPR ) and the potential of node FD2 is reset to (a 2 b 2 -a)xtona do.

[0074] At time T14, when the wiring 62 (PR) is set to "L", the potential of the node FD1 changes according to the illuminance. In response, the potential at node FD2 also begins to rise due to capacitive coupling.

[0075] At time T15, when the wiring 61 (TX) is set to "L", the nodes FD1 and F At this time, if the potential of node FD1 is x, then the potential of node FD2 is The potential is a 2 b 2 The result is x.

[0076] At time T16, when the wiring 64 (SE) is set to "H", a voltage corresponding to the potential of the node FD2 is applied. The signal (image signal) is output to a wiring 91 (OUT1).

[0077] At time T17, when the wiring 63 (FR) is set to "H", the node FD2 is connected to the wiring 74 (V FR), and a signal (reset signal) corresponding to the reset potential is sent to the wiring 9 The difference data for the second frame is acquired.

[0078] By operating in the above manner, the difference data between the reference frame and the subsequent frame can be detected. If the difference data is 0, the node F It is preferable that the potential of D2 be approximately the reset potential. However, due to the influence of capacitive coupling, The potential of node FD2 is different from the reset potential. It is preferable to extract net image data by using the correction function. The reference frame data and the differential data are combined by computer or software processing. This can be done when combining the two.

[0079] In some cases, the above correction may become unnecessary if the capacity of node FD1 is increased as much as possible. In addition, even within the range of general design, if b is sufficiently smaller than 1, the accumulation of potential fluctuations is not a problem.

[0080] For example, the capacitance of the capacitance element C1 is 52 fF, the capacitance of the capacitance element C2 is 29 fF, and the capacitance including the parasitic capacitance is If the capacitance of the capacitor C3 is 2 fF, a = 29 / (29 + 2) = 0.94, b = 29 / (29+52)=0.36. Therefore, the potential of node FD2 becomes Oitea 2 bx=0.32x, at time T15 a 3 b 2 x=0.11x, the difference Each time data is acquired, it approaches 0. The image data that can be acquired by the imaging device is assumed to be 13 bits. In this case, the potential of node FD2 is 1 gradation or less in the 8th frame of differential data acquisition, and Also, the same applies to the 6th frame in 10-bit mode and the 5th frame in 8-bit mode. In other words, although it differs depending on the number of bits of the image data, the frame that requires correction is The system memory is limited.

[0081] Furthermore, when the potential changes of the node FD1 at time T8 and time T14 are y and z, respectively, At time T9, the potential at node FD2 is V FD2 =(a 2 ba)x+ay. a and b are constants, and x is a known value read out in the reference frame, so y = (V FD2 - (a 2 ba)x) / a can be obtained. Also, at time T15, node FD2 The potential of is V FD2 =(a 3 b 2 -a 2 b)x+(a 2 ba)y+az. a and Since b is a constant and x and y are known, z = (V FD2 -(a 3 b 2 -a 2 b)x-( a 2 In this way, the original value can be calculated using an external circuit. In the example above where b=0.36, the calculation is performed using data for 8 frames. Just do that.

[0082] The pixel circuit 20 may have a configuration shown in FIG. The circuit 20 differs from the pixel circuit 20 shown in FIG. 5A in the direction in which the photoelectric conversion element PD is connected. In this case, the pixel circuit 20 is operated according to the timing chart of FIG. In addition, the wiring 72 (VPR), the wiring 74 (VFR), and the wiring 76 (VO) are connected to a high potential. ("H"), the wiring 71 (VPD), wiring 73 (VSS), and wiring 75 (VC) are set to a low potential ( "L"

[0083] The potentials of the nodes FD1 and FD2 at each time are as shown in Table 2. The potential of the node FD1 at times T3, T9, and T15 is -x. The potential change is multiplied by a and transmitted to node FD2, and the potential change at node FD2 is multiplied by b and transmitted to node Even in this configuration, corrections can be made as necessary to The value of node FD2 can be obtained.

[0084] [Table 2]

[0085] The peripheral circuit 26 includes a circuit 22 (row driver) that has the function of driving the pixel circuit 20, and a pixel Remove noise from the analog data output from the circuit 20 and convert it into digital data. and a circuit 23 having a function of selecting a pixel column from which the digital data is to be read out. a circuit 24 (column driver) and a circuit 25 having the function of storing the digital data; , (see FIG. 1(C)).

[0086] 7 is a circuit diagram and a block diagram showing one embodiment of the circuit 23. The circuit 23 is a pixel circuit 20 a circuit 27 that serves as a current source for outputting an appropriate signal potential to the wiring 91 (OUT1); The signal output to line 91 (OUT1) is CDS (Correlated Double Signal) A circuit 28 (CDS circuit) for performing a CDS operation and a A circuit 29 (A / D conversion) having the function of converting input analog data into digital data Note that the circuit 28 may not be provided.

[0087] The circuit 27 includes a transistor 48, and either the source or the drain of the transistor 48 is connected to The wiring 91 (OUT1) is electrically connected, and the power supply line is connected to the other of the source or drain. The power supply line can be, for example, a low potential power supply line.

[0088] The circuit 28 includes a transistor 46, a transistor 47, a capacitance element C4, and a capacitance element C5. One of the source and drain of the transistor 46 is connected to the transistor The source or drain of the transistor 46 is electrically connected to the source or drain of the transistor 47. One of the source and drain is electrically connected to one electrode of the capacitance element C4. The other of the source or drain of the transistor 47 is electrically connected to one electrode of the capacitance element C5. The other electrode of the capacitance element C4 is electrically connected to the wiring 91 (OUT1). The other of the source and drain of the resistor 46 is connected to, for example, a high potential power supply line (CDSVDD). The other electrode of the capacitance element C5 is electrically connected to, for example, the low potential power supply line (CDSVSS). and electrically connected to each other.

[0089] An example of the operation of the circuit 28 when the pixel circuit 20 shown in FIG. 5A is used will be described. First, The transistor 48 of the circuit 27 is turned on, and the transistors 46 and 47 of the circuit 28 are turned on. Next, the pixel circuit 20 supplies the potential of the image data to the wiring 91 (OUT1). Then, the reference potential (CDSVDD) is output to the wiring 92 (OUT2). The transistor 46 is made non-conductive, and a reset potential ( In this case, a potential lower than the potential of the image data (for example, GND potential) is output. The wiring 92 (OUT2) is connected to the reference potential, which is the absolute value of the difference between the potential of the image data and the reset potential. Therefore, the potential is subtracted from the reference potential (CDSVDD). The potential signal with less noise obtained by subtracting the potential of the net image data from the potential signal is supplied to the circuit 29. It is possible.

[0090] The reset potential is higher than the potential of the image data (for example, VDD potential). In this case, the wiring 92 (OUT2) is connected to the reference voltage VREF, and the absolute value of the difference between the potential of the image data and the reset potential VREF is used. This is the potential added to the potential (CDSVDD).

[0091] The circuit 29 includes a comparator circuit 51 (COMP1) and a comparator circuit 52 (COMP 2), a logical sum circuit 53 (OR), a latch circuit 54 (LAT1), and a latch circuit 55 ( LAT2), counter circuit 56 (COUNT), wiring 65 (RAMP1), and wiring 66 (RAMP2), wiring 67 (CLK), buffer circuit 57a (BUF), The buffer circuit 57b (BUF) is provided in plural. The number of bits of the counter circuit 56 (COUNT) is set to n bits (n is a natural number equal to or greater than 1). Therefore, the circuit 29 outputs n+1 bits of digital data. You can exert your power.

[0092] The comparator circuit 51 (COMP1) has a first input terminal (+) and a second input terminal (-). and a first output terminal. The comparator circuit 52 (COMP2) has a third input terminal The OR circuit 53 has a first input terminal (+), a fourth input terminal (-), and a second output terminal. ) has a fifth input terminal, a sixth input terminal and a third output terminal. (LAT1) has a seventh input terminal, an eighth input terminal and a fourth output terminal. The switch circuit 55 (LAT2) has a ninth input terminal, a tenth input terminal and a fifth output terminal. The counter circuit 56 (COUNT) has an eleventh input terminal, a twelfth input terminal, and a and n sixth output terminals.

[0093] In the comparator circuit 51 (COMP1), the first input terminal (+) is connected to the wiring 92 (OU T2), and the second input terminal (-) is electrically connected to the wiring 65 (RAMP1). The first output terminal is connected to the fifth input terminal of the OR circuit 53 (OR) and the latch circuit The seventh input terminal of the LAT1 is electrically connected to the seventh input terminal of the LAT2.

[0094] In the comparator circuit 52 (COMP2), the third input terminal (+) is connected to the wiring 66 (RA The fourth input terminal (-) is electrically connected to the wiring 92 (OUT2). The second output terminal is electrically connected to the sixth input terminal of the OR circuit 53 (OR). can be.

[0095] In the OR circuit 53 (OR), the third output terminal is connected to the first output terminal of the latch circuit 55 (LAT2). 0 input terminal and the 11th input terminal of the counter circuit 56 (COUNT). To be continued.

[0096] In the latch circuit 54 (LAT1), the eighth input terminal is connected to the wiring 67 (CLK) and the The fourth output terminal is electrically connected to the twelfth input terminal of the counter circuit 56 (COUNT). is electrically connected to the ninth input terminal of the latch circuit 55 (LAT2).

[0097] In the latch circuit 55 (LAT2), the fifth output terminal is connected to a buffer circuit 57a (BUF). The input terminal is electrically connected to the

[0098] In the counter circuit 56 (COUNT), n sixth output terminals are connected to n They are electrically connected to the input terminals of the buffer circuit 57b.

[0099] The operation of the circuit 29 will be explained with reference to FIGS. 8 to 10. FIGS. 8A and 8B show the input of the circuit 29. The slope signals RAMP1 and RAMP2 are input to the comparator circuit 51 (COM P1) and the output signal of the comparator circuit 52 (COMP2) is.

[0100] RAMP1 is input to the comparator circuit 51 (COMP1), and RAMP2 is input to the comparator circuit 52 (COMP2). The potentials at the starting points of RAMP1 and RAMP2 are as follows: The reference potential (CDSVDD) input to the circuit 28 can be used as the reference frame. This corresponds to the potential (hereinafter referred to as V0) when the difference data of the frame is 0. The potential at the end of RAMP1 is higher than V0, and the potential at the end of RAMP2 is lower than V0. Early in the sweep, RAMP1 and RAMP2 may cross at V0.

[0101] In one aspect of the present invention, an image is constructed using difference data between a reference frame and a target frame. There are often many pixels whose output data remains unchanged over several consecutive frames. In other words, the difference data for the same pixel often becomes 0 during those few frames. To efficiently obtain 0, it is preferable to use V0 as the starting point of the slope signal. By using an encoding process that can efficiently represent 0, the compression rate of image data can be increased. In addition, by sweeping two slope signals simultaneously, the clock frequency can be reduced. This also reduces power consumption.

[0102] On the other hand, when the difference data between the reference frame and the target frame is 0, the counter circuit 56 If (COUNT) is set to output the median data, when there is a change of one gradation, The output value of the bit may be inverted. When obtaining differential data, such a change This tends to occur frequently, making it impossible to increase the compression rate of the image data. From this viewpoint, it is preferable to set V0 as the starting point of the slope signal.

[0103] When the image data (DATA) output from the circuit 28 is on the higher potential side than V0 (FIG. 8( The operation of the circuit 29 shown in FIG.

[0104] When the sweep of the slope signal begins at time T1, the comparator circuit 51 (COMP1) goes "H". The comparator circuit 52 (COMP2) outputs "L".

[0105] FIG. 9A shows the output signals of each circuit at time T1. When "H" is output, the counter circuit 56 (COUNT) starts counting the digital data. When the latch circuit 54 (LAT1) outputs "H", the latch circuit 55 (LAT 2) outputs "H".

[0106] At time T2, when RAMP1 becomes larger than the potential of the image data (DATA), The output of comparator circuit 51 (COMP1) changes from "H" to "L" and 2 (COMP2) outputs "L".

[0107] FIG. 9B shows the output signals of each circuit at time T2. When L” is output, the counter circuit 56 (COUNT) stops counting the digital data. The digital data is held. Also, the latch circuit 54 (LAT1) outputs "L". Then, the latch circuit 55 (LAT2) holds "H". The fifth output terminal of the LAT2 is held at "H", which is the potential just before time T2. do.

[0108] After time T3, the n-bit data output from the counter circuit 56 (COUNT) The 1-bit data held at the fifth output terminal of the data and latch circuit 55 (LAT2) ("H"="1") is input to the wiring 93 via the buffer circuit 57a or the buffer circuit 57b. (OUT3)

[0109] When the image data (DATA) output from the circuit 28 is at a lower potential than V0 (FIG. 8( The operation of the circuit 29 shown in FIG.

[0110] When the sweep of the slope signal begins at time T1, the comparator circuit 51 (COMP1) goes low. The comparator circuit 52 (COMP2) outputs "H."

[0111] FIG. 10A shows the output signals of each circuit at time T1. When "H" is output, the counter circuit 56 (COUNT) starts counting digital data. Also, when the latch circuit 54 (LAT1) outputs "L", the latch circuit 55 (LA T2) outputs "L".

[0112] At time T2, when RAMP2 becomes smaller than the potential of the image data (DATA), The comparator circuit 51 (COMP1) outputs "L", and the comparator circuit 52 (COMP2) The output changes from "H" to "L".

[0113] FIG. 10B shows the output signals of each circuit at time T2. When "L" is output, the counter circuit 56 (COUNT) stops counting the digital data. The digital data is then held. Also, the latch circuit 54 (LAT1) outputs "L". When this signal is input, the latch circuit 55 (LAT2) holds "L". The fifth output terminal of (LAT2) is kept at "L", which is the potential just before time T2. become.

[0114] After time T3, the n-bit data output from the counter circuit 56 (COUNT) The 1-bit data held at the fifth output terminal of the data and latch circuit 55 (LAT2) ("L"="0") is connected to the wiring 93 via the buffer circuit 57a or the buffer circuit 57b. (OUT3)

[0115] The 1-bit data held at the fifth output terminal is the image data ( DATA) is on the higher or lower side of V0. Therefore, for convenience, the 1-bit data is It is preferable to set the bit position to the least significant bit, but other bit positions are also acceptable. This allows for the output of a large amount of digital data with small changes. This allows for a higher compression ratio when encoding digital data.

[0116] 11 is a block diagram showing one embodiment of the circuit 25. The circuit 25 receives input digital data. a circuit 701 having a function of encoding the encoded digital data; a circuit 702 (register) having the function of storing digital data of multiple bits in one bit; A circuit 703 (parallel-serial conversion circuit) that has the function of dividing the digital data into bits a memory element array 400 having a function of storing the digital data; A circuit 401 having a function as a row decoder and a circuit 402 having a function as a column decoder for writing a circuit 402 having a function as a row decoder for reading; A circuit 404 having a function as a column decoder for reading and a circuit 405 for controlling the memory address for writing. a circuit 405 having a function of controlling the read memory address; The circuit 406 and the circuit 405 and the circuit 406 specify the write and read addresses. A circuit 407 having a function of calculating the difference and converting the difference of the addresses into analog data. a circuit 408 (D / A conversion circuit) having the function of generating a clock signal in response to the analog data; and a circuit 409 (voltage controlled oscillator circuit) having a function of generating a signal. The child array 400 can be a multi-port SRAM.

[0117] Here, Huffman compression will be described as an example of encoding processing. When the value is 0, 2-bit data "10" is output, and when the differential data is +1, 3-bit data is output. When the differential data is -1, the 3-bit data "111" is output. If the differential data is other than the above, 1 bit of data "0" and the original image data are output. If the original image data is 14 bits, it will be 15 bits, and if the original image data is 8 bits, it will be 9 bits. This becomes the output data of bits.

[0118] When this compression method is applied to the image data of each pixel of a certain 8-bit natural image, the amount of data becomes 1 It is estimated that the number of 0s and 1s in the image data will increase to 12%. Therefore, when applied to one aspect of the present invention, the standard When reading out the image of a frame, the image data may be output directly without compression.

[0119] On the other hand, this compression is applied to the differential data of each pixel of a certain 8-bit continuous natural image. It is estimated that the data volume will be compressed to about 60%. At this time, the differential data will be 0 30% and ±1 occupy 35%. If we further expand it to ±2 and assign the next value, the data The amount of data is estimated to be about 55%.

[0120] As another example of encoding processing, run-length compression will be explained. The most significant bit indicates whether the differential data is positive or negative. That is, 0 is "00000000" + 1 is "00000001" + 2 is "000000 Let's say 10"-1 is "10000000" and -2 is "10000001".

[0121] Run length conversion is performed for each bit. When the data is obtained in the order 0, +1, 0, -1, the The lowest bits (bit 0) are 0, 1, 0, 0, and the first bit is 0, 0, 0, 0. The most significant bit (7th bit) is 0, 0, 0, 1. Since it is differential image data, , the 6th bit changes the least. For example, if the initial value is 0, then the number of 0s or 1s is When the bit changes, the count value is output and the counter circuit is reset. When the counter circuit is saturated, for example, by outputting 0, the external circuit can It can be determined whether it is an output or an output due to a change.

[0122] In the differential image of a natural image, if the bit width of the counter circuit is set to 8 bits, the data volume will be is estimated to be about 117%. For bits with large changes such as the 0th and 7th bits, However, since small count values ​​are output frequently, the amount of data increases. In this case, the data volume is estimated to be 79%. If 0 continues, the output increases due to saturation of the counter circuit. If the bit width of the 1st bit is set to 2, 11, 8, 7, 6, 4, 2, 2 in order, the data volume will be 54%. The compression rate depends on the original image, but the bit width of each bit is different. It is effective to use an upper circuit.

[0123] An example of the operation when the coding using the above-mentioned Huffman compression is applied to the circuit 25 will be explained. .

[0124] The data output to the wiring 93 (OUT3) is input to the circuit 701. The data to be input is 8 bits. The circuit 701 determines whether the data is 0, +1, -1, or something else. When the input data of the circuit 701 is 0, the output value is determined by comparing the 2 to the circuit 702, and outputs 10xxxxxxx to the circuit 703, where x is either 0 or 1. do.

[0125] When the input data of the circuit 701 is +1, 3 is input to the circuit 702 and 110xxxxx is input to the circuit 703. When the input data of the circuit 701 is -1, the circuit 702 outputs 3 and the circuit 703 outputs 1. If the input data of the circuit 701 is dddddddd other than the above, it outputs 11xxxxxx. When this happens, 9 is output to circuit 702 and 0dddddddd is output to circuit 703.

[0126] Before the next data is input to the circuit 701, the circuit 702 repeats decrementing until it reaches 0. Each time the value of the circuit 702 is decreased by 1, the value of the circuit 405 is incremented. The circuit 703 shifts the data by one bit to the left and outputs the most significant bit to the circuit 402. 401 and circuit 402 decode the address value of circuit 405 and receive the input from circuit 703. The 1-bit data thus obtained is written to the storage element array 400 .

[0127] The readout is performed by circuits 403 and 404, and the designated circuits 405 and 406 The difference between the write and read addresses is calculated by the circuit 407. The received digital data is converted into analog data by a circuit 408 and output to a circuit 409. The circuit 409 generates a clock signal in accordance with the analog data and supplies it to the circuit 406. With this circuit configuration, the frequency of the clock signal supplied to the circuit 406 is adjusted to the data. This allows for adjustment according to the amount of data, thereby reducing power consumption. The digital data (compressed differential data) read from the array 400 is input to an external circuit. The image of the target frame can be constructed by expanding the image and adding it to the reference frame. can.

[0128] The pixel circuit 20 may have the configuration shown in FIGS. 12(A), 12(B), and 12(C). ) is a configuration in which the transistor 42 is not provided. In this configuration, the potential of the wiring 71 (VPD) The potential of the node FD1 can be reset by setting the potential of the node FD2 to a low potential. ) is a structure in which either the source or the drain of the transistor 44 is connected to the wiring 91 (OUT). As shown in FIG. 12C, the transistors included in the pixel circuit 20 are p It may include a −ch type transistor.

[0129] The transistors used in the pixel circuit 20 are as shown in FIGS. Alternatively, the transistors 41 to 45 may be provided with back gates. FIG. 13(A) shows a configuration in which a constant potential is applied to the back gate, and the threshold voltage is controlled by In FIG. 13A, as an example, the back gate is connected to a wiring 75 that supplies a low potential. (VC) or wiring 77 (VSS2), but either one of the wiring Also, in FIG. 13(B), the same potential as the front gate is connected to the back gate. This configuration applies a voltage to the gate of the transistor, increasing the on-current and decreasing the off-current. In addition, FIG. 13C shows a method for forming a desired transistor so that it has appropriate electrical characteristics. This is a configuration that combines the configurations of Figures 13(A) and 13(B). There may be a transistor that does not have a gate. The configurations of (A) to (C) of FIG. 12 and 13 (A) to 13 (C) can be combined as needed. It can be combined.

[0130] As shown in FIG. 14, the pixel circuit 20 includes transistors 42 to 45. In FIG. 14, transistor 42 is shared by multiple pixels in the vertical direction. Although the configuration in which the transistor 45 is shared is illustrated, multiple transistors in the horizontal or horizontal / vertical directions may be used. By using such a configuration, the number of transistors per pixel can be increased. The number of registers can be reduced.

[0131] FIG. 14 shows a configuration in which transistors 42 to 45 are shared by four pixels. However, it may be shared by two, three, five or more pixels. This configuration and the configurations shown in Figs. 5(A), 6(A), 12(A) to 12(C), and 13(A) The configurations shown in Figures 13(A) to 13(C) can be combined in any manner.

[0132] A specific configuration example of the imaging device of one embodiment of the present invention will be described with reference to the drawings. (A) shows the photoelectric conversion element PD and the transistor 41 in the pixel circuit 20 shown in FIG. , an example of a specific connection configuration of the transistor 42 and the capacitance element C1 is shown. In FIG. 15(A), the transistors 43, 44 and 45 are not shown. The transistors 41 to 45 and the capacitor C1 are not included in the layer 1100. The photoelectric conversion element PD can be provided in the layer 1200 .

[0133] In the cross-sectional views described in this embodiment, wiring, electrodes, and contact plugs (conductors) are Although the electrical components 81 are shown as separate elements, they may be electrically connected. In some cases, the wiring and the electrode may be provided as the same element. The form in which the electrodes are connected to the wiring is one example, and there are also cases in which the electrodes are directly connected to the wiring.

[0134] Moreover, an insulating layer 82 having a function as a protective film, an interlayer insulating film, or a planarizing film is formed on each element. For example, the insulating layer 82 and the insulating layer 83 are made of silicon oxide. An inorganic insulating film such as a silicon oxide nitride film or an acrylic film can be used. Alternatively, an organic insulating film such as a resin or a polyimide resin may be used. The top surface of the 3rd class may be polished by CMP (Chemical Mechanical Polishing) if necessary. It is preferable to perform a planarization process by a polishing method or the like.

[0135] In addition, there may be cases where some of the wiring etc. shown in the drawings are not provided, or where wiring etc. or traces not shown in the drawings are not provided. In some cases, transistors and the like are included in each layer. Also, layers not shown in the drawings may be included in the laminate structure. In some cases, some layers shown in the drawings may not be included.

[0136] The transistors 41 to 45, which are components of the pixel circuit 20, have an off-state current It is preferable to use an OS transistor with extremely low off-state current. As shown in Figure 5(A), the dynamic range of the image can be expanded. In the circuit configuration of the pixel circuit 20, when the intensity of light incident on the photoelectric conversion element PD is low, The potentials of the nodes AN and FD are reduced. Therefore, even when the gate potential is extremely low, the current corresponding to the gate potential can be accurately generated. Therefore, the range of illuminance that can be detected, i.e., It can expand the dynamic range.

[0137] Furthermore, the low off-current characteristics of the transistors 41 and 43 reduce the voltage at the node FD Therefore, the period during which charge can be held at node FD1 and node FD2 can be made extremely long. Without complicating the circuit configuration or operation method, the GLORI device performs charge accumulation operation simultaneously in all pixels. Note that the imaging device of one embodiment of the present invention can be implemented using a low-power shutter. It can also be operated using a ring shutter system.

[0138] The operation of the imaging device will be explained with reference to Figures 16(A) and 16(B). In (B), "E" means the exposure period, and "R" means the readout period. Also, n is an arbitrary The nth frame (n is a natural number equal to or greater than 2) of -1 is the frame before the nth frame, and n+1 is the frame after the nth frame. Also, Line[1] means the first row of the pixel array 21, and Line[M] means the It means the Mth row of the ray 21 (M is a natural number equal to or greater than 4 in FIG. 16).

[0139] FIG. 16(A) is a diagram showing a schematic diagram of the operation method of the rolling shutter method. The shutter method is an operation method in which exposure and data readout are performed row by row. Therefore, there is no simultaneity in the imaging, and distortion occurs in the image when imaging a moving object.

[0140] FIG. 16(B) is a diagram showing a schematic diagram of the operation method of the global shutter system. The shutter method is an operation method in which all pixels are exposed at the same time and then the data is read out row by row. Therefore, even when capturing an image of a moving object, an image without distortion can be obtained.

[0141] OS transistors have a higher electrical conductivity than transistors that use silicon as the active region or layer. The temperature dependency of the characteristic fluctuation is small, so it can be used in an extremely wide temperature range. Therefore, imaging devices and semiconductor devices having OS transistors are expected to be widely used in automobiles, aircraft, spacecraft, and other applications. It is also suitable for installation on aircraft.

[0142] In addition, an OS transistor has a higher drain breakdown voltage than a Si transistor. In photoelectric conversion elements that use selenium-based materials as the photoelectric conversion layer, avalanche multiplication is utilized. It is preferable to operate the device by applying a relatively high voltage (for example, 10 V or more). By combining an OS transistor with a photoelectric conversion element that uses a selenium-based material as a photoelectric conversion layer, This makes it possible to provide a highly reliable imaging device.

[0143] In FIG. 15A, each transistor has a back gate. As shown in FIG. 15(B), a configuration without a back gate is also possible. As shown in (C), only some of the transistors, for example, the transistor 41, are provided with a back gate. The back gate may be formed on the opposite side of the transistor. In some cases, the back gate may be electrically connected to the front gate of the In some cases, a fixed potential different from that of the back gate may be supplied. This embodiment can also be applied to other pixel configurations described in this embodiment.

[0144] The photoelectric conversion element PD provided in the layer 1200 can be an element of various types. FIG. 15A illustrates a mode in which a selenium-based material is used for the photoelectric conversion layer 561. Photoelectric conversion elements (PDs) made of silicon-based materials have the characteristic of high external quantum efficiency for visible light. In addition, since selenium-based materials have a high light absorption coefficient, they have the advantage of making it easy to thin the photoelectric conversion layer 561. In the photoelectric conversion element PD using selenium-based materials, incident light is absorbed by the avalanche phenomenon. This makes it possible to create a highly sensitive sensor with a large amplification of electrons relative to the amount of light received. By using a photoelectric conversion layer 561 made of a photoelectric conversion material, it is possible to obtain a sufficient photocurrent even if the pixel area is reduced. Therefore, the photoelectric conversion element PD using selenium-based materials can be used in low-light environments. It can be said that this method is also suitable for imaging.

[0145] The selenium-based material can be amorphous selenium or crystalline selenium. For example, crystalline selenium can be obtained by heat treating amorphous selenium after film formation. By making the crystal grain size of the silicon smaller than the pixel pitch, the characteristic variation between pixels is reduced. Crystalline selenium has higher spectral sensitivity and photosensitivity to visible light than amorphous selenium. It has the characteristic of having a high absorption coefficient.

[0146] In FIG. 15A, the photoelectric conversion layer 561 is illustrated as a single layer. As a hole injection blocking layer 568 on the light receiving surface side, gallium oxide, cerium oxide or In- Alternatively, an electrode 566 may be provided, such as a Ga-Zn oxide. An electron injection blocking layer 569 such as nickel oxide or antimony sulfide may be provided on the side. Alternatively, as shown in FIG. 17(C), the hole injection blocking layer 568 and the electron injection blocking layer 56 9 may be provided. As shown in FIG. 5(A) and FIG. 6(A), In the circuit 20, the direction of connection of the photoelectric conversion element PD can be configured to be different. , the hole injection blocking layer 568 and the electron injection blocking layer 56 shown in FIGS. 17(A) to 17(C) It may also be configured to swap 9.

[0147] The photoelectric conversion layer 561 may be a layer containing a compound of copper, indium, and selenium (CIS). Alternatively, a layer containing a compound of copper, indium, gallium, and selenium (CIGS) may be used. CIS and CIGS utilize avalanche multiplication in the same way as selenium alone. A photoelectric conversion element can be formed.

[0148] The photoelectric conversion element PD using a selenium-based material has an electrode 56 formed of, for example, a metal material. A photoelectric conversion layer 561 can be provided between the insulating layer 6 and the light-transmitting conductive layer 562. In addition, CIS and CIGS are p-type semiconductors and do not require cadmium sulfide or An n-type semiconductor such as zinc sulfide may be provided in contact therewith.

[0149] In FIG. 15A, the light-transmitting conductive layer 562 and the wiring 71 are in direct contact with each other. As shown in FIG. 15(A), the two may be connected via a wiring 88. ) is a configuration in which the photoelectric conversion layer 561 and the light-transmitting conductive layer 562 are not separated between pixel circuits. However, as shown in FIG. 18(B), it may be configured such that the circuits are separated. In the case of the photoelectric conversion layer 561, a partition wall 567 made of an insulator is provided in an area where the electrode 566 is not provided. It is preferable to prevent cracks from occurring in the transparent conductive layer 562. Alternatively, as shown in (D), a configuration without the partition wall 567 may be used.

[0150] The electrode 566 and the wiring 71 may be multi-layered. For example, as shown in FIG. As shown, the electrode 566 is made of two layers, a conductive layer 566a and a conductive layer 566b, and the wiring 71 is made of the conductive layer In the configuration of FIG. 19(A), For example, the conductive layer 566a and the conductive layer 71a are formed by selecting a low-resistance metal or the like, and the conductive layer 566b and the conductive layer 71b are formed by selecting a metal or the like having good contact characteristics with the photoelectric conversion layer 561. By adopting such a configuration, the electrical characteristics of the photoelectric conversion element PD can be improved. In addition, some metals may be electrolytically corroded by contacting with the transparent conductive layer 562. Even if such a metal is used for the conductive layer 71a, the This can prevent electrolytic corrosion.

[0151] The conductive layer 566b and the conductive layer 71b are made of, for example, molybdenum or tungsten. The conductive layer 566a and the conductive layer 71a may be made of, for example, aluminum. , titanium, or stacks such as aluminum sandwiched between titanium can be used.

[0152] As shown in FIG. 19(B), the transparent conductive layer 562 and the wiring 71 are connected to the conductor 81 and the wiring 71. Alternatively, the insulating layer 82 may be configured to have multiple layers. For example, as shown in FIG. 19(B), the insulating layer 82 has an insulating layer 82a and an insulating layer 82b. In addition, when the insulating layer 82a and the insulating layer 82b have different etching rates, the conductor 81 The insulating layer used for the interlayer insulating film and the planarizing film is multi-layered. In this case, the insulating layer 82 is a two-layer structure. However, the insulating layer 82 and other insulating layers may be configured to have three or more layers.

[0153] The partition wall 567 can be formed using an inorganic insulator, an insulating organic resin, or the like. The wall 567 is used to shield the transistors and the like from light and / or to reduce the area of ​​the light receiving part per pixel. It may be colored black or the like to determine the position.

[0154] In addition, the photoelectric conversion element PD is made of pin A diode element or the like may also be used.

[0155] For example, Figure 20 shows an example in which a pin-type thin-film photodiode is used as the photoelectric conversion element PD. The photodiode is made up of an n-type semiconductor layer 565, an i-type semiconductor layer 564, and a p-type The i-type semiconductor layer 564 has a structure in which an amorphous semiconductor layer 565 and an i-type semiconductor layer 566 are laminated in this order. It is preferable to use silicon. In addition, the p-type semiconductor layer 563 and the n-type semiconductor layer 5 65 is made of amorphous silicon or microcrystalline silicon containing dopants that impart each conductivity type. A photodiode with amorphous silicon as the photoelectric conversion layer can be used. has high sensitivity in the visible light wavelength range and is easy to detect weak visible light.

[0156] In the photoelectric conversion element PD shown in FIG. 20, the n-type semiconductor layer 565 acting as a cathode is The electrode 566 is electrically connected to the transistor 41. The p-type semiconductor layer 563 acting as a node is electrically connected to the wiring 71 via the wiring 88. That is, Fig. 20 is an example of a configuration according to the circuit diagram shown in Fig. 6(A).

[0157] The connection between the anode and cathode of the photoelectric conversion element PD and the electrode layer and wiring is reversed. In this case, a configuration according to the circuit diagram shown in FIG. 5(A) can be achieved.

[0158] In either case, the photoelectric conversion element PD is arranged so that the p-type semiconductor layer 563 serves as the light receiving surface. By using the p-type semiconductor layer 563 as a light receiving surface, a photoelectric conversion element The output current of the PD can be increased.

[0159] Also, the configuration of the photoelectric conversion element PD having the form of a pin-type thin film photodiode, and The photoelectric conversion element PD and the wiring connection are shown in the examples in Figures 21(A), (B), and (C). The configuration of the photoelectric conversion element PD and the connection between the photoelectric conversion element PD and the wiring may be the same as above. The present invention is not limited to these, and other forms may also be used.

[0160] FIG. 21(A) shows a transparent conductive layer 562 in contact with a p-type semiconductor layer 563 of a photoelectric conversion element PD. The transparent conductive layer 562 acts as an electrode and outputs the photoelectric conversion element PD. The current can be increased.

[0161] The transparent conductive layer 562 is made of, for example, indium tin oxide or silicon-containing indium stannate. oxide, zinc oxide, zinc oxide containing gallium, aluminum zinc oxide containing fluorine, tin oxide containing antimony, graphene or The light-transmitting conductive layer 562 is not limited to a single layer. It may also be a laminate of different films.

[0162] 21(B), the transparent conductive layer 562 and the wiring 71 are connected via the conductor 81 and the wiring 88. The p-type semiconductor layer 563 of the photoelectric conversion element PD and the wiring 71 are electrically connected. It is also possible to configure the connection via the body 81 and the wiring 88. In this case, the light-transmitting conductive layer 562 may not be provided.

[0163] FIG. 21C shows an opening in the insulating layer covering the photoelectric conversion element PD, through which the p-type semiconductor layer 563 is exposed. The transparent conductive layer 562 covering the opening is electrically connected to the wiring 71. It is a composition.

[0164] As shown in FIG. 22, the photoelectric conversion element PD has a silicon substrate 600 as a photoelectric conversion layer. A photodiode having a capacitance of 1000 Ω or less can also be used.

[0165] The photoelectric conversion element PD formed using the above-mentioned selenium-based material or amorphous silicon is formed by film deposition. It is manufactured using general semiconductor manufacturing processes such as a process for forming a semiconductor substrate, a lithography process, and an etching process. In addition, selenium-based materials have high resistance, and as shown in Figure 15(A), The switching layer 561 may be configured not to separate the circuits. The imaging device can be manufactured at a high yield and low cost. When forming a photodiode with 600 as the photoelectric conversion layer, the polishing process and bonding process are This requires highly difficult processes such as

[0166] In addition, the imaging device according to one embodiment of the present invention includes a silicon substrate 600 on which a circuit is formed. For example, as shown in FIG. 23A, a silicon substrate 600 may have an active region. The layer 1400 having the transistor 610 and the transistor 620 is a pixel circuit. FIG. 23B is a cross-sectional view of the transistor in the channel width direction. is equivalent to

[0167] Here, in FIGS. 23(A) and 23(B), the Si transistor is shown as an example of a fin-type structure. However, it may be a planar type as shown in FIG. 24(A). As shown in FIG. 6, the transistor may have an active layer 650 made of a silicon thin film. The active layer 650 is made of polycrystalline silicon or SOI (Silicon on Insulator). r) single crystal silicon.

[0168] The circuit formed on the silicon substrate 600 has a function of reading out the signal output by the pixel circuit and It can have a function of converting signals, for example, the circuit shown in FIG. The transistor 610 ( The gates of transistors 610 (n-ch type) and 620 (p-ch type) are electrically connected. Also, either the source or drain of one transistor is connected to the source of the other transistor. The source or drain of both transistors is electrically connected to the The other of the drains is electrically connected to a different wiring.

[0169] The circuits formed on the silicon substrate 600 are, for example, the circuits 22 and 23 shown in FIG. , circuit 24, circuit 25, etc.

[0170] The silicon substrate 600 is not limited to a bulk silicon substrate, but may be a germanium or silicon germanium substrate. Rumanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide Substrates made of gallium nitride or organic semiconductors can also be used.

[0171] Here, as shown in FIG. 22 and FIGS. 23(A) and 23(B), a transistor having an oxide semiconductor The area where the resistor is formed and the area where the Si device (Si transistor or Si photodiode) is formed are An insulating layer 80 is provided between the region where the gate electrode is formed and the region where the gate electrode is formed.

[0172] Water in the insulating layer provided near the active regions of transistor 610 and transistor 620 The hydrogen terminates the dangling bonds of silicon. This has the effect of improving the reliability of transistor 10 and transistor 620. The hydrogen in the insulating layer provided near the oxide semiconductor layer, which is the active layer such as the oxide semiconductor layer, is This hydrogen is one of the factors that generate carriers in the layer. Therefore, silicon-based semiconductor materials are not suitable for use in semiconductor devices. One layer has a transistor using an oxide semiconductor, and the other layer has a transistor using an oxide semiconductor. When layers are stacked, an insulating layer 80 having the function of preventing hydrogen diffusion is provided between the layers. The insulating layer 80 allows hydrogen to be trapped in one layer, thereby preventing the transistor 6 from The reliability of the transistor 620 can be improved. The diffusion of hydrogen into the other layer is suppressed, which improves the reliability of the transistor 41, etc. can be done.

[0173] The insulating layer 80 may be made of, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. , gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, oxide Hafnium nitride, yttria-stabilized zirconia (YSZ), etc. can be used.

[0174] In the configuration shown in FIGS. 23(A) and 23(B), a circuit (e.g., For example, a driving circuit, a transistor 41, etc., and a photoelectric conversion element PD are formed so as to overlap each other. This allows for a higher pixel density. For example, the number of pixels can be increased to 4K2K, 8K4K, or 16K8K. The pixel circuit 20 is suitable for use in a device. The transistor 45 is formed of a Si transistor, and the transistors 41, 42, and It is also possible to configure the structure so as to have an area overlapping with the resistor 43, the photoelectric conversion element PD, and the like.

[0175] An imaging device according to one embodiment of the present invention can have a structure shown in FIG. The imaging device is a modification of the imaging device shown in FIG. 23(A), and includes an OS transistor and a Si This figure shows an example of configuring a CMOS inverter using transistors.

[0176] Here, the transistor 620, which is a Si transistor provided in the layer 1400, is a p-ch type. The OS transistor 610 provided in the layer 1100 is an n-channel transistor. By providing only the p-channel transistor on the silicon substrate 600, well formation and n-channel Steps such as forming an impurity layer can be omitted.

[0177] The imaging device shown in FIG. 25 uses selenium or the like for the photoelectric conversion element PD. Similarly, a pin type thin film photodiode may be used.

[0178] In the imaging device shown in FIG. 25, the transistor 610 is a transistor formed in the layer 1100. The transistor 41 and the transistor 42 can be fabricated in the same process. The manufacturing process of the imaging device can be simplified.

[0179] Furthermore, the imaging device according to one embodiment of the present invention is formed on a silicon substrate 660 as shown in FIG. The pixel is composed of a photoelectric conversion element PD and an OS transistor formed on it. Alternatively, a structure in which the silicon substrate 600 on which the circuit is formed is bonded to the silicon substrate 600 may be used. By adopting such a configuration, the photoelectric conversion element PD formed on the silicon substrate 660 can be effectively In addition, it is easy to increase the area required for the circuit formed on the silicon substrate 600. High-performance semiconductor devices can be provided by highly integrating silicon transistors. do.

[0180] 26, as shown in FIG. 27, an OS transistor and a Si transistor By using such a configuration, the circuit can be formed by a silicon substrate. This makes it easy to increase the effective area of ​​the photoelectric conversion element PD formed on the plate 660. The circuit formed on the silicon substrate 600 is highly integrated with miniaturized Si transistors. Therefore, a high-performance semiconductor device can be provided.

[0181] In the case of the configuration of FIG. 27, a Si transistor is formed on a silicon substrate 600 and The OS transistors thus formed can be used to construct CMOS circuits. Since the off-state current is extremely low, it is possible to construct a CMOS circuit with extremely low static leakage current. It is possible.

[0182] Note that the configuration of the transistor and the photoelectric conversion element included in the imaging device in this embodiment is This is just an example. For example, any of the transistors 41 to 45 Alternatively, one or more of the transistors may be configured with silicon or the like in the active region or active layer. Alternatively, both or either of the transistors 610 and 620 may be activated. The transistor may also have an oxide semiconductor layer.

[0183] FIG. 28(A) is a cross-sectional view of an example of an imaging device to which a color filter or the like is added. The cross-sectional view shows a part of an area having pixel circuits for three pixels. An insulating layer 2500 is formed on the formed layer 1200. The insulating layer 2500 is irradiated with visible light. A highly transparent silicon oxide film can be used for the passivation. The anti-reflection film may be a silicon nitride film. A dielectric film such as fluorine may be laminated.

[0184] A light-shielding layer 2510 may be formed on the insulating layer 2500. The light-shielding layer 2510 may be formed on the upper The light-shielding layer 2510 has a function of preventing the mixing of colors of light passing through the color filter. Metal layers such as aluminum and tungsten, and dielectric layers that function as anti-reflection films The film may be laminated.

[0185] An organic resin layer 2520 is provided as a planarization film on the insulating layer 2500 and the light-shielding layer 2510. In addition, a color filter 2530 (color filter 25 30a, color filter 2530b, and color filter 2530c) are formed. , color filter 2530a, color filter 2530b, and color filter 2530 c, R (red), G (green), B (blue), Y (yellow), C (cyan), M (magenta), etc. By assigning colors, a color image can be obtained.

[0186] A light-transmitting insulating layer 2560 or the like may be provided on the color filter 2530. do.

[0187] Also, as shown in FIG. 28(B), an optical conversion layer 255 is used instead of the color filter 2530. 0 may be used. By using such a configuration, images in various wavelength regions can be obtained. The imaging device can be configured as follows.

[0188] For example, if a filter that blocks light shorter than the wavelength of visible light is used in the optical conversion layer 2550, infrared The optical conversion layer 2550 can be used as an imaging device. If a filter such as this is used, it can be used as a far-infrared imaging device. If a filter that blocks light with wavelengths longer than visible light is used, it can be used as an ultraviolet imaging device. .

[0189] In addition, if a scintillator is used for the optical conversion layer 2550, it is possible to use a radiation detector such as that used in an X-ray imaging device. It can be used as an imaging device to obtain an image that visualizes the strength of rays. When radiation strikes a scintillator, it emits light through a phenomenon called photoluminescence. The light is converted into visible light, ultraviolet light, or other light (fluorescence). Then, the light is converted into Image data is acquired by detecting the radiation. A position may also be used.

[0190] When exposed to radiation such as X-rays or gamma rays, the scintillator absorbs the energy. These include materials that emit visible and ultraviolet light. For example, Gd2O2S:Tb, Gd2O2S:P r, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, C It is possible to use eF3, LiF, LiI, and ZnO dispersed in resin or ceramics. Cut.

[0191] Photoelectric conversion elements (PDs) made of selenium-based materials directly convert radiation such as X-rays into electric charges. Therefore, a configuration can be made in which a scintillator is not required.

[0192] Also, as shown in FIG. 28(C), the color filter 2530a, the color filter 2530 A microlens array 2540 may be provided on the color filters 2530b and 2530c. The light passing through each lens of the microlens array 2540 passes through the color filter directly below. The light passes through the photoelectric conversion element PD and is irradiated thereon. The area other than the layer 1200 shown in FIG.

[0193] FIG. 29 shows a pixel circuit 20 according to one embodiment of the present invention and the microlens array shown in FIG. 28(C). FIG. 29 is a diagram illustrating a specific layered structure of the image shown in FIG. 23(A). When the pixel shown in FIG. 27 is used, the configuration shown in FIG. This becomes:

[0194] In this way, each of the photoelectric conversion element PD, the circuit included in the pixel circuit 20, and the drive circuit Since the imaging device can be configured so that the areas overlap each other, the imaging device can be made smaller. This can be done.

[0195] Also, a configuration may be adopted in which a diffraction grating 1500 is provided as shown in FIGS. The image of the object (diffraction image) through the diffraction grating 1500 is captured by the pixel, and the captured image at the pixel is The input image (image of the subject) can be constructed by arithmetic processing from the image. By using a diffraction grating 1500 instead, the cost of the imaging device can be reduced.

[0196] The diffraction grating 1500 can be made of a light-transmitting material, such as silicon oxide. An inorganic insulating film such as a silicon oxide nitride film or an acrylic resin film can be used. Alternatively, an organic insulating film such as an oil film or a polyimide resin film may be used. and an organic insulating film may be laminated.

[0197] The diffraction grating 1500 can be formed by a lithography process using a photosensitive resin or the like. It can also be formed using a lithography process and an etching process. It can also be formed by using nanoimprint lithography, laser scribing, or the like. do.

[0198] A distance X may be provided between the diffraction grating 1500 and the microlens array 2540. X can be 1 mm or less, preferably 100 μm or less. Alternatively, a light-transmitting material may be provided as a sealing layer or an adhesive layer. An inert gas such as a rare gas can be sealed in the gap. Epoxy resin or polyimide resin may be provided in the gap. In addition, when the microlens array 2540 is not provided, In this case, a distance X may be provided between the color filter 2530 and the diffraction grating 1500 .

[0199] The imaging device may also be curved as shown in FIG. 31(A1) and FIG. 31(B1). FIG. 31(A1) shows the state in which the imaging device is bent along the two-dot chain line Y1-Y2 in the same figure. FIG. 31(A2) shows the area indicated by the two-dot chain line X1-X2 in FIG. 31(A1). 31(A3) is a cross-sectional view of the area indicated by the two-dot chain line Y1-Y2 in FIG. FIG.

[0200] FIG. 31(B1) shows the case where the imaging device is bent along the two-dot chain line X3-X4 in the same figure, and The figure shows a state where the bent portion is bent along the two-dot chain line Y3-Y4. 31(B1) is a cross-sectional view of the portion indicated by the two-dot chain line X3-X4 in FIG. 31(B1) is a cross-sectional view of a portion indicated by a two-dot chain line Y3-Y4 in FIG.

[0201] By curving the imaging device, it is possible to reduce field curvature and astigmatism. This makes it easier to design the optical system, such as lenses, that are used in combination with the imaging device. For example, The number of lenses required for aberration correction can be reduced, making it easier to make imaging devices smaller and lighter. In addition, the quality of the captured image can be improved.

[0202] Note that one embodiment of the present invention has been described in this embodiment. However, the present invention is not limited to these. That is, various inventive aspects are described in this and other embodiments. Therefore, one embodiment of the present invention is not limited to a specific embodiment. However, one embodiment of the present invention is not limited to this. In some cases or depending on the situation, one aspect of the present invention may be applied to an imaging device. For example, one embodiment of the present invention may be applied to a semiconductor device having another function. For example, in one embodiment of the present invention, a channel formation region, a source / drain region, etc. of a transistor However, one embodiment of the present invention is not limited thereto. In some cases, or depending on the situation, various transistors in one aspect of the present invention may be used. a transistor channel forming region, a transistor source / drain region, etc. may have various semiconductors. In one embodiment, various transistors, a channel formation region of a transistor, or a transistor The source and drain regions of the transistor are made of, for example, silicon, germanium, silicon gel, etc. aluminum, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, The material may include at least one of gallium nitride and organic semiconductors. For example, depending on the circumstances, various transistors in one aspect of the present invention may be a transistor channel forming region, or a transistor source / drain region, etc. The layer may not include an oxide semiconductor.

[0203] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0204] (Embodiment 2) In this embodiment, a transistor including an oxide semiconductor that can be used in one embodiment of the present invention will be described. The following description will be given with reference to the drawings. For clarity, some elements may be enlarged, reduced, or omitted.

[0205] 32A and 32B are a top view and a cross-sectional view of a transistor 101 of one embodiment of the present invention. FIG. 32(A) is a top view, and a cross section taken along the dashed line B1-B2 shown in FIG. corresponds to Fig. 32(B). Also, the cross section in the direction of the dashed line B3-B4 shown in Fig. 32(A) is 34(A). The dashed line B1-B2 direction is the channel length direction, and the dashed line B The 3-B4 direction is called the channel width direction.

[0206] The transistor 101 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 140 electrically connected to the oxide semiconductor layer 130; the oxide semiconductor layer 130, the conductive layer 140, and the insulating layer 11 in contact with the conductive layer 150. 60, a conductive layer 170 in contact with the insulating layer 160, a conductive layer 140, a conductive layer 150, an insulating layer 1 60 and an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. Furthermore, the insulating layer 180 may have a function as a planarizing film, if necessary. .

[0207] Here, the conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0208] Also, the region 231 shown in FIG. 32(B) is a source region, the region 232 is a drain region, and the region 2 The region 33 can function as a channel forming region. The conductive layers 140 and 150 are in contact with each other. If a conductive material that easily bonds with oxygen is used as the electrode, the resistance of the region 231 and the region 232 can be reduced. It is possible.

[0209] Specifically, the oxide semiconductor layer 130 is in contact with the conductive layer 140 and the conductive layer 150. Oxygen vacancies occur in the oxide semiconductor layer 130, and the oxygen vacancies and the remaining oxygen in the oxide semiconductor layer 130 Due to interaction with hydrogen that is retained or diffuses from the outside, regions 231 and 232 have low resistance. The resistance becomes n-type.

[0210] The functions of the "source" and "drain" of a transistor are different for transistors of different polarities. This may be reversed when using a current source or when the direction of current changes during circuit operation. For this reason, the terms "source" and "drain" are used interchangeably in this specification. The term "electrode layer" can also be used interchangeably with "wiring." can.

[0211] In addition, the conductive layer 170 is shown as an example formed of two layers, a conductive layer 171 and a conductive layer 172. However, it may be a single layer or a laminate of three or more layers. The present invention can also be applied to other transistors.

[0212] Although the conductive layer 140 and the conductive layer 150 are shown as being formed as a single layer, they may be formed as two or more layers. The above stacked structure may also be applied to other transistors described in this embodiment. can.

[0213] The transistor of one embodiment of the present invention may have the structure shown in FIGS. FIG. 32C is a top view of the transistor 102. The cross section in the 1-C2 direction corresponds to FIG. 32(D). The cross section in the direction of -C4 corresponds to FIG. 34(B). The direction of the dashed dotted line C3-C4 is called the channel width direction.

[0214] The transistor 102 is formed by connecting the edge of the insulating layer 160, which acts as a gate insulating film, and the gate electrode layer 101, except that the edge of the conductive layer 170 acting as a The transistor 102 has a structure in which the conductive layer 140 and the conductive layer 150 are insulating layers. Since the edge layer 160 is widely covered, the conductive layers 140, 150, and 170 are The resistance between the gate and the gate electrode is high, and the gate leakage current is low.

[0215] The transistor 101 and the transistor 102 are formed by the conductive layer 170 and the conductive layer 140 and the conductive layer 140. The top gate structure has a region where the gate electrode 150 overlaps the gate electrode 150. The width is preferably 3 nm or more and less than 300 nm in order to reduce the parasitic capacitance. In this structure, no offset region is formed in the oxide semiconductor layer 130, and therefore, the on-current is high. This makes it easier to form a small transistor.

[0216] The transistor of one embodiment of the present invention may have the structure shown in FIGS. FIG. 32E is a top view of the transistor 103. The cross section in the 1-D2 direction corresponds to FIG. 32(F). Also, the dashed line D3 shown in FIG. 32(E) The cross section in the -D4 direction corresponds to FIG. 34(A). The direction of the dashed dotted line D3-D4 is called the channel width direction.

[0217] The transistor 103 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; an insulating layer 160 in contact with the oxide semiconductor layer 130; and an insulating layer covering the oxide semiconductor layer 130, the insulating layer 160, and the conductive layer 170. The edge layer 175, the insulating layer 180 in contact with the insulating layer 175, and the insulating layer 175 and the insulating layer 180 a conductive layer 140 electrically connected to the oxide semiconductor layer 130 through an opening provided in the and a conductive layer 150. If necessary, an insulating layer 180, a conductive layer 140, and a conductive layer An insulating layer (flattening film) or the like may be provided in contact with 150 .

[0218] Here, the conductive layer 140 is a source electrode layer, the conductive layer 150 is a drain electrode layer, and the insulating layer 160 is The gate insulating film and the conductive layer 170 can each function as a gate electrode layer.

[0219] Also, the region 231 shown in FIG. 32(F) is a source region, the region 232 is a drain region, and the region 2 The region 33 can function as a channel forming region. The region 231 and the region 232 are insulating layers. For example, if an insulating material containing hydrogen is used as the insulating layer 175, the region The resistance of the region 231 and the region 232 can be reduced.

[0220] Specifically, the insulating layer 175 is formed in the regions 231 and 232 by the steps up to the formation of the insulating layer 175. The oxygen vacancies caused by the ion implantation and the hydrogen diffusing from the insulating layer 175 into the regions 231 and 232 interact with each other. As a result, the regions 231 and 232 become n-type with low resistance. As the material, for example, silicon nitride or aluminum nitride can be used.

[0221] Furthermore, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 33A is a top view of the transistor 104. The cross section in the 1-E2 direction corresponds to FIG. 33(B). The cross section in the -E4 direction corresponds to FIG. 34(A). The direction of the dashed dotted line E3-E4 is called the channel width direction.

[0222] The transistor 104 is configured such that the conductive layer 140 and the conductive layer 150 are disposed at the edge of the oxide semiconductor layer 130. The transistor 103 has a similar structure to the transistor 103 except that the transistor 103 is in contact with the transistor 103 so as to cover the transistor 103.

[0223] The regions 331 and 334 shown in FIG. 33B are source regions, and the regions 332 and The region 335 can function as a drain region, and the region 333 can function as a channel forming region. .

[0224] Regions 331 and 332 correspond to regions 231 and 232 in transistor 101. As with 2, the resistance can be reduced.

[0225] Regions 334 and 335 are the same as regions 231 and 232 in transistor 103. The resistance of the region 334 in the channel length direction can be reduced in the same manner as the region 232. and when the length of region 335 is 100 nm or less, preferably 50 nm or less, the gate The on-current does not decrease significantly due to the contribution of the electric field. In some cases, the resistance reduction step 5 is not performed.

[0226] The transistor 103 and the transistor 104 are formed by the conductive layer 170 and the conductive layer 140 and the conductive layer 140. The self-aligned structure does not have an area where the conductive layer 150 overlaps. The parasitic capacitance between the gate electrode layer and the source and drain electrode layers of the transistor is extremely small. Therefore, it is suitable for high-speed operation.

[0227] The transistor of one embodiment of the present invention may have the structure shown in FIGS. FIG. 33C is a top view of the transistor 105. The cross section in the 1-F2 direction corresponds to FIG. 33(D). Also, the dashed line F3 shown in FIG. 33(C) The cross section in the direction of -F4 corresponds to FIG. 34(A). The direction of the dashed dotted line F3-F4 is called the channel width direction.

[0228] The transistor 105 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; and a conductive layer the oxide semiconductor layer 130, the conductive layer 141, and the insulating layer 160 in contact with the conductive layer 151. the conductive layer 170 in contact with the insulating layer 160, the oxide semiconductor layer 130, the conductive layer 141, and the conductive layer 151, insulating layer 160, and conductive layer 170; insulating layer 175; and an insulating layer 180 that is electrically conductive through openings in the insulating layers 175 and 180. Conductive layer 142 and conductive layer 15 are electrically connected to layer 141 and conductive layer 151, respectively. 2. In addition, if necessary, the insulating layer 180, the conductive layer 142, and the conductive layer 152 are in contact with each other. The insulating layer may be provided.

[0229] Here, the conductive layer 141 and the conductive layer 151 are in contact with the top surface of the oxide semiconductor layer 130 and are It is designed so that it does not come into contact with the

[0230] The transistor 105 has a conductive layer 141 and a conductive layer 151, an insulating layer 175, and a and an opening formed in the insulating layer 180, and the conductive layer 14 is formed through the opening. 1 and the conductive layer 151 are electrically connected to the conductive layer 142 and the conductive layer 152, respectively. The conductive layer 140 (conductive layer 141) has a structure similar to that of the transistor 101. and conductive layer 142) can act as a source electrode layer, and conductive layer 150 (conductive Layer 151 and conductive layer 152) can act as a drain electrode layer.

[0231] The transistor of one embodiment of the present invention may have the structure shown in FIGS. FIG. 33E is a top view of the transistor 106. The cross section in the 1-G2 direction corresponds to FIG. 33(F). The cross section in the -G4 direction corresponds to FIG. 34(A). The direction of the dashed line G3-G4 is called the channel width direction.

[0232] The transistor 106 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. an oxide semiconductor layer 130; a conductive layer 141 electrically connected to the oxide semiconductor layer 130; and a conductive layer the insulating layer 160 in contact with the oxide semiconductor layer 130; layer 170, an insulating layer 120, an oxide semiconductor layer 130, a conductive layer 141, a conductive layer 151, an insulating layer 160, an insulating layer 175 in contact with the conductive layer 170, and an insulating layer 180 in contact with the insulating layer 175. , the conductive layer 141 and the conductive layer 142 are electrically connected to each other through openings provided in the insulating layer 175 and the insulating layer 180 . The conductive layer 142 and the conductive layer 152 are electrically connected to the layer 151, respectively. If necessary, the insulating layer 180, the conductive layer 142, and the insulating layer (planarization film) in contact with the conductive layer 152 are ) and the like.

[0233] Here, the conductive layer 141 and the conductive layer 151 are in contact with the top surface of the oxide semiconductor layer 130 and are It is designed so that it does not come into contact with the

[0234] Transistor 106 has the same structure as transistor 106 except that it has conductive layer 141 and conductive layer 151. The conductive layer 140 (conductive layer 141 and conductive layer 142) has the same structure as the capacitor 103. The conductive layer 150 (conductive layer 151 and conductive layer 152) can act as a base electrode layer. 2) can act as a drain electrode layer.

[0235] In the configuration of transistor 105 and transistor 106, conductive layer 140 and conductive layer 1 50 is not in contact with the insulating layer 120, the oxygen in the insulating layer 120 is and the conductive layer 150 is less likely to take away the oxide from the insulating layer 120 into the oxide semiconductor layer 130. This makes it easier to supply the raw material.

[0236] Regions 231 and 232 in transistor 103, transistor 104 and In the region 334 and the region 335 of the transistor 106, oxygen vacancies are formed to increase the conductivity. Impurities that form oxygen vacancies in the oxide semiconductor layer may be added. Examples include phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, and helix. Um, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, One or more impurities selected from zinc and carbon can be used. The methods of adding the metal oxide include plasma treatment, ion implantation, ion doping, plasma ion implantation, and the like. A method such as ion implantation can be used.

[0237] When the above-described elements are added to the oxide semiconductor layer as impurity elements, the metal in the oxide semiconductor layer The bond between the element and oxygen is broken, and oxygen vacancies are formed. The interaction between the electron vacancies and hydrogen remaining in the oxide semiconductor layer or added later causes the oxide The conductivity of the semiconductor layer can be increased.

[0238] When hydrogen is added to an oxide semiconductor in which oxygen vacancies have been formed by adding an impurity element, the oxygen vacancies are Hydrogen enters the loss site and a donor level is formed near the conduction band. Here, an oxide semiconductor that has been made into a conductor is referred to as an oxide conductor. Note that an oxide conductor has a light-transmitting property like an oxide semiconductor.

[0239] Oxide conductors are degenerate semiconductors, and the conduction band edge and the Fermi level are coincident or nearly coincident. Therefore, the oxide conductor layer and the source and drain electrode layers are The contact between the oxide conductor layer and the source electrode layer and the conductive layer that functions as a The contact resistance between the conductive layer functioning as the drain electrode layer and the conductive layer functioning as the drain electrode layer can be reduced.

[0240] Further, the transistor of one embodiment of the present invention can be formed by the following methods. 34(C) and (D) are cross-sectional views in the channel length direction shown in FIG. 34(F) and FIG. As shown in the cross-sectional view in the width direction of the glass substrate, a conductive layer 173 is formed between the oxide semiconductor layer 130 and the substrate 115. The conductive layer 173 may be used as a second gate electrode layer (back gate). By doing so, it is possible to increase the on-current and control the threshold voltage. In the cross-sectional views shown in A), B, C, D, E, and F, the conductive layer 173 The width of the conductive layer 173 may be shorter than that of the oxide semiconductor layer 130. It may be shorter than the width of 70.

[0241] To increase the on-current, for example, the conductive layer 170 and the conductive layer 173 are set to the same potential, and the double In addition, to control the threshold voltage, A constant potential different from that of the conductive layer 170 may be applied to the conductive layer 173. To make the conductive layers 170 and 173 have the same potential, for example, as shown in FIG. 73 can be electrically connected via a contact hole.

[0242] In addition, in the transistors 101 to 106 in FIGS. 32 and 33, Although the oxide semiconductor layer 130 is a single layer, the oxide semiconductor layer 130 may be a multilayer. The oxide semiconductor layer 130 of the transistors 101 to 106 may be formed as shown in FIG. 36(B), (C) or 36(D), (E) can be replaced with the oxide semiconductor layer 130 shown in FIG. This can be done.

[0243] FIG. 36(A) is a top view of the oxide semiconductor layer 130, and FIGS. 36(B) and 36(C) are views of the two-layer structure. 36(D) and (E) are cross-sectional views of an oxide semiconductor layer 130 having a three-layer structure. 1 is a cross-sectional view of an oxide semiconductor layer 130 having a structure.

[0244] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are Oxide semiconductor layers or the like having different compositions can be used.

[0245] Furthermore, the transistor of one embodiment of the present invention may have a structure illustrated in FIGS. FIG. 37A is a top view of the transistor 107. The cross section in the 1-H2 direction corresponds to FIG. 37(B). The cross section in the -H4 direction corresponds to Fig. 39(A). The longitudinal direction, the direction of the dashed dotted line H3-H4, is called the channel width direction.

[0246] The transistor 107 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. a stack of a compound semiconductor layer 130a and an oxide semiconductor layer 130b, and a The conductive layer 140 and the conductive layer 150 that are connected, and the stacked layer, the conductive layer 140 and the conductive layer 15 0, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , the conductive layer 170 in contact with the insulating layer 160, the conductive layer 140, the conductive layer 150, the oxide semiconductor layer 130c, an insulating layer 175 in contact with the insulating layer 160 and the conductive layer 170, and a and an insulating layer 180 that functions as a planarizing film, if necessary. A function may be added.

[0247] The transistor 107 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a layer (oxide semiconductor layer 130b). The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c). The conductive layer 140 and the conductive layer 150 are the insulating layer 160. The oxide semiconductor layer 130c is formed between the first and second electrodes 130a and 130b. It has the same configuration as the transistor 101 .

[0248] The transistor of one embodiment of the present invention may have the structure shown in FIGS. FIG. 37C is a top view of the transistor 108. The cross section in the direction of 1-I2 corresponds to FIG. 37(D). The cross section in the direction of -I4 corresponds to Fig. 39(B). The longitudinal direction, the direction of the dashed dotted line I3-I4, is called the channel width direction.

[0249] The transistor 108 is formed such that the insulating layer 160 and the end of the oxide semiconductor layer 130c are connected to the conductive layer 17. It differs from transistor 107 in that it does not coincide with the edge of 0.

[0250] The transistor of one embodiment of the present invention may have the structure shown in FIGS. FIG. 37E is a top view of the transistor 109. The cross section in the 1-J2 direction corresponds to FIG. 37(F). Also, the dashed line J3 shown in FIG. 37(E) The cross section in the -J4 direction corresponds to Fig. 39(A). The longitudinal direction, the direction of the dashed dotted line J3-J4, is called the channel width direction.

[0251] The transistor 109 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. A stack of a compound semiconductor layer 130a and an oxide semiconductor layer 130b, and an oxide semiconductor layer in contact with the stack. the oxide semiconductor layer 130c, the insulating layer 160 in contact with the oxide semiconductor layer 130c, and the insulating layer 16 0, the stack, the oxide semiconductor layer 130c, the insulating layer 160, and the conductive layer 170 An insulating layer 175 covering the conductive layer 170, an insulating layer 180 in contact with the insulating layer 175, and and a conductive layer 14 electrically connected to the stack through an opening provided in the insulating layer 180. 0 and conductive layer 150. In addition, an insulating layer 180, a conductive layer 140 and An insulating layer (planarizing film) or the like may be provided in contact with the conductive layer 150.

[0252] The transistor 109 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a layer (oxide semiconductor layer 130b). The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c). The transistor 103 has the same configuration as the transistor 103 except that it is a compound semiconductor layer 130c.

[0253] The transistor of one embodiment of the present invention may have a structure shown in FIGS. FIG. 38A is a top view of the transistor 110. The cross section in the direction of 1-K2 corresponds to FIG. 38(B). The cross section in the direction of -K4 corresponds to Fig. 39(A). The longitudinal direction, the direction of the dashed dotted line K3-K4, is called the channel width direction.

[0254] The transistor 110 has two oxide semiconductor layers 130 in the regions 331 and 332. In the region 333, the oxide semiconductor layer 130a is a layer (oxide semiconductor layer 130b). The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c). The transistor 104 has the same configuration as the transistor 104 except that it is a compound semiconductor layer 130c.

[0255] The transistor of one embodiment of the present invention may have the structure shown in FIGS. FIG. 38C is a top view of the transistor 111. The cross section in the 1-L2 direction corresponds to FIG. 38(D). Also, the dashed line L3 shown in FIG. 38(C) The cross section in the -L4 direction corresponds to Figure 39(A). The longitudinal direction, the direction of the dashed dotted line L3-L4, is called the channel width direction.

[0256] The transistor 111 includes an insulating layer 120 in contact with the substrate 115 and an oxide layer in contact with the insulating layer 120. a stack of a compound semiconductor layer 130a and an oxide semiconductor layer 130b, and a The conductive layer 141 and the conductive layer 151 that are connected, and the stacked layer, the conductive layer 141 and the conductive layer 15 1, and an insulating layer 160 in contact with the oxide semiconductor layer 130c. , the conductive layer 170 in contact with the insulating layer 160, the stacked conductive layer 141, the conductive layer 151, the oxide an insulating layer 175 in contact with the compound semiconductor layer 130c, the insulating layer 160, and the conductive layer 170; The insulating layer 180 is in contact with the insulating layer 175, and openings are formed in the insulating layer 175 and the insulating layer 180. Conductive layer 142 and conductive layer 151 are electrically connected to conductive layer 141 and conductive layer 151, respectively. The conductive layer 152 is also provided. If necessary, an insulating layer 180, a conductive layer 142, and a conductive layer 1 An insulating layer (flattening film) or the like may be provided in contact with 52.

[0257] The transistor 111 has two oxide semiconductor layers 130 in the regions 231 and 232. In the region 233, the oxide semiconductor layer 130a is a layer (oxide semiconductor layer 130b). The oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c). and the conductive layer 141 and the conductive layer 151 are the insulating layer 16. 0, except that a part of the oxide semiconductor layer (oxide semiconductor layer 130c) is interposed between The transistor has a similar structure to that of the transistor 105 .

[0258] The transistor of one embodiment of the present invention may have the structure shown in FIGS. FIG. 38(E) is a top view of the transistor 112, and the dashed line M The cross section in the 1-M2 direction corresponds to FIG. 38(F). Also, the dashed line M3 shown in FIG. 38(E) The cross section in the direction of -M4 corresponds to Fig. 39(A). The longitudinal direction, the direction of the dashed dotted line M3-M4, is called the channel width direction.

[0259] The transistor 112 is configured as follows: The oxide semiconductor layer 130 is a two-layer structure (oxide semiconductor layer 130a and oxide semiconductor layer 130b). In the region 333, the oxide semiconductor layer 130 is made up of three layers (oxide semiconductor layer 130a, oxide semiconductor layer 130b, oxide semiconductor layer 130c, oxide semiconductor layer 130d, oxide semiconductor layer 130e, oxide semiconductor layer 130f ...). The transistor 106 and the transistor 107 are the same except that the first and second layers are the organic semiconductor layer 130b and the oxide semiconductor layer 130c. They have a similar configuration.

[0260] Further, the transistor of one embodiment of the present invention can be formed by the following methods. 39(C) and (D) are cross-sectional views in the channel length direction shown in FIG. As shown in the cross-sectional view in the width direction of the glass substrate, a conductive layer 173 is formed between the oxide semiconductor layer 130 and the substrate 115. The conductive layer may be used as a second gate electrode layer (back gate). This allows for an increase in on-current and control of the threshold voltage. In the cross-sectional views shown in (B), (C), (D), (E), and (F), the width of the conductive layer 173 is determined by the amount of oxygen. The width of the conductive layer 173 may be set to be shorter than that of the conductive layer 170. It may be shorter than the width.

[0261] Further, a transistor of one embodiment of the present invention may have the structure shown in FIGS. FIG. 41(A) is a top view, and FIG. 41(B) is a top view of the 41 is a cross-sectional view taken along the dashed line N1-N2 and the dashed line N3-N4. In the top view of (A), some elements are omitted for clarity.

[0262] The transistor 113 shown in FIGS. 41(A) and 41(B) is a transistor including a substrate 115 and a substrate 11 5, and the oxide semiconductor layer 130 on the insulating layer 120 (oxide semiconductor layer 130 a, oxide semiconductor layer 130b, oxide semiconductor layer 130c), and The conductive layer 140 and the conductive layer 150 are spaced apart from each other, and the oxide semiconductor layer 130 The insulating layer 160 is in contact with the oxide film 160, and the conductive layer 170 is in contact with the insulating layer 160. The semiconductor layer 130c, the insulating layer 160, and the conductive layer 170 are the insulating layer on the transistor 113. The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the insulating layer 12 provided on the substrate 190 It is provided with an opening that reaches 0.

[0263] The configuration of the transistor 113 is different from the configurations of the other transistors described above in that the source The overlapping area between the conductor that will become the electrode or drain electrode and the conductor that will become the gate electrode is small. Therefore, the parasitic capacitance can be reduced. The upper surface of the transistor 113 is shown in FIG. CMP (Chemical Mechanical Polishing) It is preferable to flatten the surface by using a method such as a flattening method, but it is also possible to adopt a configuration in which flattening is not performed.

[0264] In addition, the conductive layer 140 (source electrode layer) and the conductive The layer 150 (drain electrode layer) is the oxide semiconductor layer 1 shown in the top view of FIG. 30, conductive layer 140, and conductive layer 150 are shown). (W OS ) of the conductive layer 140 and the conductive layer 150. SD ) is formed long It may be formed short. OS ≧W SD (W SD is W OS (below) As a result, the gate electric field is easily applied to the entire oxide semiconductor layer 130, and the electric field of the transistor As shown in FIG. 42(C), the conductive layer 140 and The conductive layer 150 may be formed only in the region overlapping with the oxide semiconductor layer 130 .

[0265] In the transistors of one embodiment of the present invention (transistors 101 to 113), In either configuration, the conductive layer 170, which is the gate electrode layer, is connected to the insulating layer 170, which is the gate insulating film. The oxide semiconductor layer 130 is electrically surrounded in the channel width direction through the gate insulating film 160, and the on-current Such a transistor structure is called a surrounded channel This is called the (s-channel) structure.

[0266] In addition, a transistor having the oxide semiconductor layer 130a and the oxide semiconductor layer 130b, etc. and oxide semiconductor layer 130a, oxide semiconductor layer 130b, and oxide semiconductor layer 130c. In a transistor having the above structure, the oxide semiconductor layer 130 is made of two or three layers of material. By appropriately selecting the material, a current can be passed through the oxide semiconductor layer 130b. By flowing current through the conductor layer 130b, the device is less susceptible to the influence of interface scattering and a high on-current can be obtained. Therefore, the on-current can be improved by increasing the thickness of the oxide semiconductor layer 130b. This may occur.

[0267] With the above structure, the electrical characteristics of the transistor can be improved.

[0268] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0269] (Embodiment 3) In this embodiment, components of the transistor shown in Embodiment 2 will be described in detail. do.

[0270] The substrate 115 may be a glass substrate, a quartz substrate, a semiconductor substrate, a ceramic substrate, or a substrate with an insulating surface. Alternatively, a metal substrate or a transistor or a photodiode can be used. A silicon substrate on which an insulating layer, wiring, contact plugs, etc. are formed, and The silicon substrate may be formed with a conductor or the like that functions as a gate. When forming a p-ch transistor on the substrate, n - Silicon substrate with conductivity type It is preferable to use a plate. - SOI substrate with type or i-type silicon layer In addition, when the transistor provided on the silicon substrate is a p-ch type, The surface orientation of the surface on which the transistor is formed is a (110) silicon substrate. It is preferable to form a p-channel transistor on the (110) plane to increase the mobility. It is possible.

[0271] The insulating layer 120 serves to prevent the diffusion of impurities from elements contained in the substrate 115. In addition, it can also play a role in supplying oxygen to the oxide semiconductor layer 130. The insulating layer 120 is preferably an insulating film containing oxygen, and contains more oxygen than the stoichiometric composition. The insulating layer 120 is preferably an insulating film containing a fluorine atom in an amount equivalent to an oxygen atom measured by the TDS method. The calculated amount of oxygen released is 1.0 x 10 19 atoms / cm 3 It is preferable that this is equal to or greater than this. The surface temperature of the film during the TDS analysis was 100°C or higher and 700°C or lower, or 10 The temperature is set to a range of 0° C. to 500° C. In addition, if the substrate 115 is a substrate on which other devices are formed, In this case, the insulating layer 120 also functions as an interlayer insulating film. It is preferable to perform a planarization process by CMP or the like to make the surface flat.

[0272] For example, the insulating layer 120 may be made of aluminum oxide, magnesium oxide, silicon oxide, or Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide , lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. , silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, etc. The insulating film may be a laminate of the above materials. It is also possible.

[0273] In this embodiment, the oxide semiconductor layer 130 included in the transistor is a) The oxide semiconductor layer 130b and the oxide semiconductor layer 130c are stacked in this order from the insulating layer 120 side. The details will be mainly explained for the three-layer structure.

[0274] Note that when the oxide semiconductor layer 130 is a single layer, the oxide semiconductor layer 13 Just use the layer corresponding to 0b.

[0275] In addition, when the oxide semiconductor layer 130 is a two-layer structure, the oxide semiconductor layer 13 A layer corresponding to oxide semiconductor layer 130a and a layer corresponding to oxide semiconductor layer 130b are formed in this order from the insulating layer 120 side. In this structure, the oxide semiconductor layer 130a and the oxide semiconductor layer It can also be swapped with 130b.

[0276] In addition, when the oxide semiconductor layer 130 has four or more layers, for example, A configuration in which another oxide semiconductor layer is added to the oxide semiconductor layer 130 having a three-layer structure. can be done.

[0277] For example, the oxide semiconductor layer 130b may include the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. The oxide has a larger electron affinity (energy from the vacuum level to the bottom of the conduction band) than the oxide layer 130c. The electron affinity is determined by the energy difference between the vacuum level and the top of the valence band (ion The energy gap between the bottom of the conduction band and the top of the valence band is calculated from the This can be calculated by subtracting the

[0278] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c constitute the oxide semiconductor layer 130b. For example, the energy of the conduction band minimum is 0.05 eV, 0.07 eV, 0.1 eV, or 0.15 eV or more than 0b and is close to the vacuum level within the range of 2 eV, 1 eV, 0.5 eV, or 0.4 eV. It is preferable that the insulating film be formed of a thin oxide semiconductor.

[0279] In such a structure, when an electric field is applied to the conductive layer 170, the oxide semiconductor layer 130 That is, a channel is formed in the oxide semiconductor layer 130b, which has the smallest energy at the bottom of the conduction band. Therefore, it can be said that the oxide semiconductor layer 130b has a region that functions as a semiconductor. However, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are insulators or semi-insulators. It can also be said that it has areas that function in this way.

[0280] The oxide semiconductor layer 130a contains one or more metal elements constituting the oxide semiconductor layer 130b. Since the oxide semiconductor layer 130b and the insulating layer 120 are in contact with each other, In contrast, an interface state is formed at the interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130a. The interface states may form a channel, which may cause the transistor to malfunction. Therefore, the provision of the oxide semiconductor layer 130a As a result, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced. In addition, the reliability of the transistor can be improved.

[0281] The oxide semiconductor layer 130c contains one or more metal elements constituting the oxide semiconductor layer 130b. Since the oxide semiconductor layer 130b and the gate insulating film (insulating layer 160) are in contact with each other, The interface between the oxide semiconductor layer 130b and the oxide semiconductor layer 130c is Therefore, the oxide semiconductor layer 130c is provided. This makes it possible to increase the field effect mobility of the transistor.

[0282] The oxide semiconductor layer 130a and the oxide semiconductor layer 130c may contain, for example, Al, Ti, Ga , Ge, Y, Zr, Sn, La, Ce or Hf as an element having a higher conductivity than the oxide semiconductor layer 130b. Specifically, the atomic ratio is preferably 1.5 times or more. The amount is preferably two times or more, and more preferably three times or more. The above elements bond strongly with oxygen. Therefore, the oxide semiconductor layer has a function of suppressing oxygen vacancies from occurring in the oxide semiconductor layer. The oxide semiconductor layer 130a and the oxide semiconductor layer 130c have a higher oxide content than the oxide semiconductor layer 130b. It can be said that element deficiency is less likely to occur.

[0283] In addition, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130 The oxide semiconductor that can be used as c contains at least In or Zn. It is preferable that the oxide semiconductor contains both In and Zn. In order to reduce the variation in the electrical characteristics of the transistors, stabilizers were also used. It is preferred that it contains

[0284] The stabilizer may be Ga, Sn, Hf, Al, or Zr. The stabilizers are the lanthanides La, Ce, Pr, Nd, Sm, Eu, and G. Examples include d, Tb, Dy, Ho, Er, Tm, Yb, and Lu.

[0285] For example, oxide semiconductors include indium oxide, tin oxide, gallium oxide, zinc oxide, and I n-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al- Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In -Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm- Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In -Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn- Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, I n-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, In-Hf-Al-Zn An oxide can be used.

[0286] Here, for example, In-Ga-Zn oxide is a material having In, Ga, and Zn as main components. It means oxide. Metal elements other than In, Ga, and Zn may also be included. In this specification, a film made of In-Ga-Zn oxide is also called an IGZO film. .

[0287] In addition, InMO3(ZnO) m (m>0 and m is not an integer) M may be one selected from Ga, Y, Zr, La, Ce, or Nd. It refers to a metal element or elements. Also, In2SnO5(ZnO) n(n>0, and A material expressed by the formula (n is an integer) may be used.

[0288] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c are at least Both indium, zinc and M (Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce or Hf), the oxide semiconductor layer 130a In:M:Zn=x1:y1:z1 [atomic ratio], and the oxide semiconductor layer 130b is In:M Zn=x2:y2:z2 [atomic ratio], and the oxide semiconductor layer 130c is In:M:Zn=x If the atomic ratio is 3:y3:z3, then y1 / x1 and y3 / x3 are greater than y2 / x2. It is preferable that y1 / x1 and y3 / x3 are at least 1.5 times larger than y2 / x2. The thickness of the oxide semiconductor layer is preferably two times or more, and more preferably three times or more. In 130b, when y2 is equal to or greater than x2, the electrical characteristics of the transistor can be stabilized. However, if y2 is three times or more of x2, the field effect mobility of the transistor decreases. Therefore, it is preferable that y2 is less than three times x2.

[0289] When Zn and O are removed from the oxide semiconductor layer 130a and the oxide semiconductor layer 130c, In this case, the atomic ratio of In and M is preferably less than 50 atomic %. M is 50 atomic % or more, more preferably In is less than 25 atomic %, and M is 7 In addition, the oxide semiconductor layer 130b contains Zn and O. The atomic ratio of In and M is preferably 25 atomic % or more for In and 75 atomic % or more for M. More preferably, In is 34 atomic % or more and M is 66 atomic % or less. Less than c%.

[0290] The oxide semiconductor layer 130b is formed by multiplying the oxide semiconductor layer 130a and the oxide semiconductor layer 130b by the same amount. It is preferable to have a higher indium content than the c content. In oxide semiconductors, the s orbital of heavy metals is mainly The s orbitals contribute to carrier conduction, and by increasing the In content, more s orbitals are Because the paths overlap, oxides with a composition in which In is greater than M have compositions in which In is equal to or less than M. Therefore, the oxide semiconductor layer 130b has a higher mobility than the oxide semiconductor layer 130b. By using oxides with a high content of sodium, transistors with high field-effect mobility can be realized. It is possible.

[0291] The thickness of the oxide semiconductor layer 130a is 3 nm or more and 100 nm or less, preferably 5 nm or more and 50 nm or less. The thickness of the oxide semiconductor layer 1 is preferably 0 nm or less, and more preferably 5 nm or more and 25 nm or less. The thickness of 30b is 3 nm or more and 200 nm or less, preferably 5 nm or more and 150 nm or less, more preferably More preferably, the thickness of the oxide semiconductor layer 130c is 10 nm or more and 100 nm or less. The thickness is 1 nm or more and 50 nm or less, preferably 2 nm or more and 30 nm or less, and more preferably The oxide semiconductor layer 130b has a thickness of 3 nm or more and 15 nm or less. Thicker than 0c is preferable.

[0292] In order to provide a transistor having an oxide semiconductor layer as a channel with stable electrical characteristics, The impurity concentration in the oxide semiconductor layer is reduced to make the oxide semiconductor layer intrinsic (i-type) or substantially Here, the term "substantially intrinsic" means that the carrier density of the oxide semiconductor layer is Degrees is 1 x 10 19 / cm 3 Less than 1 x 10 15 / cm 3 Less than 1 x10 13 / cm 3 less than 1×10 8 / cm 3 Less than 1 x 10 -9 / cm 3 It means that it is more than that.

[0293] In addition, in the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and a metal other than the main component Elements act as impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels, increasing the carrier density. In addition, silicon contributes to the formation of impurity levels in the oxide semiconductor layer. The impurity levels become traps and may degrade the electrical characteristics of the transistor. Therefore, the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer It is preferable to reduce the impurity concentration in the layer 130c and at the respective interfaces.

[0294] In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, SIMS (Secondary Induction Measuring Machine) is used. The hydrogen concentration estimated by ion mass spectrometry (Ion Mass Spectrometry) analysis is 2 x10 20 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 below, More preferably 1 × 10 19 atoms / cm 3 Less than 5 × 10, more preferably 18 a toms / cm 3 Less than or equal to 1×10 17 atoms / cm 3 It has an area where The nitrogen concentration is controlled to be 5×10 19 atoms / cm 3Less than, preferably is 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Less than or equal to 5 x 10 16 atoms / cm 3 The control is performed so as to have a region where the above is true.

[0295] Furthermore, when silicon or carbon is contained at a high concentration, the crystallinity of the oxide semiconductor layer is reduced. In order to prevent the crystallinity of the oxide semiconductor layer from deteriorating, the silicon concentration should be set to 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1× 10 18 atoms / cm 3 The carbon concentration is controlled to have a region where the carbon concentration is equal to or greater than 1000 ppm. 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than , and more preferably 1 × 10 18 atoms / cm 3 Less than 6 x 10 17 ato ms / cm 3 The control is performed so as to have a region where the above is true.

[0296] In addition, a transistor using the above-described highly purified oxide semiconductor layer for a channel formation region can be fabricated. The off-state current of the transistor is extremely small. For example, when the voltage between the source and drain is 0.1 V, 5 V or 10V, the off-state current per channel width of the transistor is several It is possible to reduce the resistance to yA / μm to several zA / μm.

[0297] Since insulating films containing silicon are often used as gate insulating films for transistors, For the above reasons, the region serving as a channel of the oxide semiconductor layer is Therefore, it is preferable that the gate insulating film does not come into contact with the insulating film. When a channel is formed at the interface between the oxide semiconductor layer and the silicon dioxide layer, scattering of carriers occurs at the interface. This may result in a decrease in the field-effect mobility of the transistor. It is preferable to separate the region of the compound semiconductor layer that will become the channel from the gate insulating film.

[0298] Therefore, the oxide semiconductor layer 130 is divided into the oxide semiconductor layer 130a and the oxide semiconductor layer 130b. By forming a stacked structure of the oxide semiconductor layer 130b and the oxide semiconductor layer 130c, a channel can be formed in the oxide semiconductor layer 130b. This allows the formation of a transistor with high field-effect mobility and stable electrical characteristics. It is possible to form a

[0299] The band structures of the oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c In this structure, the energy of the conduction band minimum changes continuously. The oxide semiconductor layer 30a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c have similar compositions. This can also be understood from the fact that oxygen easily diffuses between the oxide semiconductor layer 130a. The oxide semiconductor layer 130b and the oxide semiconductor layer 130c are a stack of layers with different compositions. It can also be said that the layers are physically continuous, and in the drawings, the interfaces of the laminate are is represented by a dotted line.

[0300] The oxide semiconductor layer 130, which is laminated with a common main component, is not simply laminated. Continuous junction (here, specifically, a U-shaped junction in which the energy of the bottom of the conduction band changes continuously between layers) The layers are fabricated so that a U-shaped well is formed. There are no impurities that form defect levels such as trap centers or recombination centers at the interface. If impurities are mixed between the stacked oxide semiconductor layers, When the energy band is not uniform, the continuity of the energy band is lost and carriers are trapped or recombined at the interface. It will disappear when combined.

[0301] For example, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are made of In:Ga:Zn= 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4 or 1: In-Ga-Zn oxides with atomic ratios of 9:6, 1:10:1, etc. The oxide semiconductor layer 130b can be made of a Ga-Zn oxide such as I. n:Ga:Zn=1:1:1, 2:1:3, 5:5:6, 3:1:2, 4:2:3, and In-Ga-Zn oxide with an atomic ratio of 4:2:4.1 can be used. When the above oxides are used as sputtering targets for film formation, the oxide semiconductor film formed is The atomic ratio of the conductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c is They are not necessarily identical, and there is a difference of about plus or minus 40%.

[0302] The oxide semiconductor layer 130b in the oxide semiconductor layer 130 serves as a well, and The oxide semiconductor layer 130b has an energy level at the bottom of the conduction band. Since the temperature changes continuously, it can also be called a U-shaped well. The channel formed in this configuration can also be called a buried channel.

[0303] In addition, the oxide semiconductor layer 130a and the oxide semiconductor layer 130c are formed by a film such as a silicon oxide film. Trap levels due to impurities and defects can be formed near the interface with the insulating layer. The presence of the semiconductor layer 130a and the oxide semiconductor layer 130c allows the oxide semiconductor layer 13 This can keep 0b away from the trap level.

[0304] However, the energy of the conduction band minimum of the oxide semiconductor layer 130a and the oxide semiconductor layer 130c is When the difference between the energy of the bottom of the conduction band of the oxide semiconductor layer 130b and the energy of the bottom of the conduction band of the oxide semiconductor layer 130b is small, the oxide semiconductor Electrons in the conductor layer 130b may exceed the energy difference and reach the trap level. When the electrons are captured by the trap level, a negative charge is generated at the interface of the insulating layer, and the transistor The threshold voltage of the transistor shifts in the positive direction.

[0305] The oxide semiconductor layer 130a, the oxide semiconductor layer 130b, and the oxide semiconductor layer 130c include: It is preferable that the crystal portion is included. In particular, by using crystals oriented along the c-axis, it is possible to form a transistor. In addition, the c-axis oriented crystal is resistant to distortion, The reliability of a semiconductor device using a flexible substrate can be improved.

[0306] Conductive layer 140 acts as a source electrode layer and conductive layer 1 acts as a drain electrode layer. 50 includes, for example, Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, Sc and alloys of the metallic materials. Typical examples include Ti, which is particularly susceptible to bonding with oxygen, and materials that can be processed at relatively high temperatures afterward. For these reasons, it is more preferable to use W, which has a high melting point. Also, low-resistance Cu and Cu-M A stack of an alloy such as n and the above material may be used. 06, transistor 111, transistor 112, for example, conductive layer 141 and The conductive layer 142 and the conductive layer 152 are made of a laminated film of Ti and Al. You can be there.

[0307] The above-mentioned material has a property of extracting oxygen from the oxide semiconductor layer. In a part of the oxide semiconductor layer, oxygen is released from the oxide semiconductor layer, and oxygen vacancies are formed. The oxygen vacancies are combined with the small amount of hydrogen contained in the film, and the area is significantly Therefore, the n-type region becomes the source or drain of the transistor. It can be made to act as such.

[0308] When W is used for the conductive layer 140 and the conductive layer 150, nitrogen doping is also effective. By doping with nitrogen, the oxygen-pulling property can be weakened appropriately, and n-type In addition, the conductive layer 140 and the conductive layer 141 can be prevented from expanding into the channel region. The conductive layer 150 is laminated with an n-type semiconductor layer, and the n-type semiconductor layer and the oxide semiconductor layer are connected. By contacting the n-type region with the As the n-type semiconductor layer, nitrogen-doped In-Ga-Zn oxide, zinc oxide, Indium oxide, tin oxide, indium tin oxide, etc. can be used.

[0309] The insulating layer 160, which acts as a gate insulating film, may be made of aluminum oxide, magnesium oxide, Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, oxide Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, An insulating film containing one or more of hafnium oxide and tantalum oxide can be used. The insulating layer 160 may be a laminate of the above materials. It may contain the following as impurities.

[0310] Next, an example of a laminated structure of the insulating layer 160 will be described. The insulating layer 160 is made of, for example, oxygen. , nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide and It preferably contains silicon or silicon oxynitride.

[0311] Hafnium oxide and aluminum oxide are relatively Therefore, compared to when silicon oxide is used, the thickness of the insulating layer 160 can be reduced. Therefore, the leakage current due to the tunnel current can be reduced. Furthermore, it is possible to realize a transistor with a small leakage current. Hafnium has a higher dielectric constant than hafnium oxide, which has an amorphous structure. Therefore, in order to obtain a transistor with a small off-state current, hafnium oxide having a crystalline structure is used. Examples of the crystal structure include monoclinic and cubic systems. However, one aspect of the present invention is not limited to these.

[0312] The insulating layer 120 and the insulating layer 160 in contact with the oxide semiconductor layer 130 are made of a nitrogen oxide. It is preferable to use a film with a low emission amount. When the insulating layer 120 is in contact with a conductor, the density of levels caused by nitrogen oxides may increase. The insulating layer 160 may be made of, for example, a silicon oxynitride film or a silicon nitride film that emits a small amount of nitrogen oxide. An oxide insulating layer such as an aluminum oxynitride film can be used.

[0313] The silicon oxynitride film, which emits a small amount of nitrogen oxide, is This is a membrane that releases more ammonia than it releases, typically 1×10 18 pieces / cm 3 5x10 or more 19 pieces / cm 3 The amount of ammonia released is as follows: Heat treatment at a surface temperature of the film of 50°C or higher and 650°C or lower, preferably 50°C or higher and 550°C or lower The amount released is the amount released by the

[0314] By using the oxide insulating layer as the insulating layer 120 and the insulating layer 160, It is possible to reduce the shift in the threshold voltage of the transistor, and the fluctuation in the electrical characteristics of the transistor can be reduced.

[0315] The conductive layer 170 acting as a gate electrode layer may be made of, for example, Al, Ti, Cr, Co, or Ni. Conductive films such as Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta and W Furthermore, alloys of the above materials and conductive nitrides of the above materials may also be used. In addition, a plurality of materials selected from the above materials, alloys of the above materials, and conductive nitrides of the above materials are used. Typically, tungsten or a stack of tungsten and titanium nitride is used. For example, a laminate of tungsten and tantalum nitride can be used. or Cu-Mn alloys, or laminations of the above materials with Cu or Cu-Mn alloys, etc. In this embodiment, the conductive layer 171 may be made of tantalum nitride, and the conductive layer 172 may be made of tungsten. The conductive layer 170 is formed using a silicon dioxide film.

[0316] The insulating layer 175 may be formed using a silicon nitride film or an aluminum nitride film containing hydrogen. The transistor 103, the transistor 104, and the transistor transistor 106, transistor 109, transistor 110, and transistor 112 By using an insulating film containing hydrogen as the insulating layer 175, part of the oxide semiconductor layer becomes n-type. The nitride insulating film also acts as a blocking film against moisture and the like. The reliability of the transistor can be improved.

[0317] Alternatively, an aluminum oxide film may be used as the insulating layer 175. The transistor 101, the transistor 102, the transistor 105, and the transistor In transistors 107, 108, and 111, the insulating layer 175 is made of oxide. It is preferable to use an aluminum oxide film. The aluminum oxide film is formed by removing impurities such as hydrogen and moisture. Therefore, aluminum oxide has a high blocking effect, preventing the permeation of both water and oxygen. The aluminum film is resistant to impurities such as hydrogen and moisture during and after the transistor manufacturing process. to prevent oxygen from being mixed into the oxide semiconductor layer 130, to prevent oxygen from being released from the oxide semiconductor layer, and to prevent the insulating layer 1 Suitable for use as a protective film that has the effect of preventing unnecessary release of oxygen from 20 In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor layer. do.

[0318] In addition, it is preferable that an insulating layer 180 is formed on the insulating layer 175. are magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lath oxide The insulating film contains one or more of tantalum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The insulating layer may also be a laminate of the above materials.

[0319] Here, the insulating layer 180 has a larger amount of oxygen than the stoichiometric composition, similar to the insulating layer 120. It is preferable that oxygen released from the insulating layer 180 travels through the insulating layer 160 to the oxide semiconductor. Since the layer 130 can be diffused into the channel forming region, The oxygen vacancies can be filled with oxygen, which leads to the formation of a stable transistor. Electrical properties can be obtained.

[0320] To increase the integration density of semiconductor devices, miniaturization of transistors is essential. It is known that the electrical characteristics of transistors deteriorate with the miniaturization of the channel width. When the size is reduced, the on-current decreases.

[0321] In the transistors 107 to 112 of one embodiment of the present invention, channels are formed. The oxide semiconductor layer 130c is formed so as to cover the oxide semiconductor layer 130b. The channel formation layer and the gate insulating film are not in contact with each other. This suppresses the scattering of carriers at the interface with the gate insulating film, and reduces the on-state voltage of the transistor. The flow can be increased.

[0322] In addition, in the transistor of one embodiment of the present invention, the channel of the oxide semiconductor layer 130 is The gate electrode layer (conductive layer 170) is formed so as to electrically surround the panel in the width direction. Therefore, the oxide semiconductor layer 130 is subjected to a gate electric field from the side in addition to the gate electric field from the direction perpendicular to the top surface. The gate electric field is applied from the direction perpendicular to the channel forming layer. Since the gate electric field is applied to the It can be improved.

[0323] In one embodiment of the present invention, the oxide semiconductor layer 130 is a two-layer or three-layer transistor. In the first embodiment, an oxide semiconductor layer 130b in which a channel is to be formed is formed on an oxide semiconductor layer 130a. This has the effect of making it difficult for an interface state to be formed. In a transistor having a three-layer oxide semiconductor layer 130, the oxide semiconductor layer 130b is located in the middle of the three-layer structure. By placing it in the layer above the ground, it is possible to eliminate the influence of impurities from above and below. Therefore, in addition to the improvement of the on-state current of the transistor as described above, the threshold voltage is stabilized. Therefore, it is possible to reduce the S value (subthreshold value). The current when the voltage VG is 0V can be reduced, and power consumption can be reduced. Since the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device is improved. Furthermore, the transistor of one embodiment of the present invention can improve electrical characteristics with miniaturization. Since deterioration of the semiconductor device can be suppressed, it can be said that this method is suitable for forming a highly integrated semiconductor device.

[0324] The various films such as the metal film, semiconductor film, and inorganic insulating film described in this embodiment are typically It can be formed by a deposition method or a plasma CVD method, but other methods, such as thermal CVD, are also possible. The thermal CVD method may be, for example, MOCVD (Metal Organic Chemical Vapor Deposition). Chemical Vapor Deposition (ALD) and Atomic ic Layer Deposition method.

[0325] The thermal CVD method is a film formation method that does not use plasma, so defects are generated by plasma damage. This has the advantage that it will not be

[0326] In the thermal CVD method, the source gas and oxidant are simultaneously fed into the chamber. By reacting the material near or on the substrate under atmospheric or reduced pressure, the material is deposited on the substrate. Film formation may also be performed.

[0327] In the ALD method, the pressure inside the chamber is atmospheric or reduced, and the source gas for the reaction is introduced into the chamber. The film is formed by repeating this process. For example, two or more kinds of carrier gases (e.g., argon, nitrogen, etc.) may be introduced. The source gases may be supplied to the chamber in order. In this case, multiple source gases are not mixed. In this way, after the reaction of the first source gas, an inert gas is introduced, and then the second source gas is introduced. Alternatively, instead of introducing an inert gas, the first source gas is discharged by vacuum evacuation, and then the second source gas is introduced. The first source gas may be introduced into the surface of the substrate to form a first layer by adsorbing and reacting with the surface of the substrate. The second source gas introduced later is adsorbed and reacted with the first layer, and the second layer is formed on the first layer. The order of gas introduction is controlled to form a thin film of the desired thickness. By repeating this process several times, a thin film with excellent step coverage can be formed. The thickness can be precisely adjusted by changing the number of times the gas is introduced. This is suitable for fabricating miniaturized FETs.

[0328] The thermal CVD method such as the MOCVD method or the ALD method can be used in the above-described embodiments. It can form various films such as metal films, semiconductor films, and inorganic insulating films. For example, In-Ga When forming a Zn-O film, trimethylindium (In(CH3)3), Using dimethylgallium (Ga(CH3)3) and dimethylzinc (Zn(CH3)2) The combination is not limited to these, and trimethylgallium may be replaced with triethylene. Galvanic acid (Ga(C2H5)3) can also be used, and diethyl zinc can be used instead of dimethyl zinc. Zinc (Zn(C2H5)2) can also be used.

[0329] For example, when forming a hafnium oxide film using a film formation device that uses ALD, the solvent and Liquid containing hafnium precursor (hafnium alkoxide, tetrakisdimethylamide hafnium) Hf (TDMAH, Hf[N(CH3)2]4) and tetrakis(ethylmethylamide ) hafnium amide) as a raw material gas and ozone ( Two types of gases are used:

[0330] For example, when forming an aluminum oxide film using a film forming apparatus that uses ALD, the solvent and a liquid containing an aluminum precursor (trimethylaluminum (TMA, Al(CH3)3 Two types of gases are used: the raw material gas, which is vaporized from other materials, and H2O as an oxidizing agent. The materials used are tris(dimethylamido)aluminum, triisobutylaluminum, Aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), etc. There is.

[0331] For example, when forming a silicon oxide film using a film forming device that uses ALD, The chlorodisilane is adsorbed onto the surface to be coated, and the radicals of oxidizing gases (O2, nitrous oxide) are supplied. is fed to react with the adsorbate.

[0332] For example, when forming a tungsten film using a film forming device that uses ALD, WF6 gas is used. The initial tungsten film is formed by sequentially introducing WF6 gas and H The two gases are introduced sequentially to form a tungsten film. Note that SiH4 gas is used instead of B2H6 gas. A gas may also be used.

[0333] For example, an oxide semiconductor film, such as In-Ga-Zn-O, can be formed using a film formation device that uses ALD. When forming a film, In(CH3)3 gas and O3 gas are introduced sequentially to form an In-O layer. Then, Ga(CH3)3 gas and O3 gas are introduced sequentially to form a GaO layer. Then, Zn(CH3)2 gas and O3 gas are introduced sequentially to form a ZnO layer. The order of these layers is not limited to this example. It is also possible to form a mixed compound layer such as a Ga-Zn-O layer or a Ga-Zn-O layer. H2O gas obtained by bubbling with an inert gas such as Ar may be used. It is preferable to use O3 gas, which does not contain O2.

[0334] A facing target sputtering device can also be used to form the oxide semiconductor layer. The film formation method using this facing target sputtering device is called VDSP (vapor deposition). It can also be called deposition SP).

[0335] By forming an oxide semiconductor layer using a facing target sputtering apparatus, Plasma damage during the formation of the oxide semiconductor layer can be reduced. In addition, the oxygen deficiency of the film can be reduced by using a facing target sputtering device. This allows film formation at low pressure, and the impurity concentration (e.g., For example, hydrogen, rare gases (argon, etc.), water, etc. can be reduced.

[0336] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0337] (Fourth embodiment) A structure of an oxide semiconductor layer that can be used in one embodiment of the present invention will be described below. .

[0338] In this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is between 85° and 95°.

[0339] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0340] <Oxide semiconductor structure> The structure of an oxide semiconductor will be described below.

[0341] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (c-axis-aligned crystalline oxide semiconductor), polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconducting uctor), pseudo-amorphous oxide semiconductor (a-like OS) amorphous oxide semiconductors and amorphous oxide semiconductors. do.

[0342] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC- Examples include OS, polycrystalline oxide semiconductor, and nc-OS.

[0343] Amorphous structures are generally isotropic and have no heterogeneous structure, and are metastable arrangements of atoms. The bond angles are flexible, and there is short-range order but no long-range order. It is said that...

[0344] Looking at it from the other side, a stable oxide semiconductor can be considered as completely amorphous. In addition, it is not isotropic (for example, in a small area, An oxide semiconductor having a periodic structure cannot be called a completely amorphous oxide semiconductor. On the other hand, a-like OS is not isotropic but has unstable voids. In terms of instability, a-like OS is physically an amorphous oxide. It is close to a semiconductor.

[0345] <caac-os> First, let me explain about CAAC-OS.

[0346] CAAC-OS is an oxide semiconductor having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of conductor.

[0347] CAAC-OS was analyzed by X-ray diffraction (XRD). For example, the analysis of InGaZnO4, which is classified into the space group R-3m, Structural analysis of crystalline CAAC-OS is performed using the out-of-plane method. As shown in Figure 43(A), a peak appears at a diffraction angle (2θ) of approximately 31°. The crystal structure is attributed to the (009) plane of the InGaZnO4 crystal. The crystal has a c-axis orientation, and the c-axis is the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). It can be seen that the crystal is oriented in a direction perpendicular to the surface, or in a direction approximately perpendicular to the surface. In addition to the peaks around 2θ around 36°, a peak may also appear. The peaks around the nucleus are due to the crystal structure classified into the space group Fd-3m. It is preferable that -OS does not exhibit such a peak.

[0348] On the other hand, in-pla, X-rays are incident on the CAAC-OS from a direction parallel to the surface to be formed. When structural analysis is performed using the NE method, a peak appears at 2θ around 56°. This peak is due to I The lattice constant is fixed at 2θ around 56°. The analysis (φ scan) is performed by rotating the sample around the normal vector of the sample surface (φ axis). Even if the peak is increased, no clear peak appears, as shown in Figure 43(B). When φ is scanned with 2θ fixed at around 56° for nO4, the results are as shown in Figure 43(C). As shown in Fig. 1, six peaks are observed that are attributed to the crystal plane equivalent to the (110) plane. From the structural analysis using RD, it was found that the orientation of the a-axis and b-axis of CAAC-OS is irregular. It can be confirmed that:

[0349] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe was applied parallel to the surface on which the CAAC-OS was formed. When an electron beam with a diameter of 300 nm is incident, a diffraction pattern (control pattern) as shown in Figure 43(D) is generated. This diffraction pattern may contain In. This includes spots due to the (009) plane of the GaZnO4 crystal. Even in such cases, the pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is aligned with the surface on which the film is formed. On the other hand, for the same sample, the direction of the sample surface is The diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicularly is shown in Figure 43(E). As shown in Figure 43(E), a ring-shaped diffraction pattern is observed. Electron diffraction using an electron beam with a diameter of 300 nm also revealed the presence of pellets in CAAC-OS. It can be seen that the a-axis and b-axis of the dots do not have any orientation. The ring is due to the (010) and (100) planes of the InGaZnO4 crystal. It is thought that the second ring in Figure 43(E) is due to the (110) plane, etc. It is possible.

[0350] In addition, a transmission electron microscope (TEM) A combined analysis image of the bright-field image and diffraction pattern of CAAC-OS was obtained using a microscope. (also called high-resolution TEM image) reveals multiple pellets. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries (grain bows), are not clearly visible. It may not be possible to clearly identify the CAAC It can be said that the -OS is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0351] Figure 44(A) shows a high-resolution T image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. The TEM image shown here is a spherical aberration correction (SAC) image. The spherical aberration correction function was used. A high-resolution TEM image is specifically called a Cs-corrected high-resolution TEM image. For example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. It can be observed that

[0352] From Figure 44(A), it is possible to confirm the pellet, which is the region where metal atoms are arranged in layers. It has been found that the size of a single pellet can be 1 nm or more, or 3 nm or more. Therefore, the pellets are called nanocrystals (nc). Also, CAAC-OS can be used with CANC (C-Axis Aligned Nano The pellets can also be called oxide semiconductors with CAAC -OS surface or upper surface unevenness is reflected, and CAAC-OS surface or upper surface unevenness is reflected. is parallel to the surface.

[0353] 44(B) and 44(C) show the CAAC images observed from a direction approximately perpendicular to the sample surface. Figures 44(D) and 44(E) show Cs-corrected high-resolution TEM images of the -OS surface. These are the images obtained by image processing of Figure 44(B) and Figure 44(C), respectively. First, the fast Fourier transform (FFT) of FIG. Then, the FFT image is obtained by Fourier Transform (FFT). In the FFT image, the origin is used as the reference point, and the -1 to 5.0 nm -1 Remaining range between Next, the masked FFT image is subjected to an inverse fast Fourier transform (IFFT). Inverse Fast Fourier Transform (FFT) processing The image thus obtained is called an FFT filtered image. The filtered image is an image in which the periodic components are extracted from a Cs-corrected high-resolution TEM image. The sequence is shown.

[0354] In Figure 44(D), the area where the lattice arrangement is disturbed is indicated by a dashed line. The area surrounded by the dashed line is The area indicated by the broken line is the connection between the pellets. The broken line indicates a hexagonal shape, which indicates that the pellets are hexagonal. The shape of the dot is not limited to a regular hexagon, and is often a non-regular hexagon.

[0355] In Figure 44(E), a dotted line separates an area with a uniform lattice arrangement from an area with a different uniform lattice arrangement. Even near the dotted line, no clear grain boundaries can be seen. When connecting the surrounding lattice points around a neighboring lattice point, a distorted hexagon, pentagon, or / and heptagon can be formed. In other words, by distorting the lattice arrangement, the formation of grain boundaries can be suppressed. This is because the bond distance between atoms in the ab-plane direction of CAAC-OS is The reason is that the bond distance between atoms changes due to the substitution of metal elements. Therefore, it is believed that distortion can be tolerated.

[0356] As described above, the CAAC-OS has a c-axis orientation and multiple crystals in the ab-plane direction. A number of pellets (nanocrystals) are connected to form a distorted crystal structure. AC-OS, CAA crystal(c-axis-aligned ab-pl It can also be called an oxide semiconductor with an anchored crystal. do.

[0357] CAAC-OS is an oxide semiconductor with high crystallinity. In other words, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

[0358] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more likely to be present than metal elements such as silicon that make up oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and niobium Carbon dioxide and other compounds have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes disorder and reduces crystallinity.

[0359] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in an oxide semiconductor can act as carrier traps or For example, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, the SiO 2 can become a carrier generation source by capturing hydrogen.

[0360] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, 8 × 10 11 pieces / cm 3 Less than 1 x 10 11 / cm 3 less than, More preferably, 1 × 10 10 pieces / cm 3 Less than 1 x 10 -9 pieces / cm 3 The above Such an oxide semiconductor can be a high-purity intrinsic oxide semiconductor. The CAAC-OS has a low impurity concentration. In other words, it can be said that the oxide semiconductor has stable characteristics.

[0361] <nc-os> Next, we will explain nc-OS.

[0362] We will explain the case where nc-OS is analyzed by XRD. For example, When structural analysis is performed using the out-of-plane method, no peaks indicating orientation appear. That is, the crystals of nc-OS do not have any orientation.

[0363] For example, an nc-OS having InGaZnO4 crystals was thinned to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident on the region in parallel to the surface to be formed, the A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in (A) was observed. In addition, the diffraction pattern (nano) when an electron beam with a probe diameter of 1 nm is incident on the same sample. The electron diffraction pattern (B) is shown in Figure 45(B). Therefore, nc-OS has a probe diameter of 50 nm. Although the order is not confirmed by irradiating an electron beam, the order is confirmed by irradiating an electron beam with a probe diameter of 1 nm. By projecting the images, order is confirmed.

[0364] In addition, when an electron beam with a probe diameter of 1 nm is incident on an area with a thickness of less than 10 nm, As shown in Figure 45(C), an electron diffraction pattern was observed in which the spots were arranged in a roughly regular hexagonal shape. Therefore, in the range of thickness less than 10 nm, the nc-OS is ordered. It can be seen that the crystals are oriented in various directions. Therefore, there are some areas where no regular electron diffraction pattern is observed.

[0365] Figure 45(D) shows the Cs-corrected high-resolution image of the cross section of nc-OS observed from a direction approximately parallel to the surface on which the film was formed. The nc-OS is shown in the high-resolution TEM image, with the areas indicated by the auxiliary lines. There are two areas where crystals can be seen, as shown in Fig. 1, and areas where no clear crystals can be seen. The crystal part contained in the nc-OS has a size of 1 nm to 10 nm. In particular, the size is often between 1 nm and 3 nm. An oxide semiconductor having a size of more than 0 nm and not more than 100 nm is called a microcrystalline oxide semiconductor (microcrystalline oxide semiconductor). It is sometimes called a crystalline oxide semiconductor. For example, in the case of nc-OS, the grain boundaries cannot be clearly identified in high-resolution TEM images. It is possible that the nanocrystals originate from the same source as the pellets in CAAC-OS. Therefore, the crystalline part of nc-OS may be referred to as pellets below.

[0366] In this way, the nc-OS can be used in microscopic regions (e.g., regions of 1 nm to 10 nm, especially The atomic arrangement has periodicity in the region of 1 nm to 3 nm. Therefore, no regularity in the crystal orientation is observed between different pellets. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous OS. It may be difficult to distinguish it from an oxide semiconductor.

[0367] Since the crystal orientation between the pellets (nanocrystals) is not regular, nc-OS is Oxide with RANC (Random Aligned nanocrystals) Semiconductor or NANC (Non-Aligned nanocrystals) The oxide semiconductor may also be called an oxide semiconductor.

[0368] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. nc-OS has a lower defect state density than a-like OS and amorphous oxide semiconductors. However, there is no regularity in the crystal orientation between different pellets in nc-OS. , the nc-OS has a higher density of defect states than the CAAC-OS.

[0369] <a-like OS> The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. It is a conductor.

[0370] Figure 46 shows a high-resolution cross-sectional TEM image of the a-like OS. This is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. ) is 4.3 × 10 8 e - / nm 2 electrons (e - ) High a-like OS after irradiation 46(A) and 46(B) show that the a-like OS It can be seen that bright striped regions extending in the vertical direction are observed from the start of electron irradiation. It can be seen that the bright areas change shape after electron irradiation. It is estimated to be in the degree range.

[0371] Because of the porosity, the a-like OS has an unstable structure. To demonstrate that the OS has an unstable structure compared with CAAC-OS and nc-OS. , showing the structural changes caused by electron irradiation.

[0372] The samples prepared were a-like OS, nc-OS, and CAAC-OS. The sample is also an In-Ga-Zn oxide.

[0373] First, high-resolution cross-sectional TEM images of each sample are acquired. Each of these has a crystalline portion.

[0374] The unit cell of the InGaZnO4 crystal has three In-O layers and a Ga-Zn- It is known that it has a structure in which a total of nine layers, including six O layers, are stacked in layers along the c-axis. The spacing between these adjacent layers is the same as the lattice spacing (also called the d value) of the (009) plane. The value is estimated to be 0.29 nm from crystal structure analysis. Below, the area where the lattice spacing is between 0.28 nm and 0.30 nm is InGaZn The lattice fringes correspond to the ab plane of the InGaZnO4 crystal. do.

[0375] Figure 47 shows an example of investigating the average size of the crystal parts (22 to 30 locations) of each sample. The length of the lattice fringes mentioned above is the size of the crystal part. The crystal part of the OS grows in size according to the cumulative amount of electron irradiation used to obtain the TEM image. From Figure 47, it can be seen that in the early stages of TEM observation, the size of the particles was about 1.2 nm. The crystal part (also called the initial nucleus) that was - ) cumulative exposure is 4.2 × 10 8 e - / nm 2 On the other hand, in the case of nc, the size of the crystals grows to about 1.9 nm. The cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of The size of the crystalline parts of nc-OS and CAAC-OS was It can be seen that the thicknesses are approximately 1.3 nm and 1.8 nm, respectively. A Hitachi transmission electron microscope H-9000NAR was used for the TEM observations. The acceleration voltage was 300 kV and the current density was 6.7 × 10 5 e - / (nm 2 ·s), irradiation area The diameter was set to 230 nm.

[0376] In this way, the growth of crystalline parts can be observed in a-like OS due to electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals due to electron irradiation is almost nonexistent. That is, compared with nc-OS and CAAC-OS, It is clear that this is an unstable structure.

[0377] In addition, due to its porosity, a-like OS is more flexible than nc-OS and CAAC-OS. Specifically, the density of a-like OS is lower than that of a single crystal with the same composition. The density of nc-OS and CAAC is 78.6% or more and less than 92.3% of that of the original. The density of the -OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form an oxide semiconductor film having a density of less than 78% of that of the oxide semiconductor film.

[0378] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 It is less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0379] If single crystals of the same composition do not exist, single crystals of different compositions can be combined in any ratio. By doing so, it is possible to estimate the density equivalent to that of a single crystal with a desired composition. The density corresponding to a single crystal of a desired composition is calculated by the ratio of the single crystals of different compositions combined. The density can be estimated using a weighted average. However, the density should be calculated by combining as few types of single crystals as possible. It is preferable to estimate them together.

[0380] As described above, oxide semiconductors have a variety of structures, each of which has a variety of properties. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, an nc-OS, A laminated film containing two or more CAAC-OS materials may also be used.

[0381] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0382] (Embodiment 5) In this embodiment, an example of a package and a module containing an image sensor chip is The image sensor chip uses the configuration of the imaging device according to one embodiment of the present invention. You can be there.

[0383] FIG. 48(A) is a perspective view of the top surface of a package containing an image sensor chip. The package includes a package substrate 810 for fixing an image sensor chip 850, a cover It has a bar glass 820 and an adhesive 830 that bonds the two together.

[0384] Figure 48(B) is a perspective view of the bottom surface of the package. The structure of BGA (Ball grid array) is made up of solder balls as bumps 840. In addition to BGA, LGA (Land grid array) and PGA (P in Grid Array) or the like.

[0385] FIG. 48(C) shows a package in which the cover glass 820 and part of the adhesive 830 are omitted. FIG. 48(D) is a cross-sectional view of the package. Package substrate An electrode pad 860 is formed on the substrate 810, and the electrode pad 860 and the bump 840 are The electrode pad 860 is electrically connected to the electrode pad 860 via a hole 880 and a land 885. is electrically connected to the electrodes of the image sensor chip 850 by wires 870. are.

[0386] Also, Figure 49(A) shows a camera in which an image sensor chip is housed in a lens-integrated package. FIG. 1 is a perspective view of the top surface of a camera module. A package substrate 811 that fixes the cap 851, a lens cover 821, and a lens 835 In addition, there is an imaging element between the package substrate 811 and the image sensor chip 851. An IC chip 890 having functions such as a driving circuit for the image device and a signal conversion circuit is also provided. It has a SiP (System in package) configuration.

[0387] 49(B) is a perspective view of the bottom surface of the camera module. The bottom surface and four side surfaces of the package 11 are provided with lands 841 for mounting. This structure is an example only. It may be a QFP (Quad flat package) or the BGA mentioned above. stomach.

[0388] FIG. 49(C) shows a module in which the lens cover 821 and part of the lens 835 are omitted. FIG. 49(D) is a cross-sectional view of the camera module. A part of the electrode pad 861 is used as the image sensor chip. The electrodes of the chip 851 and the IC chip 890 are electrically connected by wires 871. are.

[0389] By housing the image sensor chip in the package of the above type, it is possible to This makes it easier to mount image sensor chips on various semiconductor devices and electronic equipment. It is possible.

[0390] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0391] (Embodiment 6) An imaging device according to one aspect of the present invention and an electronic device including the imaging device include a display device, Personal computers, image storage devices or image playback devices equipped with recording media, mobile phones , game consoles including portable ones, portable data terminals, e-book terminals, video cameras, digital still cameras Cameras such as mobile cameras, goggle-type displays (head-mounted displays), navigation systems audio systems, audio playback devices (car audio, digital audio players, etc.) , copiers, facsimiles, printers, printer-combined machines, automated teller machines (ATMs) ), vending machines, etc. Specific examples of these electronic devices are shown in Figure 50.

[0392] FIG. 50(A) shows a surveillance camera having a housing 951, a lens 952, a support part 953, etc. As one of the components for acquiring images in the surveillance camera, an imaging device according to one aspect of the present invention is used. The term "surveillance camera" is a common name and does not limit its use. For example, a device that functions as a surveillance camera is a camera or video camera. Also called La.

[0393] FIG. 50(B) shows a video camera, which includes a first housing 971, a second housing 972, a display unit 973, The operation key 974, the lens 975, the connection part 976, etc. 975 is provided in the first housing 971, and the display unit 973 is provided in the second housing 972. As one of the components for acquiring images in the video camera, one aspect of the present invention is The imaging device may include:

[0394] FIG. 50(C) shows a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, and a microphone 964. 63, a light emitting unit 967, a lens 965, etc. Acquiring an image with the digital camera The imaging device according to one embodiment of the present invention can be provided as one of the components for performing the imaging.

[0395] FIG. 50(D) shows a wristwatch-type information terminal, which includes a housing 931, a display unit 932, a wristband 9 33, operation buttons 935, a crown 936, a camera 939, etc. One of the components for acquiring images in the information terminal. The imaging device according to one embodiment of the present invention can be provided as an imaging device.

[0396] FIG. 50(E) shows a portable game machine, which includes a housing 901, a housing 902, a display unit 903, and a display unit 904, microphone 905, speaker 906, operation keys 907, stylus 908, camera 909, etc. The portable game machine shown in FIG. 50(E) has two display units 903 and a display unit 904, the number of display units that the portable game machine has is not limited to this. As one of the components for acquiring images in the portable game machine, The imaging device may be provided in the above embodiment.

[0397] FIG. 50(F) shows a portable data terminal, which includes a housing 911, a display unit 912, a camera 919, etc. The display portion 912 has a touch panel function that allows input and output of information. As one of the components for acquiring images in the portable data terminal, the photographing device according to one aspect of the present invention is An imaging device may be provided.

[0398] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. . [Explanation of symbols]

[0399] 20 Pixel circuit 21 pixel array 21a Pixel array 21b Pixel array 21d pixel array 21h pixel array 21q pixel array 22 circuits 23 circuits 24 circuits 25 circuits 26 Peripheral Circuits 26a Peripheral circuit 26b Peripheral circuit 26d Peripheral circuit 26h Peripheral circuit 26q Peripheral circuit 27 circuits 28 circuits 29 circuits 31 layers 32 layers 41 Transistor 42 transistors 43 Transistor 44 transistors 45 transistors 46 transistors 47 Transistor 48 transistors 51 Comparator Circuit 52 Comparator Circuit 53 OR circuit 54 Latch Circuit 55 Latch circuit 56 Counter Circuit 57a Buffer circuit 57b Buffer circuit 61 Wiring 62 Wiring 63 Wiring 64 Wiring 65 Wiring 66 Wiring 67 Wiring 71 Wiring 71a Conductive layer 71b Conductive layer 72 Wiring 73 Wiring 74 Wiring 75 Wiring 76 Wiring 77 Wiring 80 insulating layer 81 Conductors 82 Insulating layer 82a Insulating layer 82b Insulating layer 83 Insulating layer 88 Wiring 91 Wiring 92 Wiring 93 Wiring 101 Transistor 102 transistor 103 Transistor 104 transistors 105 transistors 106 transistors 107 Transistor 108 transistors 109 Transistor 110 Transistor 111 Transistor 112 transistors 113 Transistor 115 PCB 120 insulating layer 130 Oxide semiconductor layer 130a Oxide semiconductor layer 130b Oxide semiconductor layer 130c Oxide semiconductor layer 140 Conductive layer 141 Conductive layer 142 Conductive layer 150 conductive layer 151 Conductive layer 152 Conductive layer 160 Insulating Layer 170 Conductive Layer 171 Conductive layer 172 Conductive layer 173 Conductive Layer 175 Insulating Layer 180 insulating layer 190 Insulating Layer 231 areas 232 areas 233 areas 331 areas 332 areas 333 areas 334 areas 335 areas 400 memory element array 401 Circuit 402 circuits 403 Circuit 404 Circuit 405 circuits 406 circuits 407 Circuit 408 circuits 409 Circuit 561 Photoelectric conversion layer 562 Transparent conductive layer 563 Semiconductor Layer 564 Semiconductor layer 565 Semiconductor Layer 566 Electrode 566a conductive layer 566b Conductive layer 567 Bulkhead 568 Hole injection blocking layer 569 Electron injection blocking layer 600 silicon substrate 610 Transistor 620 Transistor 650 active layer 660 silicon substrate 701 circuits 702 circuits 703 Circuit 810 package substrate 811 Package Substrate 820 Cover Glass 821 Lens cover 830 Adhesive 835 Lens 840 Bump 841 rand 850 image sensor chip 851 image sensor chip 860 electrode pads 861 Electrode Pads 870 Wire 871 Wire 880 through hole 885 rand 890 IC chips 901 Case 902 Case 903 Display section 904 Display section 905 Microphone 906 Speaker 907 Operation Key 908 Stylus 909 Camera 911 chassis 912 Display section 919 Camera 931 Case 932 Display section 933 Wristband 935 Button 936 Crown 939 Camera 951 Case 952 Lens 953 Support part 961 Case 962 Shutter button 963 Mike 965 Lens 967 Light-emitting part 971 Case 972 case 973 Display section 974 Operation Key 975 Lens 976 Connection 1100 layers 1200 layers 1400 layers 1500 diffraction grating 1600 layers 2500 insulating layer 2510 Light blocking layer 2520 Organic resin layer 2530 Color Filter 2530a Color Filter 2530b color filter 2530c Color Filter 2540 Microlens Array 2550 Optical conversion layer 2560 Insulation Layer

Claims

[Claim 1] An imaging device having a pixel, a first circuit, a second circuit, and a third circuit, the pixel has a pixel circuit; the pixel circuit is electrically connected to the first circuit; the first circuit is electrically connected to the second circuit; the second circuit is electrically connected to the third circuit; the pixel has a function of outputting a first potential held in a charge storage unit, the pixel has a function of outputting a second potential held in the charge storage unit, the first potential corresponds to difference data between imaging data of a first frame and imaging data of a second frame; the second potential corresponds to data when the charge storage unit is initialized, the first circuit has a function of outputting a third potential obtained by adding or subtracting an absolute value of a difference between the first potential and the second potential to a reference potential; the second circuit has a function of converting the third potential into n-bit (n is a natural number equal to or greater than 1) first digital data, the second circuit has a function of converting a magnitude relationship of the third potential with respect to the reference potential into 1-bit second digital data; the second circuit has a function of outputting (n+1)-bit digital data obtained by combining the first digital data and the second digital data; the third circuit has a function of compressing and storing the n+1-bit digital data, the pixel circuit includes a transistor; The imaging device includes a transistor having indium oxide in a channel formation region.

Images